Commit a5c1aad8 authored by Hauke Mehrtens's avatar Hauke Mehrtens Committed by Ralf Baechle

MIPS: Lantiq: Add SoC detection for ar10 and grx390

Signed-off-by: default avatarHauke Mehrtens <hauke.mehrtens@lantiq.com>
Acked-by: default avatarJohn Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/11390/
Patchwork: https://patchwork.linux-mips.org/patch/11399/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent eefee024
...@@ -36,6 +36,16 @@ ...@@ -36,6 +36,16 @@
#define SOC_ID_GRX288_2 0x00D /* v1.2 */ #define SOC_ID_GRX288_2 0x00D /* v1.2 */
#define SOC_ID_GRX282_2 0x00E /* v1.2 */ #define SOC_ID_GRX282_2 0x00E /* v1.2 */
#define SOC_ID_ARX362 0x004
#define SOC_ID_ARX368 0x005
#define SOC_ID_ARX382 0x007
#define SOC_ID_ARX388 0x008
#define SOC_ID_URX388 0x009
#define SOC_ID_GRX383 0x010
#define SOC_ID_GRX369 0x011
#define SOC_ID_GRX387 0x00F
#define SOC_ID_GRX389 0x012
/* SoC Types */ /* SoC Types */
#define SOC_TYPE_DANUBE 0x01 #define SOC_TYPE_DANUBE 0x01
#define SOC_TYPE_TWINPASS 0x02 #define SOC_TYPE_TWINPASS 0x02
...@@ -43,6 +53,8 @@ ...@@ -43,6 +53,8 @@
#define SOC_TYPE_VR9 0x04 /* v1.1 */ #define SOC_TYPE_VR9 0x04 /* v1.1 */
#define SOC_TYPE_VR9_2 0x05 /* v1.2 */ #define SOC_TYPE_VR9_2 0x05 /* v1.2 */
#define SOC_TYPE_AMAZON_SE 0x06 #define SOC_TYPE_AMAZON_SE 0x06
#define SOC_TYPE_AR10 0x07
#define SOC_TYPE_GRX390 0x08
/* BOOT_SEL - find what boot media we have */ /* BOOT_SEL - find what boot media we have */
#define BS_EXT_ROM 0x0 #define BS_EXT_ROM 0x0
......
...@@ -4,6 +4,7 @@ ...@@ -4,6 +4,7 @@
* by the Free Software Foundation. * by the Free Software Foundation.
* *
* Copyright (C) 2010 John Crispin <blogic@openwrt.org> * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
* Copyright (C) 2013-2015 Lantiq Beteiligungs-GmbH & Co.KG
*/ */
#include <linux/export.h> #include <linux/export.h>
...@@ -19,8 +20,10 @@ ...@@ -19,8 +20,10 @@
#define SOC_TWINPASS "Twinpass" #define SOC_TWINPASS "Twinpass"
#define SOC_AMAZON_SE "Amazon_SE" #define SOC_AMAZON_SE "Amazon_SE"
#define SOC_AR9 "AR9" #define SOC_AR9 "AR9"
#define SOC_GR9 "GR9" #define SOC_GR9 "GRX200"
#define SOC_VR9 "VR9" #define SOC_VR9 "xRX200"
#define SOC_AR10 "xRX300"
#define SOC_GRX390 "xRX330"
#define COMP_DANUBE "lantiq,danube" #define COMP_DANUBE "lantiq,danube"
#define COMP_TWINPASS "lantiq,twinpass" #define COMP_TWINPASS "lantiq,twinpass"
...@@ -28,6 +31,8 @@ ...@@ -28,6 +31,8 @@
#define COMP_AR9 "lantiq,ar9" #define COMP_AR9 "lantiq,ar9"
#define COMP_GR9 "lantiq,gr9" #define COMP_GR9 "lantiq,gr9"
#define COMP_VR9 "lantiq,vr9" #define COMP_VR9 "lantiq,vr9"
#define COMP_AR10 "lantiq,ar10"
#define COMP_GRX390 "lantiq,grx390"
#define PART_SHIFT 12 #define PART_SHIFT 12
#define PART_MASK 0x0FFFFFFF #define PART_MASK 0x0FFFFFFF
...@@ -108,6 +113,25 @@ void __init ltq_soc_detect(struct ltq_soc_info *i) ...@@ -108,6 +113,25 @@ void __init ltq_soc_detect(struct ltq_soc_info *i)
i->compatible = COMP_GR9; i->compatible = COMP_GR9;
break; break;
case SOC_ID_ARX362:
case SOC_ID_ARX368:
case SOC_ID_ARX382:
case SOC_ID_ARX388:
case SOC_ID_URX388:
i->name = SOC_AR10;
i->type = SOC_TYPE_AR10;
i->compatible = COMP_AR10;
break;
case SOC_ID_GRX383:
case SOC_ID_GRX369:
case SOC_ID_GRX387:
case SOC_ID_GRX389:
i->name = SOC_GRX390;
i->type = SOC_TYPE_GRX390;
i->compatible = COMP_GRX390;
break;
default: default:
unreachable(); unreachable();
break; break;
......
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