Commit a5ed1e96 authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'powerpc-5.1-3' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux

Pull powerpc fixes from Michael Ellerman:
 "One fix for a boot failure on 32-bit, introduced during the merge
  window.

  A fix for our handling of CLOCK_MONOTONIC in the 64-bit VDSO. Changing
  the wall clock across the Y2038 boundary could cause CLOCK_MONOTONIC
  to jump forward and backward.

  Our spectre_v2 reporting was a bit confusing due to a bug I
  introduced. On some systems it was reporting that the count cache was
  disabled and also that we were flushing the count cache on context
  switch. Only the former is true, and given that the count cache is
  disabled it doesn't make any sense to flush it. No one reported it, so
  presumably the presence of any mitigation is all people check for.

  Finally a small build fix for zsmalloc on 32-bit.

  Thanks to: Ben Hutchings, Christophe Leroy, Diana Craciun, Guenter
  Roeck, Michael Neuling"

* tag 'powerpc-5.1-3' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux:
  powerpc/security: Fix spectre_v2 reporting
  powerpc/mm: Only define MAX_PHYSMEM_BITS in SPARSEMEM configurations
  powerpc/6xx: fix setup and use of SPRN_SPRG_PGDIR for hash32
  powerpc/vdso64: Fix CLOCK_MONOTONIC inconsistencies across Y2038
parents 070c95d4 92edf8df
...@@ -352,7 +352,7 @@ static inline bool strict_kernel_rwx_enabled(void) ...@@ -352,7 +352,7 @@ static inline bool strict_kernel_rwx_enabled(void)
#if defined(CONFIG_SPARSEMEM_VMEMMAP) && defined(CONFIG_SPARSEMEM_EXTREME) && \ #if defined(CONFIG_SPARSEMEM_VMEMMAP) && defined(CONFIG_SPARSEMEM_EXTREME) && \
defined (CONFIG_PPC_64K_PAGES) defined (CONFIG_PPC_64K_PAGES)
#define MAX_PHYSMEM_BITS 51 #define MAX_PHYSMEM_BITS 51
#else #elif defined(CONFIG_SPARSEMEM)
#define MAX_PHYSMEM_BITS 46 #define MAX_PHYSMEM_BITS 46
#endif #endif
......
...@@ -82,10 +82,10 @@ struct vdso_data { ...@@ -82,10 +82,10 @@ struct vdso_data {
__u32 icache_block_size; /* L1 i-cache block size */ __u32 icache_block_size; /* L1 i-cache block size */
__u32 dcache_log_block_size; /* L1 d-cache log block size */ __u32 dcache_log_block_size; /* L1 d-cache log block size */
__u32 icache_log_block_size; /* L1 i-cache log block size */ __u32 icache_log_block_size; /* L1 i-cache log block size */
__s32 wtom_clock_sec; /* Wall to monotonic clock */
__s32 wtom_clock_nsec;
struct timespec stamp_xtime; /* xtime as at tb_orig_stamp */
__u32 stamp_sec_fraction; /* fractional seconds of stamp_xtime */ __u32 stamp_sec_fraction; /* fractional seconds of stamp_xtime */
__s32 wtom_clock_nsec; /* Wall to monotonic clock nsec */
__s64 wtom_clock_sec; /* Wall to monotonic clock sec */
struct timespec stamp_xtime; /* xtime as at tb_orig_stamp */
__u32 syscall_map_64[SYSCALL_MAP_SIZE]; /* map of syscalls */ __u32 syscall_map_64[SYSCALL_MAP_SIZE]; /* map of syscalls */
__u32 syscall_map_32[SYSCALL_MAP_SIZE]; /* map of syscalls */ __u32 syscall_map_32[SYSCALL_MAP_SIZE]; /* map of syscalls */
}; };
......
...@@ -24,9 +24,6 @@ BEGIN_MMU_FTR_SECTION ...@@ -24,9 +24,6 @@ BEGIN_MMU_FTR_SECTION
li r10,0 li r10,0
mtspr SPRN_SPRG_603_LRU,r10 /* init SW LRU tracking */ mtspr SPRN_SPRG_603_LRU,r10 /* init SW LRU tracking */
END_MMU_FTR_SECTION_IFSET(MMU_FTR_NEED_DTLB_SW_LRU) END_MMU_FTR_SECTION_IFSET(MMU_FTR_NEED_DTLB_SW_LRU)
lis r10, (swapper_pg_dir - PAGE_OFFSET)@h
ori r10, r10, (swapper_pg_dir - PAGE_OFFSET)@l
mtspr SPRN_SPRG_PGDIR, r10
BEGIN_FTR_SECTION BEGIN_FTR_SECTION
bl __init_fpu_registers bl __init_fpu_registers
......
...@@ -855,6 +855,9 @@ __secondary_start: ...@@ -855,6 +855,9 @@ __secondary_start:
li r3,0 li r3,0
stw r3, RTAS_SP(r4) /* 0 => not in RTAS */ stw r3, RTAS_SP(r4) /* 0 => not in RTAS */
#endif #endif
lis r4, (swapper_pg_dir - PAGE_OFFSET)@h
ori r4, r4, (swapper_pg_dir - PAGE_OFFSET)@l
mtspr SPRN_SPRG_PGDIR, r4
/* enable MMU and jump to start_secondary */ /* enable MMU and jump to start_secondary */
li r4,MSR_KERNEL li r4,MSR_KERNEL
...@@ -942,6 +945,9 @@ start_here: ...@@ -942,6 +945,9 @@ start_here:
li r3,0 li r3,0
stw r3, RTAS_SP(r4) /* 0 => not in RTAS */ stw r3, RTAS_SP(r4) /* 0 => not in RTAS */
#endif #endif
lis r4, (swapper_pg_dir - PAGE_OFFSET)@h
ori r4, r4, (swapper_pg_dir - PAGE_OFFSET)@l
mtspr SPRN_SPRG_PGDIR, r4
/* stack */ /* stack */
lis r1,init_thread_union@ha lis r1,init_thread_union@ha
......
...@@ -190,29 +190,22 @@ ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, c ...@@ -190,29 +190,22 @@ ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, c
bcs = security_ftr_enabled(SEC_FTR_BCCTRL_SERIALISED); bcs = security_ftr_enabled(SEC_FTR_BCCTRL_SERIALISED);
ccd = security_ftr_enabled(SEC_FTR_COUNT_CACHE_DISABLED); ccd = security_ftr_enabled(SEC_FTR_COUNT_CACHE_DISABLED);
if (bcs || ccd || count_cache_flush_type != COUNT_CACHE_FLUSH_NONE) { if (bcs || ccd) {
bool comma = false;
seq_buf_printf(&s, "Mitigation: "); seq_buf_printf(&s, "Mitigation: ");
if (bcs) { if (bcs)
seq_buf_printf(&s, "Indirect branch serialisation (kernel only)"); seq_buf_printf(&s, "Indirect branch serialisation (kernel only)");
comma = true;
}
if (ccd) {
if (comma)
seq_buf_printf(&s, ", ");
seq_buf_printf(&s, "Indirect branch cache disabled");
comma = true;
}
if (comma) if (bcs && ccd)
seq_buf_printf(&s, ", "); seq_buf_printf(&s, ", ");
seq_buf_printf(&s, "Software count cache flush"); if (ccd)
seq_buf_printf(&s, "Indirect branch cache disabled");
} else if (count_cache_flush_type != COUNT_CACHE_FLUSH_NONE) {
seq_buf_printf(&s, "Mitigation: Software count cache flush");
if (count_cache_flush_type == COUNT_CACHE_FLUSH_HW) if (count_cache_flush_type == COUNT_CACHE_FLUSH_HW)
seq_buf_printf(&s, "(hardware accelerated)"); seq_buf_printf(&s, " (hardware accelerated)");
} else if (btb_flush_enabled) { } else if (btb_flush_enabled) {
seq_buf_printf(&s, "Mitigation: Branch predictor state flush"); seq_buf_printf(&s, "Mitigation: Branch predictor state flush");
} else { } else {
......
...@@ -92,7 +92,7 @@ V_FUNCTION_BEGIN(__kernel_clock_gettime) ...@@ -92,7 +92,7 @@ V_FUNCTION_BEGIN(__kernel_clock_gettime)
* At this point, r4,r5 contain our sec/nsec values. * At this point, r4,r5 contain our sec/nsec values.
*/ */
lwa r6,WTOM_CLOCK_SEC(r3) ld r6,WTOM_CLOCK_SEC(r3)
lwa r9,WTOM_CLOCK_NSEC(r3) lwa r9,WTOM_CLOCK_NSEC(r3)
/* We now have our result in r6,r9. We create a fake dependency /* We now have our result in r6,r9. We create a fake dependency
...@@ -125,7 +125,7 @@ V_FUNCTION_BEGIN(__kernel_clock_gettime) ...@@ -125,7 +125,7 @@ V_FUNCTION_BEGIN(__kernel_clock_gettime)
bne cr6,75f bne cr6,75f
/* CLOCK_MONOTONIC_COARSE */ /* CLOCK_MONOTONIC_COARSE */
lwa r6,WTOM_CLOCK_SEC(r3) ld r6,WTOM_CLOCK_SEC(r3)
lwa r9,WTOM_CLOCK_NSEC(r3) lwa r9,WTOM_CLOCK_NSEC(r3)
/* check if counter has updated */ /* check if counter has updated */
......
...@@ -70,12 +70,12 @@ _GLOBAL(hash_page) ...@@ -70,12 +70,12 @@ _GLOBAL(hash_page)
lis r0,KERNELBASE@h /* check if kernel address */ lis r0,KERNELBASE@h /* check if kernel address */
cmplw 0,r4,r0 cmplw 0,r4,r0
ori r3,r3,_PAGE_USER|_PAGE_PRESENT /* test low addresses as user */ ori r3,r3,_PAGE_USER|_PAGE_PRESENT /* test low addresses as user */
mfspr r5, SPRN_SPRG_PGDIR /* virt page-table root */ mfspr r5, SPRN_SPRG_PGDIR /* phys page-table root */
blt+ 112f /* assume user more likely */ blt+ 112f /* assume user more likely */
lis r5,swapper_pg_dir@ha /* if kernel address, use */ lis r5, (swapper_pg_dir - PAGE_OFFSET)@ha /* if kernel address, use */
addi r5,r5,swapper_pg_dir@l /* kernel page table */ addi r5 ,r5 ,(swapper_pg_dir - PAGE_OFFSET)@l /* kernel page table */
rlwimi r3,r9,32-12,29,29 /* MSR_PR -> _PAGE_USER */ rlwimi r3,r9,32-12,29,29 /* MSR_PR -> _PAGE_USER */
112: tophys(r5, r5) 112:
#ifndef CONFIG_PTE_64BIT #ifndef CONFIG_PTE_64BIT
rlwimi r5,r4,12,20,29 /* insert top 10 bits of address */ rlwimi r5,r4,12,20,29 /* insert top 10 bits of address */
lwz r8,0(r5) /* get pmd entry */ lwz r8,0(r5) /* get pmd entry */
......
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