Commit a86b4ad6 authored by Linus Torvalds's avatar Linus Torvalds

Merge branch 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc

* 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc:
  powerpc: Fix build on some non-freescale platforms
  powerpc/powernv: Fix PCI resource handling
  powerpc/crash: Fix build error without SMP
  powerpc/cpuidle: Make it a bool, not a tristate
  powerpc/85xx: Add dr_mode property in USB nodes
  powerpc/85xx: Enable USB2 controller node for P1020RDB
  powerpc/85xx: Fix cmd12 bug and add the chip compatible for eSDHC
  arch/powerpc/sysdev/fsl_pci.c: add missing iounmap
  powerpc: fix compile error with 85xx/p1022_ds.c
parents 701b259f 3493c853
......@@ -236,6 +236,10 @@ usb@2b000 {
};
/include/ "pq3-esdhc-0.dtsi"
sdhc@2e000 {
compatible = "fsl,mpc8536-esdhc", "fsl,esdhc";
};
/include/ "pq3-sec3.0-0.dtsi"
/include/ "pq3-mpic.dtsi"
/include/ "pq3-mpic-timer-B.dtsi"
......
......@@ -158,7 +158,8 @@ L2: l2-cache-controller@20000 {
/include/ "pq3-usb2-dr-0.dtsi"
/include/ "pq3-esdhc-0.dtsi"
sdhc@2e000 {
fsl,sdhci-auto-cmd12;
compatible = "fsl,p1010-esdhc", "fsl,esdhc";
sdhci,auto-cmd12;
};
/include/ "pq3-sec4.4-0.dtsi"
......
......@@ -145,6 +145,10 @@ L2: l2-cache-controller@20000 {
/include/ "pq3-usb2-dr-1.dtsi"
/include/ "pq3-esdhc-0.dtsi"
sdhc@2e000 {
compatible = "fsl,p1020-esdhc", "fsl,esdhc";
sdhci,auto-cmd12;
};
/include/ "pq3-sec3.3-0.dtsi"
/include/ "pq3-mpic.dtsi"
......
......@@ -203,7 +203,8 @@ L2: l2-cache-controller@20000 {
/include/ "pq3-esdhc-0.dtsi"
sdhc@2e000 {
fsl,sdhci-auto-cmd12;
compatible = "fsl,p1022-esdhc", "fsl,esdhc";
sdhci,auto-cmd12;
};
/include/ "pq3-sec3.3-0.dtsi"
......
......@@ -182,6 +182,10 @@ ptp_clock@24e00 {
/include/ "pq3-etsec1-1.dtsi"
/include/ "pq3-etsec1-2.dtsi"
/include/ "pq3-esdhc-0.dtsi"
sdhc@2e000 {
compatible = "fsl,p2020-esdhc", "fsl,esdhc";
};
/include/ "pq3-sec3.1-0.dtsi"
/include/ "pq3-mpic.dtsi"
/include/ "pq3-mpic-timer-B.dtsi"
......
/*
* P1020 RDB Device Tree Source stub (no addresses or top-level ranges)
*
* Copyright 2011 Freescale Semiconductor Inc.
* Copyright 2011-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
......@@ -190,17 +190,16 @@ partition@jffs-fs {
usb@22000 {
phy_type = "ulpi";
dr_mode = "host";
};
/* USB2 is shared with localbus, so it must be disabled
by default. We can't put 'status = "disabled";' here
since U-Boot doesn't clear the status property when
it enables USB2. OTOH, U-Boot does create a new node
when there isn't any. So, just comment it out.
/* USB2 is shared with localbus. It is used
only in case of SPI and SD boot after
appropriate device-tree fixup done by uboot */
usb@23000 {
phy_type = "ulpi";
dr_mode = "host";
};
*/
mdio@24000 {
phy0: ethernet-phy@0 {
......
/*
* P1021 MDS Device Tree Source
*
* Copyright 2010 Freescale Semiconductor Inc.
* Copyright 2010,2012 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
......@@ -151,6 +151,7 @@ partition@fs {
usb@22000 {
phy_type = "ulpi";
dr_mode = "host";
};
mdio@24000 {
......
/*
* P2020DS Device Tree Source stub (no addresses or top-level ranges)
*
* Copyright 2011 Freescale Semiconductor Inc.
* Copyright 2011-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
......@@ -134,6 +134,7 @@ nand@6,0 {
&board_soc {
usb@22000 {
phy_type = "ulpi";
dr_mode = "host";
};
mdio@24520 {
......
/*
* P2020 RDB Device Tree Source
*
* Copyright 2009-2011 Freescale Semiconductor Inc.
* Copyright 2009-2012 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
......@@ -197,6 +197,7 @@ partition@900000 {
usb@22000 {
phy_type = "ulpi";
dr_mode = "host";
};
mdio@24520 {
......
......@@ -46,7 +46,6 @@
/* This keeps a track of which one is the crashing cpu. */
int crashing_cpu = -1;
static atomic_t cpus_in_crash;
static int time_to_dump;
#define CRASH_HANDLER_MAX 3
......@@ -66,6 +65,7 @@ static int handle_fault(struct pt_regs *regs)
#ifdef CONFIG_SMP
static atomic_t cpus_in_crash;
void crash_ipi_callback(struct pt_regs *regs)
{
static cpumask_t cpus_state_saved = CPU_MASK_NONE;
......
......@@ -442,8 +442,10 @@ static void __init fixup_port_irq(int index,
port->irq = virq;
#ifdef CONFIG_SERIAL_8250_FSL
if (of_device_is_compatible(np, "fsl,ns16550"))
port->handle_irq = fsl8250_handle_irq;
#endif
}
static void __init fixup_port_pio(int index,
......
......@@ -25,6 +25,7 @@
#include <sysdev/fsl_soc.h>
#include <sysdev/fsl_pci.h>
#include <asm/udbg.h>
#include <asm/fsl_guts.h>
#include "smp.h"
......
......@@ -204,11 +204,10 @@ static void __devinit pnv_ioda_offset_bus(struct pci_bus *bus,
pr_devel(" -> OBR %s [%x] +%016llx\n",
bus->self ? pci_name(bus->self) : "root", flags, offset);
for (i = 0; i < 2; i++) {
r = bus->resource[i];
pci_bus_for_each_resource(bus, r, i) {
if (r && (r->flags & flags)) {
bus->resource[i]->start += offset;
bus->resource[i]->end += offset;
r->start += offset;
r->end += offset;
}
}
list_for_each_entry(dev, &bus->devices, bus_list)
......@@ -288,12 +287,17 @@ static void __devinit pnv_ioda_calc_bus(struct pci_bus *bus, unsigned int flags,
* assignment algorithm is going to be uber-trivial for now, we
* can try to be smarter later at filling out holes.
*/
start = bus->self ? 0 : bus->resource[bres]->start;
if (bus->self) {
/* No offset for downstream bridges */
start = 0;
} else {
/* Offset from the root */
if (flags & IORESOURCE_IO)
/* Don't hand out IO 0 */
if ((flags & IORESOURCE_IO) && !bus->self)
start += 0x1000;
start = hose->io_resource.start + 0x1000;
else
start = hose->mem_resources[0].start;
}
while(!list_empty(&head)) {
w = list_first_entry(&head, struct resource_wrap, link);
list_del(&w->link);
......@@ -321,13 +325,20 @@ static void __devinit pnv_ioda_calc_bus(struct pci_bus *bus, unsigned int flags,
empty:
/* Only setup P2P's, not the PHB itself */
if (bus->self) {
WARN_ON(bus->resource[bres] == NULL);
bus->resource[bres]->start = 0;
bus->resource[bres]->flags = (*size) ? flags : 0;
bus->resource[bres]->end = (*size) ? (*size - 1) : 0;
struct resource *res = bus->resource[bres];
/* Clear prefetch bus resources for now */
bus->resource[2]->flags = 0;
if (WARN_ON(res == NULL))
return;
/*
* FIXME: We should probably export and call
* pci_bridge_check_ranges() to properly re-initialize
* the PCI portion of the flags here, and to detect
* what the bridge actually supports.
*/
res->start = 0;
res->flags = (*size) ? flags : 0;
res->end = (*size) ? (*size - 1) : 0;
}
pr_devel("<- CBR %s [%x] *size=%016llx *align=%016llx\n",
......
......@@ -122,7 +122,7 @@ config DTL
Say N if you are unsure.
config PSERIES_IDLE
tristate "Cpuidle driver for pSeries platforms"
bool "Cpuidle driver for pSeries platforms"
depends on CPU_IDLE
depends on PPC_PSERIES
default y
......
......@@ -205,12 +205,12 @@ static void __init setup_pci_atmu(struct pci_controller *hose,
if (paddr_hi == paddr_lo) {
pr_err("%s: No outbound window space\n", name);
return ;
goto out;
}
if (paddr_lo == 0) {
pr_err("%s: No space for inbound window\n", name);
return ;
goto out;
}
/* setup PCSRBAR/PEXCSRBAR */
......@@ -357,6 +357,7 @@ static void __init setup_pci_atmu(struct pci_controller *hose,
(u64)hose->dma_window_size);
}
out:
iounmap(pci);
}
......
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