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Commit a9650b7f authored by Ilkka Koskinen's avatar Ilkka Koskinen Committed by Arnaldo Carvalho de Melo
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perf vendor events arm64: Add AmpereOne core PMU events 

Add JSON files for AmpereOne core PMU events.
Reviewed-by: default avatarJohn Garry <john.g.garry@oracle.com>
Signed-off-by: default avatarDoug Rady <dcrady@os.amperecomputing.com>
Signed-off-by: default avatarIlkka Koskinen <ilkka@os.amperecomputing.com>
Acked-by: default avatarIan Rogers <irogers@google.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@arm.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Leo Yan <leo.yan@linaro.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Mike Leach <mike.leach@linaro.org>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Will Deacon <will@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Link: https://lore.kernel.org/r/20230427223220.1068356-1-ilkka@os.amperecomputing.comSigned-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
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tools/perf/pmu-events/arch/arm64/ampere/ampereone/branch.json 0 → 100644
View file @ a9650b7f
[
{
"ArchStdEvent": "BR_IMMED_SPEC"
},
{
"ArchStdEvent": "BR_RETURN_SPEC"
},
{
"ArchStdEvent": "BR_INDIRECT_SPEC"
},
{
"ArchStdEvent": "BR_MIS_PRED"
},
{
"ArchStdEvent": "BR_PRED"
}
]
tools/perf/pmu-events/arch/arm64/ampere/ampereone/bus.json 0 → 100644
View file @ a9650b7f
[
{
"ArchStdEvent": "CPU_CYCLES"
},
{
"ArchStdEvent": "BUS_CYCLES"
},
{
"ArchStdEvent": "BUS_ACCESS_RD"
},
{
"ArchStdEvent": "BUS_ACCESS_WR"
},
{
"ArchStdEvent": "BUS_ACCESS_SHARED"
},
{
"ArchStdEvent": "BUS_ACCESS_NOT_SHARED"
},
{
"ArchStdEvent": "BUS_ACCESS_NORMAL"
},
{
"ArchStdEvent": "BUS_ACCESS_PERIPH"
},
{
"ArchStdEvent": "BUS_ACCESS"
},
{
"ArchStdEvent": "CNT_CYCLES"
}
]
tools/perf/pmu-events/arch/arm64/ampere/ampereone/cache.json 0 → 100644
View file @ a9650b7f
[
{
"ArchStdEvent": "L1D_CACHE_RD"
},
{
"ArchStdEvent": "L1D_CACHE_WR"
},
{
"ArchStdEvent": "L1D_CACHE_REFILL_RD"
},
{
"ArchStdEvent": "L1D_CACHE_INVAL"
},
{
"ArchStdEvent": "L1D_TLB_REFILL_RD"
},
{
"ArchStdEvent": "L1D_TLB_REFILL_WR"
},
{
"ArchStdEvent": "L2D_CACHE_RD"
},
{
"ArchStdEvent": "L2D_CACHE_WR"
},
{
"ArchStdEvent": "L2D_CACHE_REFILL_RD"
},
{
"ArchStdEvent": "L2D_CACHE_REFILL_WR"
},
{
"ArchStdEvent": "L2D_CACHE_WB_VICTIM"
},
{
"ArchStdEvent": "L2D_CACHE_WB_CLEAN"
},
{
"ArchStdEvent": "L2D_CACHE_INVAL"
},
{
"ArchStdEvent": "L1I_CACHE_REFILL"
},
{
"ArchStdEvent": "L1I_TLB_REFILL"
},
{
"ArchStdEvent": "L1D_CACHE_REFILL"
},
{
"ArchStdEvent": "L1D_CACHE"
},
{
"ArchStdEvent": "L1D_TLB_REFILL"
},
{
"ArchStdEvent": "L1I_CACHE"
},
{
"ArchStdEvent": "L2D_CACHE"
},
{
"ArchStdEvent": "L2D_CACHE_REFILL"
},
{
"ArchStdEvent": "L2D_CACHE_WB"
},
{
"ArchStdEvent": "L1D_TLB"
},
{
"ArchStdEvent": "L1I_TLB"
},
{
"ArchStdEvent": "L2D_TLB_REFILL"
},
{
"ArchStdEvent": "L2I_TLB_REFILL"
},
{
"ArchStdEvent": "L2D_TLB"
},
{
"ArchStdEvent": "L2I_TLB"
},
{
"ArchStdEvent": "DTLB_WALK"
},
{
"ArchStdEvent": "ITLB_WALK"
},
{
"ArchStdEvent": "L1D_CACHE_LMISS_RD"
},
{
"ArchStdEvent": "L1D_CACHE_LMISS"
},
{
"ArchStdEvent": "L1I_CACHE_LMISS"
},
{
"ArchStdEvent": "L2D_CACHE_LMISS_RD"
}
]
tools/perf/pmu-events/arch/arm64/ampere/ampereone/core-imp-def.json 0 → 100644
View file @ a9650b7f
[
{
"PublicDescription": "Level 2 prefetch requests, refilled to L2 cache",
"EventCode": "0x10A",
"EventName": "L2_PREFETCH_REFILL",
"BriefDescription": "Level 2 prefetch requests, refilled to L2 cache"
},
{
"PublicDescription": "Level 2 prefetch requests, late",
"EventCode": "0x10B",
"EventName": "L2_PREFETCH_UPGRADE",
"BriefDescription": "Level 2 prefetch requests, late"
},
{
"PublicDescription": "Predictable branch speculatively executed that hit any level of BTB",
"EventCode": "0x110",
"EventName": "BPU_HIT_BTB",
"BriefDescription": "Predictable branch speculatively executed that hit any level of BTB"
},
{
"PublicDescription": "Predictable conditional branch speculatively executed that hit any level of BTB",
"EventCode": "0x111",
"EventName": "BPU_CONDITIONAL_BRANCH_HIT_BTB",
"BriefDescription": "Predictable conditional branch speculatively executed that hit any level of BTB"
},
{
"PublicDescription": "Predictable taken branch speculatively executed that hit any level of BTB that access the indirect predictor",
"EventCode": "0x112",
"EventName": "BPU_HIT_INDIRECT_PREDICTOR",
"BriefDescription": "Predictable taken branch speculatively executed that hit any level of BTB that access the indirect predictor"
},
{
"PublicDescription": "Predictable taken branch speculatively executed that hit any level of BTB that access the return predictor",
"EventCode": "0x113",
"EventName": "BPU_HIT_RSB",
"BriefDescription": "Predictable taken branch speculatively executed that hit any level of BTB that access the return predictor"
},
{
"PublicDescription": "Predictable unconditional branch speculatively executed that did not hit any level of BTB",
"EventCode": "0x114",
"EventName": "BPU_UNCONDITIONAL_BRANCH_MISS_BTB",
"BriefDescription": "Predictable unconditional branch speculatively executed that did not hit any level of BTB"
},
{
"PublicDescription": "Predictable branch speculatively executed, unpredicted",
"EventCode": "0x115",
"EventName": "BPU_BRANCH_NO_HIT",
"BriefDescription": "Predictable branch speculatively executed, unpredicted"
},
{
"PublicDescription": "Predictable branch speculatively executed that hit any level of BTB that mispredict",
"EventCode": "0x116",
"EventName": "BPU_HIT_BTB_AND_MISPREDICT",
"BriefDescription": "Predictable branch speculatively executed that hit any level of BTB that mispredict"
},
{
"PublicDescription": "Predictable conditional branch speculatively executed that hit any level of BTB that (direction) mispredict",
"EventCode": "0x117",
"EventName": "BPU_CONDITIONAL_BRANCH_HIT_BTB_AND_MISPREDICT",
"BriefDescription": "Predictable conditional branch speculatively executed that hit any level of BTB that (direction) mispredict"
},
{
"PublicDescription": "Predictable taken branch speculatively executed that hit any level of BTB that access the indirect predictor that mispredict",
"EventCode": "0x118",
"EventName": "BPU_INDIRECT_BRANCH_HIT_BTB_AND_MISPREDICT",
"BriefDescription": "Predictable taken branch speculatively executed that hit any level of BTB that access the indirect predictor that mispredict"
},
{
"PublicDescription": "Predictable taken branch speculatively executed that hit any level of BTB that access the return predictor that mispredict",
"EventCode": "0x119",
"EventName": "BPU_HIT_RSB_AND_MISPREDICT",
"BriefDescription": "Predictable taken branch speculatively executed that hit any level of BTB that access the return predictor that mispredict"
},
{
"PublicDescription": "Predictable taken branch speculatively executed that hit any level of BTB that access the overflow/underflow return predictor that mispredict",
"EventCode": "0x11a",
"EventName": "BPU_MISS_RSB_AND_MISPREDICT",
"BriefDescription": "Predictable taken branch speculatively executed that hit any level of BTB that access the overflow/underflow return predictor that mispredict"
},
{
"PublicDescription": "Predictable branch speculatively executed, unpredicted, that mispredict",
"EventCode": "0x11b",
"EventName": "BPU_NO_PREDICTION_MISPREDICT",
"BriefDescription": "Predictable branch speculatively executed, unpredicted, that mispredict"
},
{
"PublicDescription": "Predictable branch speculatively executed, unpredicted, that mispredict",
"EventCode": "0x11c",
"EventName": "BPU_BTB_UPDATE",
"BriefDescription": "Predictable branch speculatively executed, unpredicted, that mispredict"
},
{
"PublicDescription": "Count predict pipe stalls due to speculative return address predictor full",
"EventCode": "0x11d",
"EventName": "BPU_RSB_FULL_STALL",
"BriefDescription": "Count predict pipe stalls due to speculative return address predictor full"
},
{
"PublicDescription": "Macro-ops speculatively decoded",
"EventCode": "0x11f",
"EventName": "ICF_INST_SPEC_DECODE",
"BriefDescription": "Macro-ops speculatively decoded"
},
{
"PublicDescription": "Flushes",
"EventCode": "0x120",
"EventName": "GPC_FLUSH",
"BriefDescription": "Flushes"
},
{
"PublicDescription": "Flushes due to memory hazards",
"EventCode": "0x121",
"EventName": "BPU_FLUSH_MEM_FAULT",
"BriefDescription": "Flushes due to memory hazards"
},
{
"PublicDescription": "ETM extout bit 0",
"EventCode": "0x141",
"EventName": "MSC_ETM_EXTOUT0",
"BriefDescription": "ETM extout bit 0"
},
{
"PublicDescription": "ETM extout bit 1",
"EventCode": "0x142",
"EventName": "MSC_ETM_EXTOUT1",
"BriefDescription": "ETM extout bit 1"
},
{
"PublicDescription": "ETM extout bit 2",
"EventCode": "0x143",
"EventName": "MSC_ETM_EXTOUT2",
"BriefDescription": "ETM extout bit 2"
},
{
"PublicDescription": "ETM extout bit 3",
"EventCode": "0x144",
"EventName": "MSC_ETM_EXTOUT3",
"BriefDescription": "ETM extout bit 3"
},
{
"PublicDescription": "Bus request sn",
"EventCode": "0x156",
"EventName": "L2C_SNOOP",
"BriefDescription": "Bus request sn"
},
{
"PublicDescription": "L2 TXDAT LCRD blocked",
"EventCode": "0x169",
"EventName": "L2C_DAT_CRD_STALL",
"BriefDescription": "L2 TXDAT LCRD blocked"
},
{
"PublicDescription": "L2 TXRSP LCRD blocked",
"EventCode": "0x16a",
"EventName": "L2C_RSP_CRD_STALL",
"BriefDescription": "L2 TXRSP LCRD blocked"
},
{
"PublicDescription": "L2 TXREQ LCRD blocked",
"EventCode": "0x16b",
"EventName": "L2C_REQ_CRD_STALL",
"BriefDescription": "L2 TXREQ LCRD blocked"
},
{
"PublicDescription": "Early mispredict",
"EventCode": "0xD100",
"EventName": "ICF_EARLY_MIS_PRED",
"BriefDescription": "Early mispredict"
},
{
"PublicDescription": "FEQ full cycles",
"EventCode": "0xD101",
"EventName": "ICF_FEQ_FULL",
"BriefDescription": "FEQ full cycles"
},
{
"PublicDescription": "Instruction FIFO Full",
"EventCode": "0xD102",
"EventName": "ICF_INST_FIFO_FULL",
"BriefDescription": "Instruction FIFO Full"
},
{
"PublicDescription": "L1I TLB miss",
"EventCode": "0xD103",
"EventName": "L1I_TLB_MISS",
"BriefDescription": "L1I TLB miss"
},
{
"PublicDescription": "ICF sent 0 instructions to IDR this cycle",
"EventCode": "0xD104",
"EventName": "ICF_STALL",
"BriefDescription": "ICF sent 0 instructions to IDR this cycle"
},
{
"PublicDescription": "PC FIFO Full",
"EventCode": "0xD105",
"EventName": "ICF_PC_FIFO_FULL",
"BriefDescription": "PC FIFO Full"
},
{
"PublicDescription": "Stall due to BOB ID",
"EventCode": "0xD200",
"EventName": "IDR_STALL_BOB_ID",
"BriefDescription": "Stall due to BOB ID"
},
{
"PublicDescription": "Dispatch stall due to LOB entries",
"EventCode": "0xD201",
"EventName": "IDR_STALL_LOB_ID",
"BriefDescription": "Dispatch stall due to LOB entries"
},
{
"PublicDescription": "Dispatch stall due to SOB entries",
"EventCode": "0xD202",
"EventName": "IDR_STALL_SOB_ID",
"BriefDescription": "Dispatch stall due to SOB entries"
},
{
"PublicDescription": "Dispatch stall due to IXU scheduler entries",
"EventCode": "0xD203",
"EventName": "IDR_STALL_IXU_SCHED",
"BriefDescription": "Dispatch stall due to IXU scheduler entries"
},
{
"PublicDescription": "Dispatch stall due to FSU scheduler entries",
"EventCode": "0xD204",
"EventName": "IDR_STALL_FSU_SCHED",
"BriefDescription": "Dispatch stall due to FSU scheduler entries"
},
{
"PublicDescription": "Dispatch stall due to ROB entries",
"EventCode": "0xD205",
"EventName": "IDR_STALL_ROB_ID",
"BriefDescription": "Dispatch stall due to ROB entries"
},
{
"PublicDescription": "Dispatch stall due to flush (6 cycles)",
"EventCode": "0xD206",
"EventName": "IDR_STALL_FLUSH",
"BriefDescription": "Dispatch stall due to flush (6 cycles)"
},
{
"PublicDescription": "Dispatch stall due to WFI",
"EventCode": "0xD207",
"EventName": "IDR_STALL_WFI",
"BriefDescription": "Dispatch stall due to WFI"
},
{
"PublicDescription": "Number of SWOB drains triggered by timeout",
"EventCode": "0xD208",
"EventName": "IDR_STALL_SWOB_TIMEOUT",
"BriefDescription": "Number of SWOB drains triggered by timeout"
},
{
"PublicDescription": "Number of SWOB drains triggered by system register or special-purpose register read-after-write or specific special-purpose register writes that cause SWOB drain",
"EventCode": "0xD209",
"EventName": "IDR_STALL_SWOB_RAW",
"BriefDescription": "Number of SWOB drains triggered by system register or special-purpose register read-after-write or specific special-purpose register writes that cause SWOB drain"
},
{
"PublicDescription": "Number of SWOB drains triggered by system register write when SWOB full",
"EventCode": "0xD20A",
"EventName": "IDR_STALL_SWOB_FULL",
"BriefDescription": "Number of SWOB drains triggered by system register write when SWOB full"
},
{
"PublicDescription": "Dispatch stall due to L1 instruction cache miss",
"EventCode": "0xD20B",
"EventName": "STALL_FRONTEND_CACHE",
"BriefDescription": "Dispatch stall due to L1 instruction cache miss"
},
{
"PublicDescription": "Dispatch stall due to L1 instruction TLB miss",
"EventCode": "0xD20C",
"EventName": "STALL_FRONTEND_TLB",
"BriefDescription": "Dispatch stall due to L1 instruction TLB miss"
},
{
"PublicDescription": "Dispatch stall due to L1 data cache miss",
"EventCode": "0xD20D",
"EventName": "STALL_BACKEND_CACHE",
"BriefDescription": "Dispatch stall due to L1 data cache miss"
},
{
"PublicDescription": "Dispatch stall due to L1 data TLB miss",
"EventCode": "0xD20E",
"EventName": "STALL_BACKEND_TLB",
"BriefDescription": "Dispatch stall due to L1 data TLB miss"
},
{
"PublicDescription": "Dispatch stall due to lack of any core resource",
"EventCode": "0xD20F",
"EventName": "STALL_BACKEND_RESOURCE",
"BriefDescription": "Dispatch stall due to lack of any core resource"
},
{
"PublicDescription": "Instructions issued by the scheduler",
"EventCode": "0xD300",
"EventName": "IXU_NUM_UOPS_ISSUED",
"BriefDescription": "Instructions issued by the scheduler"
},
{
"PublicDescription": "Any uop issued was canceled for any reason",
"EventCode": "0xD301",
"EventName": "IXU_ISSUE_CANCEL",
"BriefDescription": "Any uop issued was canceled for any reason"
},
{
"PublicDescription": "A load wakeup to the scheduler has been cancelled",
"EventCode": "0xD302",
"EventName": "IXU_LOAD_CANCEL",
"BriefDescription": "A load wakeup to the scheduler has been cancelled"
},
{
"PublicDescription": "The scheduler had to cancel one slow Uop due to resource conflict",
"EventCode": "0xD303",
"EventName": "IXU_SLOW_CANCEL",
"BriefDescription": "The scheduler had to cancel one slow Uop due to resource conflict"
},
{
"PublicDescription": "Uops issued by the scheduler on IXA",
"EventCode": "0xD304",
"EventName": "IXU_IXA_ISSUED",
"BriefDescription": "Uops issued by the scheduler on IXA"
},
{
"PublicDescription": "Uops issued by the scheduler on IXA Par 0",
"EventCode": "0xD305",
"EventName": "IXU_IXA_PAR0_ISSUED",
"BriefDescription": "Uops issued by the scheduler on IXA Par 0"
},
{
"PublicDescription": "Uops issued by the scheduler on IXA Par 1",
"EventCode": "0xD306",
"EventName": "IXU_IXA_PAR1_ISSUED",
"BriefDescription": "Uops issued by the scheduler on IXA Par 1"
},
{
"PublicDescription": "Uops issued by the scheduler on IXB",
"EventCode": "0xD307",
"EventName": "IXU_IXB_ISSUED",
"BriefDescription": "Uops issued by the scheduler on IXB"
},
{
"PublicDescription": "Uops issued by the scheduler on IXB Par 0",
"EventCode": "0xD308",
"EventName": "IXU_IXB_PAR0_ISSUED",
"BriefDescription": "Uops issued by the scheduler on IXB Par 0"
},
{
"PublicDescription": "Uops issued by the scheduler on IXB Par 1",
"EventCode": "0xD309",
"EventName": "IXU_IXB_PAR1_ISSUED",
"BriefDescription": "Uops issued by the scheduler on IXB Par 1"
},
{
"PublicDescription": "Uops issued by the scheduler on IXC",
"EventCode": "0xD30A",
"EventName": "IXU_IXC_ISSUED",
"BriefDescription": "Uops issued by the scheduler on IXC"
},
{
"PublicDescription": "Uops issued by the scheduler on IXC Par 0",
"EventCode": "0xD30B",
"EventName": "IXU_IXC_PAR0_ISSUED",
"BriefDescription": "Uops issued by the scheduler on IXC Par 0"
},
{
"PublicDescription": "Uops issued by the scheduler on IXC Par 1",
"EventCode": "0xD30C",
"EventName": "IXU_IXC_PAR1_ISSUED",
"BriefDescription": "Uops issued by the scheduler on IXC Par 1"
},
{
"PublicDescription": "Uops issued by the scheduler on IXD",
"EventCode": "0xD30D",
"EventName": "IXU_IXD_ISSUED",
"BriefDescription": "Uops issued by the scheduler on IXD"
},
{
"PublicDescription": "Uops issued by the scheduler on IXD Par 0",
"EventCode": "0xD30E",
"EventName": "IXU_IXD_PAR0_ISSUED",
"BriefDescription": "Uops issued by the scheduler on IXD Par 0"
},
{
"PublicDescription": "Uops issued by the scheduler on IXD Par 1",
"EventCode": "0xD30F",
"EventName": "IXU_IXD_PAR1_ISSUED",
"BriefDescription": "Uops issued by the scheduler on IXD Par 1"
},
{
"PublicDescription": "Uops issued by the FSU scheduler",
"EventCode": "0xD400",
"EventName": "FSU_ISSUED",
"BriefDescription": "Uops issued by the FSU scheduler"
},
{
"PublicDescription": "Uops issued by the scheduler on pipe X",
"EventCode": "0xD401",
"EventName": "FSU_FSX_ISSUED",
"BriefDescription": "Uops issued by the scheduler on pipe X"
},
{
"PublicDescription": "Uops issued by the scheduler on pipe Y",
"EventCode": "0xD402",
"EventName": "FSU_FSY_ISSUED",
"BriefDescription": "Uops issued by the scheduler on pipe Y"
},
{
"PublicDescription": "Uops issued by the scheduler on pipe Z",
"EventCode": "0xD403",
"EventName": "FSU_FSZ_ISSUED",
"BriefDescription": "Uops issued by the scheduler on pipe Z"
},
{
"PublicDescription": "Uops canceled (load cancels)",
"EventCode": "0xD404",
"EventName": "FSU_CANCEL",
"BriefDescription": "Uops canceled (load cancels)"
},
{
"PublicDescription": "Count scheduler stalls due to divide/sqrt",
"EventCode": "0xD405",
"EventName": "FSU_DIV_SQRT_STALL",
"BriefDescription": "Count scheduler stalls due to divide/sqrt"
},
{
"PublicDescription": "Number of SWOB drains",
"EventCode": "0xD500",
"EventName": "GPC_SWOB_DRAIN",
"BriefDescription": "Number of SWOB drains"
},
{
"PublicDescription": "GPC detected a Breakpoint instruction match",
"EventCode": "0xD501",
"EventName": "BREAKPOINT_MATCH",
"BriefDescription": "GPC detected a Breakpoint instruction match"
},
{
"PublicDescription": "L1D TLB miss",
"EventCode": "0xD600",
"EventName": "L1D_TLB_MISS",
"BriefDescription": "L1D TLB miss"
},
{
"PublicDescription": "OFB full cycles",
"EventCode": "0xD601",
"EventName": "OFB_FULL",
"BriefDescription": "OFB full cycles"
},
{
"PublicDescription": "Load satisified from store forwarded data",
"EventCode": "0xD605",
"EventName": "LD_FROM_ST_FWD",
"BriefDescription": "Load satisified from store forwarded data"
},
{
"PublicDescription": "L1 prefetcher, load prefetch requests generated",
"EventCode": "0xD606",
"EventName": "L1_PFETCH_LD_GEN",
"BriefDescription": "L1 prefetcher, load prefetch requests generated"
},
{
"PublicDescription": "L1 prefetcher, load prefetch fills into the L1 cache",
"EventCode": "0xD607",
"EventName": "L1_PFETCH_LD_FILL",
"BriefDescription": "L1 prefetcher, load prefetch fills into the L1 cache"
},
{
"PublicDescription": "L1 prefetcher, load prefetch to L2 generated",
"EventCode": "0xD608",
"EventName": "L1_PFETCH_L2_REQ",
"BriefDescription": "L1 prefetcher, load prefetch to L2 generated"
},
{
"PublicDescription": "L1 prefetcher, distance was reset",
"EventCode": "0xD609",
"EventName": "L1_PFETCH_DIST_RST",
"BriefDescription": "L1 prefetcher, distance was reset"
},
{
"PublicDescription": "L1 prefetcher, distance was increased",
"EventCode": "0xD60A",
"EventName": "L1_PFETCH_DIST_INC",
"BriefDescription": "L1 prefetcher, distance was increased"
},
{
"PublicDescription": "L1 prefetcher, table entry is trained",
"EventCode": "0xD60B",
"EventName": "L1_PFETCH_ENTRY_TRAINED",
"BriefDescription": "L1 prefetcher, table entry is trained"
},
{
"PublicDescription": "Store retirement pipe stall",
"EventCode": "0xD60C",
"EventName": "LSU_ST_RETIRE_STALL",
"BriefDescription": "Store retirement pipe stall"
},
{
"PublicDescription": "LSU detected a Watchpoint data match",
"EventCode": "0xD60D",
"EventName": "WATCHPOINT_MATCH",
"BriefDescription": "LSU detected a Watchpoint data match"
},
{
"PublicDescription": "L2 pipeline replay",
"EventCode": "0xD700",
"EventName": "L2C_PIPE_REPLAY",
"BriefDescription": "L2 pipeline replay"
},
{
"PublicDescription": "L2 refill from I-side miss",
"EventCode": "0xD701",
"EventName": "L2C_INST_REFILL",
"BriefDescription": "L2 refill from I-side miss"
},
{
"PublicDescription": "L2 refill from D-side miss",
"EventCode": "0xD702",
"EventName": "L2C_DATA_REFILL",
"BriefDescription": "L2 refill from D-side miss"
},
{
"PublicDescription": "L2 prefetcher, load prefetch requests generated",
"EventCode": "0xD703",
"EventName": "L2_PREFETCH_REQ",
"BriefDescription": "L2 prefetcher, load prefetch requests generated"
},
{
"PublicDescription": "L2D OTB allocate",
"EventCode": "0xD800",
"EventName": "MMU_D_OTB_ALLOC",
"BriefDescription": "L2D OTB allocate"
},
{
"PublicDescription": "DTLB Translation cache hit on S1L2 walk cache entry",
"EventCode": "0xD801",
"EventName": "MMU_D_TRANS_CACHE_HIT_S1L2_WALK",
"BriefDescription": "DTLB Translation cache hit on S1L2 walk cache entry"
},
{
"PublicDescription": "DTLB Translation cache hit on S1L1 walk cache entry",
"EventCode": "0xD802",
"EventName": "MMU_D_TRANS_CACHE_HIT_S1L1_WALK",
"BriefDescription": "DTLB Translation cache hit on S1L1 walk cache entry"
},
{
"PublicDescription": "DTLB Translation cache hit on S1L0 walk cache entry",
"EventCode": "0xD803",
"EventName": "MMU_D_TRANS_CACHE_HIT_S1L0_WALK",
"BriefDescription": "DTLB Translation cache hit on S1L0 walk cache entry"
},
{
"PublicDescription": "DTLB Translation cache hit on S2L2 walk cache entry",
"EventCode": "0xD804",
"EventName": "MMU_D_TRANS_CACHE_HIT_S2L2_WALK",
"BriefDescription": "DTLB Translation cache hit on S2L2 walk cache entry"
},
{
"PublicDescription": "DTLB Translation cache hit on S2L1 walk cache entry",
"EventCode": "0xD805",
"EventName": "MMU_D_TRANS_CACHE_HIT_S2L1_WALK",
"BriefDescription": "DTLB Translation cache hit on S2L1 walk cache entry"
},
{
"PublicDescription": "DTLB Translation cache hit on S2L0 walk cache entry",
"EventCode": "0xD806",
"EventName": "MMU_D_TRANS_CACHE_HIT_S2L0_WALK",
"BriefDescription": "DTLB Translation cache hit on S2L0 walk cache entry"
},
{
"PublicDescription": "D-side S1 Page walk cache lookup",
"EventCode": "0xD807",
"EventName": "MMU_D_S1_WALK_CACHE_LOOKUP",
"BriefDescription": "D-side S1 Page walk cache lookup"
},
{
"PublicDescription": "D-side S1 Page walk cache refill",
"EventCode": "0xD808",
"EventName": "MMU_D_S1_WALK_CACHE_REFILL",
"BriefDescription": "D-side S1 Page walk cache refill"
},
{
"PublicDescription": "D-side S2 Page walk cache lookup",
"EventCode": "0xD809",
"EventName": "MMU_D_S2_WALK_CACHE_LOOKUP",
"BriefDescription": "D-side S2 Page walk cache lookup"
},
{
"PublicDescription": "D-side S2 Page walk cache refill",
"EventCode": "0xD80A",
"EventName": "MMU_D_S2_WALK_CACHE_REFILL",
"BriefDescription": "D-side S2 Page walk cache refill"
},
{
"PublicDescription": "D-side Stage1 tablewalk fault",
"EventCode": "0xD80B",
"EventName": "MMU_D_S1_WALK_FAULT",
"BriefDescription": "D-side Stage1 tablewalk fault"
},
{
"PublicDescription": "D-side Stage2 tablewalk fault",
"EventCode": "0xD80C",
"EventName": "MMU_D_S2_WALK_FAULT",
"BriefDescription": "D-side Stage2 tablewalk fault"
},
{
"PublicDescription": "D-side Tablewalk steps or descriptor fetches",
"EventCode": "0xD80D",
"EventName": "MMU_D_WALK_STEPS",
"BriefDescription": "D-side Tablewalk steps or descriptor fetches"
},
{
"PublicDescription": "L2I OTB allocate",
"EventCode": "0xD900",
"EventName": "MMU_I_OTB_ALLOC",
"BriefDescription": "L2I OTB allocate"
},
{
"PublicDescription": "ITLB Translation cache hit on S1L2 walk cache entry",
"EventCode": "0xD901",
"EventName": "MMU_I_TRANS_CACHE_HIT_S1L2_WALK",
"BriefDescription": "ITLB Translation cache hit on S1L2 walk cache entry"
},
{
"PublicDescription": "ITLB Translation cache hit on S1L1 walk cache entry",
"EventCode": "0xD902",
"EventName": "MMU_I_TRANS_CACHE_HIT_S1L1_WALK",
"BriefDescription": "ITLB Translation cache hit on S1L1 walk cache entry"
},
{
"PublicDescription": "ITLB Translation cache hit on S1L0 walk cache entry",
"EventCode": "0xD903",
"EventName": "MMU_I_TRANS_CACHE_HIT_S1L0_WALK",
"BriefDescription": "ITLB Translation cache hit on S1L0 walk cache entry"
},
{
"PublicDescription": "ITLB Translation cache hit on S2L2 walk cache entry",
"EventCode": "0xD904",
"EventName": "MMU_I_TRANS_CACHE_HIT_S2L2_WALK",
"BriefDescription": "ITLB Translation cache hit on S2L2 walk cache entry"
},
{
"PublicDescription": "ITLB Translation cache hit on S2L1 walk cache entry",
"EventCode": "0xD905",
"EventName": "MMU_I_TRANS_CACHE_HIT_S2L1_WALK",
"BriefDescription": "ITLB Translation cache hit on S2L1 walk cache entry"
},
{
"PublicDescription": "ITLB Translation cache hit on S2L0 walk cache entry",
"EventCode": "0xD906",
"EventName": "MMU_I_TRANS_CACHE_HIT_S2L0_WALK",
"BriefDescription": "ITLB Translation cache hit on S2L0 walk cache entry"
},
{
"PublicDescription": "I-side S1 Page walk cache lookup",
"EventCode": "0xD907",
"EventName": "MMU_I_S1_WALK_CACHE_LOOKUP",
"BriefDescription": "I-side S1 Page walk cache lookup"
},
{
"PublicDescription": "I-side S1 Page walk cache refill",
"EventCode": "0xD908",
"EventName": "MMU_I_S1_WALK_CACHE_REFILL",
"BriefDescription": "I-side S1 Page walk cache refill"
},
{
"PublicDescription": "I-side S2 Page walk cache lookup",
"EventCode": "0xD909",
"EventName": "MMU_I_S2_WALK_CACHE_LOOKUP",
"BriefDescription": "I-side S2 Page walk cache lookup"
},
{
"PublicDescription": "I-side S2 Page walk cache refill",
"EventCode": "0xD90A",
"EventName": "MMU_I_S2_WALK_CACHE_REFILL",
"BriefDescription": "I-side S2 Page walk cache refill"
},
{
"PublicDescription": "I-side Stage1 tablewalk fault",
"EventCode": "0xD90B",
"EventName": "MMU_I_S1_WALK_FAULT",
"BriefDescription": "I-side Stage1 tablewalk fault"
},
{
"PublicDescription": "I-side Stage2 tablewalk fault",
"EventCode": "0xD90C",
"EventName": "MMU_I_S2_WALK_FAULT",
"BriefDescription": "I-side Stage2 tablewalk fault"
},
{
"PublicDescription": "I-side Tablewalk steps or descriptor fetches",
"EventCode": "0xD90D",
"EventName": "MMU_I_WALK_STEPS",
"BriefDescription": "I-side Tablewalk steps or descriptor fetches"
}
]
tools/perf/pmu-events/arch/arm64/ampere/ampereone/exception.json 0 → 100644
View file @ a9650b7f
[
{
"ArchStdEvent": "EXC_UNDEF"
},
{
"ArchStdEvent": "EXC_SVC"
},
{
"ArchStdEvent": "EXC_PABORT"
},
{
"ArchStdEvent": "EXC_DABORT"
},
{
"ArchStdEvent": "EXC_IRQ"
},
{
"ArchStdEvent": "EXC_FIQ"
},
{
"ArchStdEvent": "EXC_HVC"
},
{
"ArchStdEvent": "EXC_TRAP_PABORT"
},
{
"ArchStdEvent": "EXC_TRAP_DABORT"
},
{
"ArchStdEvent": "EXC_TRAP_OTHER"
},
{
"ArchStdEvent": "EXC_TRAP_IRQ"
},
{
"ArchStdEvent": "EXC_TRAP_FIQ"
},
{
"ArchStdEvent": "EXC_TAKEN"
},
{
"ArchStdEvent": "EXC_RETURN"
}
]
tools/perf/pmu-events/arch/arm64/ampere/ampereone/instruction.json 0 → 100644
View file @ a9650b7f
[
{
"ArchStdEvent": "SW_INCR"
},
{
"ArchStdEvent": "ST_RETIRED"
},
{
"ArchStdEvent": "OP_SPEC"
},
{
"ArchStdEvent": "LD_SPEC"
},
{
"ArchStdEvent": "ST_SPEC"
},
{
"ArchStdEvent": "LDST_SPEC"
},
{
"ArchStdEvent": "DP_SPEC"
},
{
"ArchStdEvent": "ASE_SPEC"
},
{
"ArchStdEvent": "VFP_SPEC"
},
{
"ArchStdEvent": "PC_WRITE_SPEC"
},
{
"ArchStdEvent": "BR_IMMED_RETIRED"
},
{
"ArchStdEvent": "BR_RETURN_RETIRED"
},
{
"ArchStdEvent": "CRYPTO_SPEC"
},
{
"ArchStdEvent": "ISB_SPEC"
},
{
"ArchStdEvent": "DSB_SPEC"
},
{
"ArchStdEvent": "DMB_SPEC"
},
{
"ArchStdEvent": "RC_LD_SPEC"
},
{
"ArchStdEvent": "RC_ST_SPEC"
},
{
"ArchStdEvent": "INST_RETIRED"
},
{
"ArchStdEvent": "CID_WRITE_RETIRED"
},
{
"ArchStdEvent": "PC_WRITE_RETIRED"
},
{
"ArchStdEvent": "INST_SPEC"
},
{
"ArchStdEvent": "TTBR_WRITE_RETIRED"
},
{
"ArchStdEvent": "BR_RETIRED"
},
{
"ArchStdEvent": "BR_MIS_PRED_RETIRED"
},
{
"ArchStdEvent": "OP_RETIRED"
},
{
"ArchStdEvent": "OP_SPEC"
},
{
"PublicDescription": "Operation speculatively executed, NOP",
"EventCode": "0x100",
"EventName": "NOP_SPEC",
"BriefDescription": "Speculatively executed, NOP"
}
]
tools/perf/pmu-events/arch/arm64/ampere/ampereone/intrinsic.json 0 → 100644
View file @ a9650b7f
[
{
"ArchStdEvent": "LDREX_SPEC"
},
{
"ArchStdEvent": "STREX_PASS_SPEC"
},
{
"ArchStdEvent": "STREX_FAIL_SPEC"
},
{
"ArchStdEvent": "STREX_SPEC"
}
]
tools/perf/pmu-events/arch/arm64/ampere/ampereone/memory.json 0 → 100644
View file @ a9650b7f
[
{
"ArchStdEvent": "LD_RETIRED"
},
{
"ArchStdEvent": "MEM_ACCESS_RD"
},
{
"ArchStdEvent": "MEM_ACCESS_WR"
},
{
"ArchStdEvent": "UNALIGNED_LD_SPEC"
},
{
"ArchStdEvent": "UNALIGNED_ST_SPEC"
},
{
"ArchStdEvent": "UNALIGNED_LDST_SPEC"
},
{
"ArchStdEvent": "LD_ALIGN_LAT"
},
{
"ArchStdEvent": "ST_ALIGN_LAT"
},
{
"ArchStdEvent": "MEM_ACCESS"
},
{
"ArchStdEvent": "MEMORY_ERROR"
},
{
"ArchStdEvent": "LDST_ALIGN_LAT"
},
{
"ArchStdEvent": "MEM_ACCESS_CHECKED"
},
{
"ArchStdEvent": "MEM_ACCESS_CHECKED_RD"
},
{
"ArchStdEvent": "MEM_ACCESS_CHECKED_WR"
}
]
tools/perf/pmu-events/arch/arm64/ampere/ampereone/pipeline.json 0 → 100644
View file @ a9650b7f
[
{
"ArchStdEvent": "STALL_FRONTEND"
},
{
"ArchStdEvent": "STALL_BACKEND"
},
{
"ArchStdEvent": "STALL"
},
{
"ArchStdEvent": "STALL_SLOT_BACKEND"
},
{
"ArchStdEvent": "STALL_SLOT_FRONTEND"
},
{
"ArchStdEvent": "STALL_SLOT"
},
{
"ArchStdEvent": "STALL_BACKEND_MEM"
}
]
tools/perf/pmu-events/arch/arm64/ampere/ampereone/spe.json 0 → 100644
View file @ a9650b7f
[
{
"ArchStdEvent": "SAMPLE_POP"
},
{
"ArchStdEvent": "SAMPLE_FEED"
},
{
"ArchStdEvent": "SAMPLE_FILTRATE"
},
{
"ArchStdEvent": "SAMPLE_COLLISION"
}
]
tools/perf/pmu-events/arch/arm64/mapfile.csv
View file @ a9650b7f
......@@ -41,3 +41,4 @@
0x00000000460f0010,v1,fujitsu/a64fx,core
0x00000000480fd010,v1,hisilicon/hip08,core
0x00000000500f0000,v1,ampere/emag,core
0x00000000c00fac30,v1,ampere/ampereone,core
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