Commit aa6c32f9 authored by Sergio Paracuellos's avatar Sergio Paracuellos Committed by Greg Kroah-Hartman

staging: mt7621-pci: remove 'RALINK_PCI_BAR0SETUP_ADDR' definition

Instead of define RALINK_PCI_BAR0SETUP_ADDR just use standard
pci defnition for this which is 'PCI_BASE_ADDRESS_0'.
Signed-off-by: default avatarSergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20210607120153.24989-3-sergio.paracuellos@gmail.comSigned-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent a3bb1d05
......@@ -47,7 +47,6 @@
#define MT7621_PCIE_OFFSET 0x2000
#define MT7621_NEXT_PORT 0x1000
#define RALINK_PCI_BAR0SETUP_ADDR 0x0010
#define RALINK_PCI_ID 0x0030
#define RALINK_PCI_CLASS 0x0034
#define RALINK_PCI_SUBID 0x0038
......@@ -494,7 +493,7 @@ static void mt7621_pcie_enable_port(struct mt7621_pcie_port *port)
/* map 2G DDR region */
pcie_write(pcie, PCIE_BAR_MAP_MAX | PCIE_BAR_ENABLE,
offset + RALINK_PCI_BAR0SETUP_ADDR);
offset + PCI_BASE_ADDRESS_0);
/* configure class code and revision ID */
pcie_write(pcie, PCIE_CLASS_CODE | PCIE_REVISION_ID,
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment