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Commit ab3ee7a5 authored by Zeyu Fan's avatar Zeyu Fan Committed by Alex Deucher
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drm/amd/display: OPP refactor and consolidation for DCE. 

Signed-off-by: default avatarZeyu Fan <Zeyu.Fan@amd.com>
Reviewed-by: default avatarTony Cheng <Tony.Cheng@amd.com>
Acked-by: default avatarHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent e63d86dc
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Showing with 1547 additions and 3960 deletions
drivers/gpu/drm/amd/display/dc/dce/Makefile
View file @ ab3ee7a5
......@@ -7,7 +7,7 @@
DCE = dce_audio.o dce_stream_encoder.o dce_link_encoder.o dce_hwseq.o \
dce_mem_input.o dce_clock_source.o dce_scl_filters.o dce_transform.o \
dce_clocks.o
dce_clocks.o dce_opp.o
AMD_DAL_DCE = $(addprefix $(AMDDALPATH)/dc/dce/,$(DCE))
......
drivers/gpu/drm/amd/display/dc/dce/dce_opp.c 0 → 100644
View file @ ab3ee7a5
This diff is collapsed.
drivers/gpu/drm/amd/display/dc/dce/dce_opp.h 0 → 100644
View file @ ab3ee7a5
This diff is collapsed.
drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
View file @ ab3ee7a5
......@@ -39,7 +39,7 @@
#include "dce110/dce110_mem_input_v.h"
#include "dce110/dce110_ipp.h"
#include "dce/dce_transform.h"
#include "dce110/dce110_opp.h"
#include "dce/dce_opp.h"
#include "dce/dce_clocks.h"
#include "dce/dce_clock_source.h"
#include "dce/dce_audio.h"
......@@ -302,6 +302,29 @@ static const struct dce_stream_encoder_mask se_mask = {
SE_COMMON_MASK_SH_LIST_DCE80_100(_MASK)
};
#define opp_regs(id)\
[id] = {\
OPP_DCE_100_REG_LIST(id),\
}
static const struct dce_opp_registers opp_regs[] = {
opp_regs(0),
opp_regs(1),
opp_regs(2),
opp_regs(3),
opp_regs(4),
opp_regs(5)
};
static const struct dce_opp_shift opp_shift = {
OPP_COMMON_MASK_SH_LIST_DCE_100(__SHIFT)
};
static const struct dce_opp_mask opp_mask = {
OPP_COMMON_MASK_SH_LIST_DCE_100(_MASK)
};
#define audio_regs(id)\
[id] = {\
AUD_COMMON_REG_LIST(id)\
......@@ -348,35 +371,6 @@ static const struct dce110_clk_src_mask cs_mask = {
#define DCFE_MEM_PWR_CTRL_REG_BASE 0x1b03
static const struct dce110_opp_reg_offsets dce100_opp_reg_offsets[] = {
{
.fmt_offset = (mmFMT0_FMT_CONTROL - mmFMT_CONTROL),
.dcfe_offset = (mmCRTC0_DCFE_MEM_PWR_CTRL - DCFE_MEM_PWR_CTRL_REG_BASE),
.dcp_offset = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL),
},
{ .fmt_offset = (mmFMT1_FMT_CONTROL - mmFMT0_FMT_CONTROL),
.dcfe_offset = (mmCRTC1_DCFE_MEM_PWR_CTRL - DCFE_MEM_PWR_CTRL_REG_BASE),
.dcp_offset = (mmDCP1_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
},
{ .fmt_offset = (mmFMT2_FMT_CONTROL - mmFMT0_FMT_CONTROL),
.dcfe_offset = (mmCRTC2_DCFE_MEM_PWR_CTRL - DCFE_MEM_PWR_CTRL_REG_BASE),
.dcp_offset = (mmDCP2_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
},
{
.fmt_offset = (mmFMT3_FMT_CONTROL - mmFMT0_FMT_CONTROL),
.dcfe_offset = (mmCRTC3_DCFE_MEM_PWR_CTRL - DCFE_MEM_PWR_CTRL_REG_BASE),
.dcp_offset = (mmDCP3_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
},
{ .fmt_offset = (mmFMT4_FMT_CONTROL - mmFMT0_FMT_CONTROL),
.dcfe_offset = (mmCRTC4_DCFE_MEM_PWR_CTRL - DCFE_MEM_PWR_CTRL_REG_BASE),
.dcp_offset = (mmDCP4_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
},
{ .fmt_offset = (mmFMT5_FMT_CONTROL - mmFMT0_FMT_CONTROL),
.dcfe_offset = (mmCRTC5_DCFE_MEM_PWR_CTRL - DCFE_MEM_PWR_CTRL_REG_BASE),
.dcp_offset = (mmDCP5_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
}
};
static const struct bios_registers bios_regs = {
.BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6
};
......@@ -615,8 +609,7 @@ struct link_encoder *dce100_link_encoder_create(
struct output_pixel_processor *dce100_opp_create(
struct dc_context *ctx,
uint32_t inst,
const struct dce110_opp_reg_offsets *offset)
uint32_t inst)
{
struct dce110_opp *opp =
dm_alloc(sizeof(struct dce110_opp));
......@@ -625,7 +618,7 @@ struct output_pixel_processor *dce100_opp_create(
return NULL;
if (dce110_opp_construct(opp,
ctx, inst, offset))
ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask))
return &opp->base;
BREAK_TO_DEBUGGER();
......@@ -1052,7 +1045,7 @@ static bool construct(
goto res_create_fail;
}
pool->base.opps[i] = dce100_opp_create(ctx, i, &dce100_opp_reg_offsets[i]);
pool->base.opps[i] = dce100_opp_create(ctx, i);
if (pool->base.opps[i] == NULL) {
BREAK_TO_DEBUGGER();
dm_error(
......
drivers/gpu/drm/amd/display/dc/dce110/Makefile
View file @ ab3ee7a5
......@@ -3,8 +3,8 @@
# It provides the control and status of HW CRTC block.
DCE110 = dce110_ipp.o dce110_ipp_cursor.o \
dce110_ipp_gamma.o dce110_opp.o dce110_opp_csc.o \
dce110_timing_generator.o dce110_opp_formatter.o dce110_opp_regamma.o \
dce110_ipp_gamma.o \
dce110_timing_generator.o \
dce110_compressor.o dce110_mem_input.o dce110_hw_sequencer.o \
dce110_resource.o \
dce110_opp_regamma_v.o dce110_opp_csc_v.o dce110_timing_generator_v.o \
......
drivers/gpu/drm/amd/display/dc/dce110/dce110_opp.c deleted 100644 → 0
View file @ e63d86dc
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#include "dm_services.h"
/* include DCE11 register header files */
#include "dce/dce_11_0_d.h"
#include "dce/dce_11_0_sh_mask.h"
#include "dce110_opp.h"
#include "gamma_types.h"
enum {
MAX_LUT_ENTRY = 256,
MAX_NUMBER_OF_ENTRIES = 256
};
/*****************************************/
/* Constructor, Destructor */
/*****************************************/
static const struct opp_funcs funcs = {
.opp_power_on_regamma_lut = dce110_opp_power_on_regamma_lut,
.opp_set_csc_adjustment = dce110_opp_set_csc_adjustment,
.opp_set_csc_default = dce110_opp_set_csc_default,
.opp_set_dyn_expansion = dce110_opp_set_dyn_expansion,
.opp_program_regamma_pwl = dce110_opp_program_regamma_pwl,
.opp_set_regamma_mode = dce110_opp_set_regamma_mode,
.opp_destroy = dce110_opp_destroy,
.opp_program_fmt = dce110_opp_program_fmt,
};
bool dce110_opp_construct(struct dce110_opp *opp110,
struct dc_context *ctx,
uint32_t inst,
const struct dce110_opp_reg_offsets *offsets)
{
opp110->base.funcs = &funcs;
opp110->base.ctx = ctx;
opp110->base.inst = inst;
opp110->offsets = *offsets;
return true;
}
void dce110_opp_destroy(struct output_pixel_processor **opp)
{
dm_free(FROM_DCE11_OPP(*opp));
*opp = NULL;
}
drivers/gpu/drm/amd/display/dc/dce110/dce110_opp.h deleted 100644 → 0
View file @ e63d86dc
/* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DC_OPP_DCE110_H__
#define __DC_OPP_DCE110_H__
#include "dc_types.h"
#include "opp.h"
#include "core_types.h"
#include "gamma_types.h" /* decprecated */
struct gamma_parameters;
#define FROM_DCE11_OPP(opp)\
container_of(opp, struct dce110_opp, base)
enum dce110_opp_reg_type {
DCE110_OPP_REG_DCP = 0,
DCE110_OPP_REG_DCFE,
DCE110_OPP_REG_FMT,
DCE110_OPP_REG_MAX
};
struct dce110_regamma {
struct gamma_curve arr_curve_points[16];
struct curve_points arr_points[3];
uint32_t hw_points_num;
struct hw_x_point *coordinates_x;
struct pwl_result_data *rgb_resulted;
/* re-gamma curve */
struct pwl_float_data_ex *rgb_regamma;
/* coeff used to map user evenly distributed points
* to our hardware points (predefined) for gamma 256 */
struct pixel_gamma_point *coeff128;
struct pixel_gamma_point *coeff128_oem;
/* coeff used to map user evenly distributed points
* to our hardware points (predefined) for gamma 1025 */
struct pixel_gamma_point *coeff128_dx;
/* evenly distributed points, gamma 256 software points 0-255 */
struct gamma_pixel *axis_x_256;
/* evenly distributed points, gamma 1025 software points 0-1025 */
struct gamma_pixel *axis_x_1025;
/* OEM supplied gamma for regamma LUT */
struct pwl_float_data *rgb_oem;
/* user supplied gamma */
struct pwl_float_data *rgb_user;
uint32_t extra_points;
bool use_half_points;
struct fixed31_32 x_max1;
struct fixed31_32 x_max2;
struct fixed31_32 x_min;
struct fixed31_32 divider1;
struct fixed31_32 divider2;
struct fixed31_32 divider3;
};
/* OPP RELATED */
#define TO_DCE110_OPP(opp)\
container_of(opp, struct dce110_opp, base)
struct dce110_opp_reg_offsets {
uint32_t fmt_offset;
uint32_t fmt_mem_offset;
uint32_t dcp_offset;
uint32_t dcfe_offset;
};
struct dce110_opp {
struct output_pixel_processor base;
struct dce110_opp_reg_offsets offsets;
struct dce110_regamma regamma;
};
bool dce110_opp_construct(struct dce110_opp *opp110,
struct dc_context *ctx,
uint32_t inst,
const struct dce110_opp_reg_offsets *offsets);
void dce110_opp_destroy(struct output_pixel_processor **opp);
/* REGAMMA RELATED */
void dce110_opp_power_on_regamma_lut(
struct output_pixel_processor *opp,
bool power_on);
bool dce110_opp_program_regamma_pwl(
struct output_pixel_processor *opp,
const struct pwl_params *params);
void dce110_opp_set_regamma_mode(struct output_pixel_processor *opp,
enum opp_regamma mode);
void dce110_opp_set_csc_adjustment(
struct output_pixel_processor *opp,
const struct out_csc_color_matrix *tbl_entry);
void dce110_opp_set_csc_default(
struct output_pixel_processor *opp,
const struct default_adjustment *default_adjust);
/* FORMATTER RELATED */
void dce110_opp_program_bit_depth_reduction(
struct output_pixel_processor *opp,
const struct bit_depth_reduction_params *params);
void dce110_opp_program_clamping_and_pixel_encoding(
struct output_pixel_processor *opp,
const struct clamping_and_pixel_encoding_params *params);
void dce110_opp_set_dyn_expansion(
struct output_pixel_processor *opp,
enum dc_color_space color_sp,
enum dc_color_depth color_dpth,
enum signal_type signal);
void dce110_opp_program_fmt(
struct output_pixel_processor *opp,
struct bit_depth_reduction_params *fmt_bit_depth,
struct clamping_and_pixel_encoding_params *clamping);
void dce110_opp_set_clamping(
struct dce110_opp *opp110,
const struct clamping_and_pixel_encoding_params *params);
#endif
drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc.c deleted 100644 → 0
View file @ e63d86dc
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#include "dm_services.h"
#include "dce110_opp.h"
#include "basics/conversion.h"
/* include DCE11 register header files */
#include "dce/dce_11_0_d.h"
#include "dce/dce_11_0_sh_mask.h"
#define DCP_REG(reg)\
(reg + opp110->offsets.dcp_offset)
enum {
OUTPUT_CSC_MATRIX_SIZE = 12
};
static const struct out_csc_color_matrix global_color_matrix[] = {
{ COLOR_SPACE_SRGB,
{ 0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0} },
{ COLOR_SPACE_SRGB_LIMITED,
{ 0x1B60, 0, 0, 0x200, 0, 0x1B60, 0, 0x200, 0, 0, 0x1B60, 0x200} },
{ COLOR_SPACE_YCBCR601,
{ 0xE00, 0xF447, 0xFDB9, 0x1000, 0x82F, 0x1012, 0x31F, 0x200, 0xFB47,
0xF6B9, 0xE00, 0x1000} },
{ COLOR_SPACE_YCBCR709, { 0xE00, 0xF349, 0xFEB7, 0x1000, 0x5D2, 0x1394, 0x1FA,
0x200, 0xFCCB, 0xF535, 0xE00, 0x1000} },
/* TODO: correct values below */
{ COLOR_SPACE_YCBCR601_LIMITED, { 0xE00, 0xF447, 0xFDB9, 0x1000, 0x991,
0x12C9, 0x3A6, 0x200, 0xFB47, 0xF6B9, 0xE00, 0x1000} },
{ COLOR_SPACE_YCBCR709_LIMITED, { 0xE00, 0xF349, 0xFEB7, 0x1000, 0x6CE, 0x16E3,
0x24F, 0x200, 0xFCCB, 0xF535, 0xE00, 0x1000} }
};
enum csc_color_mode {
/* 00 - BITS2:0 Bypass */
CSC_COLOR_MODE_GRAPHICS_BYPASS,
/* 01 - hard coded coefficient TV RGB */
CSC_COLOR_MODE_GRAPHICS_PREDEFINED,
/* 04 - programmable OUTPUT CSC coefficient */
CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC,
};
static void program_color_matrix(
struct dce110_opp *opp110,
const struct out_csc_color_matrix *tbl_entry,
enum grph_color_adjust_option options)
{
struct dc_context *ctx = opp110->base.ctx;
{
uint32_t value = 0;
uint32_t addr = DCP_REG(mmOUTPUT_CSC_C11_C12);
/* fixed S2.13 format */
set_reg_field_value(
value,
tbl_entry->regval[0],
OUTPUT_CSC_C11_C12,
OUTPUT_CSC_C11);
set_reg_field_value(
value,
tbl_entry->regval[1],
OUTPUT_CSC_C11_C12,
OUTPUT_CSC_C12);
dm_write_reg(ctx, addr, value);
}
{
uint32_t value = 0;
uint32_t addr = DCP_REG(mmOUTPUT_CSC_C13_C14);
/* fixed S2.13 format */
set_reg_field_value(
value,
tbl_entry->regval[2],
OUTPUT_CSC_C13_C14,
OUTPUT_CSC_C13);
/* fixed S0.13 format */
set_reg_field_value(
value,
tbl_entry->regval[3],
OUTPUT_CSC_C13_C14,
OUTPUT_CSC_C14);
dm_write_reg(ctx, addr, value);
}
{
uint32_t value = 0;
uint32_t addr = DCP_REG(mmOUTPUT_CSC_C21_C22);
/* fixed S2.13 format */
set_reg_field_value(
value,
tbl_entry->regval[4],
OUTPUT_CSC_C21_C22,
OUTPUT_CSC_C21);
/* fixed S2.13 format */
set_reg_field_value(
value,
tbl_entry->regval[5],
OUTPUT_CSC_C21_C22,
OUTPUT_CSC_C22);
dm_write_reg(ctx, addr, value);
}
{
uint32_t value = 0;
uint32_t addr = DCP_REG(mmOUTPUT_CSC_C23_C24);
/* fixed S2.13 format */
set_reg_field_value(
value,
tbl_entry->regval[6],
OUTPUT_CSC_C23_C24,
OUTPUT_CSC_C23);
/* fixed S0.13 format */
set_reg_field_value(
value,
tbl_entry->regval[7],
OUTPUT_CSC_C23_C24,
OUTPUT_CSC_C24);
dm_write_reg(ctx, addr, value);
}
{
uint32_t value = 0;
uint32_t addr = DCP_REG(mmOUTPUT_CSC_C31_C32);
/* fixed S2.13 format */
set_reg_field_value(
value,
tbl_entry->regval[8],
OUTPUT_CSC_C31_C32,
OUTPUT_CSC_C31);
/* fixed S0.13 format */
set_reg_field_value(
value,
tbl_entry->regval[9],
OUTPUT_CSC_C31_C32,
OUTPUT_CSC_C32);
dm_write_reg(ctx, addr, value);
}
{
uint32_t value = 0;
uint32_t addr = DCP_REG(mmOUTPUT_CSC_C33_C34);
/* fixed S2.13 format */
set_reg_field_value(
value,
tbl_entry->regval[10],
OUTPUT_CSC_C33_C34,
OUTPUT_CSC_C33);
/* fixed S0.13 format */
set_reg_field_value(
value,
tbl_entry->regval[11],
OUTPUT_CSC_C33_C34,
OUTPUT_CSC_C34);
dm_write_reg(ctx, addr, value);
}
}
static bool configure_graphics_mode(
struct dce110_opp *opp110,
enum csc_color_mode config,
enum graphics_csc_adjust_type csc_adjust_type,
enum dc_color_space color_space)
{
struct dc_context *ctx = opp110->base.ctx;
uint32_t addr = DCP_REG(mmOUTPUT_CSC_CONTROL);
uint32_t value = dm_read_reg(ctx, addr);
set_reg_field_value(
value,
0,
OUTPUT_CSC_CONTROL,
OUTPUT_CSC_GRPH_MODE);
if (csc_adjust_type == GRAPHICS_CSC_ADJUST_TYPE_SW) {
if (config == CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC) {
set_reg_field_value(
value,
4,
OUTPUT_CSC_CONTROL,
OUTPUT_CSC_GRPH_MODE);
} else {
switch (color_space) {
case COLOR_SPACE_SRGB:
/* by pass */
set_reg_field_value(
value,
0,
OUTPUT_CSC_CONTROL,
OUTPUT_CSC_GRPH_MODE);
break;
case COLOR_SPACE_SRGB_LIMITED:
/* TV RGB */
set_reg_field_value(
value,
1,
OUTPUT_CSC_CONTROL,
OUTPUT_CSC_GRPH_MODE);
break;
case COLOR_SPACE_YCBCR601:
case COLOR_SPACE_YPBPR601:
case COLOR_SPACE_YCBCR601_LIMITED:
/* YCbCr601 */
set_reg_field_value(
value,
2,
OUTPUT_CSC_CONTROL,
OUTPUT_CSC_GRPH_MODE);
break;
case COLOR_SPACE_YCBCR709:
case COLOR_SPACE_YPBPR709:
case COLOR_SPACE_YCBCR709_LIMITED:
/* YCbCr709 */
set_reg_field_value(
value,
3,
OUTPUT_CSC_CONTROL,
OUTPUT_CSC_GRPH_MODE);
break;
default:
return false;
}
}
} else if (csc_adjust_type == GRAPHICS_CSC_ADJUST_TYPE_HW) {
switch (color_space) {
case COLOR_SPACE_SRGB:
/* by pass */
set_reg_field_value(
value,
0,
OUTPUT_CSC_CONTROL,
OUTPUT_CSC_GRPH_MODE);
break;
case COLOR_SPACE_SRGB_LIMITED:
/* TV RGB */
set_reg_field_value(
value,
1,
OUTPUT_CSC_CONTROL,
OUTPUT_CSC_GRPH_MODE);
break;
case COLOR_SPACE_YCBCR601:
case COLOR_SPACE_YPBPR601:
case COLOR_SPACE_YCBCR601_LIMITED:
/* YCbCr601 */
set_reg_field_value(
value,
2,
OUTPUT_CSC_CONTROL,
OUTPUT_CSC_GRPH_MODE);
break;
case COLOR_SPACE_YCBCR709:
case COLOR_SPACE_YPBPR709:
case COLOR_SPACE_YCBCR709_LIMITED:
/* YCbCr709 */
set_reg_field_value(
value,
3,
OUTPUT_CSC_CONTROL,
OUTPUT_CSC_GRPH_MODE);
break;
default:
return false;
}
} else
/* by pass */
set_reg_field_value(
value,
0,
OUTPUT_CSC_CONTROL,
OUTPUT_CSC_GRPH_MODE);
addr = DCP_REG(mmOUTPUT_CSC_CONTROL);
dm_write_reg(ctx, addr, value);
return true;
}
void dce110_opp_set_csc_adjustment(
struct output_pixel_processor *opp,
const struct out_csc_color_matrix *tbl_entry)
{
struct dce110_opp *opp110 = TO_DCE110_OPP(opp);
enum csc_color_mode config =
CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC;
program_color_matrix(
opp110, tbl_entry, GRAPHICS_CSC_ADJUST_TYPE_SW);
/* We did everything ,now program DxOUTPUT_CSC_CONTROL */
configure_graphics_mode(opp110, config, GRAPHICS_CSC_ADJUST_TYPE_SW,
tbl_entry->color_space);
}
void dce110_opp_set_csc_default(
struct output_pixel_processor *opp,
const struct default_adjustment *default_adjust)
{
struct dce110_opp *opp110 = TO_DCE110_OPP(opp);
enum csc_color_mode config =
CSC_COLOR_MODE_GRAPHICS_PREDEFINED;
if (default_adjust->force_hw_default == false) {
const struct out_csc_color_matrix *elm;
/* currently parameter not in use */
enum grph_color_adjust_option option =
GRPH_COLOR_MATRIX_HW_DEFAULT;
uint32_t i;
/*
* HW default false we program locally defined matrix
* HW default true we use predefined hw matrix and we
* do not need to program matrix
* OEM wants the HW default via runtime parameter.
*/
option = GRPH_COLOR_MATRIX_SW;
for (i = 0; i < ARRAY_SIZE(global_color_matrix); ++i) {
elm = &global_color_matrix[i];
if (elm->color_space != default_adjust->out_color_space)
continue;
/* program the matrix with default values from this
* file */
program_color_matrix(opp110, elm, option);
config = CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC;
break;
}
}
/* configure the what we programmed :
* 1. Default values from this file
* 2. Use hardware default from ROM_A and we do not need to program
* matrix */
configure_graphics_mode(opp110, config,
default_adjust->csc_adjust_type,
default_adjust->out_color_space);
}
drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c
View file @ ab3ee7a5
......@@ -24,7 +24,7 @@
*/
#include "dm_services.h"
#include "dce110_opp.h"
#include "dce/dce_opp.h"
#include "basics/conversion.h"
/* include DCE11 register header files */
......
drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c
View file @ ab3ee7a5
......@@ -29,7 +29,7 @@
#include "dce/dce_11_0_d.h"
#include "dce/dce_11_0_sh_mask.h"
#include "dce110_opp.h"
#include "dce/dce_opp.h"
#include "gamma_types.h"
static void power_on_lut(struct output_pixel_processor *opp,
......
drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.c
View file @ ab3ee7a5
......@@ -29,7 +29,7 @@
#include "dce/dce_11_0_d.h"
#include "dce/dce_11_0_sh_mask.h"
#include "dce110_opp.h"
#include "dce/dce_opp.h"
#include "dce110_opp_v.h"
#include "gamma_types.h"
......
drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
View file @ ab3ee7a5
......@@ -43,7 +43,7 @@
#include "dce110/dce110_ipp.h"
#include "dce/dce_transform.h"
#include "dce110/dce110_transform_v.h"
#include "dce110/dce110_opp.h"
#include "dce/dce_opp.h"
#include "dce110/dce110_opp_v.h"
#include "dce/dce_clocks.h"
#include "dce/dce_clock_source.h"
......@@ -283,6 +283,28 @@ static const struct dce_stream_encoder_mask se_mask = {
SE_COMMON_MASK_SH_LIST_DCE110(_MASK)
};
#define opp_regs(id)\
[id] = {\
OPP_DCE_110_REG_LIST(id),\
}
static const struct dce_opp_registers opp_regs[] = {
opp_regs(0),
opp_regs(1),
opp_regs(2),
opp_regs(3),
opp_regs(4),
opp_regs(5)
};
static const struct dce_opp_shift opp_shift = {
OPP_COMMON_MASK_SH_LIST_DCE_110(__SHIFT)
};
static const struct dce_opp_mask opp_mask = {
OPP_COMMON_MASK_SH_LIST_DCE_110(_MASK)
};
#define audio_regs(id)\
[id] = {\
AUD_COMMON_REG_LIST(id)\
......@@ -307,34 +329,7 @@ static const struct dce_aduio_mask audio_mask = {
};
/* AG TBD Needs to be reduced back to 3 pipes once dce10 hw sequencer implemented. */
static const struct dce110_opp_reg_offsets dce110_opp_reg_offsets[] = {
{
.fmt_offset = (mmFMT0_FMT_CONTROL - mmFMT0_FMT_CONTROL),
.dcfe_offset = (mmDCFE0_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL),
.dcp_offset = (mmDCP0_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
},
{ .fmt_offset = (mmFMT1_FMT_CONTROL - mmFMT0_FMT_CONTROL),
.dcfe_offset = (mmDCFE1_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL),
.dcp_offset = (mmDCP1_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
},
{ .fmt_offset = (mmFMT2_FMT_CONTROL - mmFMT0_FMT_CONTROL),
.dcfe_offset = (mmDCFE2_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL),
.dcp_offset = (mmDCP2_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
},
{
.fmt_offset = (mmFMT3_FMT_CONTROL - mmFMT0_FMT_CONTROL),
.dcfe_offset = (mmDCFE3_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL),
.dcp_offset = (mmDCP3_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
},
{ .fmt_offset = (mmFMT4_FMT_CONTROL - mmFMT0_FMT_CONTROL),
.dcfe_offset = (mmDCFE4_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL),
.dcp_offset = (mmDCP4_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
},
{ .fmt_offset = (mmFMT5_FMT_CONTROL - mmFMT0_FMT_CONTROL),
.dcfe_offset = (mmDCFE5_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL),
.dcp_offset = (mmDCP5_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
}
};
#define clk_src_regs(id)\
[id] = {\
......@@ -603,8 +598,7 @@ struct link_encoder *dce110_link_encoder_create(
static struct output_pixel_processor *dce110_opp_create(
struct dc_context *ctx,
uint32_t inst,
const struct dce110_opp_reg_offsets *offsets)
uint32_t inst)
{
struct dce110_opp *opp =
dm_alloc(sizeof(struct dce110_opp));
......@@ -613,7 +607,7 @@ static struct output_pixel_processor *dce110_opp_create(
return NULL;
if (dce110_opp_construct(opp,
ctx, inst, offsets))
ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask))
return &opp->base;
BREAK_TO_DEBUGGER();
......@@ -1329,7 +1323,7 @@ static bool construct(
goto res_create_fail;
}
pool->base.opps[i] = dce110_opp_create(ctx, i, &dce110_opp_reg_offsets[i]);
pool->base.opps[i] = dce110_opp_create(ctx, i);
if (pool->base.opps[i] == NULL) {
BREAK_TO_DEBUGGER();
dm_error(
......
drivers/gpu/drm/amd/display/dc/dce112/Makefile
View file @ ab3ee7a5
......@@ -3,8 +3,7 @@
# It provides the control and status of HW CRTC block.
DCE112 = dce112_compressor.o dce112_hw_sequencer.o \
dce112_resource.o dce112_mem_input.o dce112_opp_formatter.o \
dce112_opp.o
dce112_resource.o dce112_mem_input.o
AMD_DAL_DCE112 = $(addprefix $(AMDDALPATH)/dc/dce112/,$(DCE112))
......
drivers/gpu/drm/amd/display/dc/dce112/dce112_opp.c deleted 100644 → 0
View file @ e63d86dc
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#include "dm_services.h"
/* include DCE11 register header files */
#include "dce/dce_11_2_d.h"
#include "dce/dce_11_2_sh_mask.h"
#include "dce112_opp.h"
#include "gamma_types.h"
enum {
MAX_LUT_ENTRY = 256,
MAX_NUMBER_OF_ENTRIES = 256
};
/*****************************************/
/* Constructor, Destructor */
/*****************************************/
static struct opp_funcs funcs = {
.opp_power_on_regamma_lut = dce110_opp_power_on_regamma_lut,
.opp_set_csc_adjustment = dce110_opp_set_csc_adjustment,
.opp_set_csc_default = dce110_opp_set_csc_default,
.opp_set_dyn_expansion = dce110_opp_set_dyn_expansion,
.opp_program_regamma_pwl = dce110_opp_program_regamma_pwl,
.opp_set_regamma_mode = dce110_opp_set_regamma_mode,
.opp_destroy = dce110_opp_destroy,
.opp_program_fmt = dce112_opp_program_fmt,
.opp_program_bit_depth_reduction =
dce110_opp_program_bit_depth_reduction
};
bool dce112_opp_construct(struct dce110_opp *opp110,
struct dc_context *ctx,
uint32_t inst,
const struct dce110_opp_reg_offsets *offsets)
{
opp110->base.funcs = &funcs;
opp110->base.ctx = ctx;
opp110->base.inst = inst;
opp110->offsets = *offsets;
return true;
}
drivers/gpu/drm/amd/display/dc/dce112/dce112_opp.h deleted 100644 → 0
View file @ e63d86dc
/* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DC_OPP_DCE112_H__
#define __DC_OPP_DCE112_H__
#include "dc_types.h"
#include "opp.h"
#include "../dce110/dce110_opp.h"
#include "core_types.h"
void dce112_opp_program_clamping_and_pixel_encoding(
struct output_pixel_processor *opp,
const struct clamping_and_pixel_encoding_params *params);
void dce112_opp_program_fmt(
struct output_pixel_processor *opp,
struct bit_depth_reduction_params *fmt_bit_depth,
struct clamping_and_pixel_encoding_params *clamping);
bool dce112_opp_construct(struct dce110_opp *opp110,
struct dc_context *ctx,
uint32_t inst,
const struct dce110_opp_reg_offsets *offsets);
#endif
drivers/gpu/drm/amd/display/dc/dce112/dce112_opp_formatter.c deleted 100644 → 0
View file @ e63d86dc
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#include "dm_services.h"
#include "dce/dce_11_2_d.h"
#include "dce/dce_11_2_sh_mask.h"
#include "dce112_opp.h"
#define FMT_REG(reg)\
(reg + opp110->offsets.fmt_offset)
#define FMT_MEM_REG(reg)\
(reg + opp110->offsets.fmt_mem_offset)
/**
* Set Clamping
* 1) Set clamping format based on bpc - 0 for 6bpc (No clamping)
* 1 for 8 bpc
* 2 for 10 bpc
* 3 for 12 bpc
* 7 for programable
* 2) Enable clamp if Limited range requested
*/
/**
* set_pixel_encoding
*
* Set Pixel Encoding
* 0: RGB 4:4:4 or YCbCr 4:4:4 or YOnly
* 1: YCbCr 4:2:2
* 2: YCbCr 4:2:0
*/
static void set_pixel_encoding(
struct dce110_opp *opp110,
const struct clamping_and_pixel_encoding_params *params)
{
uint32_t fmt_cntl_value;
uint32_t addr = FMT_REG(mmFMT_CONTROL);
/*RGB 4:4:4 or YCbCr 4:4:4 - 0; YCbCr 4:2:2 -1.*/
fmt_cntl_value = dm_read_reg(opp110->base.ctx, addr);
set_reg_field_value(fmt_cntl_value,
0,
FMT_CONTROL,
FMT_PIXEL_ENCODING);
/*00 - Pixels drop mode HW default*/
set_reg_field_value(fmt_cntl_value,
0,
FMT_CONTROL,
FMT_SUBSAMPLING_MODE);
/* By default no bypass*/
set_reg_field_value(fmt_cntl_value,
0,
FMT_CONTROL,
FMT_CBCR_BIT_REDUCTION_BYPASS);
if (params->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
set_reg_field_value(fmt_cntl_value,
1,
FMT_CONTROL,
FMT_PIXEL_ENCODING);
/*00 - Cb before Cr ,01 - Cr before Cb*/
set_reg_field_value(fmt_cntl_value,
0,
FMT_CONTROL,
FMT_SUBSAMPLING_ORDER);
}
if (params->pixel_encoding == PIXEL_ENCODING_YCBCR420) {
set_reg_field_value(fmt_cntl_value,
2,
FMT_CONTROL,
FMT_PIXEL_ENCODING);
/* 02 - Subsampling mode, 3 taps*/
set_reg_field_value(fmt_cntl_value,
2,
FMT_CONTROL,
FMT_SUBSAMPLING_MODE);
/* 00 - Enable CbCr bit reduction bypass to preserve precision*/
set_reg_field_value(fmt_cntl_value,
1,
FMT_CONTROL,
FMT_CBCR_BIT_REDUCTION_BYPASS);
}
dm_write_reg(opp110->base.ctx, addr, fmt_cntl_value);
}
void dce112_opp_program_clamping_and_pixel_encoding(
struct output_pixel_processor *opp,
const struct clamping_and_pixel_encoding_params *params)
{
struct dce110_opp *opp110 = TO_DCE110_OPP(opp);
dce110_opp_set_clamping(opp110, params);
set_pixel_encoding(opp110, params);
}
static void program_formatter_420_memory(struct output_pixel_processor *opp)
{
struct dce110_opp *opp110 = TO_DCE110_OPP(opp);
uint32_t fmt_cntl_value;
uint32_t fmt_mem_cntl_value;
uint32_t fmt_cntl_addr = FMT_REG(mmFMT_CONTROL);
uint32_t fmt_mem_cntl_addr = FMT_MEM_REG(mmFMT_MEMORY0_CONTROL);
fmt_mem_cntl_value = dm_read_reg(opp110->base.ctx, fmt_mem_cntl_addr);
fmt_cntl_value = dm_read_reg(opp110->base.ctx, fmt_cntl_addr);
/* Program source select*/
/* Use HW default source select for FMT_MEMORYx_CONTROL */
/* Use that value for FMT_SRC_SELECT as well*/
set_reg_field_value(fmt_cntl_value,
get_reg_field_value(fmt_mem_cntl_value, FMT_MEMORY0_CONTROL, FMT420_MEM0_SOURCE_SEL),
FMT_CONTROL,
FMT_SRC_SELECT);
dm_write_reg(opp110->base.ctx, fmt_cntl_addr, fmt_cntl_value);
/* Turn on the memory */
set_reg_field_value(fmt_mem_cntl_value,
0,
FMT_MEMORY0_CONTROL,
FMT420_MEM0_PWR_FORCE);
dm_write_reg(opp110->base.ctx, fmt_mem_cntl_addr, fmt_mem_cntl_value);
}
static void program_formatter_reset_dig_resync_fifo(struct output_pixel_processor *opp)
{
struct dce110_opp *opp110 = TO_DCE110_OPP(opp);
uint32_t value;
uint32_t addr = FMT_REG(mmFMT_CONTROL);
uint8_t counter = 10;
value = dm_read_reg(opp110->base.ctx, addr);
/* clear previous phase lock status*/
set_reg_field_value(value,
1,
FMT_CONTROL,
FMT_420_PIXEL_PHASE_LOCKED_CLEAR);
dm_write_reg(opp110->base.ctx, addr, value);
/* poll until FMT_420_PIXEL_PHASE_LOCKED become 1*/
while (counter > 0) {
value = dm_read_reg(opp110->base.ctx, addr);
if (get_reg_field_value(
value,
FMT_CONTROL,
FMT_420_PIXEL_PHASE_LOCKED) == 1)
break;
msleep(10);
counter--;
}
if (counter == 0)
dm_logger_write(opp->ctx->logger, LOG_ERROR,
"%s:opp program formattter reset dig resync info time out.\n",
__func__);
}
void dce112_opp_program_fmt(
struct output_pixel_processor *opp,
struct bit_depth_reduction_params *fmt_bit_depth,
struct clamping_and_pixel_encoding_params *clamping)
{
/* dithering is affected by <CrtcSourceSelect>, hence should be
* programmed afterwards */
if (clamping->pixel_encoding == PIXEL_ENCODING_YCBCR420)
program_formatter_420_memory(opp);
dce110_opp_program_bit_depth_reduction(
opp,
fmt_bit_depth);
dce112_opp_program_clamping_and_pixel_encoding(
opp,
clamping);
if (clamping->pixel_encoding == PIXEL_ENCODING_YCBCR420)
program_formatter_reset_dig_resync_fifo(opp);
return;
}
drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
View file @ ab3ee7a5
......@@ -39,7 +39,7 @@
#include "dce/dce_link_encoder.h"
#include "dce/dce_stream_encoder.h"
#include "dce/dce_audio.h"
#include "dce112/dce112_opp.h"
#include "dce/dce_opp.h"
#include "dce110/dce110_ipp.h"
#include "dce/dce_clocks.h"
#include "dce/dce_clock_source.h"
......@@ -306,6 +306,28 @@ static const struct dce_stream_encoder_mask se_mask = {
SE_COMMON_MASK_SH_LIST_DCE112(_MASK)
};
#define opp_regs(id)\
[id] = {\
OPP_DCE_112_REG_LIST(id),\
}
static const struct dce_opp_registers opp_regs[] = {
opp_regs(0),
opp_regs(1),
opp_regs(2),
opp_regs(3),
opp_regs(4),
opp_regs(5)
};
static const struct dce_opp_shift opp_shift = {
OPP_COMMON_MASK_SH_LIST_DCE_112(__SHIFT)
};
static const struct dce_opp_mask opp_mask = {
OPP_COMMON_MASK_SH_LIST_DCE_112(_MASK)
};
#define audio_regs(id)\
[id] = {\
AUD_COMMON_REG_LIST(id)\
......@@ -328,42 +350,6 @@ static const struct dce_aduio_mask audio_mask = {
AUD_COMMON_MASK_SH_LIST(_MASK)
};
static const struct dce110_opp_reg_offsets dce112_opp_reg_offsets[] = {
{
.fmt_offset = (mmFMT0_FMT_CONTROL - mmFMT0_FMT_CONTROL),
.fmt_mem_offset = (mmFMT_MEMORY0_CONTROL - mmFMT_MEMORY0_CONTROL),
.dcfe_offset = (mmDCFE0_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL),
.dcp_offset = (mmDCP0_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
},
{ .fmt_offset = (mmFMT1_FMT_CONTROL - mmFMT0_FMT_CONTROL),
.fmt_mem_offset = (mmFMT_MEMORY1_CONTROL - mmFMT_MEMORY0_CONTROL),
.dcfe_offset = (mmDCFE1_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL),
.dcp_offset = (mmDCP1_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
},
{ .fmt_offset = (mmFMT2_FMT_CONTROL - mmFMT0_FMT_CONTROL),
.fmt_mem_offset = (mmFMT_MEMORY2_CONTROL - mmFMT_MEMORY0_CONTROL),
.dcfe_offset = (mmDCFE2_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL),
.dcp_offset = (mmDCP2_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
},
{
.fmt_offset = (mmFMT3_FMT_CONTROL - mmFMT0_FMT_CONTROL),
.fmt_mem_offset = (mmFMT_MEMORY3_CONTROL - mmFMT_MEMORY0_CONTROL),
.dcfe_offset = (mmDCFE3_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL),
.dcp_offset = (mmDCP3_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
},
{ .fmt_offset = (mmFMT4_FMT_CONTROL - mmFMT0_FMT_CONTROL),
.fmt_mem_offset = (mmFMT_MEMORY4_CONTROL - mmFMT_MEMORY0_CONTROL),
.dcfe_offset = (mmDCFE4_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL),
.dcp_offset = (mmDCP4_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
},
{ .fmt_offset = (mmFMT5_FMT_CONTROL - mmFMT0_FMT_CONTROL),
.fmt_mem_offset = (mmFMT_MEMORY5_CONTROL - mmFMT_MEMORY0_CONTROL),
.dcfe_offset = (mmDCFE5_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL),
.dcp_offset = (mmDCP5_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
}
};
#define clk_src_regs(index, id)\
[index] = {\
CS_COMMON_REG_LIST_DCE_112(id),\
......@@ -631,8 +617,7 @@ void dce112_ipp_destroy(struct input_pixel_processor **ipp)
struct output_pixel_processor *dce112_opp_create(
struct dc_context *ctx,
uint32_t inst,
const struct dce110_opp_reg_offsets *offset)
uint32_t inst)
{
struct dce110_opp *opp =
dm_alloc(sizeof(struct dce110_opp));
......@@ -640,8 +625,8 @@ struct output_pixel_processor *dce112_opp_create(
if (!opp)
return NULL;
if (dce112_opp_construct(opp,
ctx, inst, offset))
if (dce110_opp_construct(opp,
ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask))
return &opp->base;
BREAK_TO_DEBUGGER();
......@@ -1381,8 +1366,7 @@ static bool construct(
pool->base.opps[i] = dce112_opp_create(
ctx,
i,
&dce112_opp_reg_offsets[i]);
i);
if (pool->base.opps[i] == NULL) {
BREAK_TO_DEBUGGER();
dm_error(
......
drivers/gpu/drm/amd/display/dc/dce80/Makefile
View file @ ab3ee7a5
......@@ -2,9 +2,8 @@
# Makefile for the 'controller' sub-component of DAL.
# It provides the control and status of HW CRTC block.
DCE80 = dce80_ipp.o dce80_ipp_gamma.o dce80_opp.o \
dce80_opp_formatter.o dce80_opp_regamma.o \
dce80_timing_generator.o dce80_opp_csc.o\
DCE80 = dce80_ipp.o dce80_ipp_gamma.o \
dce80_timing_generator.o \
dce80_compressor.o dce80_mem_input.o dce80_hw_sequencer.o \
dce80_resource.o
......
drivers/gpu/drm/amd/display/dc/dce80/dce80_opp.c deleted 100644 → 0
View file @ e63d86dc
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#include "dm_services.h"
/* include DCE8 register header files */
#include "dce/dce_8_0_d.h"
#include "dce/dce_8_0_sh_mask.h"
#include "dce80_opp.h"
#define FROM_OPP(opp)\
container_of(opp, struct dce80_opp, base)
enum {
MAX_LUT_ENTRY = 256,
MAX_NUMBER_OF_ENTRIES = 256
};
static const struct dce80_opp_reg_offsets reg_offsets[] = {
{
.fmt_offset = (mmFMT0_FMT_CONTROL - mmFMT0_FMT_CONTROL),
.crtc_offset = (mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL -
mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
.dcp_offset = (mmDCP0_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
},
{ .fmt_offset = (mmFMT1_FMT_CONTROL - mmFMT0_FMT_CONTROL),
.crtc_offset = (mmCRTC1_DCFE_MEM_LIGHT_SLEEP_CNTL -
mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
.dcp_offset = (mmDCP1_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
},
{ .fmt_offset = (mmFMT2_FMT_CONTROL - mmFMT0_FMT_CONTROL),
.crtc_offset = (mmCRTC2_DCFE_MEM_LIGHT_SLEEP_CNTL -
mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
.dcp_offset = (mmDCP2_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
},
{
.fmt_offset = (mmFMT3_FMT_CONTROL - mmFMT0_FMT_CONTROL),
.crtc_offset = (mmCRTC3_DCFE_MEM_LIGHT_SLEEP_CNTL -
mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
.dcp_offset = (mmDCP3_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
},
{
.fmt_offset = (mmFMT4_FMT_CONTROL - mmFMT0_FMT_CONTROL),
.crtc_offset = (mmCRTC4_DCFE_MEM_LIGHT_SLEEP_CNTL -
mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
.dcp_offset = (mmDCP4_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
},
{
.fmt_offset = (mmFMT5_FMT_CONTROL - mmFMT0_FMT_CONTROL),
.crtc_offset = (mmCRTC5_DCFE_MEM_LIGHT_SLEEP_CNTL -
mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
.dcp_offset = (mmDCP5_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
}
};
static const struct opp_funcs funcs = {
.opp_power_on_regamma_lut = dce80_opp_power_on_regamma_lut,
.opp_set_csc_adjustment = dce80_opp_set_csc_adjustment,
.opp_set_csc_default = dce80_opp_set_csc_default,
.opp_set_dyn_expansion = dce80_opp_set_dyn_expansion,
.opp_program_regamma_pwl = dce80_opp_program_regamma_pwl,
.opp_set_regamma_mode = dce80_opp_set_regamma_mode,
.opp_destroy = dce80_opp_destroy,
.opp_program_fmt = dce110_opp_program_fmt,
};
/*****************************************/
/* Constructor, Destructor */
/*****************************************/
bool dce80_opp_construct(struct dce80_opp *opp80,
struct dc_context *ctx,
uint32_t inst)
{
if (inst >= ARRAY_SIZE(reg_offsets))
return false;
opp80->base.funcs = &funcs;
opp80->base.ctx = ctx;
opp80->base.inst = inst;
opp80->offsets = reg_offsets[inst];
return true;
}
void dce80_opp_destroy(struct output_pixel_processor **opp)
{
dm_free(FROM_OPP(*opp));
*opp = NULL;
}
struct output_pixel_processor *dce80_opp_create(
struct dc_context *ctx,
uint32_t inst)
{
struct dce80_opp *opp =
dm_alloc(sizeof(struct dce80_opp));
if (!opp)
return NULL;
if (dce80_opp_construct(opp,
ctx, inst))
return &opp->base;
BREAK_TO_DEBUGGER();
dm_free(opp);
return NULL;
}
drivers/gpu/drm/amd/display/dc/dce80/dce80_opp.h deleted 100644 → 0
View file @ e63d86dc
/* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DC_OPP_DCE80_H__
#define __DC_OPP_DCE80_H__
#include "dc_types.h"
#include "opp.h"
#include "gamma_types.h"
#include "../dce110/dce110_opp.h"
struct gamma_parameters;
struct dce80_regamma {
struct gamma_curve arr_curve_points[16];
struct curve_points arr_points[3];
uint32_t hw_points_num;
struct hw_x_point *coordinates_x;
struct pwl_result_data *rgb_resulted;
/* re-gamma curve */
struct pwl_float_data_ex *rgb_regamma;
/* coeff used to map user evenly distributed points
* to our hardware points (predefined) for gamma 256 */
struct pixel_gamma_point *coeff128;
struct pixel_gamma_point *coeff128_oem;
/* coeff used to map user evenly distributed points
* to our hardware points (predefined) for gamma 1025 */
struct pixel_gamma_point *coeff128_dx;
/* evenly distributed points, gamma 256 software points 0-255 */
struct gamma_pixel *axis_x_256;
/* evenly distributed points, gamma 1025 software points 0-1025 */
struct gamma_pixel *axis_x_1025;
/* OEM supplied gamma for regamma LUT */
struct pwl_float_data *rgb_oem;
/* user supplied gamma */
struct pwl_float_data *rgb_user;
uint32_t extra_points;
bool use_half_points;
struct fixed31_32 x_max1;
struct fixed31_32 x_max2;
struct fixed31_32 x_min;
struct fixed31_32 divider1;
struct fixed31_32 divider2;
struct fixed31_32 divider3;
};
/* OPP RELATED */
#define TO_DCE80_OPP(opp)\
container_of(opp, struct dce80_opp, base)
struct dce80_opp_reg_offsets {
uint32_t fmt_offset;
uint32_t dcp_offset;
uint32_t crtc_offset;
};
struct dce80_opp {
struct output_pixel_processor base;
struct dce80_opp_reg_offsets offsets;
struct dce80_regamma regamma;
};
bool dce80_opp_construct(struct dce80_opp *opp80,
struct dc_context *ctx,
uint32_t inst);
void dce80_opp_destroy(struct output_pixel_processor **opp);
struct output_pixel_processor *dce80_opp_create(
struct dc_context *ctx,
uint32_t inst);
/* REGAMMA RELATED */
void dce80_opp_power_on_regamma_lut(
struct output_pixel_processor *opp,
bool power_on);
bool dce80_opp_program_regamma_pwl(
struct output_pixel_processor *opp,
const struct pwl_params *pamras);
void dce80_opp_set_regamma_mode(struct output_pixel_processor *opp,
enum opp_regamma mode);
void dce80_opp_set_csc_adjustment(
struct output_pixel_processor *opp,
const struct out_csc_color_matrix *tbl_entry);
void dce80_opp_set_csc_default(
struct output_pixel_processor *opp,
const struct default_adjustment *default_adjust);
/* FORMATTER RELATED */
void dce80_opp_program_bit_depth_reduction(
struct output_pixel_processor *opp,
const struct bit_depth_reduction_params *params);
void dce80_opp_program_clamping_and_pixel_encoding(
struct output_pixel_processor *opp,
const struct clamping_and_pixel_encoding_params *params);
void dce80_opp_set_dyn_expansion(
struct output_pixel_processor *opp,
enum dc_color_space color_sp,
enum dc_color_depth color_dpth,
enum signal_type signal);
#endif
drivers/gpu/drm/amd/display/dc/dce80/dce80_opp_csc.c deleted 100644 → 0
View file @ e63d86dc
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#include "dm_services.h"
#include "dce80_opp.h"
#include "basics/conversion.h"
/* include DCE8 register header files */
#include "dce/dce_8_0_d.h"
#include "dce/dce_8_0_sh_mask.h"
#define DCP_REG(reg)\
(reg + opp80->offsets.dcp_offset)
enum {
OUTPUT_CSC_MATRIX_SIZE = 12
};
static const struct out_csc_color_matrix global_color_matrix[] = {
{ COLOR_SPACE_SRGB,
{ 0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0} },
{ COLOR_SPACE_SRGB_LIMITED,
{ 0x1B60, 0, 0, 0x200, 0, 0x1B60, 0, 0x200, 0, 0, 0x1B60, 0x200} },
{ COLOR_SPACE_YCBCR601,
{ 0xE00, 0xF447, 0xFDB9, 0x1000, 0x82F, 0x1012, 0x31F, 0x200, 0xFB47,
0xF6B9, 0xE00, 0x1000} },
{ COLOR_SPACE_YCBCR709, { 0xE00, 0xF349, 0xFEB7, 0x1000, 0x5D2, 0x1394, 0x1FA,
0x200, 0xFCCB, 0xF535, 0xE00, 0x1000} },
/* TODO: correct values below */
{ COLOR_SPACE_YCBCR601_LIMITED, { 0xE00, 0xF447, 0xFDB9, 0x1000, 0x991,
0x12C9, 0x3A6, 0x200, 0xFB47, 0xF6B9, 0xE00, 0x1000} },
{ COLOR_SPACE_YCBCR709_LIMITED, { 0xE00, 0xF349, 0xFEB7, 0x1000, 0x6CE, 0x16E3,
0x24F, 0x200, 0xFCCB, 0xF535, 0xE00, 0x1000} }
};
enum csc_color_mode {
/* 00 - BITS2:0 Bypass */
CSC_COLOR_MODE_GRAPHICS_BYPASS,
/* 01 - hard coded coefficient TV RGB */
CSC_COLOR_MODE_GRAPHICS_PREDEFINED,
/* 04 - programmable OUTPUT CSC coefficient */
CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC,
};
static void program_color_matrix(
struct dce80_opp *opp80,
const struct out_csc_color_matrix *tbl_entry,
enum grph_color_adjust_option options)
{
struct dc_context *ctx = opp80->base.ctx;
{
uint32_t value = 0;
uint32_t addr = DCP_REG(mmOUTPUT_CSC_C11_C12);
/* fixed S2.13 format */
set_reg_field_value(
value,
tbl_entry->regval[0],
OUTPUT_CSC_C11_C12,
OUTPUT_CSC_C11);
set_reg_field_value(
value,
tbl_entry->regval[1],
OUTPUT_CSC_C11_C12,
OUTPUT_CSC_C12);
dm_write_reg(ctx, addr, value);
}
{
uint32_t value = 0;
uint32_t addr = DCP_REG(mmOUTPUT_CSC_C13_C14);
/* fixed S2.13 format */
set_reg_field_value(
value,
tbl_entry->regval[2],
OUTPUT_CSC_C13_C14,
OUTPUT_CSC_C13);
/* fixed S0.13 format */
set_reg_field_value(
value,
tbl_entry->regval[3],
OUTPUT_CSC_C13_C14,
OUTPUT_CSC_C14);
dm_write_reg(ctx, addr, value);
}
{
uint32_t value = 0;
uint32_t addr = DCP_REG(mmOUTPUT_CSC_C21_C22);
/* fixed S2.13 format */
set_reg_field_value(
value,
tbl_entry->regval[4],
OUTPUT_CSC_C21_C22,
OUTPUT_CSC_C21);
/* fixed S2.13 format */
set_reg_field_value(
value,
tbl_entry->regval[5],
OUTPUT_CSC_C21_C22,
OUTPUT_CSC_C22);
dm_write_reg(ctx, addr, value);
}
{
uint32_t value = 0;
uint32_t addr = DCP_REG(mmOUTPUT_CSC_C23_C24);
/* fixed S2.13 format */
set_reg_field_value(
value,
tbl_entry->regval[6],
OUTPUT_CSC_C23_C24,
OUTPUT_CSC_C23);
/* fixed S0.13 format */
set_reg_field_value(
value,
tbl_entry->regval[7],
OUTPUT_CSC_C23_C24,
OUTPUT_CSC_C24);
dm_write_reg(ctx, addr, value);
}
{
uint32_t value = 0;
uint32_t addr = DCP_REG(mmOUTPUT_CSC_C31_C32);
/* fixed S2.13 format */
set_reg_field_value(
value,
tbl_entry->regval[8],
OUTPUT_CSC_C31_C32,
OUTPUT_CSC_C31);
/* fixed S0.13 format */
set_reg_field_value(
value,
tbl_entry->regval[9],
OUTPUT_CSC_C31_C32,
OUTPUT_CSC_C32);
dm_write_reg(ctx, addr, value);
}
{
uint32_t value = 0;
uint32_t addr = DCP_REG(mmOUTPUT_CSC_C33_C34);
/* fixed S2.13 format */
set_reg_field_value(
value,
tbl_entry->regval[10],
OUTPUT_CSC_C33_C34,
OUTPUT_CSC_C33);
/* fixed S0.13 format */
set_reg_field_value(
value,
tbl_entry->regval[11],
OUTPUT_CSC_C33_C34,
OUTPUT_CSC_C34);
dm_write_reg(ctx, addr, value);
}
}
static bool configure_graphics_mode(
struct dce80_opp *opp80,
enum csc_color_mode config,
enum graphics_csc_adjust_type csc_adjust_type,
enum dc_color_space color_space)
{
struct dc_context *ctx = opp80->base.ctx;
uint32_t addr = DCP_REG(mmOUTPUT_CSC_CONTROL);
uint32_t value = dm_read_reg(ctx, addr);
set_reg_field_value(
value,
0,
OUTPUT_CSC_CONTROL,
OUTPUT_CSC_GRPH_MODE);
if (csc_adjust_type == GRAPHICS_CSC_ADJUST_TYPE_SW) {
if (config == CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC) {
set_reg_field_value(
value,
4,
OUTPUT_CSC_CONTROL,
OUTPUT_CSC_GRPH_MODE);
} else {
switch (color_space) {
case COLOR_SPACE_SRGB:
/* by pass */
set_reg_field_value(
value,
0,
OUTPUT_CSC_CONTROL,
OUTPUT_CSC_GRPH_MODE);
break;
case COLOR_SPACE_SRGB_LIMITED:
/* TV RGB */
set_reg_field_value(
value,
1,
OUTPUT_CSC_CONTROL,
OUTPUT_CSC_GRPH_MODE);
break;
case COLOR_SPACE_YCBCR601:
case COLOR_SPACE_YPBPR601:
case COLOR_SPACE_YCBCR601_LIMITED:
/* YCbCr601 */
set_reg_field_value(
value,
2,
OUTPUT_CSC_CONTROL,
OUTPUT_CSC_GRPH_MODE);
break;
case COLOR_SPACE_YCBCR709:
case COLOR_SPACE_YPBPR709:
case COLOR_SPACE_YCBCR709_LIMITED:
/* YCbCr709 */
set_reg_field_value(
value,
3,
OUTPUT_CSC_CONTROL,
OUTPUT_CSC_GRPH_MODE);
break;
default:
return false;
}
}
} else if (csc_adjust_type == GRAPHICS_CSC_ADJUST_TYPE_HW) {
switch (color_space) {
case COLOR_SPACE_SRGB:
/* by pass */
set_reg_field_value(
value,
0,
OUTPUT_CSC_CONTROL,
OUTPUT_CSC_GRPH_MODE);
break;
case COLOR_SPACE_SRGB_LIMITED:
/* TV RGB */
set_reg_field_value(
value,
1,
OUTPUT_CSC_CONTROL,
OUTPUT_CSC_GRPH_MODE);
break;
case COLOR_SPACE_YCBCR601:
case COLOR_SPACE_YPBPR601:
case COLOR_SPACE_YCBCR601_LIMITED:
/* YCbCr601 */
set_reg_field_value(
value,
2,
OUTPUT_CSC_CONTROL,
OUTPUT_CSC_GRPH_MODE);
break;
case COLOR_SPACE_YCBCR709:
case COLOR_SPACE_YPBPR709:
case COLOR_SPACE_YCBCR709_LIMITED:
/* YCbCr709 */
set_reg_field_value(
value,
3,
OUTPUT_CSC_CONTROL,
OUTPUT_CSC_GRPH_MODE);
break;
default:
return false;
}
} else
/* by pass */
set_reg_field_value(
value,
0,
OUTPUT_CSC_CONTROL,
OUTPUT_CSC_GRPH_MODE);
addr = DCP_REG(mmOUTPUT_CSC_CONTROL);
dm_write_reg(ctx, addr, value);
return true;
}
void dce80_opp_set_csc_adjustment(
struct output_pixel_processor *opp,
const struct out_csc_color_matrix *tbl_entry)
{
struct dce80_opp *opp80 = TO_DCE80_OPP(opp);
enum csc_color_mode config =
CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC;
program_color_matrix(opp80, tbl_entry, GRAPHICS_CSC_ADJUST_TYPE_SW);
/* We did everything ,now program DxOUTPUT_CSC_CONTROL */
configure_graphics_mode(opp80, config, GRAPHICS_CSC_ADJUST_TYPE_SW,
tbl_entry->color_space);
}
void dce80_opp_set_csc_default(
struct output_pixel_processor *opp,
const struct default_adjustment *default_adjust)
{
struct dce80_opp *opp80 = TO_DCE80_OPP(opp);
enum csc_color_mode config =
CSC_COLOR_MODE_GRAPHICS_PREDEFINED;
if (default_adjust->force_hw_default == false) {
const struct out_csc_color_matrix *elm;
/* currently parameter not in use */
enum grph_color_adjust_option option =
GRPH_COLOR_MATRIX_HW_DEFAULT;
uint32_t i;
/*
* HW default false we program locally defined matrix
* HW default true we use predefined hw matrix and we
* do not need to program matrix
* OEM wants the HW default via runtime parameter.
*/
option = GRPH_COLOR_MATRIX_SW;
for (i = 0; i < ARRAY_SIZE(global_color_matrix); ++i) {
elm = &global_color_matrix[i];
if (elm->color_space != default_adjust->out_color_space)
continue;
/* program the matrix with default values from this
* file */
program_color_matrix(opp80, elm, option);
config = CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC;
break;
}
}
/* configure the what we programmed :
* 1. Default values from this file
* 2. Use hardware default from ROM_A and we do not need to program
* matrix */
configure_graphics_mode(opp80, config,
default_adjust->csc_adjust_type,
default_adjust->out_color_space);
}
drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
View file @ ab3ee7a5
......@@ -43,7 +43,7 @@
#include "dce80/dce80_mem_input.h"
#include "dce80/dce80_ipp.h"
#include "dce/dce_transform.h"
#include "dce80/dce80_opp.h"
#include "dce/dce_opp.h"
#include "dce110/dce110_ipp.h"
#include "dce/dce_clocks.h"
#include "dce/dce_clock_source.h"
......@@ -317,6 +317,28 @@ static const struct dce_stream_encoder_mask se_mask = {
SE_COMMON_MASK_SH_LIST_DCE80_100(_MASK)
};
#define opp_regs(id)\
[id] = {\
OPP_DCE_80_REG_LIST(id),\
}
static const struct dce_opp_registers opp_regs[] = {
opp_regs(0),
opp_regs(1),
opp_regs(2),
opp_regs(3),
opp_regs(4),
opp_regs(5)
};
static const struct dce_opp_shift opp_shift = {
OPP_COMMON_MASK_SH_LIST_DCE_80(__SHIFT)
};
static const struct dce_opp_mask opp_mask = {
OPP_COMMON_MASK_SH_LIST_DCE_80(_MASK)
};
#define audio_regs(id)\
[id] = {\
AUD_COMMON_REG_LIST(id)\
......@@ -419,6 +441,25 @@ static struct timing_generator *dce80_timing_generator_create(
return NULL;
}
static struct output_pixel_processor *dce80_opp_create(
struct dc_context *ctx,
uint32_t inst)
{
struct dce110_opp *opp =
dm_alloc(sizeof(struct dce110_opp));
if (!opp)
return NULL;
if (dce110_opp_construct(opp,
ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask))
return &opp->base;
BREAK_TO_DEBUGGER();
dm_free(opp);
return NULL;
}
static struct stream_encoder *dce80_stream_encoder_create(
enum engine_id eng_id,
struct dc_context *ctx)
......@@ -631,7 +672,7 @@ static void destruct(struct dce110_resource_pool *pool)
for (i = 0; i < pool->base.pipe_count; i++) {
if (pool->base.opps[i] != NULL)
dce80_opp_destroy(&pool->base.opps[i]);
dce110_opp_destroy(&pool->base.opps[i]);
if (pool->base.transforms[i] != NULL)
dce80_transform_destroy(&pool->base.transforms[i]);
......
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