Commit ab4c6a24 authored by Haibo Chen's avatar Haibo Chen Committed by Shawn Guo

clk: imx7d: add ADC root clock

Add ADC root clock support in imx7d clock tree.
Signed-off-by: default avatarHaibo Chen <haibo.chen@freescale.com>
Acked-by: default avatarStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent d9388c84
......@@ -829,6 +829,7 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
clks[IMX7D_CSI_MCLK_ROOT_CLK] = imx_clk_gate2("csi_mclk_root_clk", "csi_mclk_post_div", base + 0x4490, 0);
clks[IMX7D_AUDIO_MCLK_ROOT_CLK] = imx_clk_gate2("audio_mclk_root_clk", "audio_mclk_post_div", base + 0x4790, 0);
clks[IMX7D_WRCLK_ROOT_CLK] = imx_clk_gate2("wrclk_root_clk", "wrclk_post_div", base + 0x47a0, 0);
clks[IMX7D_ADC_ROOT_CLK] = imx_clk_gate2("adc_root_clk", "ipg_root_clk", base + 0x4200, 0);
clks[IMX7D_GPT_3M_CLK] = imx_clk_fixed_factor("gpt_3m", "osc", 1, 8);
......
......@@ -446,5 +446,6 @@
#define IMX7D_MU_ROOT_CLK 433
#define IMX7D_SEMA4_HS_ROOT_CLK 434
#define IMX7D_PLL_DRAM_TEST_DIV 435
#define IMX7D_CLK_END 436
#define IMX7D_ADC_ROOT_CLK 436
#define IMX7D_CLK_END 437
#endif /* __DT_BINDINGS_CLOCK_IMX7D_H */
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