V4L/DVB (13339): stv0900: big rework to support cut 3.0.

Patch 2 of 4. Also patch changes logic to prevent code repetitions and big indents. It makes checkpatch silent :) Signed-off-by: Igor M. Liplianin <liplianin@netup.ru> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>

V4L/DVB (13339): stv0900: big rework to support cut 3.0.
Patch 2 of 4. Also patch changes logic to prevent code repetitions and big indents. It makes checkpatch silent :) Signed-off-by: Igor M. Liplianin <liplianin@netup.ru> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
ab7134f1 · Igor M. Liplianin · Mauro Carvalho Chehab · 46960eea · ab7134f1
Commit ab7134f1 authored Nov 06, 2009 by Igor M. Liplianin Committed by Mauro Carvalho Chehab Dec 05, 2009
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drivers/media/dvb/frontends/stv0900_reg.h drivers/media/dvb/frontends/stv0900_reg.h +2594 -2406

No files found.
--- a/drivers/media/dvb/frontends/stv0900_reg.h
+++ b/drivers/media/dvb/frontends/stv0900_reg.h
@@ -26,6 +26,11 @@
 #ifndef STV0900_REG_H
 #define STV0900_REG_H

+extern s32 shiftx(s32 x, int demod, s32 shift);
+
+#define REGx(x) shiftx(x, demod, 0x200)
+#define FLDx(x) shiftx(x, demod, 0x2000000)
+
 /*MID*/
 #define R0900_MID 0xf100
 #define F0900_MCHIP_IDENT 0xf10000f0
@@ -42,21 +47,10 @@

 /*OUTCFG*/
 #define R0900_OUTCFG 0xf11c
-#define F0900_INV_DATA6  0xf11c0080
 #define F0900_OUTSERRS1_HZ 0xf11c0040
 #define F0900_OUTSERRS2_HZ 0xf11c0020
 #define F0900_OUTSERRS3_HZ 0xf11c0010
 #define F0900_OUTPARRS3_HZ 0xf11c0008
-#define F0900_OUTHZ3_CONTROL  0xf11c0007
-
-/*MODECFG*/
-#define R0900_MODECFG  0xf11d
-#define F0900_FECSPY_SEL_2  0xf11d0020
-#define F0900_HWARE_SEL_2  0xf11d0010
-#define F0900_PKTDEL_SEL_2  0xf11d0008
-#define F0900_DISEQC_SEL_2  0xf11d0004
-#define F0900_VIT_SEL_2  0xf11d0002
-#define F0900_DEMOD_SEL_2  0xf11d0001

 /*IRQSTATUS3*/
 #define R0900_IRQSTATUS3 0xf120
@@ -81,10 +75,6 @@
 /*IRQSTATUS1*/
 #define R0900_IRQSTATUS1 0xf122
 #define F0900_SPKTDEL_LOCK_1 0xf1220080
-#define F0900_SEXTPINB2  0xf1220040
-#define F0900_SEXTPIN2  0xf1220020
-#define F0900_SEXTPINB1  0xf1220010
-#define F0900_SEXTPIN1  0xf1220008
 #define F0900_SDEMOD_LOCKB_2 0xf1220004
 #define F0900_SDEMOD_LOCK_2 0xf1220002
 #define F0900_SDEMOD_IRQ_2 0xf1220001
@@ -144,16 +134,14 @@

 /*I2CCFG*/
 #define R0900_I2CCFG 0xf129
-#define F0900_I2C2_FASTMODE  0xf1290080
-#define F0900_STATUS_WR2  0xf1290040
-#define F0900_I2C2ADDR_INC  0xf1290030
 #define F0900_I2C_FASTMODE 0xf1290008
-#define F0900_STATUS_WR  0xf1290004
 #define F0900_I2CADDR_INC 0xf1290003

 /*P1_I2CRPT*/
 #define R0900_P1_I2CRPT 0xf12a
+#define I2CRPT shiftx(R0900_P1_I2CRPT, demod, -1)
 #define F0900_P1_I2CT_ON 0xf12a0080
+#define I2CT_ON shiftx(F0900_P1_I2CT_ON, demod, -0x10000)
 #define F0900_P1_ENARPT_LEVEL 0xf12a0070
 #define F0900_P1_SCLT_DELAY 0xf12a0008
 #define F0900_P1_STOP_ENABLE 0xf12a0004
@@ -167,6 +155,78 @@
 #define F0900_P2_STOP_ENABLE 0xf12b0004
 #define F0900_P2_STOP_SDAT2SDA 0xf12b0002

+/*IOPVALUE6*/
+#define R0900_IOPVALUE6 0xf138
+#define F0900_VSCL 0xf1380004
+#define F0900_VSDA 0xf1380002
+#define F0900_VDATA3_0 0xf1380001
+
+/*IOPVALUE5*/
+#define R0900_IOPVALUE5 0xf139
+#define F0900_VDATA3_1 0xf1390080
+#define F0900_VDATA3_2 0xf1390040
+#define F0900_VDATA3_3 0xf1390020
+#define F0900_VDATA3_4 0xf1390010
+#define F0900_VDATA3_5 0xf1390008
+#define F0900_VDATA3_6 0xf1390004
+#define F0900_VDATA3_7 0xf1390002
+#define F0900_VCLKOUT3 0xf1390001
+
+/*IOPVALUE4*/
+#define R0900_IOPVALUE4 0xf13a
+#define F0900_VSTROUT3 0xf13a0080
+#define F0900_VDPN3 0xf13a0040
+#define F0900_VERROR3 0xf13a0020
+#define F0900_VDATA2_7 0xf13a0010
+#define F0900_VCLKOUT2 0xf13a0008
+#define F0900_VSTROUT2 0xf13a0004
+#define F0900_VDPN2 0xf13a0002
+#define F0900_VERROR2 0xf13a0001
+
+/*IOPVALUE3*/
+#define R0900_IOPVALUE3 0xf13b
+#define F0900_VDATA1_7 0xf13b0080
+#define F0900_VCLKOUT1 0xf13b0040
+#define F0900_VSTROUT1 0xf13b0020
+#define F0900_VDPN1 0xf13b0010
+#define F0900_VERROR1 0xf13b0008
+#define F0900_VCLKOUT27 0xf13b0004
+#define F0900_VDISEQCOUT2 0xf13b0002
+#define F0900_VSCLT2 0xf13b0001
+
+/*IOPVALUE2*/
+#define R0900_IOPVALUE2 0xf13c
+#define F0900_VSDAT2 0xf13c0080
+#define F0900_VAGCRF2 0xf13c0040
+#define F0900_VDISEQCOUT1 0xf13c0020
+#define F0900_VSCLT1 0xf13c0010
+#define F0900_VSDAT1 0xf13c0008
+#define F0900_VAGCRF1 0xf13c0004
+#define F0900_VDIRCLK 0xf13c0002
+#define F0900_VSTDBY 0xf13c0001
+
+/*IOPVALUE1*/
+#define R0900_IOPVALUE1 0xf13d
+#define F0900_VCS1 0xf13d0080
+#define F0900_VCS0 0xf13d0040
+#define F0900_VGPIO13 0xf13d0020
+#define F0900_VGPIO12 0xf13d0010
+#define F0900_VGPIO11 0xf13d0008
+#define F0900_VGPIO10 0xf13d0004
+#define F0900_VGPIO9 0xf13d0002
+#define F0900_VGPIO8 0xf13d0001
+
+/*IOPVALUE0*/
+#define R0900_IOPVALUE0 0xf13e
+#define F0900_VGPIO7 0xf13e0080
+#define F0900_VGPIO6 0xf13e0040
+#define F0900_VGPIO5 0xf13e0020
+#define F0900_VGPIO4 0xf13e0010
+#define F0900_VGPIO3 0xf13e0008
+#define F0900_VGPIO2 0xf13e0004
+#define F0900_VGPIO1 0xf13e0002
+#define F0900_VCLKI2 0xf13e0001
+
 /*CLKI2CFG*/
 #define R0900_CLKI2CFG 0xf140
 #define F0900_CLKI2_OPD 0xf1400080
@@ -419,6 +479,21 @@
 #define F0900_DATA73_CONFIG 0xf169007e
 #define F0900_DATA73_XOR 0xf1690001

+/*STRSTATUS1*/
+#define R0900_STRSTATUS1 0xf16a
+#define F0900_STRSTATUS_SEL2 0xf16a00f0
+#define F0900_STRSTATUS_SEL1 0xf16a000f
+
+/*STRSTATUS2*/
+#define R0900_STRSTATUS2 0xf16b
+#define F0900_STRSTATUS_SEL4 0xf16b00f0
+#define F0900_STRSTATUS_SEL3 0xf16b000f
+
+/*STRSTATUS3*/
+#define R0900_STRSTATUS3 0xf16c
+#define F0900_STRSTATUS_SEL6 0xf16c00f0
+#define F0900_STRSTATUS_SEL5 0xf16c000f
+
 /*FSKTFC2*/
 #define R0900_FSKTFC2 0xf170
 #define F0900_FSKT_KMOD 0xf17000fc
@@ -548,7 +623,7 @@
 #define F0900_P2_IGNO_SHORT22K 0xf1910040
 #define F0900_P2_ONECHIP_TRX 0xf1910020
 #define F0900_P2_EXT_ENVELOP 0xf1910010
-#define F0900_P2_PIN_SELECT  0xf191000c
+#define F0900_P2_PIN_SELECT0 0xf191000c
 #define F0900_P2_IRQ_RXEND 0xf1910002
 #define F0900_P2_IRQ_4NBYTES 0xf1910001

@@ -596,7 +671,6 @@

 /*P2_ACRPRESC*/
 #define R0900_P2_ACRPRESC 0xf19c
-#define F0900_P2_ACR_CODFRDY  0xf19c0008
 #define F0900_P2_ACR_PRESC 0xf19c0007

 /*P2_ACRDIV*/
@@ -605,25 +679,32 @@

 /*P1_DISTXCTL*/
 #define R0900_P1_DISTXCTL 0xf1a0
+#define DISTXCTL shiftx(R0900_P1_DISTXCTL, demod, 0x10)
 #define F0900_P1_TIM_OFF 0xf1a00080
 #define F0900_P1_DISEQC_RESET 0xf1a00040
+#define DISEQC_RESET shiftx(F0900_P1_DISEQC_RESET, demod, 0x100000)
 #define F0900_P1_TIM_CMD 0xf1a00030
 #define F0900_P1_DIS_PRECHARGE 0xf1a00008
+#define DIS_PRECHARGE shiftx(F0900_P1_DIS_PRECHARGE, demod, 0x100000)
 #define F0900_P1_DISTX_MODE 0xf1a00007
+#define DISTX_MODE shiftx(F0900_P1_DISTX_MODE, demod, 0x100000)

 /*P1_DISRXCTL*/
 #define R0900_P1_DISRXCTL 0xf1a1
+#define DISRXCTL shiftx(R0900_P1_DISRXCTL, demod, 0x10)
 #define F0900_P1_RECEIVER_ON 0xf1a10080
 #define F0900_P1_IGNO_SHORT22K 0xf1a10040
 #define F0900_P1_ONECHIP_TRX 0xf1a10020
 #define F0900_P1_EXT_ENVELOP 0xf1a10010
-#define F0900_P1_PIN_SELECT  0xf1a1000c
+#define F0900_P1_PIN_SELECT0 0xf1a1000c
 #define F0900_P1_IRQ_RXEND 0xf1a10002
 #define F0900_P1_IRQ_4NBYTES 0xf1a10001

 /*P1_DISRX_ST0*/
 #define R0900_P1_DISRX_ST0 0xf1a4
+#define DISRX_ST0 shiftx(R0900_P1_DISRX_ST0, demod, 0x10)
 #define F0900_P1_RX_END 0xf1a40080
+#define RX_END shiftx(F0900_P1_RX_END, demod, 0x100000)
 #define F0900_P1_RX_ACTIVE 0xf1a40040
 #define F0900_P1_SHORT_22KHZ 0xf1a40020
 #define F0900_P1_CONT_TONE 0xf1a40010
@@ -633,43 +714,52 @@

 /*P1_DISRX_ST1*/
 #define R0900_P1_DISRX_ST1 0xf1a5
+#define DISRX_ST1 shiftx(R0900_P1_DISRX_ST1, demod, 0x10)
 #define F0900_P1_RX_FAIL 0xf1a50080
 #define F0900_P1_FIFO_PARITYFAIL 0xf1a50040
 #define F0900_P1_RX_NONBYTE 0xf1a50020
 #define F0900_P1_FIFO_OVERFLOW 0xf1a50010
 #define F0900_P1_FIFO_BYTENBR 0xf1a5000f
+#define FIFO_BYTENBR shiftx(F0900_P1_FIFO_BYTENBR, demod, 0x100000)

 /*P1_DISRXDATA*/
 #define R0900_P1_DISRXDATA 0xf1a6
+#define DISRXDATA shiftx(R0900_P1_DISRXDATA, demod, 0x10)
 #define F0900_P1_DISRX_DATA 0xf1a600ff

 /*P1_DISTXDATA*/
 #define R0900_P1_DISTXDATA 0xf1a7
+#define DISTXDATA shiftx(R0900_P1_DISTXDATA, demod, 0x10)
 #define F0900_P1_DISEQC_FIFO 0xf1a700ff

 /*P1_DISTXSTATUS*/
 #define R0900_P1_DISTXSTATUS 0xf1a8
 #define F0900_P1_TX_FAIL 0xf1a80080
 #define F0900_P1_FIFO_FULL 0xf1a80040
+#define FIFO_FULL shiftx(F0900_P1_FIFO_FULL, demod, 0x100000)
 #define F0900_P1_TX_IDLE 0xf1a80020
+#define TX_IDLE shiftx(F0900_P1_TX_IDLE, demod, 0x100000)
 #define F0900_P1_GAP_BURST 0xf1a80010
 #define F0900_P1_TXFIFO_BYTES 0xf1a8000f

 /*P1_F22TX*/
 #define R0900_P1_F22TX 0xf1a9
+#define F22TX shiftx(R0900_P1_F22TX, demod, 0x10)
 #define F0900_P1_F22_REG 0xf1a900ff

 /*P1_F22RX*/
 #define R0900_P1_F22RX 0xf1aa
+#define F22RX shiftx(R0900_P1_F22RX, demod, 0x10)
 #define F0900_P1_F22RX_REG 0xf1aa00ff

 /*P1_ACRPRESC*/
 #define R0900_P1_ACRPRESC 0xf1ac
-#define F0900_P1_ACR_CODFRDY  0xf1ac0008
+#define ACRPRESC shiftx(R0900_P1_ACRPRESC, demod, 0x10)
 #define F0900_P1_ACR_PRESC 0xf1ac0007

 /*P1_ACRDIV*/
 #define R0900_P1_ACRDIV 0xf1ad
+#define ACRDIV shiftx(R0900_P1_ACRDIV, demod, 0x10)
 #define F0900_P1_ACR_DIV 0xf1ad00ff

 /*NCOARSE*/
@@ -681,7 +771,6 @@
 #define F0900_STANDBY 0xf1b60080
 #define F0900_BYPASSPLLCORE 0xf1b60040
 #define F0900_SELX1RATIO 0xf1b60020
-#define F0900_I2C_TUD  0xf1b60010
 #define F0900_STOP_PLL 0xf1b60008
 #define F0900_BYPASSPLLFSK 0xf1b60004
 #define F0900_SELOSCI 0xf1b60002
@@ -690,15 +779,12 @@
 /*FILTCTRL*/
 #define R0900_FILTCTRL 0xf1b7
 #define F0900_INV_CLK135 0xf1b70080
-#define F0900_PERM_BYPDIS  0xf1b70040
 #define F0900_SEL_FSKCKDIV 0xf1b70004
 #define F0900_INV_CLKFSK 0xf1b70002
 #define F0900_BYPASS_APPLI 0xf1b70001

 /*PLLSTAT*/
 #define R0900_PLLSTAT 0xf1b8
-#define F0900_ACM_SEL  0xf1b80080
-#define F0900_DTV_SEL  0xf1b80040
 #define F0900_PLLLOCK 0xf1b80001

 /*STOPCLK1*/
@@ -717,39 +803,31 @@
 #define F0900_STOP_CLKSAMP1 0xf1c30008
 #define F0900_STOP_CLKVIT2 0xf1c30004
 #define F0900_STOP_CLKVIT1 0xf1c30002
+#define STOP_CLKVIT shiftx(F0900_STOP_CLKVIT1, demod, -2)
 #define F0900_STOP_CLKTS 0xf1c30001

 /*TSTTNR0*/
 #define R0900_TSTTNR0 0xf1df
 #define F0900_SEL_FSK 0xf1df0080
 #define F0900_FSK_PON 0xf1df0004
-#define F0900_FSK_OPENLOOP  0xf1df0002

 /*TSTTNR1*/
 #define R0900_TSTTNR1 0xf1e0
-#define F0900_BYPASS_ADC1  0xf1e00080
-#define F0900_INVADC1_CKOUT  0xf1e00040
-#define F0900_SELIQSRC1  0xf1e00030
 #define F0900_ADC1_PON 0xf1e00002
 #define F0900_ADC1_INMODE 0xf1e00001

 /*TSTTNR2*/
 #define R0900_TSTTNR2 0xf1e1
 #define F0900_DISEQC1_PON 0xf1e10020
-#define F0900_DISEQC1_TEST  0xf1e1001f

 /*TSTTNR3*/
 #define R0900_TSTTNR3 0xf1e2
-#define F0900_BYPASS_ADC2  0xf1e20080
-#define F0900_INVADC2_CKOUT  0xf1e20040
-#define F0900_SELIQSRC2  0xf1e20030
 #define F0900_ADC2_PON 0xf1e20002
 #define F0900_ADC2_INMODE 0xf1e20001

 /*TSTTNR4*/
 #define R0900_TSTTNR4 0xf1e3
 #define F0900_DISEQC2_PON 0xf1e30020
-#define F0900_DISEQC2_TEST  0xf1e3001f

 /*P2_IQCONST*/
 #define R0900_P2_IQCONST 0xf200
@@ -778,14 +856,10 @@
 #define F0900_P2_AMM_CORRECT 0xf2040010
 #define F0900_P2_QUAD_FROZEN 0xf2040008
 #define F0900_P2_QUAD_CORRECT 0xf2040004
-#define F0900_P2_DCCOMP_SLOW  0xf2040002
-#define F0900_P2_IQMISM_SLOW  0xf2040001

 /*P2_AGC1CN*/
 #define R0900_P2_AGC1CN 0xf206
 #define F0900_P2_AGC1_LOCKED 0xf2060080
-#define F0900_P2_AGC1_OVERFLOW  0xf2060040
-#define F0900_P2_AGC1_NOSLOWLK  0xf2060020
 #define F0900_P2_AGC1_MINPOWER 0xf2060010
 #define F0900_P2_AGCOUT_FAST 0xf2060008
 #define F0900_P2_AGCIQ_BETA 0xf2060007
@@ -828,10 +902,10 @@

 /*P2_DEMOD*/
 #define R0900_P2_DEMOD 0xf210
-#define F0900_P2_DEMOD_STOP  0xf2100040
+#define F0900_P2_MANUALS2_ROLLOFF 0xf2100080
 #define F0900_P2_SPECINV_CONTROL 0xf2100030
 #define F0900_P2_FORCE_ENASAMP 0xf2100008
-#define F0900_P2_MANUAL_ROLLOFF  0xf2100004
+#define F0900_P2_MANUALSX_ROLLOFF 0xf2100004
 #define F0900_P2_ROLLOFF_CONTROL 0xf2100003

 /*P2_DMDMODCOD*/
@@ -844,18 +918,12 @@
 #define R0900_P2_DSTATUS 0xf212
 #define F0900_P2_CAR_LOCK 0xf2120080
 #define F0900_P2_TMGLOCK_QUALITY 0xf2120060
-#define F0900_P2_SDVBS1_ENABLE  0xf2120010
 #define F0900_P2_LOCK_DEFINITIF 0xf2120008
-#define F0900_P2_TIMING_IS_LOCKED  0xf2120004
-#define F0900_P2_COARSE_TMGLOCK  0xf2120002
-#define F0900_P2_COARSE_CARLOCK  0xf2120001
+#define F0900_P2_OVADC_DETECT 0xf2120001

 /*P2_DSTATUS2*/
 #define R0900_P2_DSTATUS2 0xf213
 #define F0900_P2_DEMOD_DELOCK 0xf2130080
-#define F0900_P2_DEMOD_TIMEOUT  0xf2130040
-#define F0900_P2_MODCODRQ_SYNCTAG  0xf2130020
-#define F0900_P2_POLYPH_SATEVENT  0xf2130010
 #define F0900_P2_AGC1_NOSIGNALACK 0xf2130008
 #define F0900_P2_AGC2_OVERFLOW 0xf2130004
 #define F0900_P2_CFR_OVERFLOW 0xf2130002
@@ -865,28 +933,17 @@
 #define R0900_P2_DMDCFGMD 0xf214
 #define F0900_P2_DVBS2_ENABLE 0xf2140080
 #define F0900_P2_DVBS1_ENABLE 0xf2140040
-#define F0900_P2_CFR_AUTOSCAN  0xf2140020
 #define F0900_P2_SCAN_ENABLE 0xf2140010
-#define F0900_P2_TUN_AUTOSCAN  0xf2140008
-#define F0900_P2_NOFORCE_RELOCK  0xf2140004
+#define F0900_P2_CFR_AUTOSCAN 0xf2140008
 #define F0900_P2_TUN_RNG 0xf2140003

 /*P2_DMDCFG2*/
 #define R0900_P2_DMDCFG2 0xf215
-#define F0900_P2_AGC1_WAITLOCK  0xf2150080
 #define F0900_P2_S1S2_SEQUENTIAL 0xf2150040
-#define F0900_P2_OVERFLOW_TIMEOUT  0xf2150020
-#define F0900_P2_SCANFAIL_TIMEOUT  0xf2150010
-#define F0900_P2_DMDTOUT_BACK  0xf2150008
-#define F0900_P2_CARLOCK_S1ENABLE  0xf2150004
-#define F0900_P2_COARSE_LK3MODE  0xf2150002
-#define F0900_P2_COARSE_LK2MODE  0xf2150001
+#define F0900_P2_INFINITE_RELOCK 0xf2150010

 /*P2_DMDISTATE*/
 #define R0900_P2_DMDISTATE 0xf216
-#define F0900_P2_I2C_NORESETDMODE  0xf2160080
-#define F0900_P2_FORCE_ETAPED  0xf2160040
-#define F0900_P2_SDMDRST_DIRCLK  0xf2160020
 #define F0900_P2_I2C_DEMOD_MODE 0xf216001f

 /*P2_DMDT0M*/
@@ -895,9 +952,7 @@

 /*P2_DMDSTATE*/
 #define R0900_P2_DMDSTATE 0xf21b
-#define F0900_P2_DEMOD_LOCKED  0xf21b0080
 #define F0900_P2_HEADER_MODE 0xf21b0060
-#define F0900_P2_DEMOD_MODE  0xf21b001f

 /*P2_DMDFLYW*/
 #define R0900_P2_DMDFLYW 0xf21c
@@ -906,28 +961,15 @@

 /*P2_DSTATUS3*/
 #define R0900_P2_DSTATUS3 0xf21d
-#define F0900_P2_CFR_ZIGZAG  0xf21d0080
 #define F0900_P2_DEMOD_CFGMODE 0xf21d0060
-#define F0900_P2_GAMMA_LOWBAUDRATE  0xf21d0010
-#define F0900_P2_RELOCK_MODE  0xf21d0008
-#define F0900_P2_DEMOD_FAIL  0xf21d0004
-#define F0900_P2_ETAPE1A_DVBXMEM  0xf21d0003

 /*P2_DMDCFG3*/
 #define R0900_P2_DMDCFG3 0xf21e
-#define F0900_P2_DVBS1_TMGWAIT  0xf21e0080
-#define F0900_P2_NO_BWCENTERING  0xf21e0040
-#define F0900_P2_INV_SEQSRCH  0xf21e0020
-#define F0900_P2_DIS_SFRUPLOW_TRK  0xf21e0010
 #define F0900_P2_NOSTOP_FIFOFULL 0xf21e0008
-#define F0900_P2_LOCKTIME_MODE  0xf21e0007

 /*P2_DMDCFG4*/
 #define R0900_P2_DMDCFG4 0xf21f
 #define F0900_P2_TUNER_NRELAUNCH 0xf21f0008
-#define F0900_P2_DIS_CLKENABLE  0xf21f0004
-#define F0900_P2_DIS_HDRDIVLOCK  0xf21f0002
-#define F0900_P2_NO_TNRWBINIT  0xf21f0001

 /*P2_CORRELMANT*/
 #define R0900_P2_CORRELMANT 0xf220
@@ -948,20 +990,12 @@
 #define F0900_P2_PLH_MODCOD 0xf224007c
 #define F0900_P2_PLH_TYPE 0xf2240003

-/*P2_AGCK32*/
-#define R0900_P2_AGCK32  0xf22b
-#define F0900_P2_R3ADJOFF_32APSK  0xf22b0080
-#define F0900_P2_R2ADJOFF_32APSK  0xf22b0040
-#define F0900_P2_R1ADJOFF_32APSK  0xf22b0020
-#define F0900_P2_RADJ_32APSK  0xf22b001f
+/*P2_DMDREG*/
+#define R0900_P2_DMDREG 0xf225
+#define F0900_P2_DECIM_PLFRAMES 0xf2250001

 /*P2_AGC2O*/
 #define R0900_P2_AGC2O 0xf22c
-#define F0900_P2_AGC2REF_ADJUSTING  0xf22c0080
-#define F0900_P2_AGC2_COARSEFAST  0xf22c0040
-#define F0900_P2_AGC2_LKSQRT  0xf22c0020
-#define F0900_P2_AGC2_LKMODE  0xf22c0010
-#define F0900_P2_AGC2_LKEQUA  0xf22c0008
 #define F0900_P2_AGC2_COEF 0xf22c0007

 /*P2_AGC2REF*/
@@ -970,8 +1004,7 @@

 /*P2_AGC1ADJ*/
 #define R0900_P2_AGC1ADJ 0xf22e
-#define F0900_P2_AGC1ADJ_MANUAL  0xf22e0080
-#define F0900_P2_AGC1_ADJUSTED  0xf22e017f
+#define F0900_P2_AGC1_ADJUSTED 0xf22e007f

 /*P2_AGC2I1*/
 #define R0900_P2_AGC2I1 0xf236
@@ -985,21 +1018,16 @@
 #define R0900_P2_CARCFG 0xf238
 #define F0900_P2_CFRUPLOW_AUTO 0xf2380080
 #define F0900_P2_CFRUPLOW_TEST 0xf2380040
-#define F0900_P2_EN_CAR2CENTER  0xf2380020
-#define F0900_P2_CARHDR_NODIV8  0xf2380010
-#define F0900_P2_I2C_ROTA  0xf2380008
 #define F0900_P2_ROTAON 0xf2380004
 #define F0900_P2_PH_DET_ALGO 0xf2380003

 /*P2_ACLC*/
 #define R0900_P2_ACLC 0xf239
-#define F0900_P2_STOP_S2ALPHA  0xf23900c0
 #define F0900_P2_CAR_ALPHA_MANT 0xf2390030
 #define F0900_P2_CAR_ALPHA_EXP 0xf239000f

 /*P2_BCLC*/
 #define R0900_P2_BCLC 0xf23a
-#define F0900_P2_STOP_S2BETA  0xf23a00c0
 #define F0900_P2_CAR_BETA_MANT 0xf23a0030
 #define F0900_P2_CAR_BETA_EXP 0xf23a000f

@@ -1022,12 +1050,6 @@

 /*P2_CFRICFG*/
 #define R0900_P2_CFRICFG 0xf241
-#define F0900_P2_CFRINIT_UNVALRNG  0xf2410080
-#define F0900_P2_CFRINIT_LUNVALCPT  0xf2410040
-#define F0900_P2_CFRINIT_ABORTDBL  0xf2410020
-#define F0900_P2_CFRINIT_ABORTPRED  0xf2410010
-#define F0900_P2_CFRINIT_UNVALSKIP  0xf2410008
-#define F0900_P2_CFRINIT_CSTINC  0xf2410004
 #define F0900_P2_NEG_CFRSTEP 0xf2410001

 /*P2_CFRUP1*/
@@ -1057,11 +1079,11 @@
 /*P2_CFRINC1*/
 #define R0900_P2_CFRINC1 0xf24a
 #define F0900_P2_MANUAL_CFRINC 0xf24a0080
-#define F0900_P2_CFR_INC1  0xf24a017f
+#define F0900_P2_CFR_INC1 0xf24a003f

 /*P2_CFRINC0*/
 #define R0900_P2_CFRINC0 0xf24b
-#define F0900_P2_CFR_INC0  0xf24b00f0
+#define F0900_P2_CFR_INC0 0xf24b00f8

 /*P2_CFR2*/
 #define R0900_P2_CFR2 0xf24c
@@ -1082,9 +1104,7 @@
 /*P2_TMGCFG*/
 #define R0900_P2_TMGCFG 0xf250
 #define F0900_P2_TMGLOCK_BETA 0xf25000c0
-#define F0900_P2_NOTMG_GROUPDELAY  0xf2500020
 #define F0900_P2_DO_TIMING_CORR 0xf2500010
-#define F0900_P2_MANUAL_SCAN  0xf250000c
 #define F0900_P2_TMG_MINFREQ 0xf2500003

 /*P2_RTC*/
@@ -1124,14 +1144,15 @@

 /*P2_TMGCFG2*/
 #define R0900_P2_TMGCFG2 0xf25a
-#define F0900_P2_DIS_AUTOSAMP  0xf25a0008
-#define F0900_P2_SCANINIT_QUART  0xf25a0004
-#define F0900_P2_NOTMG_DVBS1DERAT  0xf25a0002
 #define F0900_P2_SFRRATIO_FINE 0xf25a0001

+/*P2_KREFTMG2*/
+#define R0900_P2_KREFTMG2 0xf25b
+#define F0900_P2_KREF_TMG2 0xf25b00ff
+
 /*P2_SFRINIT1*/
 #define R0900_P2_SFRINIT1 0xf25e
-#define F0900_P2_SFR_INIT1  0xf25e00ff
+#define F0900_P2_SFR_INIT1 0xf25e007f

 /*P2_SFRINIT0*/
 #define R0900_P2_SFRINIT0 0xf25f
@@ -1194,16 +1215,10 @@
 /*P2_TMGOBS*/
 #define R0900_P2_TMGOBS 0xf26d
 #define F0900_P2_ROLLOFF_STATUS 0xf26d00c0
-#define F0900_P2_SCAN_SIGN  0xf26d0030
-#define F0900_P2_TMG_SCANNING  0xf26d0008
-#define F0900_P2_CHCENTERING_MODE  0xf26d0004
-#define F0900_P2_TMG_SCANFAIL  0xf26d0002

 /*P2_EQUALCFG*/
 #define R0900_P2_EQUALCFG 0xf26f
-#define F0900_P2_NOTMG_NEGALWAIT  0xf26f0080
 #define F0900_P2_EQUAL_ON 0xf26f0040
-#define F0900_P2_SEL_EQUALCOR  0xf26f0038
 #define F0900_P2_MU_EQUALDFE 0xf26f0007

 /*P2_EQUAI1*/
@@ -1336,26 +1351,16 @@

 /*P2_CAR2CFG*/
 #define R0900_P2_CAR2CFG 0xf290
-#define F0900_P2_DESCRAMB_OFF  0xf2900080
-#define F0900_P2_PN4_SELECT  0xf2900040
-#define F0900_P2_CFR2_STOPDVBS1  0xf2900020
-#define F0900_P2_STOP_CFR2UPDATE  0xf2900010
-#define F0900_P2_STOP_NCO2UPDATE  0xf2900008
+#define F0900_P2_CARRIER3_DISABLE 0xf2900040
 #define F0900_P2_ROTA2ON 0xf2900004
 #define F0900_P2_PH_DET_ALGO2 0xf2900003

-/*P2_ACLC2*/
-#define R0900_P2_ACLC2  0xf291
-#define F0900_P2_CAR2_PUNCT_ADERAT  0xf2910040
-#define F0900_P2_CAR2_ALPHA_MANT  0xf2910030
-#define F0900_P2_CAR2_ALPHA_EXP  0xf291000f
-
-/*P2_BCLC2*/
-#define R0900_P2_BCLC2  0xf292
-#define F0900_P2_DVBS2_NIP  0xf2920080
-#define F0900_P2_CAR2_PUNCT_BDERAT  0xf2920040
-#define F0900_P2_CAR2_BETA_MANT  0xf2920030
-#define F0900_P2_CAR2_BETA_EXP  0xf292000f
+/*P2_CFR2CFR1*/
+#define R0900_P2_CFR2CFR1 0xf291
+#define F0900_P2_CFR2TOCFR1_DVBS1 0xf29100c0
+#define F0900_P2_EN_S2CAR2CENTER 0xf2910020
+#define F0900_P2_DIS_BCHERRCFR2 0xf2910010
+#define F0900_P2_CFR2TOCFR1_BETA 0xf2910007

 /*P2_CFR22*/
 #define R0900_P2_CFR22 0xf293
@@ -1372,19 +1377,18 @@
 /*P2_ACLC2S2Q*/
 #define R0900_P2_ACLC2S2Q 0xf297
 #define F0900_P2_ENAB_SPSKSYMB 0xf2970080
-#define F0900_P2_CAR2S2_QADERAT  0xf2970040
 #define F0900_P2_CAR2S2_Q_ALPH_M 0xf2970030
 #define F0900_P2_CAR2S2_Q_ALPH_E 0xf297000f

 /*P2_ACLC2S28*/
 #define R0900_P2_ACLC2S28 0xf298
 #define F0900_P2_OLDI3Q_MODE 0xf2980080
-#define F0900_P2_CAR2S2_8ADERAT  0xf2980040
 #define F0900_P2_CAR2S2_8_ALPH_M 0xf2980030
 #define F0900_P2_CAR2S2_8_ALPH_E 0xf298000f

 /*P2_ACLC2S216A*/
 #define R0900_P2_ACLC2S216A 0xf299
+#define F0900_P2_DIS_C3STOPA2 0xf2990080
 #define F0900_P2_CAR2S2_16ADERAT 0xf2990040
 #define F0900_P2_CAR2S2_16A_ALPH_M 0xf2990030
 #define F0900_P2_CAR2S2_16A_ALPH_E 0xf299000f
@@ -1397,38 +1401,22 @@

 /*P2_BCLC2S2Q*/
 #define R0900_P2_BCLC2S2Q 0xf29c
-#define F0900_P2_DVBS2S2Q_NIP  0xf29c0080
-#define F0900_P2_CAR2S2_QBDERAT  0xf29c0040
 #define F0900_P2_CAR2S2_Q_BETA_M 0xf29c0030
 #define F0900_P2_CAR2S2_Q_BETA_E 0xf29c000f

 /*P2_BCLC2S28*/
 #define R0900_P2_BCLC2S28 0xf29d
-#define F0900_P2_DVBS2S28_NIP  0xf29d0080
-#define F0900_P2_CAR2S2_8BDERAT  0xf29d0040
 #define F0900_P2_CAR2S2_8_BETA_M 0xf29d0030
 #define F0900_P2_CAR2S2_8_BETA_E 0xf29d000f

 /*P2_BCLC2S216A*/
 #define R0900_P2_BCLC2S216A 0xf29e
-#define F0900_P2_DVBS2S216A_NIP  0xf29e0080
-#define F0900_P2_CAR2S2_16BDERAT  0xf29e0040
-#define F0900_P2_CAR2S2_16A_BETA_M  0xf29e0030
-#define F0900_P2_CAR2S2_16A_BETA_E  0xf29e000f

 /*P2_BCLC2S232A*/
 #define R0900_P2_BCLC2S232A 0xf29f
-#define F0900_P2_DVBS2S232A_NIP  0xf29f0080
-#define F0900_P2_CAR2S2_32BDERAT  0xf29f0040
-#define F0900_P2_CAR2S2_32A_BETA_M  0xf29f0030
-#define F0900_P2_CAR2S2_32A_BETA_E  0xf29f000f

 /*P2_PLROOT2*/
 #define R0900_P2_PLROOT2 0xf2ac
-#define F0900_P2_SHORTFR_DISABLE  0xf2ac0080
-#define F0900_P2_LONGFR_DISABLE  0xf2ac0040
-#define F0900_P2_DUMMYPL_DISABLE  0xf2ac0020
-#define F0900_P2_SHORTFR_AVOID  0xf2ac0010
 #define F0900_P2_PLSCRAMB_MODE 0xf2ac000c
 #define F0900_P2_PLSCRAMB_ROOT2 0xf2ac0003

@@ -1442,9 +1430,6 @@

 /*P2_MODCODLST0*/
 #define R0900_P2_MODCODLST0 0xf2b0
-#define F0900_P2_EN_TOKEN31  0xf2b00080
-#define F0900_P2_SYNCTAG_SELECT  0xf2b00040
-#define F0900_P2_MODCODRQ_MODE  0xf2b00030

 /*P2_MODCODLST1*/
 #define R0900_P2_MODCODLST1 0xf2b1
@@ -1519,21 +1504,39 @@
 /*P2_MODCODLSTF*/
 #define R0900_P2_MODCODLSTF 0xf2bf
 #define F0900_P2_DIS_QP_1_4 0xf2bf00f0
-#define F0900_P2_DDEMOD_SET  0xf2bf0002
-#define F0900_P2_DDEMOD_MASK  0xf2bf0001
+
+/*P2_GAUSSR0*/
+#define R0900_P2_GAUSSR0 0xf2c0
+#define F0900_P2_EN_CCIMODE 0xf2c00080
+#define F0900_P2_R0_GAUSSIEN 0xf2c0007f
+
+/*P2_CCIR0*/
+#define R0900_P2_CCIR0 0xf2c1
+#define F0900_P2_CCIDETECT_PLHONLY 0xf2c10080
+#define F0900_P2_R0_CCI 0xf2c1007f
+
+/*P2_CCIQUANT*/
+#define R0900_P2_CCIQUANT 0xf2c2
+#define F0900_P2_CCI_BETA 0xf2c200e0
+#define F0900_P2_CCI_QUANT 0xf2c2001f
+
+/*P2_CCITHRES*/
+#define R0900_P2_CCITHRES 0xf2c3
+#define F0900_P2_CCI_THRESHOLD 0xf2c300ff
+
+/*P2_CCIACC*/
+#define R0900_P2_CCIACC 0xf2c4
+#define F0900_P2_CCI_VALUE 0xf2c400ff

 /*P2_DMDRESCFG*/
 #define R0900_P2_DMDRESCFG 0xf2c6
 #define F0900_P2_DMDRES_RESET 0xf2c60080
-#define F0900_P2_DMDRES_NOISESQR  0xf2c60010
 #define F0900_P2_DMDRES_STRALL 0xf2c60008
 #define F0900_P2_DMDRES_NEWONLY 0xf2c60004
 #define F0900_P2_DMDRES_NOSTORE 0xf2c60002
-#define F0900_P2_DMDRES_AGC2MEM  0xf2c60001

 /*P2_DMDRESADR*/
 #define R0900_P2_DMDRESADR 0xf2c7
-#define F0900_P2_SUSP_PREDCANAL  0xf2c70080
 #define F0900_P2_DMDRES_VALIDCFR 0xf2c70040
 #define F0900_P2_DMDRES_MEMFULL 0xf2c70030
 #define F0900_P2_DMDRES_RESNBR 0xf2c7000f
@@ -1605,7 +1608,6 @@
 /*P2_FFECFG*/
 #define R0900_P2_FFECFG 0xf2d8
 #define F0900_P2_EQUALFFE_ON 0xf2d80040
-#define F0900_P2_EQUAL_USEDSYMB  0xf2d80030
 #define F0900_P2_MU_EQUALFFE 0xf2d80007

 /*P2_TNRCFG*/
@@ -1619,25 +1621,19 @@
 /*P2_TNRCFG2*/
 #define R0900_P2_TNRCFG2 0xf2e1
 #define F0900_P2_TUN_IQSWAP 0xf2e10080
-#define F0900_P2_STB6110_STEP2MHZ  0xf2e10040
-#define F0900_P2_STB6120_DBLI2C  0xf2e10020
-#define F0900_P2_DIS_FCCK  0xf2e10010
-#define F0900_P2_DIS_LPEN  0xf2e10008
 #define F0900_P2_DIS_BWCALC 0xf2e10004
 #define F0900_P2_SHORT_WAITSTATES 0xf2e10002
-#define F0900_P2_DIS_2BWAGC1  0xf2e10001

 /*P2_TNRXTAL*/
 #define R0900_P2_TNRXTAL 0xf2e4
-#define F0900_P2_TUN_MCLKDECIMAL  0xf2e400e0
 #define F0900_P2_TUN_XTALFREQ 0xf2e4001f

 /*P2_TNRSTEPS*/
 #define R0900_P2_TNRSTEPS 0xf2e7
-#define F0900_P2_TUNER_BW1P6  0xf2e70080
-#define F0900_P2_BWINC_OFFSET  0xf2e70070
+#define F0900_P2_TUNER_BW0P125 0xf2e70080
+#define F0900_P2_BWINC_OFFSET 0xf2e70170
 #define F0900_P2_SOFTSTEP_RNG 0xf2e70008
-#define F0900_P2_TUN_BWOFFSET  0xf2e70107
+#define F0900_P2_TUN_BWOFFSET 0xf2e70007

 /*P2_TNRGAIN*/
 #define R0900_P2_TNRGAIN 0xf2e8
@@ -1660,27 +1656,21 @@

 /*P2_TNRADJ*/
 #define R0900_P2_TNRADJ 0xf2ec
-#define F0900_P2_STB61X0_RCLK  0xf2ec0080
 #define F0900_P2_STB61X0_CALTIME 0xf2ec0040
-#define F0900_P2_STB6X00_DLB  0xf2ec0038
-#define F0900_P2_STB6000_FCL  0xf2ec0007

 /*P2_TNRCTL2*/
 #define R0900_P2_TNRCTL2 0xf2ed
-#define F0900_P2_STB61X0_LCP1_RCCKOFF  0xf2ed0080
-#define F0900_P2_STB61X0_LCP0  0xf2ed0040
-#define F0900_P2_STB61X0_XTOUT_RFOUTS  0xf2ed0020
-#define F0900_P2_STB61X0_XTON_MCKDV  0xf2ed0010
-#define F0900_P2_STB61X0_CALOFF_DCOFF  0xf2ed0008
-#define F0900_P2_STB6110_LPT  0xf2ed0004
-#define F0900_P2_STB6110_RX  0xf2ed0002
-#define F0900_P2_STB6110_SYN  0xf2ed0001
+#define F0900_P2_STB61X0_RCCKOFF 0xf2ed0080
+#define F0900_P2_STB61X0_ICP_SDOFF 0xf2ed0040
+#define F0900_P2_STB61X0_DCLOOPOFF 0xf2ed0020
+#define F0900_P2_STB61X0_REFOUTSEL 0xf2ed0010
+#define F0900_P2_STB61X0_CALOFF 0xf2ed0008
+#define F0900_P2_STB6XX0_LPT_BEN 0xf2ed0004
+#define F0900_P2_STB6XX0_RX_OSCP 0xf2ed0002
+#define F0900_P2_STB6XX0_SYN 0xf2ed0001

 /*P2_TNRCFG3*/
 #define R0900_P2_TNRCFG3 0xf2ee
-#define F0900_P2_STB6120_DISCTRL1  0xf2ee0080
-#define F0900_P2_STB6120_INVORDER  0xf2ee0040
-#define F0900_P2_STB6120_ENCTRL6  0xf2ee0020
 #define F0900_P2_TUN_PLLFREQ 0xf2ee001c
 #define F0900_P2_TUN_I2CFREQ_MODE 0xf2ee0003

@@ -1718,7 +1708,6 @@

 /*P2_SMAPCOEF6*/
 #define R0900_P2_SMAPCOEF6 0xf301
-#define F0900_P2_DIS_NEWSCALE  0xf3010008
 #define F0900_P2_ADJ_8PSKLLR1 0xf3010004
 #define F0900_P2_OLD_8PSKLLR1 0xf3010002
 #define F0900_P2_DIS_AB8PSK 0xf3010001
@@ -1728,6 +1717,30 @@
 #define F0900_P2_DIS_8SCALE 0xf3020080
 #define F0900_P2_SMAPCOEF_8P_LLR23 0xf302017f

+/*P2_NCO2MAX1*/
+#define R0900_P2_NCO2MAX1 0xf314
+#define F0900_P2_TETA2_MAXVABS1 0xf31400ff
+
+/*P2_NCO2MAX0*/
+#define R0900_P2_NCO2MAX0 0xf315
+#define F0900_P2_TETA2_MAXVABS0 0xf31500ff
+
+/*P2_NCO2FR1*/
+#define R0900_P2_NCO2FR1 0xf316
+#define F0900_P2_NCO2FINAL_ANGLE1 0xf31600ff
+
+/*P2_NCO2FR0*/
+#define R0900_P2_NCO2FR0 0xf317
+#define F0900_P2_NCO2FINAL_ANGLE0 0xf31700ff
+
+/*P2_CFR2AVRGE1*/
+#define R0900_P2_CFR2AVRGE1 0xf318
+#define F0900_P2_I2C_CFR2AVERAGE1 0xf31800ff
+
+/*P2_CFR2AVRGE0*/
+#define R0900_P2_CFR2AVRGE0 0xf319
+#define F0900_P2_I2C_CFR2AVERAGE0 0xf31900ff
+
 /*P2_DMDPLHSTAT*/
 #define R0900_P2_DMDPLHSTAT 0xf320
 #define F0900_P2_PLH_STATISTIC 0xf32000ff
@@ -1752,18 +1765,13 @@
 #define R0900_P2_VITSCALE 0xf332
 #define F0900_P2_NVTH_NOSRANGE 0xf3320080
 #define F0900_P2_VERROR_MAXMODE 0xf3320040
-#define F0900_P2_KDIV_MODE  0xf3320030
 #define F0900_P2_NSLOWSN_LOCKED 0xf3320008
-#define F0900_P2_DELOCK_PRFLOSS  0xf3320004
 #define F0900_P2_DIS_RSFLOCK 0xf3320002

 /*P2_FECM*/
 #define R0900_P2_FECM 0xf333
 #define F0900_P2_DSS_DVB 0xf3330080
-#define F0900_P2_DEMOD_BYPASS  0xf3330040
-#define F0900_P2_CMP_SLOWMODE  0xf3330020
 #define F0900_P2_DSS_SRCH 0xf3330010
-#define F0900_P2_DIFF_MODEVIT  0xf3330004
 #define F0900_P2_SYNCVIT 0xf3330002
 #define F0900_P2_IQINV 0xf3330001

@@ -1793,7 +1801,6 @@

 /*P2_VITCURPUN*/
 #define R0900_P2_VITCURPUN 0xf33a
-#define F0900_P2_VIT_MAPPING  0xf33a00e0
 #define F0900_P2_VIT_CURPUN 0xf33a001f

 /*P2_VERROR*/
@@ -1820,14 +1827,8 @@

 /*P2_VSTATUSVIT*/
 #define R0900_P2_VSTATUSVIT 0xf33e
-#define F0900_P2_VITERBI_ON  0xf33e0080
-#define F0900_P2_END_LOOPVIT  0xf33e0040
-#define F0900_P2_VITERBI_DEPRF  0xf33e0020
 #define F0900_P2_PRFVIT 0xf33e0010
 #define F0900_P2_LOCKEDVIT 0xf33e0008
-#define F0900_P2_VITERBI_DELOCK  0xf33e0004
-#define F0900_P2_VIT_DEMODSEL  0xf33e0002
-#define F0900_P2_VITERBI_COMPOUT  0xf33e0001

 /*P2_VTHINUSE*/
 #define R0900_P2_VTHINUSE 0xf33f
@@ -1835,54 +1836,40 @@

 /*P2_KDIV12*/
 #define R0900_P2_KDIV12 0xf340
-#define F0900_P2_KDIV12_MANUAL  0xf3400080
 #define F0900_P2_K_DIVIDER_12 0xf340007f

 /*P2_KDIV23*/
 #define R0900_P2_KDIV23 0xf341
-#define F0900_P2_KDIV23_MANUAL  0xf3410080
 #define F0900_P2_K_DIVIDER_23 0xf341007f

 /*P2_KDIV34*/
 #define R0900_P2_KDIV34 0xf342
-#define F0900_P2_KDIV34_MANUAL  0xf3420080
 #define F0900_P2_K_DIVIDER_34 0xf342007f

 /*P2_KDIV56*/
 #define R0900_P2_KDIV56 0xf343
-#define F0900_P2_KDIV56_MANUAL  0xf3430080
 #define F0900_P2_K_DIVIDER_56 0xf343007f

 /*P2_KDIV67*/
 #define R0900_P2_KDIV67 0xf344
-#define F0900_P2_KDIV67_MANUAL  0xf3440080
 #define F0900_P2_K_DIVIDER_67 0xf344007f

 /*P2_KDIV78*/
 #define R0900_P2_KDIV78 0xf345
-#define F0900_P2_KDIV78_MANUAL  0xf3450080
 #define F0900_P2_K_DIVIDER_78 0xf345007f

 /*P2_PDELCTRL1*/
 #define R0900_P2_PDELCTRL1 0xf350
 #define F0900_P2_INV_MISMASK 0xf3500080
-#define F0900_P2_FORCE_ACCEPTED  0xf3500040
 #define F0900_P2_FILTER_EN 0xf3500020
-#define F0900_P2_FORCE_PKTDELINUSE  0xf3500010
-#define F0900_P2_HYSTEN  0xf3500008
-#define F0900_P2_HYSTSWRST  0xf3500004
 #define F0900_P2_EN_MIS00 0xf3500002
 #define F0900_P2_ALGOSWRST 0xf3500001

 /*P2_PDELCTRL2*/
 #define R0900_P2_PDELCTRL2 0xf351
-#define F0900_P2_FORCE_CONTINUOUS  0xf3510080
 #define F0900_P2_RESET_UPKO_COUNT 0xf3510040
-#define F0900_P2_USER_PKTDELIN_NB  0xf3510020
-#define F0900_P2_FORCE_LOCKED  0xf3510010
-#define F0900_P2_DATA_UNBBSCRAM  0xf3510008
-#define F0900_P2_FORCE_LONGPKT  0xf3510004
 #define F0900_P2_FRAME_MODE 0xf3510002
+#define F0900_P2_NOBCHERRFLG_USE 0xf3510001

 /*P2_HYSTTHRESH*/
 #define R0900_P2_HYSTTHRESH 0xf354
@@ -1940,13 +1927,11 @@
 #define F0900_P2_CONTINUOUS_STREAM 0xf3690020
 #define F0900_P2_UNACCEPTED_STREAM 0xf3690010
 #define F0900_P2_BCH_ERROR_FLAG 0xf3690008
-#define F0900_P2_BBHCRCKO  0xf3690004
 #define F0900_P2_PKTDELIN_LOCK 0xf3690002
 #define F0900_P2_FIRST_LOCK 0xf3690001

 /*P2_PDELSTATUS2*/
 #define R0900_P2_PDELSTATUS2 0xf36a
-#define F0900_P2_PKTDEL_DEMODSEL  0xf36a0080
 #define F0900_P2_FRAME_MODCOD 0xf36a007c
 #define F0900_P2_FRAME_TYPE 0xf36a0003

@@ -1966,15 +1951,18 @@
 #define R0900_P2_UPCRCKO0 0xf36e
 #define F0900_P2_PKTCRC_KOCNT0 0xf36e00ff

+/*P2_PDELCTRL3*/
+#define R0900_P2_PDELCTRL3 0xf36f
+#define F0900_P2_PKTDEL_CONTFAIL 0xf36f0080
+#define F0900_P2_NOFIFO_BCHERR 0xf36f0020
+
 /*P2_TSSTATEM*/
 #define R0900_P2_TSSTATEM 0xf370
 #define F0900_P2_TSDIL_ON 0xf3700080
-#define F0900_P2_TSSKIPRS_ON  0xf3700040
 #define F0900_P2_TSRS_ON 0xf3700020
 #define F0900_P2_TSDESCRAMB_ON 0xf3700010
 #define F0900_P2_TSFRAME_MODE 0xf3700008
 #define F0900_P2_TS_DISABLE 0xf3700004
-#define F0900_P2_TSACM_MODE  0xf3700002
 #define F0900_P2_TSOUT_NOSYNC 0xf3700001

 /*P2_TSCFGH*/
@@ -1991,10 +1979,7 @@
 #define R0900_P2_TSCFGM 0xf373
 #define F0900_P2_TSFIFO_MANSPEED 0xf37300c0
 #define F0900_P2_TSFIFO_PERMDATA 0xf3730020
-#define F0900_P2_TSFIFO_NONEWSGNL  0xf3730010
-#define F0900_P2_TSFIFO_BITSPEED  0xf3730008
-#define F0900_P2_NPD_SPECDVBS2  0xf3730004
-#define F0900_P2_TSFIFO_STOPCKDIS  0xf3730002
+#define F0900_P2_TSFIFO_DPUNACT 0xf3730002
 #define F0900_P2_TSFIFO_INVDATA 0xf3730001

 /*P2_TSCFGL*/
@@ -2003,8 +1988,7 @@
 #define F0900_P2_BCHERROR_MODE 0xf3740030
 #define F0900_P2_TSFIFO_NSGNL2DATA 0xf3740008
 #define F0900_P2_TSFIFO_EMBINDVB 0xf3740004
-#define F0900_P2_TSFIFO_DPUNACT  0xf3740002
-#define F0900_P2_TSFIFO_NPDOFF  0xf3740001
+#define F0900_P2_TSFIFO_BITSPEED 0xf3740003

 /*P2_TSINSDELH*/
 #define R0900_P2_TSINSDELH 0xf376
@@ -2017,6 +2001,14 @@
 #define F0900_P2_TSINSDEL_RSPARITY 0xf3760002
 #define F0900_P2_TSINSDEL_CRC8 0xf3760001

+/*P2_TSDIVN*/
+#define R0900_P2_TSDIVN 0xf379
+#define F0900_P2_TSFIFO_SPEEDMODE 0xf37900c0
+
+/*P2_TSCFG4*/
+#define R0900_P2_TSCFG4 0xf37a
+#define F0900_P2_TSFIFO_TSSPEEDMODE 0xf37a00c0
+
 /*P2_TSSPEED*/
 #define R0900_P2_TSSPEED 0xf380
 #define F0900_P2_TSFIFO_OUTSPEED 0xf38000ff
@@ -2025,11 +2017,6 @@
 #define R0900_P2_TSSTATUS 0xf381
 #define F0900_P2_TSFIFO_LINEOK 0xf3810080
 #define F0900_P2_TSFIFO_ERROR 0xf3810040
-#define F0900_P2_TSFIFO_DATA7  0xf3810020
-#define F0900_P2_TSFIFO_NOSYNC  0xf3810010
-#define F0900_P2_ISCR_INITIALIZED  0xf3810008
-#define F0900_P2_ISCR_UPDATED  0xf3810004
-#define F0900_P2_SOFFIFO_UNREGUL  0xf3810002
 #define F0900_P2_DIL_READY 0xf3810001

 /*P2_TSSTATUS2*/
@@ -2038,10 +2025,7 @@
 #define F0900_P2_TSFIFOSPEED_STORE 0xf3820040
 #define F0900_P2_DILXX_RESET 0xf3820020
 #define F0900_P2_TSSERIAL_IMPOS 0xf3820010
-#define F0900_P2_TSFIFO_LINENOK  0xf3820008
-#define F0900_P2_BITSPEED_EVENT  0xf3820004
 #define F0900_P2_SCRAMBDETECT 0xf3820002
-#define F0900_P2_ULDTV67_FALSELOCK  0xf3820001

 /*P2_TSBITRATE1*/
 #define R0900_P2_TSBITRATE1 0xf383
@@ -2093,7 +2077,7 @@
 #define F0900_P2_NO_SYNCBYTE 0xf3a00040
 #define F0900_P2_SERIAL_MODE 0xf3a00020
 #define F0900_P2_UNUSUAL_PACKET 0xf3a00010
-#define F0900_P2_BER_PACKMODE  0xf3a00008
+#define F0900_P2_BERMETER_DATAMODE 0xf3a00008
 #define F0900_P2_BERMETER_LMODE 0xf3a00002
 #define F0900_P2_BERMETER_RESET 0xf3a00001

@@ -2108,14 +2092,12 @@
 /*P2_FSPYDATA*/
 #define R0900_P2_FSPYDATA 0xf3a2
 #define F0900_P2_SPY_STUFFING 0xf3a20080
-#define F0900_P2_NOERROR_PKTJITTER  0xf3a20040
 #define F0900_P2_SPY_CNULLPKT 0xf3a20020
 #define F0900_P2_SPY_OUTDATA_MODE 0xf3a2001f

 /*P2_FSPYOUT*/
 #define R0900_P2_FSPYOUT 0xf3a3
 #define F0900_P2_FSPY_DIRECT 0xf3a30080
-#define F0900_P2_SPY_OUTDATA_BUS  0xf3a30038
 #define F0900_P2_STUFF_MODE 0xf3a30007

 /*P2_FSTATUS*/
@@ -2160,117 +2142,137 @@

 /*P2_FSPYBER*/
 #define R0900_P2_FSPYBER 0xf3b2
-#define F0900_P2_FSPYOBS_XORREAD  0xf3b20040
-#define F0900_P2_FSPYBER_OBSMODE  0xf3b20020
 #define F0900_P2_FSPYBER_SYNCBYTE 0xf3b20010
 #define F0900_P2_FSPYBER_UNSYNC 0xf3b20008
 #define F0900_P2_FSPYBER_CTIME 0xf3b20007

 /*P1_IQCONST*/
 #define R0900_P1_IQCONST 0xf400
+#define IQCONST REGx(R0900_P1_IQCONST)
 #define F0900_P1_CONSTEL_SELECT 0xf4000060
 #define F0900_P1_IQSYMB_SEL 0xf400001f

 /*P1_NOSCFG*/
 #define R0900_P1_NOSCFG 0xf401
+#define NOSCFG REGx(R0900_P1_NOSCFG)
 #define F0900_P1_DUMMYPL_NOSDATA 0xf4010020
 #define F0900_P1_NOSPLH_BETA 0xf4010018
 #define F0900_P1_NOSDATA_BETA 0xf4010007

 /*P1_ISYMB*/
 #define R0900_P1_ISYMB 0xf402
+#define ISYMB REGx(R0900_P1_ISYMB)
 #define F0900_P1_I_SYMBOL 0xf40201ff

 /*P1_QSYMB*/
 #define R0900_P1_QSYMB 0xf403
+#define QSYMB REGx(R0900_P1_QSYMB)
 #define F0900_P1_Q_SYMBOL 0xf40301ff

 /*P1_AGC1CFG*/
 #define R0900_P1_AGC1CFG 0xf404
+#define AGC1CFG REGx(R0900_P1_AGC1CFG)
 #define F0900_P1_DC_FROZEN 0xf4040080
 #define F0900_P1_DC_CORRECT 0xf4040040
 #define F0900_P1_AMM_FROZEN 0xf4040020
 #define F0900_P1_AMM_CORRECT 0xf4040010
 #define F0900_P1_QUAD_FROZEN 0xf4040008
 #define F0900_P1_QUAD_CORRECT 0xf4040004
-#define F0900_P1_DCCOMP_SLOW  0xf4040002
-#define F0900_P1_IQMISM_SLOW  0xf4040001

 /*P1_AGC1CN*/
 #define R0900_P1_AGC1CN 0xf406
+#define AGC1CN REGx(R0900_P1_AGC1CN)
 #define F0900_P1_AGC1_LOCKED 0xf4060080
-#define F0900_P1_AGC1_OVERFLOW  0xf4060040
-#define F0900_P1_AGC1_NOSLOWLK  0xf4060020
 #define F0900_P1_AGC1_MINPOWER 0xf4060010
 #define F0900_P1_AGCOUT_FAST 0xf4060008
 #define F0900_P1_AGCIQ_BETA 0xf4060007

 /*P1_AGC1REF*/
 #define R0900_P1_AGC1REF 0xf407
+#define AGC1REF REGx(R0900_P1_AGC1REF)
 #define F0900_P1_AGCIQ_REF 0xf40700ff

 /*P1_IDCCOMP*/
 #define R0900_P1_IDCCOMP 0xf408
+#define IDCCOMP REGx(R0900_P1_IDCCOMP)
 #define F0900_P1_IAVERAGE_ADJ 0xf40801ff

 /*P1_QDCCOMP*/
 #define R0900_P1_QDCCOMP 0xf409
+#define QDCCOMP REGx(R0900_P1_QDCCOMP)
 #define F0900_P1_QAVERAGE_ADJ 0xf40901ff

 /*P1_POWERI*/
 #define R0900_P1_POWERI 0xf40a
+#define POWERI REGx(R0900_P1_POWERI)
 #define F0900_P1_POWER_I 0xf40a00ff
+#define POWER_I FLDx(F0900_P1_POWER_I)

 /*P1_POWERQ*/
 #define R0900_P1_POWERQ 0xf40b
+#define POWERQ REGx(R0900_P1_POWERQ)
 #define F0900_P1_POWER_Q 0xf40b00ff
+#define POWER_Q FLDx(F0900_P1_POWER_Q)

 /*P1_AGC1AMM*/
 #define R0900_P1_AGC1AMM 0xf40c
+#define AGC1AMM REGx(R0900_P1_AGC1AMM)
 #define F0900_P1_AMM_VALUE 0xf40c00ff

 /*P1_AGC1QUAD*/
 #define R0900_P1_AGC1QUAD 0xf40d
+#define AGC1QUAD REGx(R0900_P1_AGC1QUAD)
 #define F0900_P1_QUAD_VALUE 0xf40d01ff

 /*P1_AGCIQIN1*/
 #define R0900_P1_AGCIQIN1 0xf40e
+#define AGCIQIN1 REGx(R0900_P1_AGCIQIN1)
 #define F0900_P1_AGCIQ_VALUE1 0xf40e00ff
+#define AGCIQ_VALUE1 FLDx(F0900_P1_AGCIQ_VALUE1)

 /*P1_AGCIQIN0*/
 #define R0900_P1_AGCIQIN0 0xf40f
+#define AGCIQIN0 REGx(R0900_P1_AGCIQIN0)
 #define F0900_P1_AGCIQ_VALUE0 0xf40f00ff
+#define AGCIQ_VALUE0 FLDx(F0900_P1_AGCIQ_VALUE0)

 /*P1_DEMOD*/
 #define R0900_P1_DEMOD 0xf410
-#define F0900_P1_DEMOD_STOP  0xf4100040
+#define DEMOD REGx(R0900_P1_DEMOD)
+#define F0900_P1_MANUALS2_ROLLOFF 0xf4100080
+#define MANUALS2_ROLLOFF FLDx(F0900_P1_MANUALS2_ROLLOFF)
+
 #define F0900_P1_SPECINV_CONTROL 0xf4100030
+#define SPECINV_CONTROL FLDx(F0900_P1_SPECINV_CONTROL)
 #define F0900_P1_FORCE_ENASAMP 0xf4100008
-#define F0900_P1_MANUAL_ROLLOFF  0xf4100004
+#define F0900_P1_MANUALSX_ROLLOFF 0xf4100004
+#define MANUALSX_ROLLOFF FLDx(F0900_P1_MANUALSX_ROLLOFF)
 #define F0900_P1_ROLLOFF_CONTROL 0xf4100003
+#define ROLLOFF_CONTROL FLDx(F0900_P1_ROLLOFF_CONTROL)

 /*P1_DMDMODCOD*/
 #define R0900_P1_DMDMODCOD 0xf411
+#define DMDMODCOD REGx(R0900_P1_DMDMODCOD)
 #define F0900_P1_MANUAL_MODCOD 0xf4110080
 #define F0900_P1_DEMOD_MODCOD 0xf411007c
+#define DEMOD_MODCOD FLDx(F0900_P1_DEMOD_MODCOD)
 #define F0900_P1_DEMOD_TYPE 0xf4110003
+#define DEMOD_TYPE FLDx(F0900_P1_DEMOD_TYPE)

 /*P1_DSTATUS*/
 #define R0900_P1_DSTATUS 0xf412
+#define DSTATUS REGx(R0900_P1_DSTATUS)
 #define F0900_P1_CAR_LOCK 0xf4120080
 #define F0900_P1_TMGLOCK_QUALITY 0xf4120060
-#define F0900_P1_SDVBS1_ENABLE  0xf4120010
+#define TMGLOCK_QUALITY FLDx(F0900_P1_TMGLOCK_QUALITY)
 #define F0900_P1_LOCK_DEFINITIF 0xf4120008
-#define F0900_P1_TIMING_IS_LOCKED  0xf4120004
-#define F0900_P1_COARSE_TMGLOCK  0xf4120002
-#define F0900_P1_COARSE_CARLOCK  0xf4120001
+#define LOCK_DEFINITIF FLDx(F0900_P1_LOCK_DEFINITIF)
+#define F0900_P1_OVADC_DETECT 0xf4120001

 /*P1_DSTATUS2*/
 #define R0900_P1_DSTATUS2 0xf413
+#define DSTATUS2 REGx(R0900_P1_DSTATUS2)
 #define F0900_P1_DEMOD_DELOCK 0xf4130080
-#define F0900_P1_DEMOD_TIMEOUT  0xf4130040
-#define F0900_P1_MODCODRQ_SYNCTAG  0xf4130020
-#define F0900_P1_POLYPH_SATEVENT  0xf4130010
 #define F0900_P1_AGC1_NOSIGNALACK 0xf4130008
 #define F0900_P1_AGC2_OVERFLOW 0xf4130004
 #define F0900_P1_CFR_OVERFLOW 0xf4130002
@@ -2278,250 +2280,265 @@

 /*P1_DMDCFGMD*/
 #define R0900_P1_DMDCFGMD 0xf414
+#define DMDCFGMD REGx(R0900_P1_DMDCFGMD)
 #define F0900_P1_DVBS2_ENABLE 0xf4140080
+#define DVBS2_ENABLE FLDx(F0900_P1_DVBS2_ENABLE)
 #define F0900_P1_DVBS1_ENABLE 0xf4140040
-#define F0900_P1_CFR_AUTOSCAN  0xf4140020
+#define DVBS1_ENABLE FLDx(F0900_P1_DVBS1_ENABLE)
 #define F0900_P1_SCAN_ENABLE 0xf4140010
-#define F0900_P1_TUN_AUTOSCAN  0xf4140008
-#define F0900_P1_NOFORCE_RELOCK  0xf4140004
+#define SCAN_ENABLE FLDx(F0900_P1_SCAN_ENABLE)
+#define F0900_P1_CFR_AUTOSCAN 0xf4140008
+#define CFR_AUTOSCAN FLDx(F0900_P1_CFR_AUTOSCAN)
 #define F0900_P1_TUN_RNG 0xf4140003

 /*P1_DMDCFG2*/
 #define R0900_P1_DMDCFG2 0xf415
-#define F0900_P1_AGC1_WAITLOCK  0xf4150080
+#define DMDCFG2 REGx(R0900_P1_DMDCFG2)
 #define F0900_P1_S1S2_SEQUENTIAL 0xf4150040
-#define F0900_P1_OVERFLOW_TIMEOUT  0xf4150020
-#define F0900_P1_SCANFAIL_TIMEOUT  0xf4150010
-#define F0900_P1_DMDTOUT_BACK  0xf4150008
-#define F0900_P1_CARLOCK_S1ENABLE  0xf4150004
-#define F0900_P1_COARSE_LK3MODE  0xf4150002
-#define F0900_P1_COARSE_LK2MODE  0xf4150001
+#define S1S2_SEQUENTIAL FLDx(F0900_P1_S1S2_SEQUENTIAL)
+#define F0900_P1_INFINITE_RELOCK 0xf4150010

 /*P1_DMDISTATE*/
 #define R0900_P1_DMDISTATE 0xf416
-#define F0900_P1_I2C_NORESETDMODE  0xf4160080
-#define F0900_P1_FORCE_ETAPED  0xf4160040
-#define F0900_P1_SDMDRST_DIRCLK  0xf4160020
+#define DMDISTATE REGx(R0900_P1_DMDISTATE)
 #define F0900_P1_I2C_DEMOD_MODE 0xf416001f
+#define DEMOD_MODE FLDx(F0900_P1_I2C_DEMOD_MODE)

 /*P1_DMDT0M*/
 #define R0900_P1_DMDT0M 0xf417
+#define DMDT0M REGx(R0900_P1_DMDT0M)
 #define F0900_P1_DMDT0_MIN 0xf41700ff

 /*P1_DMDSTATE*/
 #define R0900_P1_DMDSTATE 0xf41b
-#define F0900_P1_DEMOD_LOCKED  0xf41b0080
+#define DMDSTATE REGx(R0900_P1_DMDSTATE)
 #define F0900_P1_HEADER_MODE 0xf41b0060
-#define F0900_P1_DEMOD_MODE  0xf41b001f
+#define HEADER_MODE FLDx(F0900_P1_HEADER_MODE)

 /*P1_DMDFLYW*/
 #define R0900_P1_DMDFLYW 0xf41c
+#define DMDFLYW REGx(R0900_P1_DMDFLYW)
 #define F0900_P1_I2C_IRQVAL 0xf41c00f0
 #define F0900_P1_FLYWHEEL_CPT 0xf41c000f
+#define FLYWHEEL_CPT FLDx(F0900_P1_FLYWHEEL_CPT)

 /*P1_DSTATUS3*/
 #define R0900_P1_DSTATUS3 0xf41d
-#define F0900_P1_CFR_ZIGZAG  0xf41d0080
+#define DSTATUS3 REGx(R0900_P1_DSTATUS3)
 #define F0900_P1_DEMOD_CFGMODE 0xf41d0060
-#define F0900_P1_GAMMA_LOWBAUDRATE  0xf41d0010
-#define F0900_P1_RELOCK_MODE  0xf41d0008
-#define F0900_P1_DEMOD_FAIL  0xf41d0004
-#define F0900_P1_ETAPE1A_DVBXMEM  0xf41d0003

 /*P1_DMDCFG3*/
 #define R0900_P1_DMDCFG3 0xf41e
-#define F0900_P1_DVBS1_TMGWAIT  0xf41e0080
-#define F0900_P1_NO_BWCENTERING  0xf41e0040
-#define F0900_P1_INV_SEQSRCH  0xf41e0020
-#define F0900_P1_DIS_SFRUPLOW_TRK  0xf41e0010
+#define DMDCFG3 REGx(R0900_P1_DMDCFG3)
 #define F0900_P1_NOSTOP_FIFOFULL 0xf41e0008
-#define F0900_P1_LOCKTIME_MODE  0xf41e0007

 /*P1_DMDCFG4*/
 #define R0900_P1_DMDCFG4 0xf41f
+#define DMDCFG4 REGx(R0900_P1_DMDCFG4)
 #define F0900_P1_TUNER_NRELAUNCH 0xf41f0008
-#define F0900_P1_DIS_CLKENABLE  0xf41f0004
-#define F0900_P1_DIS_HDRDIVLOCK  0xf41f0002
-#define F0900_P1_NO_TNRWBINIT  0xf41f0001

 /*P1_CORRELMANT*/
 #define R0900_P1_CORRELMANT 0xf420
+#define CORRELMANT REGx(R0900_P1_CORRELMANT)
 #define F0900_P1_CORREL_MANT 0xf42000ff

 /*P1_CORRELABS*/
 #define R0900_P1_CORRELABS 0xf421
+#define CORRELABS REGx(R0900_P1_CORRELABS)
 #define F0900_P1_CORREL_ABS 0xf42100ff

 /*P1_CORRELEXP*/
 #define R0900_P1_CORRELEXP 0xf422
+#define CORRELEXP REGx(R0900_P1_CORRELEXP)
 #define F0900_P1_CORREL_ABSEXP 0xf42200f0
 #define F0900_P1_CORREL_EXP 0xf422000f

 /*P1_PLHMODCOD*/
 #define R0900_P1_PLHMODCOD 0xf424
+#define PLHMODCOD REGx(R0900_P1_PLHMODCOD)
 #define F0900_P1_SPECINV_DEMOD 0xf4240080
+#define SPECINV_DEMOD FLDx(F0900_P1_SPECINV_DEMOD)
 #define F0900_P1_PLH_MODCOD 0xf424007c
 #define F0900_P1_PLH_TYPE 0xf4240003

-/*P1_AGCK32*/
-#define R0900_P1_AGCK32  0xf42b
-#define F0900_P1_R3ADJOFF_32APSK  0xf42b0080
-#define F0900_P1_R2ADJOFF_32APSK  0xf42b0040
-#define F0900_P1_R1ADJOFF_32APSK  0xf42b0020
-#define F0900_P1_RADJ_32APSK  0xf42b001f
+/*P1_DMDREG*/
+#define R0900_P1_DMDREG 0xf425
+#define DMDREG REGx(R0900_P1_DMDREG)
+#define F0900_P1_DECIM_PLFRAMES 0xf4250001

 /*P1_AGC2O*/
 #define R0900_P1_AGC2O 0xf42c
-#define F0900_P1_AGC2REF_ADJUSTING  0xf42c0080
-#define F0900_P1_AGC2_COARSEFAST  0xf42c0040
-#define F0900_P1_AGC2_LKSQRT  0xf42c0020
-#define F0900_P1_AGC2_LKMODE  0xf42c0010
-#define F0900_P1_AGC2_LKEQUA  0xf42c0008
+#define AGC2O REGx(R0900_P1_AGC2O)
 #define F0900_P1_AGC2_COEF 0xf42c0007

 /*P1_AGC2REF*/
 #define R0900_P1_AGC2REF 0xf42d
+#define AGC2REF REGx(R0900_P1_AGC2REF)
 #define F0900_P1_AGC2_REF 0xf42d00ff

 /*P1_AGC1ADJ*/
 #define R0900_P1_AGC1ADJ 0xf42e
-#define F0900_P1_AGC1ADJ_MANUAL  0xf42e0080
-#define F0900_P1_AGC1_ADJUSTED  0xf42e017f
+#define AGC1ADJ REGx(R0900_P1_AGC1ADJ)
+#define F0900_P1_AGC1_ADJUSTED 0xf42e007f

 /*P1_AGC2I1*/
 #define R0900_P1_AGC2I1 0xf436
+#define AGC2I1 REGx(R0900_P1_AGC2I1)
 #define F0900_P1_AGC2_INTEGRATOR1 0xf43600ff

 /*P1_AGC2I0*/
 #define R0900_P1_AGC2I0 0xf437
+#define AGC2I0 REGx(R0900_P1_AGC2I0)
 #define F0900_P1_AGC2_INTEGRATOR0 0xf43700ff

 /*P1_CARCFG*/
 #define R0900_P1_CARCFG 0xf438
+#define CARCFG REGx(R0900_P1_CARCFG)
 #define F0900_P1_CFRUPLOW_AUTO 0xf4380080
 #define F0900_P1_CFRUPLOW_TEST 0xf4380040
-#define F0900_P1_EN_CAR2CENTER  0xf4380020
-#define F0900_P1_CARHDR_NODIV8  0xf4380010
-#define F0900_P1_I2C_ROTA  0xf4380008
 #define F0900_P1_ROTAON 0xf4380004
 #define F0900_P1_PH_DET_ALGO 0xf4380003

 /*P1_ACLC*/
 #define R0900_P1_ACLC 0xf439
-#define F0900_P1_STOP_S2ALPHA  0xf43900c0
+#define ACLC REGx(R0900_P1_ACLC)
 #define F0900_P1_CAR_ALPHA_MANT 0xf4390030
 #define F0900_P1_CAR_ALPHA_EXP 0xf439000f

 /*P1_BCLC*/
 #define R0900_P1_BCLC 0xf43a
-#define F0900_P1_STOP_S2BETA  0xf43a00c0
+#define BCLC REGx(R0900_P1_BCLC)
 #define F0900_P1_CAR_BETA_MANT 0xf43a0030
 #define F0900_P1_CAR_BETA_EXP 0xf43a000f

 /*P1_CARFREQ*/
 #define R0900_P1_CARFREQ 0xf43d
+#define CARFREQ REGx(R0900_P1_CARFREQ)
 #define F0900_P1_KC_COARSE_EXP 0xf43d00f0
 #define F0900_P1_BETA_FREQ 0xf43d000f

 /*P1_CARHDR*/
 #define R0900_P1_CARHDR 0xf43e
+#define CARHDR REGx(R0900_P1_CARHDR)
 #define F0900_P1_K_FREQ_HDR 0xf43e00ff

 /*P1_LDT*/
 #define R0900_P1_LDT 0xf43f
+#define LDT REGx(R0900_P1_LDT)
 #define F0900_P1_CARLOCK_THRES 0xf43f01ff

 /*P1_LDT2*/
 #define R0900_P1_LDT2 0xf440
+#define LDT2 REGx(R0900_P1_LDT2)
 #define F0900_P1_CARLOCK_THRES2 0xf44001ff

 /*P1_CFRICFG*/
 #define R0900_P1_CFRICFG 0xf441
-#define F0900_P1_CFRINIT_UNVALRNG  0xf4410080
-#define F0900_P1_CFRINIT_LUNVALCPT  0xf4410040
-#define F0900_P1_CFRINIT_ABORTDBL  0xf4410020
-#define F0900_P1_CFRINIT_ABORTPRED  0xf4410010
-#define F0900_P1_CFRINIT_UNVALSKIP  0xf4410008
-#define F0900_P1_CFRINIT_CSTINC  0xf4410004
+#define CFRICFG REGx(R0900_P1_CFRICFG)
 #define F0900_P1_NEG_CFRSTEP 0xf4410001

 /*P1_CFRUP1*/
 #define R0900_P1_CFRUP1 0xf442
+#define CFRUP1 REGx(R0900_P1_CFRUP1)
 #define F0900_P1_CFR_UP1 0xf44201ff
+#define CFR_UP1 FLDx(F0900_P1_CFR_UP1)

 /*P1_CFRUP0*/
 #define R0900_P1_CFRUP0 0xf443
+#define CFRUP0 REGx(R0900_P1_CFRUP0)
 #define F0900_P1_CFR_UP0 0xf44300ff
+#define CFR_UP0 FLDx(F0900_P1_CFR_UP0)

 /*P1_CFRLOW1*/
 #define R0900_P1_CFRLOW1 0xf446
+#define CFRLOW1 REGx(R0900_P1_CFRLOW1)
 #define F0900_P1_CFR_LOW1 0xf44601ff
+#define CFR_LOW1 FLDx(F0900_P1_CFR_LOW1)

 /*P1_CFRLOW0*/
 #define R0900_P1_CFRLOW0 0xf447
+#define CFRLOW0 REGx(R0900_P1_CFRLOW0)
 #define F0900_P1_CFR_LOW0 0xf44700ff
+#define CFR_LOW0 FLDx(F0900_P1_CFR_LOW0)

 /*P1_CFRINIT1*/
 #define R0900_P1_CFRINIT1 0xf448
+#define CFRINIT1 REGx(R0900_P1_CFRINIT1)
 #define F0900_P1_CFR_INIT1 0xf44801ff
+#define CFR_INIT1 FLDx(F0900_P1_CFR_INIT1)

 /*P1_CFRINIT0*/
 #define R0900_P1_CFRINIT0 0xf449
+#define CFRINIT0 REGx(R0900_P1_CFRINIT0)
 #define F0900_P1_CFR_INIT0 0xf44900ff
+#define CFR_INIT0 FLDx(F0900_P1_CFR_INIT0)

 /*P1_CFRINC1*/
 #define R0900_P1_CFRINC1 0xf44a
+#define CFRINC1 REGx(R0900_P1_CFRINC1)
 #define F0900_P1_MANUAL_CFRINC 0xf44a0080
-#define F0900_P1_CFR_INC1  0xf44a017f
+#define F0900_P1_CFR_INC1 0xf44a003f

 /*P1_CFRINC0*/
 #define R0900_P1_CFRINC0 0xf44b
-#define F0900_P1_CFR_INC0  0xf44b00f0
+#define CFRINC0 REGx(R0900_P1_CFRINC0)
+#define F0900_P1_CFR_INC0 0xf44b00f8

 /*P1_CFR2*/
 #define R0900_P1_CFR2 0xf44c
+#define CFR2 REGx(R0900_P1_CFR2)
 #define F0900_P1_CAR_FREQ2 0xf44c01ff
+#define CAR_FREQ2 FLDx(F0900_P1_CAR_FREQ2)

 /*P1_CFR1*/
 #define R0900_P1_CFR1 0xf44d
+#define CFR1 REGx(R0900_P1_CFR1)
 #define F0900_P1_CAR_FREQ1 0xf44d00ff
+#define CAR_FREQ1 FLDx(F0900_P1_CAR_FREQ1)

 /*P1_CFR0*/
 #define R0900_P1_CFR0 0xf44e
+#define CFR0 REGx(R0900_P1_CFR0)
 #define F0900_P1_CAR_FREQ0 0xf44e00ff
+#define CAR_FREQ0 FLDx(F0900_P1_CAR_FREQ0)

 /*P1_LDI*/
 #define R0900_P1_LDI 0xf44f
+#define LDI REGx(R0900_P1_LDI)
 #define F0900_P1_LOCK_DET_INTEGR 0xf44f01ff

 /*P1_TMGCFG*/
 #define R0900_P1_TMGCFG 0xf450
+#define TMGCFG REGx(R0900_P1_TMGCFG)
 #define F0900_P1_TMGLOCK_BETA 0xf45000c0
-#define F0900_P1_NOTMG_GROUPDELAY  0xf4500020
 #define F0900_P1_DO_TIMING_CORR 0xf4500010
-#define F0900_P1_MANUAL_SCAN  0xf450000c
 #define F0900_P1_TMG_MINFREQ 0xf4500003

 /*P1_RTC*/
 #define R0900_P1_RTC 0xf451
+#define RTC REGx(R0900_P1_RTC)
 #define F0900_P1_TMGALPHA_EXP 0xf45100f0
 #define F0900_P1_TMGBETA_EXP 0xf451000f

 /*P1_RTCS2*/
 #define R0900_P1_RTCS2 0xf452
+#define RTCS2 REGx(R0900_P1_RTCS2)
 #define F0900_P1_TMGALPHAS2_EXP 0xf45200f0
 #define F0900_P1_TMGBETAS2_EXP 0xf452000f

 /*P1_TMGTHRISE*/
 #define R0900_P1_TMGTHRISE 0xf453
+#define TMGTHRISE REGx(R0900_P1_TMGTHRISE)
 #define F0900_P1_TMGLOCK_THRISE 0xf45300ff

 /*P1_TMGTHFALL*/
 #define R0900_P1_TMGTHFALL 0xf454
+#define TMGTHFALL REGx(R0900_P1_TMGTHFALL)
 #define F0900_P1_TMGLOCK_THFALL 0xf45400ff

 /*P1_SFRUPRATIO*/
 #define R0900_P1_SFRUPRATIO 0xf455
+#define SFRUPRATIO REGx(R0900_P1_SFRUPRATIO)
 #define F0900_P1_SFR_UPRATIO 0xf45500ff

 /*P1_SFRLOWRATIO*/
@@ -2530,425 +2547,511 @@

 /*P1_KREFTMG*/
 #define R0900_P1_KREFTMG 0xf458
+#define KREFTMG REGx(R0900_P1_KREFTMG)
 #define F0900_P1_KREF_TMG 0xf45800ff

 /*P1_SFRSTEP*/
 #define R0900_P1_SFRSTEP 0xf459
+#define SFRSTEP REGx(R0900_P1_SFRSTEP)
 #define F0900_P1_SFR_SCANSTEP 0xf45900f0
 #define F0900_P1_SFR_CENTERSTEP 0xf459000f

 /*P1_TMGCFG2*/
 #define R0900_P1_TMGCFG2 0xf45a
-#define F0900_P1_DIS_AUTOSAMP  0xf45a0008
-#define F0900_P1_SCANINIT_QUART  0xf45a0004
-#define F0900_P1_NOTMG_DVBS1DERAT  0xf45a0002
+#define TMGCFG2 REGx(R0900_P1_TMGCFG2)
 #define F0900_P1_SFRRATIO_FINE 0xf45a0001

+/*P1_KREFTMG2*/
+#define R0900_P1_KREFTMG2 0xf45b
+#define KREFTMG2 REGx(R0900_P1_KREFTMG2)
+#define F0900_P1_KREF_TMG2 0xf45b00ff
+
 /*P1_SFRINIT1*/
 #define R0900_P1_SFRINIT1 0xf45e
-#define F0900_P1_SFR_INIT1  0xf45e00ff
+#define SFRINIT1 REGx(R0900_P1_SFRINIT1)
+#define F0900_P1_SFR_INIT1 0xf45e007f

 /*P1_SFRINIT0*/
 #define R0900_P1_SFRINIT0 0xf45f
+#define SFRINIT0 REGx(R0900_P1_SFRINIT0)
 #define F0900_P1_SFR_INIT0 0xf45f00ff

 /*P1_SFRUP1*/
 #define R0900_P1_SFRUP1 0xf460
+#define SFRUP1 REGx(R0900_P1_SFRUP1)
 #define F0900_P1_AUTO_GUP 0xf4600080
+#define AUTO_GUP FLDx(F0900_P1_AUTO_GUP)
 #define F0900_P1_SYMB_FREQ_UP1 0xf460007f

 /*P1_SFRUP0*/
 #define R0900_P1_SFRUP0 0xf461
+#define SFRUP0 REGx(R0900_P1_SFRUP0)
 #define F0900_P1_SYMB_FREQ_UP0 0xf46100ff

 /*P1_SFRLOW1*/
 #define R0900_P1_SFRLOW1 0xf462
+#define SFRLOW1 REGx(R0900_P1_SFRLOW1)
 #define F0900_P1_AUTO_GLOW 0xf4620080
+#define AUTO_GLOW FLDx(F0900_P1_AUTO_GLOW)
 #define F0900_P1_SYMB_FREQ_LOW1 0xf462007f

 /*P1_SFRLOW0*/
 #define R0900_P1_SFRLOW0 0xf463
+#define SFRLOW0 REGx(R0900_P1_SFRLOW0)
 #define F0900_P1_SYMB_FREQ_LOW0 0xf46300ff

 /*P1_SFR3*/
 #define R0900_P1_SFR3 0xf464
+#define SFR3 REGx(R0900_P1_SFR3)
 #define F0900_P1_SYMB_FREQ3 0xf46400ff
+#define SYMB_FREQ3 FLDx(F0900_P1_SYMB_FREQ3)

 /*P1_SFR2*/
 #define R0900_P1_SFR2 0xf465
+#define SFR2 REGx(R0900_P1_SFR2)
 #define F0900_P1_SYMB_FREQ2 0xf46500ff
+#define SYMB_FREQ2 FLDx(F0900_P1_SYMB_FREQ2)

 /*P1_SFR1*/
 #define R0900_P1_SFR1 0xf466
+#define SFR1 REGx(R0900_P1_SFR1)
 #define F0900_P1_SYMB_FREQ1 0xf46600ff
+#define SYMB_FREQ1 FLDx(F0900_P1_SYMB_FREQ1)

 /*P1_SFR0*/
 #define R0900_P1_SFR0 0xf467
+#define SFR0 REGx(R0900_P1_SFR0)
 #define F0900_P1_SYMB_FREQ0 0xf46700ff
+#define SYMB_FREQ0 FLDx(F0900_P1_SYMB_FREQ0)

 /*P1_TMGREG2*/
 #define R0900_P1_TMGREG2 0xf468
+#define TMGREG2 REGx(R0900_P1_TMGREG2)
 #define F0900_P1_TMGREG2 0xf46800ff

 /*P1_TMGREG1*/
 #define R0900_P1_TMGREG1 0xf469
+#define TMGREG1 REGx(R0900_P1_TMGREG1)
 #define F0900_P1_TMGREG1 0xf46900ff

 /*P1_TMGREG0*/
 #define R0900_P1_TMGREG0 0xf46a
+#define TMGREG0 REGx(R0900_P1_TMGREG0)
 #define F0900_P1_TMGREG0 0xf46a00ff

 /*P1_TMGLOCK1*/
 #define R0900_P1_TMGLOCK1 0xf46b
+#define TMGLOCK1 REGx(R0900_P1_TMGLOCK1)
 #define F0900_P1_TMGLOCK_LEVEL1 0xf46b01ff

 /*P1_TMGLOCK0*/
 #define R0900_P1_TMGLOCK0 0xf46c
+#define TMGLOCK0 REGx(R0900_P1_TMGLOCK0)
 #define F0900_P1_TMGLOCK_LEVEL0 0xf46c00ff

 /*P1_TMGOBS*/
 #define R0900_P1_TMGOBS 0xf46d
+#define TMGOBS REGx(R0900_P1_TMGOBS)
 #define F0900_P1_ROLLOFF_STATUS 0xf46d00c0
-#define F0900_P1_SCAN_SIGN  0xf46d0030
-#define F0900_P1_TMG_SCANNING  0xf46d0008
-#define F0900_P1_CHCENTERING_MODE  0xf46d0004
-#define F0900_P1_TMG_SCANFAIL  0xf46d0002
+#define ROLLOFF_STATUS FLDx(F0900_P1_ROLLOFF_STATUS)

 /*P1_EQUALCFG*/
 #define R0900_P1_EQUALCFG 0xf46f
-#define F0900_P1_NOTMG_NEGALWAIT  0xf46f0080
+#define EQUALCFG REGx(R0900_P1_EQUALCFG)
 #define F0900_P1_EQUAL_ON 0xf46f0040
-#define F0900_P1_SEL_EQUALCOR  0xf46f0038
 #define F0900_P1_MU_EQUALDFE 0xf46f0007

 /*P1_EQUAI1*/
 #define R0900_P1_EQUAI1 0xf470
+#define EQUAI1 REGx(R0900_P1_EQUAI1)
 #define F0900_P1_EQUA_ACCI1 0xf47001ff

 /*P1_EQUAQ1*/
 #define R0900_P1_EQUAQ1 0xf471
+#define EQUAQ1 REGx(R0900_P1_EQUAQ1)
 #define F0900_P1_EQUA_ACCQ1 0xf47101ff

 /*P1_EQUAI2*/
 #define R0900_P1_EQUAI2 0xf472
+#define EQUAI2 REGx(R0900_P1_EQUAI2)
 #define F0900_P1_EQUA_ACCI2 0xf47201ff

 /*P1_EQUAQ2*/
 #define R0900_P1_EQUAQ2 0xf473
+#define EQUAQ2 REGx(R0900_P1_EQUAQ2)
 #define F0900_P1_EQUA_ACCQ2 0xf47301ff

 /*P1_EQUAI3*/
 #define R0900_P1_EQUAI3 0xf474
+#define EQUAI3 REGx(R0900_P1_EQUAI3)
 #define F0900_P1_EQUA_ACCI3 0xf47401ff

 /*P1_EQUAQ3*/
 #define R0900_P1_EQUAQ3 0xf475
+#define EQUAQ3 REGx(R0900_P1_EQUAQ3)
 #define F0900_P1_EQUA_ACCQ3 0xf47501ff

 /*P1_EQUAI4*/
 #define R0900_P1_EQUAI4 0xf476
+#define EQUAI4 REGx(R0900_P1_EQUAI4)
 #define F0900_P1_EQUA_ACCI4 0xf47601ff

 /*P1_EQUAQ4*/
 #define R0900_P1_EQUAQ4 0xf477
+#define EQUAQ4 REGx(R0900_P1_EQUAQ4)
 #define F0900_P1_EQUA_ACCQ4 0xf47701ff

 /*P1_EQUAI5*/
 #define R0900_P1_EQUAI5 0xf478
+#define EQUAI5 REGx(R0900_P1_EQUAI5)
 #define F0900_P1_EQUA_ACCI5 0xf47801ff

 /*P1_EQUAQ5*/
 #define R0900_P1_EQUAQ5 0xf479
+#define EQUAQ5 REGx(R0900_P1_EQUAQ5)
 #define F0900_P1_EQUA_ACCQ5 0xf47901ff

 /*P1_EQUAI6*/
 #define R0900_P1_EQUAI6 0xf47a
+#define EQUAI6 REGx(R0900_P1_EQUAI6)
 #define F0900_P1_EQUA_ACCI6 0xf47a01ff

 /*P1_EQUAQ6*/
 #define R0900_P1_EQUAQ6 0xf47b
+#define EQUAQ6 REGx(R0900_P1_EQUAQ6)
 #define F0900_P1_EQUA_ACCQ6 0xf47b01ff

 /*P1_EQUAI7*/
 #define R0900_P1_EQUAI7 0xf47c
+#define EQUAI7 REGx(R0900_P1_EQUAI7)
 #define F0900_P1_EQUA_ACCI7 0xf47c01ff

 /*P1_EQUAQ7*/
 #define R0900_P1_EQUAQ7 0xf47d
+#define EQUAQ7 REGx(R0900_P1_EQUAQ7)
 #define F0900_P1_EQUA_ACCQ7 0xf47d01ff

 /*P1_EQUAI8*/
 #define R0900_P1_EQUAI8 0xf47e
+#define EQUAI8 REGx(R0900_P1_EQUAI8)
 #define F0900_P1_EQUA_ACCI8 0xf47e01ff

 /*P1_EQUAQ8*/
 #define R0900_P1_EQUAQ8 0xf47f
+#define EQUAQ8 REGx(R0900_P1_EQUAQ8)
 #define F0900_P1_EQUA_ACCQ8 0xf47f01ff

 /*P1_NNOSDATAT1*/
 #define R0900_P1_NNOSDATAT1 0xf480
+#define NNOSDATAT1 REGx(R0900_P1_NNOSDATAT1)
 #define F0900_P1_NOSDATAT_NORMED1 0xf48000ff
+#define NOSDATAT_NORMED1 FLDx(F0900_P1_NOSDATAT_NORMED1)

 /*P1_NNOSDATAT0*/
 #define R0900_P1_NNOSDATAT0 0xf481
+#define NNOSDATAT0 REGx(R0900_P1_NNOSDATAT0)
 #define F0900_P1_NOSDATAT_NORMED0 0xf48100ff
+#define NOSDATAT_NORMED0 FLDx(F0900_P1_NOSDATAT_NORMED0)

 /*P1_NNOSDATA1*/
 #define R0900_P1_NNOSDATA1 0xf482
+#define NNOSDATA1 REGx(R0900_P1_NNOSDATA1)
 #define F0900_P1_NOSDATA_NORMED1 0xf48200ff

 /*P1_NNOSDATA0*/
 #define R0900_P1_NNOSDATA0 0xf483
+#define NNOSDATA0 REGx(R0900_P1_NNOSDATA0)
 #define F0900_P1_NOSDATA_NORMED0 0xf48300ff

 /*P1_NNOSPLHT1*/
 #define R0900_P1_NNOSPLHT1 0xf484
+#define NNOSPLHT1 REGx(R0900_P1_NNOSPLHT1)
 #define F0900_P1_NOSPLHT_NORMED1 0xf48400ff
+#define NOSPLHT_NORMED1 FLDx(F0900_P1_NOSPLHT_NORMED1)

 /*P1_NNOSPLHT0*/
 #define R0900_P1_NNOSPLHT0 0xf485
+#define NNOSPLHT0 REGx(R0900_P1_NNOSPLHT0)
 #define F0900_P1_NOSPLHT_NORMED0 0xf48500ff
+#define NOSPLHT_NORMED0 FLDx(F0900_P1_NOSPLHT_NORMED0)

 /*P1_NNOSPLH1*/
 #define R0900_P1_NNOSPLH1 0xf486
+#define NNOSPLH1 REGx(R0900_P1_NNOSPLH1)
 #define F0900_P1_NOSPLH_NORMED1 0xf48600ff

 /*P1_NNOSPLH0*/
 #define R0900_P1_NNOSPLH0 0xf487
+#define NNOSPLH0 REGx(R0900_P1_NNOSPLH0)
 #define F0900_P1_NOSPLH_NORMED0 0xf48700ff

 /*P1_NOSDATAT1*/
 #define R0900_P1_NOSDATAT1 0xf488
+#define NOSDATAT1 REGx(R0900_P1_NOSDATAT1)
 #define F0900_P1_NOSDATAT_UNNORMED1 0xf48800ff

 /*P1_NOSDATAT0*/
 #define R0900_P1_NOSDATAT0 0xf489
+#define NOSDATAT0 REGx(R0900_P1_NOSDATAT0)
 #define F0900_P1_NOSDATAT_UNNORMED0 0xf48900ff

 /*P1_NOSDATA1*/
 #define R0900_P1_NOSDATA1 0xf48a
+#define NOSDATA1 REGx(R0900_P1_NOSDATA1)
 #define F0900_P1_NOSDATA_UNNORMED1 0xf48a00ff

 /*P1_NOSDATA0*/
 #define R0900_P1_NOSDATA0 0xf48b
+#define NOSDATA0 REGx(R0900_P1_NOSDATA0)
 #define F0900_P1_NOSDATA_UNNORMED0 0xf48b00ff

 /*P1_NOSPLHT1*/
 #define R0900_P1_NOSPLHT1 0xf48c
+#define NOSPLHT1 REGx(R0900_P1_NOSPLHT1)
 #define F0900_P1_NOSPLHT_UNNORMED1 0xf48c00ff

 /*P1_NOSPLHT0*/
 #define R0900_P1_NOSPLHT0 0xf48d
+#define NOSPLHT0 REGx(R0900_P1_NOSPLHT0)
 #define F0900_P1_NOSPLHT_UNNORMED0 0xf48d00ff

 /*P1_NOSPLH1*/
 #define R0900_P1_NOSPLH1 0xf48e
+#define NOSPLH1 REGx(R0900_P1_NOSPLH1)
 #define F0900_P1_NOSPLH_UNNORMED1 0xf48e00ff

 /*P1_NOSPLH0*/
 #define R0900_P1_NOSPLH0 0xf48f
+#define NOSPLH0 REGx(R0900_P1_NOSPLH0)
 #define F0900_P1_NOSPLH_UNNORMED0 0xf48f00ff

 /*P1_CAR2CFG*/
 #define R0900_P1_CAR2CFG 0xf490
-#define F0900_P1_DESCRAMB_OFF  0xf4900080
-#define F0900_P1_PN4_SELECT  0xf4900040
-#define F0900_P1_CFR2_STOPDVBS1  0xf4900020
-#define F0900_P1_STOP_CFR2UPDATE  0xf4900010
-#define F0900_P1_STOP_NCO2UPDATE  0xf4900008
+#define CAR2CFG REGx(R0900_P1_CAR2CFG)
+#define F0900_P1_CARRIER3_DISABLE 0xf4900040
 #define F0900_P1_ROTA2ON 0xf4900004
 #define F0900_P1_PH_DET_ALGO2 0xf4900003

-/*P1_ACLC2*/
-#define R0900_P1_ACLC2  0xf491
-#define F0900_P1_CAR2_PUNCT_ADERAT  0xf4910040
-#define F0900_P1_CAR2_ALPHA_MANT  0xf4910030
-#define F0900_P1_CAR2_ALPHA_EXP  0xf491000f
-
-/*P1_BCLC2*/
-#define R0900_P1_BCLC2  0xf492
-#define F0900_P1_DVBS2_NIP  0xf4920080
-#define F0900_P1_CAR2_PUNCT_BDERAT  0xf4920040
-#define F0900_P1_CAR2_BETA_MANT  0xf4920030
-#define F0900_P1_CAR2_BETA_EXP  0xf492000f
+/*P1_CFR2CFR1*/
+#define R0900_P1_CFR2CFR1 0xf491
+#define CFR2CFR1 REGx(R0900_P1_CFR2CFR1)
+#define F0900_P1_CFR2TOCFR1_DVBS1 0xf49100c0
+#define F0900_P1_EN_S2CAR2CENTER 0xf4910020
+#define F0900_P1_DIS_BCHERRCFR2 0xf4910010
+#define F0900_P1_CFR2TOCFR1_BETA 0xf4910007

 /*P1_CFR22*/
 #define R0900_P1_CFR22 0xf493
+#define CFR22 REGx(R0900_P1_CFR22)
 #define F0900_P1_CAR2_FREQ2 0xf49301ff

 /*P1_CFR21*/
 #define R0900_P1_CFR21 0xf494
+#define CFR21 REGx(R0900_P1_CFR21)
 #define F0900_P1_CAR2_FREQ1 0xf49400ff

 /*P1_CFR20*/
 #define R0900_P1_CFR20 0xf495
+#define CFR20 REGx(R0900_P1_CFR20)
 #define F0900_P1_CAR2_FREQ0 0xf49500ff

 /*P1_ACLC2S2Q*/
 #define R0900_P1_ACLC2S2Q 0xf497
+#define ACLC2S2Q REGx(R0900_P1_ACLC2S2Q)
 #define F0900_P1_ENAB_SPSKSYMB 0xf4970080
-#define F0900_P1_CAR2S2_QADERAT  0xf4970040
 #define F0900_P1_CAR2S2_Q_ALPH_M 0xf4970030
 #define F0900_P1_CAR2S2_Q_ALPH_E 0xf497000f

 /*P1_ACLC2S28*/
 #define R0900_P1_ACLC2S28 0xf498
+#define ACLC2S28 REGx(R0900_P1_ACLC2S28)
 #define F0900_P1_OLDI3Q_MODE 0xf4980080
-#define F0900_P1_CAR2S2_8ADERAT  0xf4980040
 #define F0900_P1_CAR2S2_8_ALPH_M 0xf4980030
 #define F0900_P1_CAR2S2_8_ALPH_E 0xf498000f

 /*P1_ACLC2S216A*/
 #define R0900_P1_ACLC2S216A 0xf499
+#define ACLC2S216A REGx(R0900_P1_ACLC2S216A)
+#define F0900_P1_DIS_C3STOPA2 0xf4990080
 #define F0900_P1_CAR2S2_16ADERAT 0xf4990040
 #define F0900_P1_CAR2S2_16A_ALPH_M 0xf4990030
 #define F0900_P1_CAR2S2_16A_ALPH_E 0xf499000f

 /*P1_ACLC2S232A*/
 #define R0900_P1_ACLC2S232A 0xf49a
+#define ACLC2S232A REGx(R0900_P1_ACLC2S232A)
 #define F0900_P1_CAR2S2_32ADERAT 0xf49a0040
 #define F0900_P1_CAR2S2_32A_ALPH_M 0xf49a0030
 #define F0900_P1_CAR2S2_32A_ALPH_E 0xf49a000f

 /*P1_BCLC2S2Q*/
 #define R0900_P1_BCLC2S2Q 0xf49c
-#define F0900_P1_DVBS2S2Q_NIP  0xf49c0080
-#define F0900_P1_CAR2S2_QBDERAT  0xf49c0040
+#define BCLC2S2Q REGx(R0900_P1_BCLC2S2Q)
 #define F0900_P1_CAR2S2_Q_BETA_M 0xf49c0030
 #define F0900_P1_CAR2S2_Q_BETA_E 0xf49c000f

 /*P1_BCLC2S28*/
 #define R0900_P1_BCLC2S28 0xf49d
-#define F0900_P1_DVBS2S28_NIP  0xf49d0080
-#define F0900_P1_CAR2S2_8BDERAT  0xf49d0040
+#define BCLC2S28 REGx(R0900_P1_BCLC2S28)
 #define F0900_P1_CAR2S2_8_BETA_M 0xf49d0030
 #define F0900_P1_CAR2S2_8_BETA_E 0xf49d000f

 /*P1_BCLC2S216A*/
 #define R0900_P1_BCLC2S216A 0xf49e
-#define F0900_P1_DVBS2S216A_NIP  0xf49e0080
-#define F0900_P1_CAR2S2_16BDERAT  0xf49e0040
-#define F0900_P1_CAR2S2_16A_BETA_M  0xf49e0030
-#define F0900_P1_CAR2S2_16A_BETA_E  0xf49e000f
+#define BCLC2S216A REGx(R0900_P1_BCLC2S216A)

 /*P1_BCLC2S232A*/
 #define R0900_P1_BCLC2S232A 0xf49f
-#define F0900_P1_DVBS2S232A_NIP  0xf49f0080
-#define F0900_P1_CAR2S2_32BDERAT  0xf49f0040
-#define F0900_P1_CAR2S2_32A_BETA_M  0xf49f0030
-#define F0900_P1_CAR2S2_32A_BETA_E  0xf49f000f
+#define BCLC2S232A REGx(R0900_P1_BCLC2S232A)

 /*P1_PLROOT2*/
 #define R0900_P1_PLROOT2 0xf4ac
-#define F0900_P1_SHORTFR_DISABLE  0xf4ac0080
-#define F0900_P1_LONGFR_DISABLE  0xf4ac0040
-#define F0900_P1_DUMMYPL_DISABLE  0xf4ac0020
-#define F0900_P1_SHORTFR_AVOID  0xf4ac0010
+#define PLROOT2 REGx(R0900_P1_PLROOT2)
 #define F0900_P1_PLSCRAMB_MODE 0xf4ac000c
 #define F0900_P1_PLSCRAMB_ROOT2 0xf4ac0003

 /*P1_PLROOT1*/
 #define R0900_P1_PLROOT1 0xf4ad
+#define PLROOT1 REGx(R0900_P1_PLROOT1)
 #define F0900_P1_PLSCRAMB_ROOT1 0xf4ad00ff

 /*P1_PLROOT0*/
 #define R0900_P1_PLROOT0 0xf4ae
+#define PLROOT0 REGx(R0900_P1_PLROOT0)
 #define F0900_P1_PLSCRAMB_ROOT0 0xf4ae00ff

 /*P1_MODCODLST0*/
 #define R0900_P1_MODCODLST0 0xf4b0
-#define F0900_P1_EN_TOKEN31  0xf4b00080
-#define F0900_P1_SYNCTAG_SELECT  0xf4b00040
-#define F0900_P1_MODCODRQ_MODE  0xf4b00030
+#define MODCODLST0 REGx(R0900_P1_MODCODLST0)

 /*P1_MODCODLST1*/
 #define R0900_P1_MODCODLST1 0xf4b1
+#define MODCODLST1 REGx(R0900_P1_MODCODLST1)
 #define F0900_P1_DIS_MODCOD29 0xf4b100f0
 #define F0900_P1_DIS_32PSK_9_10 0xf4b1000f

 /*P1_MODCODLST2*/
 #define R0900_P1_MODCODLST2 0xf4b2
+#define MODCODLST2 REGx(R0900_P1_MODCODLST2)
 #define F0900_P1_DIS_32PSK_8_9 0xf4b200f0
 #define F0900_P1_DIS_32PSK_5_6 0xf4b2000f

 /*P1_MODCODLST3*/
 #define R0900_P1_MODCODLST3 0xf4b3
+#define MODCODLST3 REGx(R0900_P1_MODCODLST3)
 #define F0900_P1_DIS_32PSK_4_5 0xf4b300f0
 #define F0900_P1_DIS_32PSK_3_4 0xf4b3000f

 /*P1_MODCODLST4*/
 #define R0900_P1_MODCODLST4 0xf4b4
+#define MODCODLST4 REGx(R0900_P1_MODCODLST4)
 #define F0900_P1_DIS_16PSK_9_10 0xf4b400f0
 #define F0900_P1_DIS_16PSK_8_9 0xf4b4000f

 /*P1_MODCODLST5*/
 #define R0900_P1_MODCODLST5 0xf4b5
+#define MODCODLST5 REGx(R0900_P1_MODCODLST5)
 #define F0900_P1_DIS_16PSK_5_6 0xf4b500f0
 #define F0900_P1_DIS_16PSK_4_5 0xf4b5000f

 /*P1_MODCODLST6*/
 #define R0900_P1_MODCODLST6 0xf4b6
+#define MODCODLST6 REGx(R0900_P1_MODCODLST6)
 #define F0900_P1_DIS_16PSK_3_4 0xf4b600f0
 #define F0900_P1_DIS_16PSK_2_3 0xf4b6000f

 /*P1_MODCODLST7*/
 #define R0900_P1_MODCODLST7 0xf4b7
+#define MODCODLST7 REGx(R0900_P1_MODCODLST7)
 #define F0900_P1_DIS_8P_9_10 0xf4b700f0
 #define F0900_P1_DIS_8P_8_9 0xf4b7000f

 /*P1_MODCODLST8*/
 #define R0900_P1_MODCODLST8 0xf4b8
+#define MODCODLST8 REGx(R0900_P1_MODCODLST8)
 #define F0900_P1_DIS_8P_5_6 0xf4b800f0
 #define F0900_P1_DIS_8P_3_4 0xf4b8000f

 /*P1_MODCODLST9*/
 #define R0900_P1_MODCODLST9 0xf4b9
+#define MODCODLST9 REGx(R0900_P1_MODCODLST9)
 #define F0900_P1_DIS_8P_2_3 0xf4b900f0
 #define F0900_P1_DIS_8P_3_5 0xf4b9000f

 /*P1_MODCODLSTA*/
 #define R0900_P1_MODCODLSTA 0xf4ba
+#define MODCODLSTA REGx(R0900_P1_MODCODLSTA)
 #define F0900_P1_DIS_QP_9_10 0xf4ba00f0
 #define F0900_P1_DIS_QP_8_9 0xf4ba000f

 /*P1_MODCODLSTB*/
 #define R0900_P1_MODCODLSTB 0xf4bb
+#define MODCODLSTB REGx(R0900_P1_MODCODLSTB)
 #define F0900_P1_DIS_QP_5_6 0xf4bb00f0
 #define F0900_P1_DIS_QP_4_5 0xf4bb000f

 /*P1_MODCODLSTC*/
 #define R0900_P1_MODCODLSTC 0xf4bc
+#define MODCODLSTC REGx(R0900_P1_MODCODLSTC)
 #define F0900_P1_DIS_QP_3_4 0xf4bc00f0
 #define F0900_P1_DIS_QP_2_3 0xf4bc000f

 /*P1_MODCODLSTD*/
 #define R0900_P1_MODCODLSTD 0xf4bd
+#define MODCODLSTD REGx(R0900_P1_MODCODLSTD)
 #define F0900_P1_DIS_QP_3_5 0xf4bd00f0
 #define F0900_P1_DIS_QP_1_2 0xf4bd000f

 /*P1_MODCODLSTE*/
 #define R0900_P1_MODCODLSTE 0xf4be
+#define MODCODLSTE REGx(R0900_P1_MODCODLSTE)
 #define F0900_P1_DIS_QP_2_5 0xf4be00f0
 #define F0900_P1_DIS_QP_1_3 0xf4be000f

 /*P1_MODCODLSTF*/
 #define R0900_P1_MODCODLSTF 0xf4bf
+#define MODCODLSTF REGx(R0900_P1_MODCODLSTF)
 #define F0900_P1_DIS_QP_1_4 0xf4bf00f0
-#define F0900_P1_DDEMOD_SET  0xf4bf0002
-#define F0900_P1_DDEMOD_MASK  0xf4bf0001
+
+/*P1_GAUSSR0*/
+#define R0900_P1_GAUSSR0 0xf4c0
+#define GAUSSR0 REGx(R0900_P1_GAUSSR0)
+#define F0900_P1_EN_CCIMODE 0xf4c00080
+#define F0900_P1_R0_GAUSSIEN 0xf4c0007f
+
+/*P1_CCIR0*/
+#define R0900_P1_CCIR0 0xf4c1
+#define CCIR0 REGx(R0900_P1_CCIR0)
+#define F0900_P1_CCIDETECT_PLHONLY 0xf4c10080
+#define F0900_P1_R0_CCI 0xf4c1007f
+
+/*P1_CCIQUANT*/
+#define R0900_P1_CCIQUANT 0xf4c2
+#define CCIQUANT REGx(R0900_P1_CCIQUANT)
+#define F0900_P1_CCI_BETA 0xf4c200e0
+#define F0900_P1_CCI_QUANT 0xf4c2001f
+
+/*P1_CCITHRES*/
+#define R0900_P1_CCITHRES 0xf4c3
+#define CCITHRES REGx(R0900_P1_CCITHRES)
+#define F0900_P1_CCI_THRESHOLD 0xf4c300ff
+
+/*P1_CCIACC*/
+#define R0900_P1_CCIACC 0xf4c4
+#define CCIACC REGx(R0900_P1_CCIACC)
+#define F0900_P1_CCI_VALUE 0xf4c400ff

 /*P1_DMDRESCFG*/
 #define R0900_P1_DMDRESCFG 0xf4c6
+#define DMDRESCFG REGx(R0900_P1_DMDRESCFG)
 #define F0900_P1_DMDRES_RESET 0xf4c60080
-#define F0900_P1_DMDRES_NOISESQR  0xf4c60010
 #define F0900_P1_DMDRES_STRALL 0xf4c60008
 #define F0900_P1_DMDRES_NEWONLY 0xf4c60004
 #define F0900_P1_DMDRES_NOSTORE 0xf4c60002
-#define F0900_P1_DMDRES_AGC2MEM  0xf4c60001

 /*P1_DMDRESADR*/
 #define R0900_P1_DMDRESADR 0xf4c7
-#define F0900_P1_SUSP_PREDCANAL  0xf4c70080
+#define DMDRESADR REGx(R0900_P1_DMDRESADR)
 #define F0900_P1_DMDRES_VALIDCFR 0xf4c70040
 #define F0900_P1_DMDRES_MEMFULL 0xf4c70030
 #define F0900_P1_DMDRES_RESNBR 0xf4c7000f
@@ -2987,44 +3090,53 @@

 /*P1_FFEI1*/
 #define R0900_P1_FFEI1 0xf4d0
+#define FFEI1 REGx(R0900_P1_FFEI1)
 #define F0900_P1_FFE_ACCI1 0xf4d001ff

 /*P1_FFEQ1*/
 #define R0900_P1_FFEQ1 0xf4d1
+#define FFEQ1 REGx(R0900_P1_FFEQ1)
 #define F0900_P1_FFE_ACCQ1 0xf4d101ff

 /*P1_FFEI2*/
 #define R0900_P1_FFEI2 0xf4d2
+#define FFEI2 REGx(R0900_P1_FFEI2)
 #define F0900_P1_FFE_ACCI2 0xf4d201ff

 /*P1_FFEQ2*/
 #define R0900_P1_FFEQ2 0xf4d3
+#define FFEQ2 REGx(R0900_P1_FFEQ2)
 #define F0900_P1_FFE_ACCQ2 0xf4d301ff

 /*P1_FFEI3*/
 #define R0900_P1_FFEI3 0xf4d4
+#define FFEI3 REGx(R0900_P1_FFEI3)
 #define F0900_P1_FFE_ACCI3 0xf4d401ff

 /*P1_FFEQ3*/
 #define R0900_P1_FFEQ3 0xf4d5
+#define FFEQ3 REGx(R0900_P1_FFEQ3)
 #define F0900_P1_FFE_ACCQ3 0xf4d501ff

 /*P1_FFEI4*/
 #define R0900_P1_FFEI4 0xf4d6
+#define FFEI4 REGx(R0900_P1_FFEI4)
 #define F0900_P1_FFE_ACCI4 0xf4d601ff

 /*P1_FFEQ4*/
 #define R0900_P1_FFEQ4 0xf4d7
+#define FFEQ4 REGx(R0900_P1_FFEQ4)
 #define F0900_P1_FFE_ACCQ4 0xf4d701ff

 /*P1_FFECFG*/
 #define R0900_P1_FFECFG 0xf4d8
+#define FFECFG REGx(R0900_P1_FFECFG)
 #define F0900_P1_EQUALFFE_ON 0xf4d80040
-#define F0900_P1_EQUAL_USEDSYMB  0xf4d80030
 #define F0900_P1_MU_EQUALFFE 0xf4d80007

 /*P1_TNRCFG*/
 #define R0900_P1_TNRCFG 0xf4e0
+#define TNRCFG REGx(R0900_P1_TNRCFG)
 #define F0900_P1_TUN_ACKFAIL 0xf4e00080
 #define F0900_P1_TUN_TYPE 0xf4e00070
 #define F0900_P1_TUN_SECSTOP 0xf4e00008
@@ -3033,77 +3145,77 @@

 /*P1_TNRCFG2*/
 #define R0900_P1_TNRCFG2 0xf4e1
+#define TNRCFG2 REGx(R0900_P1_TNRCFG2)
 #define F0900_P1_TUN_IQSWAP 0xf4e10080
-#define F0900_P1_STB6110_STEP2MHZ  0xf4e10040
-#define F0900_P1_STB6120_DBLI2C  0xf4e10020
-#define F0900_P1_DIS_FCCK  0xf4e10010
-#define F0900_P1_DIS_LPEN  0xf4e10008
 #define F0900_P1_DIS_BWCALC 0xf4e10004
 #define F0900_P1_SHORT_WAITSTATES 0xf4e10002
-#define F0900_P1_DIS_2BWAGC1  0xf4e10001

 /*P1_TNRXTAL*/
 #define R0900_P1_TNRXTAL 0xf4e4
-#define F0900_P1_TUN_MCLKDECIMAL  0xf4e400e0
+#define TNRXTAL REGx(R0900_P1_TNRXTAL)
 #define F0900_P1_TUN_XTALFREQ 0xf4e4001f

 /*P1_TNRSTEPS*/
 #define R0900_P1_TNRSTEPS 0xf4e7
-#define F0900_P1_TUNER_BW1P6  0xf4e70080
-#define F0900_P1_BWINC_OFFSET  0xf4e70070
+#define TNRSTEPS REGx(R0900_P1_TNRSTEPS)
+#define F0900_P1_TUNER_BW0P125 0xf4e70080
+#define F0900_P1_BWINC_OFFSET 0xf4e70170
 #define F0900_P1_SOFTSTEP_RNG 0xf4e70008
-#define F0900_P1_TUN_BWOFFSET  0xf4e70107
+#define F0900_P1_TUN_BWOFFSET 0xf4e70007

 /*P1_TNRGAIN*/
 #define R0900_P1_TNRGAIN 0xf4e8
+#define TNRGAIN REGx(R0900_P1_TNRGAIN)
 #define F0900_P1_TUN_KDIVEN 0xf4e800c0
 #define F0900_P1_STB6X00_OCK 0xf4e80030
 #define F0900_P1_TUN_GAIN 0xf4e8000f

 /*P1_TNRRF1*/
 #define R0900_P1_TNRRF1 0xf4e9
+#define TNRRF1 REGx(R0900_P1_TNRRF1)
 #define F0900_P1_TUN_RFFREQ2 0xf4e900ff

 /*P1_TNRRF0*/
 #define R0900_P1_TNRRF0 0xf4ea
+#define TNRRF0 REGx(R0900_P1_TNRRF0)
 #define F0900_P1_TUN_RFFREQ1 0xf4ea00ff

 /*P1_TNRBW*/
 #define R0900_P1_TNRBW 0xf4eb
+#define TNRBW REGx(R0900_P1_TNRBW)
 #define F0900_P1_TUN_RFFREQ0 0xf4eb00c0
 #define F0900_P1_TUN_BW 0xf4eb003f

 /*P1_TNRADJ*/
 #define R0900_P1_TNRADJ 0xf4ec
-#define F0900_P1_STB61X0_RCLK  0xf4ec0080
+#define TNRADJ REGx(R0900_P1_TNRADJ)
 #define F0900_P1_STB61X0_CALTIME 0xf4ec0040
-#define F0900_P1_STB6X00_DLB  0xf4ec0038
-#define F0900_P1_STB6000_FCL  0xf4ec0007

 /*P1_TNRCTL2*/
 #define R0900_P1_TNRCTL2 0xf4ed
-#define F0900_P1_STB61X0_LCP1_RCCKOFF  0xf4ed0080
-#define F0900_P1_STB61X0_LCP0  0xf4ed0040
-#define F0900_P1_STB61X0_XTOUT_RFOUTS  0xf4ed0020
-#define F0900_P1_STB61X0_XTON_MCKDV  0xf4ed0010
-#define F0900_P1_STB61X0_CALOFF_DCOFF  0xf4ed0008
-#define F0900_P1_STB6110_LPT  0xf4ed0004
-#define F0900_P1_STB6110_RX  0xf4ed0002
-#define F0900_P1_STB6110_SYN  0xf4ed0001
+#define TNRCTL2 REGx(R0900_P1_TNRCTL2)
+#define F0900_P1_STB61X0_RCCKOFF 0xf4ed0080
+#define F0900_P1_STB61X0_ICP_SDOFF 0xf4ed0040
+#define F0900_P1_STB61X0_DCLOOPOFF 0xf4ed0020
+#define F0900_P1_STB61X0_REFOUTSEL 0xf4ed0010
+#define F0900_P1_STB61X0_CALOFF 0xf4ed0008
+#define F0900_P1_STB6XX0_LPT_BEN 0xf4ed0004
+#define F0900_P1_STB6XX0_RX_OSCP 0xf4ed0002
+#define F0900_P1_STB6XX0_SYN 0xf4ed0001

 /*P1_TNRCFG3*/
 #define R0900_P1_TNRCFG3 0xf4ee
-#define F0900_P1_STB6120_DISCTRL1  0xf4ee0080
-#define F0900_P1_STB6120_INVORDER  0xf4ee0040
-#define F0900_P1_STB6120_ENCTRL6  0xf4ee0020
+#define TNRCFG3 REGx(R0900_P1_TNRCFG3)
 #define F0900_P1_TUN_PLLFREQ 0xf4ee001c
 #define F0900_P1_TUN_I2CFREQ_MODE 0xf4ee0003

 /*P1_TNRLAUNCH*/
 #define R0900_P1_TNRLAUNCH 0xf4f0
+#define TNRLAUNCH REGx(R0900_P1_TNRLAUNCH)

 /*P1_TNRLD*/
 #define R0900_P1_TNRLD 0xf4f0
+#define TNRLD REGx(R0900_P1_TNRLD)
 #define F0900_P1_TUNLD_VCOING 0xf4f00080
 #define F0900_P1_TUN_REG1FAIL 0xf4f00040
 #define F0900_P1_TUN_REG2FAIL 0xf4f00020
@@ -3115,6 +3227,7 @@

 /*P1_TNROBSL*/
 #define R0900_P1_TNROBSL 0xf4f6
+#define TNROBSL REGx(R0900_P1_TNROBSL)
 #define F0900_P1_TUN_I2CABORTED 0xf4f60080
 #define F0900_P1_TUN_LPEN 0xf4f60040
 #define F0900_P1_TUN_FCCK 0xf4f60020
@@ -3124,99 +3237,145 @@

 /*P1_TNRRESTE*/
 #define R0900_P1_TNRRESTE 0xf4f7
+#define TNRRESTE REGx(R0900_P1_TNRRESTE)
 #define F0900_P1_TUN_RFRESTE0 0xf4f700ff

 /*P1_SMAPCOEF7*/
 #define R0900_P1_SMAPCOEF7 0xf500
+#define SMAPCOEF7 REGx(R0900_P1_SMAPCOEF7)
 #define F0900_P1_DIS_QSCALE 0xf5000080
 #define F0900_P1_SMAPCOEF_Q_LLR12 0xf500017f

 /*P1_SMAPCOEF6*/
 #define R0900_P1_SMAPCOEF6 0xf501
-#define F0900_P1_DIS_NEWSCALE  0xf5010008
+#define SMAPCOEF6 REGx(R0900_P1_SMAPCOEF6)
 #define F0900_P1_ADJ_8PSKLLR1 0xf5010004
 #define F0900_P1_OLD_8PSKLLR1 0xf5010002
 #define F0900_P1_DIS_AB8PSK 0xf5010001

 /*P1_SMAPCOEF5*/
 #define R0900_P1_SMAPCOEF5 0xf502
+#define SMAPCOEF5 REGx(R0900_P1_SMAPCOEF5)
 #define F0900_P1_DIS_8SCALE 0xf5020080
 #define F0900_P1_SMAPCOEF_8P_LLR23 0xf502017f

+/*P1_NCO2MAX1*/
+#define R0900_P1_NCO2MAX1 0xf514
+#define NCO2MAX1 REGx(R0900_P1_NCO2MAX1)
+#define F0900_P1_TETA2_MAXVABS1 0xf51400ff
+
+/*P1_NCO2MAX0*/
+#define R0900_P1_NCO2MAX0 0xf515
+#define NCO2MAX0 REGx(R0900_P1_NCO2MAX0)
+#define F0900_P1_TETA2_MAXVABS0 0xf51500ff
+
+/*P1_NCO2FR1*/
+#define R0900_P1_NCO2FR1 0xf516
+#define NCO2FR1 REGx(R0900_P1_NCO2FR1)
+#define F0900_P1_NCO2FINAL_ANGLE1 0xf51600ff
+
+/*P1_NCO2FR0*/
+#define R0900_P1_NCO2FR0 0xf517
+#define NCO2FR0 REGx(R0900_P1_NCO2FR0)
+#define F0900_P1_NCO2FINAL_ANGLE0 0xf51700ff
+
+/*P1_CFR2AVRGE1*/
+#define R0900_P1_CFR2AVRGE1 0xf518
+#define CFR2AVRGE1 REGx(R0900_P1_CFR2AVRGE1)
+#define F0900_P1_I2C_CFR2AVERAGE1 0xf51800ff
+
+/*P1_CFR2AVRGE0*/
+#define R0900_P1_CFR2AVRGE0 0xf519
+#define CFR2AVRGE0 REGx(R0900_P1_CFR2AVRGE0)
+#define F0900_P1_I2C_CFR2AVERAGE0 0xf51900ff
+
 /*P1_DMDPLHSTAT*/
 #define R0900_P1_DMDPLHSTAT 0xf520
+#define DMDPLHSTAT REGx(R0900_P1_DMDPLHSTAT)
 #define F0900_P1_PLH_STATISTIC 0xf52000ff

 /*P1_LOCKTIME3*/
 #define R0900_P1_LOCKTIME3 0xf522
+#define LOCKTIME3 REGx(R0900_P1_LOCKTIME3)
 #define F0900_P1_DEMOD_LOCKTIME3 0xf52200ff

 /*P1_LOCKTIME2*/
 #define R0900_P1_LOCKTIME2 0xf523
+#define LOCKTIME2 REGx(R0900_P1_LOCKTIME2)
 #define F0900_P1_DEMOD_LOCKTIME2 0xf52300ff

 /*P1_LOCKTIME1*/
 #define R0900_P1_LOCKTIME1 0xf524
+#define LOCKTIME1 REGx(R0900_P1_LOCKTIME1)
 #define F0900_P1_DEMOD_LOCKTIME1 0xf52400ff

 /*P1_LOCKTIME0*/
 #define R0900_P1_LOCKTIME0 0xf525
+#define LOCKTIME0 REGx(R0900_P1_LOCKTIME0)
 #define F0900_P1_DEMOD_LOCKTIME0 0xf52500ff

 /*P1_VITSCALE*/
 #define R0900_P1_VITSCALE 0xf532
+#define VITSCALE REGx(R0900_P1_VITSCALE)
 #define F0900_P1_NVTH_NOSRANGE 0xf5320080
 #define F0900_P1_VERROR_MAXMODE 0xf5320040
-#define F0900_P1_KDIV_MODE  0xf5320030
 #define F0900_P1_NSLOWSN_LOCKED 0xf5320008
-#define F0900_P1_DELOCK_PRFLOSS  0xf5320004
 #define F0900_P1_DIS_RSFLOCK 0xf5320002

 /*P1_FECM*/
 #define R0900_P1_FECM 0xf533
+#define FECM REGx(R0900_P1_FECM)
 #define F0900_P1_DSS_DVB 0xf5330080
-#define F0900_P1_DEMOD_BYPASS  0xf5330040
-#define F0900_P1_CMP_SLOWMODE  0xf5330020
+#define DSS_DVB FLDx(F0900_P1_DSS_DVB)
 #define F0900_P1_DSS_SRCH 0xf5330010
-#define F0900_P1_DIFF_MODEVIT  0xf5330004
 #define F0900_P1_SYNCVIT 0xf5330002
 #define F0900_P1_IQINV 0xf5330001
+#define IQINV FLDx(F0900_P1_IQINV)

 /*P1_VTH12*/
 #define R0900_P1_VTH12 0xf534
+#define VTH12 REGx(R0900_P1_VTH12)
 #define F0900_P1_VTH12 0xf53400ff

 /*P1_VTH23*/
 #define R0900_P1_VTH23 0xf535
+#define VTH23 REGx(R0900_P1_VTH23)
 #define F0900_P1_VTH23 0xf53500ff

 /*P1_VTH34*/
 #define R0900_P1_VTH34 0xf536
+#define VTH34 REGx(R0900_P1_VTH34)
 #define F0900_P1_VTH34 0xf53600ff

 /*P1_VTH56*/
 #define R0900_P1_VTH56 0xf537
+#define VTH56 REGx(R0900_P1_VTH56)
 #define F0900_P1_VTH56 0xf53700ff

 /*P1_VTH67*/
 #define R0900_P1_VTH67 0xf538
+#define VTH67 REGx(R0900_P1_VTH67)
 #define F0900_P1_VTH67 0xf53800ff

 /*P1_VTH78*/
 #define R0900_P1_VTH78 0xf539
+#define VTH78 REGx(R0900_P1_VTH78)
 #define F0900_P1_VTH78 0xf53900ff

 /*P1_VITCURPUN*/
 #define R0900_P1_VITCURPUN 0xf53a
-#define F0900_P1_VIT_MAPPING  0xf53a00e0
+#define VITCURPUN REGx(R0900_P1_VITCURPUN)
 #define F0900_P1_VIT_CURPUN 0xf53a001f
+#define VIT_CURPUN FLDx(F0900_P1_VIT_CURPUN)

 /*P1_VERROR*/
 #define R0900_P1_VERROR 0xf53b
+#define VERROR REGx(R0900_P1_VERROR)
 #define F0900_P1_REGERR_VIT 0xf53b00ff

 /*P1_PRVIT*/
 #define R0900_P1_PRVIT 0xf53c
+#define PRVIT REGx(R0900_P1_PRVIT)
 #define F0900_P1_DIS_VTHLOCK 0xf53c0040
 #define F0900_P1_E7_8VIT 0xf53c0020
 #define F0900_P1_E6_7VIT 0xf53c0010
@@ -3227,6 +3386,7 @@

 /*P1_VAVSRVIT*/
 #define R0900_P1_VAVSRVIT 0xf53d
+#define VAVSRVIT REGx(R0900_P1_VAVSRVIT)
 #define F0900_P1_AMVIT 0xf53d0080
 #define F0900_P1_FROZENVIT 0xf53d0040
 #define F0900_P1_SNVIT 0xf53d0030
@@ -3235,117 +3395,123 @@

 /*P1_VSTATUSVIT*/
 #define R0900_P1_VSTATUSVIT 0xf53e
-#define F0900_P1_VITERBI_ON  0xf53e0080
-#define F0900_P1_END_LOOPVIT  0xf53e0040
-#define F0900_P1_VITERBI_DEPRF  0xf53e0020
+#define VSTATUSVIT REGx(R0900_P1_VSTATUSVIT)
 #define F0900_P1_PRFVIT 0xf53e0010
+#define PRFVIT FLDx(F0900_P1_PRFVIT)
 #define F0900_P1_LOCKEDVIT 0xf53e0008
-#define F0900_P1_VITERBI_DELOCK  0xf53e0004
-#define F0900_P1_VIT_DEMODSEL  0xf53e0002
-#define F0900_P1_VITERBI_COMPOUT  0xf53e0001
+#define LOCKEDVIT FLDx(F0900_P1_LOCKEDVIT)

 /*P1_VTHINUSE*/
 #define R0900_P1_VTHINUSE 0xf53f
+#define VTHINUSE REGx(R0900_P1_VTHINUSE)
 #define F0900_P1_VIT_INUSE 0xf53f00ff

 /*P1_KDIV12*/
 #define R0900_P1_KDIV12 0xf540
-#define F0900_P1_KDIV12_MANUAL  0xf5400080
+#define KDIV12 REGx(R0900_P1_KDIV12)
 #define F0900_P1_K_DIVIDER_12 0xf540007f

 /*P1_KDIV23*/
 #define R0900_P1_KDIV23 0xf541
-#define F0900_P1_KDIV23_MANUAL  0xf5410080
+#define KDIV23 REGx(R0900_P1_KDIV23)
 #define F0900_P1_K_DIVIDER_23 0xf541007f

 /*P1_KDIV34*/
 #define R0900_P1_KDIV34 0xf542
-#define F0900_P1_KDIV34_MANUAL  0xf5420080
+#define KDIV34 REGx(R0900_P1_KDIV34)
 #define F0900_P1_K_DIVIDER_34 0xf542007f

 /*P1_KDIV56*/
 #define R0900_P1_KDIV56 0xf543
-#define F0900_P1_KDIV56_MANUAL  0xf5430080
+#define KDIV56 REGx(R0900_P1_KDIV56)
 #define F0900_P1_K_DIVIDER_56 0xf543007f

 /*P1_KDIV67*/
 #define R0900_P1_KDIV67 0xf544
-#define F0900_P1_KDIV67_MANUAL  0xf5440080
+#define KDIV67 REGx(R0900_P1_KDIV67)
 #define F0900_P1_K_DIVIDER_67 0xf544007f

 /*P1_KDIV78*/
 #define R0900_P1_KDIV78 0xf545
-#define F0900_P1_KDIV78_MANUAL  0xf5450080
+#define KDIV78 REGx(R0900_P1_KDIV78)
 #define F0900_P1_K_DIVIDER_78 0xf545007f

 /*P1_PDELCTRL1*/
 #define R0900_P1_PDELCTRL1 0xf550
+#define PDELCTRL1 REGx(R0900_P1_PDELCTRL1)
 #define F0900_P1_INV_MISMASK 0xf5500080
-#define F0900_P1_FORCE_ACCEPTED  0xf5500040
 #define F0900_P1_FILTER_EN 0xf5500020
-#define F0900_P1_FORCE_PKTDELINUSE  0xf5500010
-#define F0900_P1_HYSTEN  0xf5500008
-#define F0900_P1_HYSTSWRST  0xf5500004
 #define F0900_P1_EN_MIS00 0xf5500002
 #define F0900_P1_ALGOSWRST 0xf5500001
+#define ALGOSWRST FLDx(F0900_P1_ALGOSWRST)

 /*P1_PDELCTRL2*/
 #define R0900_P1_PDELCTRL2 0xf551
-#define F0900_P1_FORCE_CONTINUOUS  0xf5510080
+#define PDELCTRL2 REGx(R0900_P1_PDELCTRL2)
 #define F0900_P1_RESET_UPKO_COUNT 0xf5510040
-#define F0900_P1_USER_PKTDELIN_NB  0xf5510020
-#define F0900_P1_FORCE_LOCKED  0xf5510010
-#define F0900_P1_DATA_UNBBSCRAM  0xf5510008
-#define F0900_P1_FORCE_LONGPKT  0xf5510004
+#define RESET_UPKO_COUNT FLDx(F0900_P1_RESET_UPKO_COUNT)
 #define F0900_P1_FRAME_MODE 0xf5510002
+#define F0900_P1_NOBCHERRFLG_USE 0xf5510001

 /*P1_HYSTTHRESH*/
 #define R0900_P1_HYSTTHRESH 0xf554
+#define HYSTTHRESH REGx(R0900_P1_HYSTTHRESH)
 #define F0900_P1_UNLCK_THRESH 0xf55400f0
 #define F0900_P1_DELIN_LCK_THRESH 0xf554000f

 /*P1_ISIENTRY*/
 #define R0900_P1_ISIENTRY 0xf55e
+#define ISIENTRY REGx(R0900_P1_ISIENTRY)
 #define F0900_P1_ISI_ENTRY 0xf55e00ff

 /*P1_ISIBITENA*/
 #define R0900_P1_ISIBITENA 0xf55f
+#define ISIBITENA REGx(R0900_P1_ISIBITENA)
 #define F0900_P1_ISI_BIT_EN 0xf55f00ff

 /*P1_MATSTR1*/
 #define R0900_P1_MATSTR1 0xf560
+#define MATSTR1 REGx(R0900_P1_MATSTR1)
 #define F0900_P1_MATYPE_CURRENT1 0xf56000ff

 /*P1_MATSTR0*/
 #define R0900_P1_MATSTR0 0xf561
+#define MATSTR0 REGx(R0900_P1_MATSTR0)
 #define F0900_P1_MATYPE_CURRENT0 0xf56100ff

 /*P1_UPLSTR1*/
 #define R0900_P1_UPLSTR1 0xf562
+#define UPLSTR1 REGx(R0900_P1_UPLSTR1)
 #define F0900_P1_UPL_CURRENT1 0xf56200ff

 /*P1_UPLSTR0*/
 #define R0900_P1_UPLSTR0 0xf563
+#define UPLSTR0 REGx(R0900_P1_UPLSTR0)
 #define F0900_P1_UPL_CURRENT0 0xf56300ff

 /*P1_DFLSTR1*/
 #define R0900_P1_DFLSTR1 0xf564
+#define DFLSTR1 REGx(R0900_P1_DFLSTR1)
 #define F0900_P1_DFL_CURRENT1 0xf56400ff

 /*P1_DFLSTR0*/
 #define R0900_P1_DFLSTR0 0xf565
+#define DFLSTR0 REGx(R0900_P1_DFLSTR0)
 #define F0900_P1_DFL_CURRENT0 0xf56500ff

 /*P1_SYNCSTR*/
 #define R0900_P1_SYNCSTR 0xf566
+#define SYNCSTR REGx(R0900_P1_SYNCSTR)
 #define F0900_P1_SYNC_CURRENT 0xf56600ff

 /*P1_SYNCDSTR1*/
 #define R0900_P1_SYNCDSTR1 0xf567
+#define SYNCDSTR1 REGx(R0900_P1_SYNCDSTR1)
 #define F0900_P1_SYNCD_CURRENT1 0xf56700ff

 /*P1_SYNCDSTR0*/
 #define R0900_P1_SYNCDSTR0 0xf568
+#define SYNCDSTR0 REGx(R0900_P1_SYNCDSTR0)
 #define F0900_P1_SYNCD_CURRENT0 0xf56800ff

 /*P1_PDELSTATUS1*/
@@ -3355,45 +3521,54 @@
 #define F0900_P1_CONTINUOUS_STREAM 0xf5690020
 #define F0900_P1_UNACCEPTED_STREAM 0xf5690010
 #define F0900_P1_BCH_ERROR_FLAG 0xf5690008
-#define F0900_P1_BBHCRCKO  0xf5690004
 #define F0900_P1_PKTDELIN_LOCK 0xf5690002
+#define PKTDELIN_LOCK FLDx(F0900_P1_PKTDELIN_LOCK)
 #define F0900_P1_FIRST_LOCK 0xf5690001

 /*P1_PDELSTATUS2*/
 #define R0900_P1_PDELSTATUS2 0xf56a
-#define F0900_P1_PKTDEL_DEMODSEL  0xf56a0080
 #define F0900_P1_FRAME_MODCOD 0xf56a007c
 #define F0900_P1_FRAME_TYPE 0xf56a0003

 /*P1_BBFCRCKO1*/
 #define R0900_P1_BBFCRCKO1 0xf56b
+#define BBFCRCKO1 REGx(R0900_P1_BBFCRCKO1)
 #define F0900_P1_BBHCRC_KOCNT1 0xf56b00ff

 /*P1_BBFCRCKO0*/
 #define R0900_P1_BBFCRCKO0 0xf56c
+#define BBFCRCKO0 REGx(R0900_P1_BBFCRCKO0)
 #define F0900_P1_BBHCRC_KOCNT0 0xf56c00ff

 /*P1_UPCRCKO1*/
 #define R0900_P1_UPCRCKO1 0xf56d
+#define UPCRCKO1 REGx(R0900_P1_UPCRCKO1)
 #define F0900_P1_PKTCRC_KOCNT1 0xf56d00ff

 /*P1_UPCRCKO0*/
 #define R0900_P1_UPCRCKO0 0xf56e
+#define UPCRCKO0 REGx(R0900_P1_UPCRCKO0)
 #define F0900_P1_PKTCRC_KOCNT0 0xf56e00ff

+/*P1_PDELCTRL3*/
+#define R0900_P1_PDELCTRL3 0xf56f
+#define PDELCTRL3 REGx(R0900_P1_PDELCTRL3)
+#define F0900_P1_PKTDEL_CONTFAIL 0xf56f0080
+#define F0900_P1_NOFIFO_BCHERR 0xf56f0020
+
 /*P1_TSSTATEM*/
 #define R0900_P1_TSSTATEM 0xf570
+#define TSSTATEM REGx(R0900_P1_TSSTATEM)
 #define F0900_P1_TSDIL_ON 0xf5700080
-#define F0900_P1_TSSKIPRS_ON  0xf5700040
 #define F0900_P1_TSRS_ON 0xf5700020
 #define F0900_P1_TSDESCRAMB_ON 0xf5700010
 #define F0900_P1_TSFRAME_MODE 0xf5700008
 #define F0900_P1_TS_DISABLE 0xf5700004
-#define F0900_P1_TSACM_MODE  0xf5700002
 #define F0900_P1_TSOUT_NOSYNC 0xf5700001

 /*P1_TSCFGH*/
 #define R0900_P1_TSCFGH 0xf572
+#define TSCFGH REGx(R0900_P1_TSCFGH)
 #define F0900_P1_TSFIFO_DVBCI 0xf5720080
 #define F0900_P1_TSFIFO_SERIAL 0xf5720040
 #define F0900_P1_TSFIFO_TEIUPDATE 0xf5720020
@@ -3401,28 +3576,28 @@
 #define F0900_P1_TSFIFO_HSGNLOUT 0xf5720008
 #define F0900_P1_TSFIFO_ERRMODE 0xf5720006
 #define F0900_P1_RST_HWARE 0xf5720001
+#define RST_HWARE FLDx(F0900_P1_RST_HWARE)

 /*P1_TSCFGM*/
 #define R0900_P1_TSCFGM 0xf573
+#define TSCFGM REGx(R0900_P1_TSCFGM)
 #define F0900_P1_TSFIFO_MANSPEED 0xf57300c0
 #define F0900_P1_TSFIFO_PERMDATA 0xf5730020
-#define F0900_P1_TSFIFO_NONEWSGNL  0xf5730010
-#define F0900_P1_TSFIFO_BITSPEED  0xf5730008
-#define F0900_P1_NPD_SPECDVBS2  0xf5730004
-#define F0900_P1_TSFIFO_STOPCKDIS  0xf5730002
+#define F0900_P1_TSFIFO_DPUNACT 0xf5730002
 #define F0900_P1_TSFIFO_INVDATA 0xf5730001

 /*P1_TSCFGL*/
 #define R0900_P1_TSCFGL 0xf574
+#define TSCFGL REGx(R0900_P1_TSCFGL)
 #define F0900_P1_TSFIFO_BCLKDEL1CK 0xf57400c0
 #define F0900_P1_BCHERROR_MODE 0xf5740030
 #define F0900_P1_TSFIFO_NSGNL2DATA 0xf5740008
 #define F0900_P1_TSFIFO_EMBINDVB 0xf5740004
-#define F0900_P1_TSFIFO_DPUNACT  0xf5740002
-#define F0900_P1_TSFIFO_NPDOFF  0xf5740001
+#define F0900_P1_TSFIFO_BITSPEED 0xf5740003

 /*P1_TSINSDELH*/
 #define R0900_P1_TSINSDELH 0xf576
+#define TSINSDELH REGx(R0900_P1_TSINSDELH)
 #define F0900_P1_TSDEL_SYNCBYTE 0xf5760080
 #define F0900_P1_TSDEL_XXHEADER 0xf5760040
 #define F0900_P1_TSDEL_BBHEADER 0xf5760020
@@ -3432,88 +3607,112 @@
 #define F0900_P1_TSINSDEL_RSPARITY 0xf5760002
 #define F0900_P1_TSINSDEL_CRC8 0xf5760001

+/*P1_TSDIVN*/
+#define R0900_P1_TSDIVN 0xf579
+#define TSDIVN REGx(R0900_P1_TSDIVN)
+#define F0900_P1_TSFIFO_SPEEDMODE 0xf57900c0
+
+/*P1_TSCFG4*/
+#define R0900_P1_TSCFG4 0xf57a
+#define TSCFG4 REGx(R0900_P1_TSCFG4)
+#define F0900_P1_TSFIFO_TSSPEEDMODE 0xf57a00c0
+
 /*P1_TSSPEED*/
 #define R0900_P1_TSSPEED 0xf580
+#define TSSPEED REGx(R0900_P1_TSSPEED)
 #define F0900_P1_TSFIFO_OUTSPEED 0xf58000ff

 /*P1_TSSTATUS*/
 #define R0900_P1_TSSTATUS 0xf581
+#define TSSTATUS REGx(R0900_P1_TSSTATUS)
 #define F0900_P1_TSFIFO_LINEOK 0xf5810080
+#define TSFIFO_LINEOK FLDx(F0900_P1_TSFIFO_LINEOK)
 #define F0900_P1_TSFIFO_ERROR 0xf5810040
-#define F0900_P1_TSFIFO_DATA7  0xf5810020
-#define F0900_P1_TSFIFO_NOSYNC  0xf5810010
-#define F0900_P1_ISCR_INITIALIZED  0xf5810008
-#define F0900_P1_ISCR_UPDATED  0xf5810004
-#define F0900_P1_SOFFIFO_UNREGUL  0xf5810002
 #define F0900_P1_DIL_READY 0xf5810001

 /*P1_TSSTATUS2*/
 #define R0900_P1_TSSTATUS2 0xf582
+#define TSSTATUS2 REGx(R0900_P1_TSSTATUS2)
 #define F0900_P1_TSFIFO_DEMODSEL 0xf5820080
 #define F0900_P1_TSFIFOSPEED_STORE 0xf5820040
 #define F0900_P1_DILXX_RESET 0xf5820020
 #define F0900_P1_TSSERIAL_IMPOS 0xf5820010
-#define F0900_P1_TSFIFO_LINENOK  0xf5820008
-#define F0900_P1_BITSPEED_EVENT  0xf5820004
 #define F0900_P1_SCRAMBDETECT 0xf5820002
-#define F0900_P1_ULDTV67_FALSELOCK  0xf5820001

 /*P1_TSBITRATE1*/
 #define R0900_P1_TSBITRATE1 0xf583
+#define TSBITRATE1 REGx(R0900_P1_TSBITRATE1)
 #define F0900_P1_TSFIFO_BITRATE1 0xf58300ff

 /*P1_TSBITRATE0*/
 #define R0900_P1_TSBITRATE0 0xf584
+#define TSBITRATE0 REGx(R0900_P1_TSBITRATE0)
 #define F0900_P1_TSFIFO_BITRATE0 0xf58400ff

 /*P1_ERRCTRL1*/
 #define R0900_P1_ERRCTRL1 0xf598
+#define ERRCTRL1 REGx(R0900_P1_ERRCTRL1)
 #define F0900_P1_ERR_SOURCE1 0xf59800f0
 #define F0900_P1_NUM_EVENT1 0xf5980007

 /*P1_ERRCNT12*/
 #define R0900_P1_ERRCNT12 0xf599
+#define ERRCNT12 REGx(R0900_P1_ERRCNT12)
 #define F0900_P1_ERRCNT1_OLDVALUE 0xf5990080
 #define F0900_P1_ERR_CNT12 0xf599007f
+#define ERR_CNT12 FLDx(F0900_P1_ERR_CNT12)

 /*P1_ERRCNT11*/
 #define R0900_P1_ERRCNT11 0xf59a
+#define ERRCNT11 REGx(R0900_P1_ERRCNT11)
 #define F0900_P1_ERR_CNT11 0xf59a00ff
+#define ERR_CNT11 FLDx(F0900_P1_ERR_CNT11)

 /*P1_ERRCNT10*/
 #define R0900_P1_ERRCNT10 0xf59b
+#define ERRCNT10 REGx(R0900_P1_ERRCNT10)
 #define F0900_P1_ERR_CNT10 0xf59b00ff
+#define ERR_CNT10 FLDx(F0900_P1_ERR_CNT10)

 /*P1_ERRCTRL2*/
 #define R0900_P1_ERRCTRL2 0xf59c
+#define ERRCTRL2 REGx(R0900_P1_ERRCTRL2)
 #define F0900_P1_ERR_SOURCE2 0xf59c00f0
 #define F0900_P1_NUM_EVENT2 0xf59c0007

 /*P1_ERRCNT22*/
 #define R0900_P1_ERRCNT22 0xf59d
+#define ERRCNT22 REGx(R0900_P1_ERRCNT22)
 #define F0900_P1_ERRCNT2_OLDVALUE 0xf59d0080
 #define F0900_P1_ERR_CNT22 0xf59d007f
+#define ERR_CNT22 FLDx(F0900_P1_ERR_CNT22)

 /*P1_ERRCNT21*/
 #define R0900_P1_ERRCNT21 0xf59e
+#define ERRCNT21 REGx(R0900_P1_ERRCNT21)
 #define F0900_P1_ERR_CNT21 0xf59e00ff
+#define ERR_CNT21 FLDx(F0900_P1_ERR_CNT21)

 /*P1_ERRCNT20*/
 #define R0900_P1_ERRCNT20 0xf59f
+#define ERRCNT20 REGx(R0900_P1_ERRCNT20)
 #define F0900_P1_ERR_CNT20 0xf59f00ff
+#define ERR_CNT20 FLDx(F0900_P1_ERR_CNT20)

 /*P1_FECSPY*/
 #define R0900_P1_FECSPY 0xf5a0
+#define FECSPY REGx(R0900_P1_FECSPY)
 #define F0900_P1_SPY_ENABLE 0xf5a00080
 #define F0900_P1_NO_SYNCBYTE 0xf5a00040
 #define F0900_P1_SERIAL_MODE 0xf5a00020
 #define F0900_P1_UNUSUAL_PACKET 0xf5a00010
-#define F0900_P1_BER_PACKMODE  0xf5a00008
+#define F0900_P1_BERMETER_DATAMODE 0xf5a00008
 #define F0900_P1_BERMETER_LMODE 0xf5a00002
 #define F0900_P1_BERMETER_RESET 0xf5a00001

 /*P1_FSPYCFG*/
 #define R0900_P1_FSPYCFG 0xf5a1
+#define FSPYCFG REGx(R0900_P1_FSPYCFG)
 #define F0900_P1_FECSPY_INPUT 0xf5a100c0
 #define F0900_P1_RST_ON_ERROR 0xf5a10020
 #define F0900_P1_ONE_SHOT 0xf5a10010
@@ -3522,19 +3721,20 @@

 /*P1_FSPYDATA*/
 #define R0900_P1_FSPYDATA 0xf5a2
+#define FSPYDATA REGx(R0900_P1_FSPYDATA)
 #define F0900_P1_SPY_STUFFING 0xf5a20080
-#define F0900_P1_NOERROR_PKTJITTER  0xf5a20040
 #define F0900_P1_SPY_CNULLPKT 0xf5a20020
 #define F0900_P1_SPY_OUTDATA_MODE 0xf5a2001f

 /*P1_FSPYOUT*/
 #define R0900_P1_FSPYOUT 0xf5a3
+#define FSPYOUT REGx(R0900_P1_FSPYOUT)
 #define F0900_P1_FSPY_DIRECT 0xf5a30080
-#define F0900_P1_SPY_OUTDATA_BUS  0xf5a30038
 #define F0900_P1_STUFF_MODE 0xf5a30007

 /*P1_FSTATUS*/
 #define R0900_P1_FSTATUS 0xf5a4
+#define FSTATUS REGx(R0900_P1_FSTATUS)
 #define F0900_P1_SPY_ENDSIM 0xf5a40080
 #define F0900_P1_VALID_SIM 0xf5a40040
 #define F0900_P1_FOUND_SIGNAL 0xf5a40020
@@ -3543,66 +3743,62 @@

 /*P1_FBERCPT4*/
 #define R0900_P1_FBERCPT4 0xf5a8
+#define FBERCPT4 REGx(R0900_P1_FBERCPT4)
 #define F0900_P1_FBERMETER_CPT4 0xf5a800ff

 /*P1_FBERCPT3*/
 #define R0900_P1_FBERCPT3 0xf5a9
+#define FBERCPT3 REGx(R0900_P1_FBERCPT3)
 #define F0900_P1_FBERMETER_CPT3 0xf5a900ff

 /*P1_FBERCPT2*/
 #define R0900_P1_FBERCPT2 0xf5aa
+#define FBERCPT2 REGx(R0900_P1_FBERCPT2)
 #define F0900_P1_FBERMETER_CPT2 0xf5aa00ff

 /*P1_FBERCPT1*/
 #define R0900_P1_FBERCPT1 0xf5ab
+#define FBERCPT1 REGx(R0900_P1_FBERCPT1)
 #define F0900_P1_FBERMETER_CPT1 0xf5ab00ff

 /*P1_FBERCPT0*/
 #define R0900_P1_FBERCPT0 0xf5ac
+#define FBERCPT0 REGx(R0900_P1_FBERCPT0)
 #define F0900_P1_FBERMETER_CPT0 0xf5ac00ff

 /*P1_FBERERR2*/
 #define R0900_P1_FBERERR2 0xf5ad
+#define FBERERR2 REGx(R0900_P1_FBERERR2)
 #define F0900_P1_FBERMETER_ERR2 0xf5ad00ff

 /*P1_FBERERR1*/
 #define R0900_P1_FBERERR1 0xf5ae
+#define FBERERR1 REGx(R0900_P1_FBERERR1)
 #define F0900_P1_FBERMETER_ERR1 0xf5ae00ff

 /*P1_FBERERR0*/
 #define R0900_P1_FBERERR0 0xf5af
+#define FBERERR0 REGx(R0900_P1_FBERERR0)
 #define F0900_P1_FBERMETER_ERR0 0xf5af00ff

 /*P1_FSPYBER*/
 #define R0900_P1_FSPYBER 0xf5b2
-#define F0900_P1_FSPYOBS_XORREAD  0xf5b20040
-#define F0900_P1_FSPYBER_OBSMODE  0xf5b20020
+#define FSPYBER REGx(R0900_P1_FSPYBER)
 #define F0900_P1_FSPYBER_SYNCBYTE 0xf5b20010
 #define F0900_P1_FSPYBER_UNSYNC 0xf5b20008
 #define F0900_P1_FSPYBER_CTIME 0xf5b20007

-/*RCCFGH*/
-#define R0900_RCCFGH  0xf600
-#define F0900_TSRCFIFO_DVBCI  0xf6000080
-#define F0900_TSRCFIFO_SERIAL  0xf6000040
-#define F0900_TSRCFIFO_DISABLE  0xf6000020
-#define F0900_TSFIFO_2TORC  0xf6000010
-#define F0900_TSRCFIFO_HSGNLOUT  0xf6000008
-#define F0900_TSRCFIFO_ERRMODE  0xf6000006
+/*RCCFG2*/
+#define R0900_RCCFG2 0xf600

 /*TSGENERAL*/
 #define R0900_TSGENERAL 0xf630
-#define F0900_TSFIFO_BCLK1ALL  0xf6300020
+#define F0900_TSFIFO_DISTS2PAR 0xf6300040
 #define F0900_MUXSTREAM_OUTMODE 0xf6300008
 #define F0900_TSFIFO_PERMPARAL 0xf6300006
-#define F0900_RST_REEDSOLO  0xf6300001

 /*TSGENERAL1X*/
 #define R0900_TSGENERAL1X 0xf670
-#define F0900_TSFIFO1X_BCLK1ALL  0xf6700020
-#define F0900_MUXSTREAM1X_OUTMODE  0xf6700008
-#define F0900_TSFIFO1X_PERMPARAL  0xf6700006
-#define F0900_RST1X_REEDSOLO  0xf6700001

 /*NBITER_NF4*/
 #define R0900_NBITER_NF4 0xfa03
@@ -3733,8 +3929,6 @@
 /*GENCFG*/
 #define R0900_GENCFG 0xfa86
 #define F0900_BROADCAST 0xfa860010
-#define F0900_NOSHFRD2  0xfa860008
-#define F0900_BCHERRFLAG  0xfa860004
 #define F0900_PRIORITY 0xfa860002
 #define F0900_DDEMOD 0xfa860001

@@ -3754,34 +3948,28 @@
 /*TSTRES0*/
 #define R0900_TSTRES0 0xff11
 #define F0900_FRESFEC 0xff110080
-#define F0900_FRESTS  0xff110040
-#define F0900_FRESVIT1  0xff110020
-#define F0900_FRESVIT2  0xff110010
-#define F0900_FRESSYM1  0xff110008
-#define F0900_FRESSYM2  0xff110004
-#define F0900_FRESMAS  0xff110002
-#define F0900_FRESINT  0xff110001
+
+/*P2_TCTL4*/
+#define R0900_P2_TCTL4 0xff28
+#define F0900_P2_PN4_SELECT 0xff280020
+
+/*P1_TCTL4*/
+#define R0900_P1_TCTL4 0xff48
+#define TCTL4 shiftx(R0900_P1_TCTL4, demod, 0x20)
+#define F0900_P1_PN4_SELECT 0xff480020

 /*P2_TSTDISRX*/
 #define R0900_P2_TSTDISRX 0xff65
-#define F0900_P2_EN_DISRX  0xff650080
-#define F0900_P2_TST_CURRSRC  0xff650040
-#define F0900_P2_IN_DIGSIGNAL  0xff650020
-#define F0900_P2_HIZ_CURRENTSRC  0xff650010
-#define F0900_TST_P2_PIN_SELECT  0xff650008
-#define F0900_P2_TST_DISRX  0xff650007
+#define F0900_P2_PIN_SELECT1 0xff650008

 /*P1_TSTDISRX*/
 #define R0900_P1_TSTDISRX 0xff67
-#define F0900_P1_EN_DISRX  0xff670080
-#define F0900_P1_TST_CURRSRC  0xff670040
-#define F0900_P1_IN_DIGSIGNAL  0xff670020
-#define F0900_P1_HIZ_CURRENTSRC  0xff670010
-#define F0900_TST_P1_PIN_SELECT  0xff670008
-#define F0900_P1_TST_DISRX  0xff670007
-
-#define STV0900_NBREGS		684
-#define STV0900_NBFIELDS		1702
+#define TSTDISRX shiftx(R0900_P1_TSTDISRX, demod, 2)
+#define F0900_P1_PIN_SELECT1 0xff670008
+#define PIN_SELECT1 shiftx(F0900_P1_PIN_SELECT1, demod, 0x20000)
+
+#define STV0900_NBREGS 723
+#define STV0900_NBFIELDS 1420

 #endif