Merge tag 'mfd-for-linus-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd

Pull MFD updates from Lee Jones:
 "New Device Support
   - Add support for Ricoh RC5T619 PMIC to rn5t618
   - Add support for PM8821 PMIC to qcom-pm8xxx

  New Functionality:
   - Add support for GPIO to lpc_ich
   - Add support for GPADC to sun4i
   - Add ability for rk808 to shutdown

  Fix-ups:
   - Simplify/strip unnecessary code; tps65218, palmas, tps65217
   - Device Tree binding updates; tps65218, altera-a10sr
   - Provide/export device ID info; tps65218, axp20x-i2c, hi655x-pmic,
     fsl-imx25-tsadc, intel_soc_pmic_bxtwc
   - Use MFD API instead of of_platform_populate(); tps65218
   - Generalise name-space; pm8xxx
   - Supply/edit regmap configuration; axp20x, cs47l24-tables, axp20x
   - Enable compile testing; max77620, max77686, exynos-lpass,
     abx500-core
   - Coding style issues; wm8994-core, wm5102-tables
   - Supply endian support; syscon
   - Remove module support; ab3100-core, ab8500-debugfs, ab8500-gpadc,
     abx500-core

  Bug Fixes:
   - Fix ordering issues; wm8994
   - Fix dependencies (build-time/run-time); exynos_lpass, sun4i-gpadc
   - Fix compiler warnings; sun4i-gpadc
   - Fix leaks; mfd-core
   - Fix page fault during module unload; tps65217"

* tag 'mfd-for-linus-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd: (49 commits)
  mfd: tps65217: Support an interrupt pin as the system wakeup
  mfd: tps65217: Make an interrupt handler simpler
  mfd: tps65217: Update register interrupt mask bits instead of writing operation
  mfd: tps65217: Specify the IRQ name
  mfd: tps65217: Fix page fault on unloading modules
  mfd: palmas: Remove redundant check in palmas_power_off
  mfd: arizona: Disable IRQs during driver remove
  mfd: pm8xxx: add support to pm8821
  mfd: intel-lpss: Try to enable Memory-Write-Invalidate
  mfd: rn5t618: Add Ricoh RC5T619 PMIC support
  mfd: axp20x: Add address extension registers for AXP806 regmap
  mfd: intel_soc_pmic_bxtwc: Fix a typo in MODULE_DEVICE_TABLE()
  mfd: core: Fix device reference leak in mfd_clone_cell
  mfd: bcm590xx: Simplify a test
  mfd: sun4i-gpadc: Select regmap-irq
  mfd: abx500-core: drop unused MODULE_ tags from non-modular code
  mfd: ab8500: make sysctrl explicitly non-modular
  mfd: ab8500-gpadc: Make it explicitly non-modular
  mfd: ab8500-debugfs: Make it explicitly non-modular
  mfd: ab8500-core: Make it explicitly non-modular
  ...

Documentation/devicetree/bindings/mfd/altera-a10sr.txt

+* Altera Arria10 Development Kit System Resource Chip
+
+Required parent device properties:
+- compatible		: "altr,a10sr"
+- spi-max-frequency	: Maximum SPI frequency.
+- reg			: The SPI Chip Select address for the Arria10
+			  System Resource chip
+- interrupt-parent	: The parent interrupt controller.
+- interrupts		: The interrupt line the device is connected to.
+- interrupt-controller	: Marks the device node as an interrupt controller.
+- #interrupt-cells	: The number of cells to describe an IRQ, should be 2.
+			    The first cell is the IRQ number.
+			    The second cell is the flags, encoded as trigger
+			    masks from ../interrupt-controller/interrupts.txt.
+
+The A10SR consists of these sub-devices:
+
+Device                   Description
+------                   ----------
+a10sr_gpio               GPIO Controller
+
+Arria10 GPIO
+Required Properties:
+- compatible        : Should be "altr,a10sr-gpio"
+- gpio-controller   : Marks the device node as a GPIO Controller.
+- #gpio-cells       : Should be two.  The first cell is the pin number and
+                      the second cell is used to specify flags.
+                      See ../gpio/gpio.txt for more information.
+
+Example:
+
+        resource-manager@0 {
+		compatible = "altr,a10sr";
+		reg = <0>;
+		spi-max-frequency = <100000>;
+		interrupt-parent = <&portb>;
+		interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+
+		a10sr_gpio: gpio-controller {
+			compatible = "altr,a10sr-gpio";
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+	};

Documentation/devicetree/bindings/mfd/qcom-pm8xxx.txt

@@ -10,6 +10,7 @@ voltages and other various functionality to Qualcomm SoCs.
 	Value type: <string>
 	Definition: must be one of:
 		    "qcom,pm8058"
+		    "qcom,pm8821"
 		    "qcom,pm8921"
 
 - #address-cells:

Documentation/devicetree/bindings/mfd/rn5t618.txt

 * Ricoh RN5T567/RN5T618 PMIC
 
-Ricoh RN5T567/RN5T618 is a power management IC family which integrates
-3 to 4 step-down DCDC converters, 7 low-dropout regulators, GPIOs and
-a watchdog timer. The RN5T618 provides additionally a Li-ion battery
-charger, fuel gauge and an ADC. It can be controlled through an I2C
-interface.
+Ricoh RN5T567/RN5T618/RC5T619 is a power management IC family which
+integrates 3 to 5 step-down DCDC converters, 7 to 10 low-dropout regulators,
+GPIOs, and a watchdog timer. It can be controlled through an I2C interface.
+The RN5T618/RC5T619 provides additionally a Li-ion battery charger,
+fuel gauge, and an ADC.
+The RC5T619 additionnally includes USB charger detection and an RTC.
 
 Required properties:
  - compatible: must be one of
 		"ricoh,rn5t567"
 		"ricoh,rn5t618"
+		"ricoh,rc5t619"
  - reg: the I2C slave address of the device
 
 Sub-nodes:
  - regulators: the node is required if the regulator functionality is
    needed. The valid regulator names are: DCDC1, DCDC2, DCDC3, DCDC4
-   (RN5T567), LDO1, LDO2, LDO3, LDO4, LDO5, LDORTC1 and LDORTC2.
+   (RN5T567/RC5T619), LDO1, LDO2, LDO3, LDO4, LDO5, LDO6, LDO7, LDO8,
+   LDO9, LDO10, LDORTC1 and LDORTC2.
+   LDO7-10 are specific to RC5T619.
    The common bindings for each individual regulator can be found in:
    Documentation/devicetree/bindings/regulator/regulator.txt
 

Documentation/devicetree/bindings/regulator/tps65218.txt

 TPS65218 family of regulators
 
 Required properties:
-For tps65218 regulators/LDOs
-- compatible:
-  - "ti,tps65218-dcdc1" for DCDC1
-  - "ti,tps65218-dcdc2" for DCDC2
-  - "ti,tps65218-dcdc3" for DCDC3
-  - "ti,tps65218-dcdc4" for DCDC4
-  - "ti,tps65218-dcdc5" for DCDC5
-  - "ti,tps65218-dcdc6" for DCDC6
-  - "ti,tps65218-ldo1" for LDO1
-
-Optional properties:
-- Any optional property defined in bindings/regulator/regulator.txt
+- compatible: "ti,tps65218"
+- reg: I2C slave address
+
+- List of regulators provided by this controller, must be named
+  after their hardware counterparts: dcdc[1-6] and ldo1
+- This is the list of child nodes that specify the regulator
+  initialization data for defined regulators. Not all regulators for the given
+  device need to be present. The definition for each of these nodes is defined
+  using the standard binding for regulators found at ./regulator.txt.
+
+  The valid names for regulators are:
+  tps65217: regulator-dcdc1, regulator-dcdc2, regulator-dcdc3, regulator-dcdc4,
+  regulator-dcdc5, regulator-dcdc6, regulator-ldo1, regulator-ls3.
+  Each regulator is defined using the standard binding for regulators.
 
 Example:
+tps65218: tps65218@24 {
+	reg = <0x24>;
+	compatible = "ti,tps65218";
+	interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* NMIn */
+	interrupt-controller;
+	#interrupt-cells = <2>;
+
+	dcdc1: regulator-dcdc1 {
+		regulator-name = "vdd_core";
+		regulator-min-microvolt = <912000>;
+		regulator-max-microvolt = <1144000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	dcdc2: regulator-dcdc2 {
+		regulator-name = "vdd_mpu";
+		regulator-min-microvolt = <912000>;
+		regulator-max-microvolt = <1378000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	dcdc3: regulator-dcdc3 {
+		regulator-name = "vdcdc3";
+		regulator-min-microvolt = <1500000>;
+		regulator-max-microvolt = <1500000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	dcdc5: regulator-dcdc5 {
+		regulator-name = "v1_0bat";
+		regulator-min-microvolt = <1000000>;
+		regulator-max-microvolt = <1000000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	dcdc6: regulator-dcdc6 {
+		regulator-name = "v1_8bat";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	ldo1: regulator-ldo1 {
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
 
-	xyz: regulator@0 {
-		compatible = "ti,tps65218-dcdc1";
-		regulator-min-microvolt  = <1000000>;
-		regulator-max-microvolt  = <3000000>;
+	ls3: regulator-ls3 {
+		regulator-min-microvolt = <100000>;
+		regulator-max-microvolt = <1000000>;
 	};
+};

drivers/gpio/gpio-tps65218.c

@@ -16,6 +16,7 @@
 #include <linux/errno.h>
 #include <linux/gpio/driver.h>
 #include <linux/platform_device.h>
+#include <linux/regmap.h>
 #include <linux/mfd/tps65218.h>
 
 struct tps65218_gpio {
@@ -30,7 +31,7 @@ static int tps65218_gpio_get(struct gpio_chip *gc, unsigned offset)
 	unsigned int val;
 	int ret;
 
-	ret = tps65218_reg_read(tps65218, TPS65218_REG_ENABLE2, &val);
+	ret = regmap_read(tps65218->regmap, TPS65218_REG_ENABLE2, &val);
 	if (ret)
 		return ret;
 

drivers/input/misc/tps65218-pwrbutton.c

@@ -150,12 +150,20 @@ static int tps6521x_pb_probe(struct platform_device *pdev)
 	return 0;
 }
 
+static const struct platform_device_id tps6521x_pwrbtn_id_table[] = {
+	{ "tps65218-pwrbutton", },
+	{ "tps65217-pwrbutton", },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(platform, tps6521x_pwrbtn_id_table);
+
 static struct platform_driver tps6521x_pb_driver = {
 	.probe	= tps6521x_pb_probe,
 	.driver	= {
 		.name	= "tps6521x_pwrbutton",
 		.of_match_table = of_tps6521x_pb_match,
 	},
+	.id_table = tps6521x_pwrbtn_id_table,
 };
 module_platform_driver(tps6521x_pb_driver);
 

drivers/mfd/Kconfig

@@ -40,6 +40,22 @@ config MFD_ACT8945A
 	  linear regulators, along with a complete ActivePath battery
 	  charger.
 
+config MFD_SUN4I_GPADC
+	tristate "Allwinner sunxi platforms' GPADC MFD driver"
+	select MFD_CORE
+	select REGMAP_MMIO
+	select REGMAP_IRQ
+	depends on ARCH_SUNXI || COMPILE_TEST
+	help
+	  Select this to get support for Allwinner SoCs (A10, A13 and A31) ADC.
+	  This driver will only map the hardware interrupt and registers, you
+	  have to select individual drivers based on this MFD to be able to use
+	  the ADC or the thermal sensor. This will try to probe the ADC driver
+	  sun4i-gpadc-iio and the hwmon driver iio_hwmon.
+
+	  To compile this driver as a module, choose M here: the module will be
+	  called sun4i-gpadc.
+
 config MFD_AS3711
 	bool "AMS AS3711"
 	select MFD_CORE
@@ -293,6 +309,7 @@ config MFD_DLN2
 
 config MFD_EXYNOS_LPASS
 	tristate "Samsung Exynos SoC Low Power Audio Subsystem"
+	depends on ARCH_EXYNOS || COMPILE_TEST
 	select MFD_CORE
 	select REGMAP_MMIO
 	help
@@ -563,7 +580,7 @@ config MFD_MAX14577
 config MFD_MAX77620
 	bool "Maxim Semiconductor MAX77620 and MAX20024 PMIC Support"
 	depends on I2C=y
-	depends on OF
+	depends on OF || COMPILE_TEST
 	select MFD_CORE
 	select REGMAP_I2C
 	select REGMAP_IRQ
@@ -578,7 +595,7 @@ config MFD_MAX77620
 config MFD_MAX77686
 	tristate "Maxim Semiconductor MAX77686/802 PMIC Support"
 	depends on I2C
-	depends on OF
+	depends on OF || COMPILE_TEST
 	select MFD_CORE
 	select REGMAP_I2C
 	select REGMAP_IRQ
@@ -877,7 +894,8 @@ config MFD_RN5T618
 	select MFD_CORE
 	select REGMAP_I2C
 	help
-	  Say yes here to add support for the Ricoh RN5T567 or R5T618 PMIC.
+	  Say yes here to add support for the Ricoh RN5T567,
+          RN5T618, RC5T619 PMIC.
 	  This driver provides common support for accessing the device,
 	  additional drivers must be enabled in order to use the
 	  functionality of the device.
@@ -951,7 +969,7 @@ config MFD_SMSC
 
 config ABX500_CORE
 	bool "ST-Ericsson ABX500 Mixed Signal Circuit register functions"
-	default y if ARCH_U300 || ARCH_U8500
+	default y if ARCH_U300 || ARCH_U8500 || COMPILE_TEST
 	help
 	  Say yes here if you have the ABX500 Mixed Signal IC family
 	  chips. This core driver expose register access functions.

drivers/mfd/Makefile

@@ -211,3 +211,4 @@ obj-$(CONFIG_INTEL_SOC_PMIC)	+= intel-soc-pmic.o
 obj-$(CONFIG_MFD_MT6397)	+= mt6397-core.o
 
 obj-$(CONFIG_MFD_ALTERA_A10SR)	+= altera-a10sr.o
+obj-$(CONFIG_MFD_SUN4I_GPADC)	+= sun4i-gpadc.o

drivers/mfd/ab3100-core.c

@@ -12,7 +12,7 @@
 #include <linux/notifier.h>
 #include <linux/slab.h>
 #include <linux/err.h>
-#include <linux/module.h>
+#include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/device.h>
 #include <linux/interrupt.h>
@@ -628,20 +628,10 @@ static void ab3100_setup_debugfs(struct ab3100 *ab3100)
  exit_no_debugfs:
 	return;
 }
-static inline void ab3100_remove_debugfs(void)
-{
-	debugfs_remove(ab3100_set_reg_file);
-	debugfs_remove(ab3100_get_reg_file);
-	debugfs_remove(ab3100_reg_file);
-	debugfs_remove(ab3100_dir);
-}
 #else
 static inline void ab3100_setup_debugfs(struct ab3100 *ab3100)
 {
 }
-static inline void ab3100_remove_debugfs(void)
-{
-}
 #endif
 
 /*
@@ -949,45 +939,22 @@ static int ab3100_probe(struct i2c_client *client,
 	return err;
 }
 
-static int ab3100_remove(struct i2c_client *client)
-{
-	struct ab3100 *ab3100 = i2c_get_clientdata(client);
-
-	/* Unregister subdevices */
-	mfd_remove_devices(&client->dev);
-	ab3100_remove_debugfs();
-	i2c_unregister_device(ab3100->testreg_client);
-	return 0;
-}
-
 static const struct i2c_device_id ab3100_id[] = {
 	{ "ab3100", 0 },
 	{ }
 };
-MODULE_DEVICE_TABLE(i2c, ab3100_id);
 
 static struct i2c_driver ab3100_driver = {
 	.driver = {
-		.name	= "ab3100",
+		.name			= "ab3100",
+		.suppress_bind_attrs	= true,
 	},
 	.id_table	= ab3100_id,
 	.probe		= ab3100_probe,
-	.remove		= ab3100_remove,
 };
 
 static int __init ab3100_i2c_init(void)
 {
 	return i2c_add_driver(&ab3100_driver);
 }
-
-static void __exit ab3100_i2c_exit(void)
-{
-	i2c_del_driver(&ab3100_driver);
-}
-
 subsys_initcall(ab3100_i2c_init);
-module_exit(ab3100_i2c_exit);
-
-MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>");
-MODULE_DESCRIPTION("AB3100 core driver");
-MODULE_LICENSE("GPL");

drivers/mfd/ab8500-core.c

@@ -14,7 +14,7 @@
 #include <linux/irqdomain.h>
 #include <linux/delay.h>
 #include <linux/interrupt.h>
-#include <linux/module.h>
+#include <linux/moduleparam.h>
 #include <linux/platform_device.h>
 #include <linux/mfd/core.h>
 #include <linux/mfd/abx500.h>
@@ -123,6 +123,10 @@ static DEFINE_SPINLOCK(on_stat_lock);
 static u8 turn_on_stat_mask = 0xFF;
 static u8 turn_on_stat_set;
 static bool no_bm; /* No battery management */
+/*
+ * not really modular, but the easiest way to keep compat with existing
+ * bootargs behaviour is to continue using module_param here.
+ */
 module_param(no_bm, bool, S_IRUGO);
 
 #define AB9540_MODEM_CTRL2_REG			0x23
@@ -1324,25 +1328,6 @@ static int ab8500_probe(struct platform_device *pdev)
 	return ret;
 }
 
-static int ab8500_remove(struct platform_device *pdev)
-{
-	struct ab8500 *ab8500 = platform_get_drvdata(pdev);
-
-	if (((is_ab8505(ab8500) || is_ab9540(ab8500)) &&
-			ab8500->chip_id >= AB8500_CUT2P0) || is_ab8540(ab8500))
-		sysfs_remove_group(&ab8500->dev->kobj, &ab9540_attr_group);
-	else
-		sysfs_remove_group(&ab8500->dev->kobj, &ab8500_attr_group);
-
-	if ((is_ab8505(ab8500) || is_ab9540(ab8500)) &&
-			ab8500->chip_id >= AB8500_CUT2P0)
-		sysfs_remove_group(&ab8500->dev->kobj, &ab8505_attr_group);
-
-	mfd_remove_devices(ab8500->dev);
-
-	return 0;
-}
-
 static const struct platform_device_id ab8500_id[] = {
 	{ "ab8500-core", AB8500_VERSION_AB8500 },
 	{ "ab8505-i2c", AB8500_VERSION_AB8505 },
@@ -1354,9 +1339,9 @@ static const struct platform_device_id ab8500_id[] = {
 static struct platform_driver ab8500_core_driver = {
 	.driver = {
 		.name = "ab8500-core",
+		.suppress_bind_attrs = true,
 	},
 	.probe	= ab8500_probe,
-	.remove	= ab8500_remove,
 	.id_table = ab8500_id,
 };
 
@@ -1364,14 +1349,4 @@ static int __init ab8500_core_init(void)
 {
 	return platform_driver_register(&ab8500_core_driver);
 }
-
-static void __exit ab8500_core_exit(void)
-{
-	platform_driver_unregister(&ab8500_core_driver);
-}
 core_initcall(ab8500_core_init);
-module_exit(ab8500_core_exit);
-
-MODULE_AUTHOR("Mattias Wallin, Srinidhi Kasagar, Rabin Vincent");
-MODULE_DESCRIPTION("AB8500 MFD core");
-MODULE_LICENSE("GPL v2");

drivers/mfd/ab8500-debugfs.c

@@ -74,7 +74,7 @@
 #include <linux/seq_file.h>
 #include <linux/uaccess.h>
 #include <linux/fs.h>
-#include <linux/module.h>
+#include <linux/init.h>
 #include <linux/debugfs.h>
 #include <linux/platform_device.h>
 #include <linux/interrupt.h>
@@ -3234,33 +3234,16 @@ static int ab8500_debug_probe(struct platform_device *plf)
 	return -ENOMEM;
 }
 
-static int ab8500_debug_remove(struct platform_device *plf)
-{
-	debugfs_remove_recursive(ab8500_dir);
-
-	return 0;
-}
-
 static struct platform_driver ab8500_debug_driver = {
 	.driver = {
 		.name = "ab8500-debug",
+		.suppress_bind_attrs = true,
 	},
 	.probe  = ab8500_debug_probe,
-	.remove = ab8500_debug_remove
 };
 
 static int __init ab8500_debug_init(void)
 {
 	return platform_driver_register(&ab8500_debug_driver);
 }
-
-static void __exit ab8500_debug_exit(void)
-{
-	platform_driver_unregister(&ab8500_debug_driver);
-}
 subsys_initcall(ab8500_debug_init);
-module_exit(ab8500_debug_exit);
-
-MODULE_AUTHOR("Mattias WALLIN <mattias.wallin@stericsson.com");
-MODULE_DESCRIPTION("AB8500 DEBUG");
-MODULE_LICENSE("GPL v2");

drivers/mfd/ab8500-gpadc.c

@@ -5,9 +5,9 @@
  * Author: Arun R Murthy <arun.murthy@stericsson.com>
  * Author: Daniel Willerud <daniel.willerud@stericsson.com>
  * Author: Johan Palsson <johan.palsson@stericsson.com>
+ * Author: M'boumba Cedric Madianga
  */
 #include <linux/init.h>
-#include <linux/module.h>
 #include <linux/device.h>
 #include <linux/interrupt.h>
 #include <linux/spinlock.h>
@@ -1054,11 +1054,7 @@ static int __init ab8500_gpadc_init(void)
 {
 	return platform_driver_register(&ab8500_gpadc_driver);
 }
-
-static void __exit ab8500_gpadc_exit(void)
-{
-	platform_driver_unregister(&ab8500_gpadc_driver);
-}
+subsys_initcall_sync(ab8500_gpadc_init);
 
 /**
  * ab8540_gpadc_get_otp() - returns OTP values
@@ -1077,14 +1073,3 @@ void ab8540_gpadc_get_otp(struct ab8500_gpadc *gpadc,
 	*ibat_l  = gpadc->cal_data[ADC_INPUT_IBAT].otp_calib_lo;
 	*ibat_h  = gpadc->cal_data[ADC_INPUT_IBAT].otp_calib_hi;
 }
-
-subsys_initcall_sync(ab8500_gpadc_init);
-module_exit(ab8500_gpadc_exit);
-
-MODULE_LICENSE("GPL v2");
-MODULE_AUTHOR("Arun R Murthy");
-MODULE_AUTHOR("Daniel Willerud");
-MODULE_AUTHOR("Johan Palsson");
-MODULE_AUTHOR("M'boumba Cedric Madianga");
-MODULE_ALIAS("platform:ab8500_gpadc");
-MODULE_DESCRIPTION("AB8500 GPADC driver");

drivers/mfd/ab8500-sysctrl.c

 /*
+ * AB8500 system control driver
+ *
  * Copyright (C) ST-Ericsson SA 2010
  * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com> for ST Ericsson.
  * License terms: GNU General Public License (GPL) version 2
  */
 
 #include <linux/err.h>
-#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/export.h>
 #include <linux/platform_device.h>
 #include <linux/pm.h>
 #include <linux/reboot.h>
@@ -158,7 +161,3 @@ static int __init ab8500_sysctrl_init(void)
 	return platform_driver_register(&ab8500_sysctrl_driver);
 }
 arch_initcall(ab8500_sysctrl_init);
-
-MODULE_AUTHOR("Mattias Nilsson <mattias.i.nilsson@stericsson.com");
-MODULE_DESCRIPTION("AB8500 system control driver");
-MODULE_LICENSE("GPL v2");

drivers/mfd/abx500-core.c

@@ -8,7 +8,8 @@
 #include <linux/list.h>
 #include <linux/slab.h>
 #include <linux/err.h>
-#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/export.h>
 #include <linux/mfd/abx500.h>
 
 static LIST_HEAD(abx500_list);
@@ -150,7 +151,3 @@ int abx500_startup_irq_enabled(struct device *dev, unsigned int irq)
 		return -ENOTSUPP;
 }
 EXPORT_SYMBOL(abx500_startup_irq_enabled);
-
-MODULE_AUTHOR("Mattias Wallin <mattias.wallin@stericsson.com>");
-MODULE_DESCRIPTION("ABX500 core driver");
-MODULE_LICENSE("GPL");

drivers/mfd/arizona-core.c

@@ -1553,6 +1553,7 @@ EXPORT_SYMBOL_GPL(arizona_dev_init);
 
 int arizona_dev_exit(struct arizona *arizona)
 {
+	disable_irq(arizona->irq);
 	pm_runtime_disable(arizona->dev);
 
 	regulator_disable(arizona->dcvdd);

drivers/mfd/arizona-irq.c

@@ -398,10 +398,10 @@ int arizona_irq_init(struct arizona *arizona)
 err_boot_done:
 	free_irq(arizona->irq, arizona);
 err_main_irq:
-	regmap_del_irq_chip(irq_create_mapping(arizona->virq, 1),
+	regmap_del_irq_chip(irq_find_mapping(arizona->virq, 1),
 			    arizona->irq_chip);
 err_aod:
-	regmap_del_irq_chip(irq_create_mapping(arizona->virq, 0),
+	regmap_del_irq_chip(irq_find_mapping(arizona->virq, 0),
 			    arizona->aod_irq_chip);
 err:
 	return ret;
@@ -413,9 +413,9 @@ int arizona_irq_exit(struct arizona *arizona)
 		free_irq(arizona_map_irq(arizona, ARIZONA_IRQ_CTRLIF_ERR),
 			 arizona);
 	free_irq(arizona_map_irq(arizona, ARIZONA_IRQ_BOOT_DONE), arizona);
-	regmap_del_irq_chip(irq_create_mapping(arizona->virq, 1),
+	regmap_del_irq_chip(irq_find_mapping(arizona->virq, 1),
 			    arizona->irq_chip);
-	regmap_del_irq_chip(irq_create_mapping(arizona->virq, 0),
+	regmap_del_irq_chip(irq_find_mapping(arizona->virq, 0),
 			    arizona->aod_irq_chip);
 	free_irq(arizona->irq, arizona);
 

drivers/mfd/axp20x-i2c.c

@@ -69,10 +69,11 @@ static const struct of_device_id axp20x_i2c_of_match[] = {
 };
 MODULE_DEVICE_TABLE(of, axp20x_i2c_of_match);
 
-/*
- * This is useless for OF-enabled devices, but it is needed by I2C subsystem
- */
 static const struct i2c_device_id axp20x_i2c_id[] = {
+	{ "axp152", 0 },
+	{ "axp202", 0 },
+	{ "axp209", 0 },
+	{ "axp221", 0 },
 	{ },
 };
 MODULE_DEVICE_TABLE(i2c, axp20x_i2c_id);

drivers/mfd/axp20x.c

@@ -98,6 +98,7 @@ static const struct regmap_range axp22x_volatile_ranges[] = {
 	regmap_reg_range(AXP20X_PWR_INPUT_STATUS, AXP20X_PWR_OP_MODE),
 	regmap_reg_range(AXP20X_IRQ1_EN, AXP20X_IRQ5_STATE),
 	regmap_reg_range(AXP22X_GPIO_STATE, AXP22X_GPIO_STATE),
+	regmap_reg_range(AXP22X_PMIC_ADC_H, AXP20X_IPSOUT_V_HIGH_L),
 	regmap_reg_range(AXP20X_FG_RES, AXP20X_FG_RES),
 };
 
@@ -135,6 +136,7 @@ static const struct regmap_range axp806_writeable_ranges[] = {
 	regmap_reg_range(AXP806_PWR_OUT_CTRL1, AXP806_CLDO3_V_CTRL),
 	regmap_reg_range(AXP20X_IRQ1_EN, AXP20X_IRQ2_EN),
 	regmap_reg_range(AXP20X_IRQ1_STATE, AXP20X_IRQ2_STATE),
+	regmap_reg_range(AXP806_REG_ADDR_EXT, AXP806_REG_ADDR_EXT),
 };
 
 static const struct regmap_range axp806_volatile_ranges[] = {
@@ -305,7 +307,7 @@ static const struct regmap_config axp806_regmap_config = {
 	.val_bits	= 8,
 	.wr_table	= &axp806_writeable_table,
 	.volatile_table	= &axp806_volatile_table,
-	.max_register	= AXP806_VREF_TEMP_WARN_L,
+	.max_register	= AXP806_REG_ADDR_EXT,
 	.cache_type	= REGCACHE_RBTREE,
 };
 

drivers/mfd/bcm590xx.c

@@ -67,7 +67,7 @@ static int bcm590xx_i2c_probe(struct i2c_client *i2c_pri,
 	/* Secondary I2C slave address is the base address with A(2) asserted */
 	bcm590xx->i2c_sec = i2c_new_dummy(i2c_pri->adapter,
 					  i2c_pri->addr | BIT(2));
-	if (IS_ERR_OR_NULL(bcm590xx->i2c_sec)) {
+	if (!bcm590xx->i2c_sec) {
 		dev_err(&i2c_pri->dev, "failed to add secondary I2C device\n");
 		return -ENODEV;
 	}

drivers/mfd/cs47l24-tables.c

@@ -292,6 +292,7 @@ static const struct reg_default cs47l24_reg_default[] = {
 	{ 0x00000502, 0x0000 },    /* R1282  - AIF1 Rx Pin Ctrl */
 	{ 0x00000503, 0x0000 },    /* R1283  - AIF1 Rate Ctrl */
 	{ 0x00000504, 0x0000 },    /* R1284  - AIF1 Format */
+	{ 0x00000505, 0x0040 },    /* R1285  - AIF1 Tx BCLK Rate */
 	{ 0x00000506, 0x0040 },    /* R1286  - AIF1 Rx BCLK Rate */
 	{ 0x00000507, 0x1818 },    /* R1287  - AIF1 Frame Ctrl 1 */
 	{ 0x00000508, 0x1818 },    /* R1288  - AIF1 Frame Ctrl 2 */
@@ -318,6 +319,7 @@ static const struct reg_default cs47l24_reg_default[] = {
 	{ 0x00000542, 0x0000 },    /* R1346  - AIF2 Rx Pin Ctrl */
 	{ 0x00000543, 0x0000 },    /* R1347  - AIF2 Rate Ctrl */
 	{ 0x00000544, 0x0000 },    /* R1348  - AIF2 Format */
+	{ 0x00000545, 0x0040 },    /* R1349  - AIF2 Tx BCLK Rate */
 	{ 0x00000546, 0x0040 },    /* R1350  - AIF2 Rx BCLK Rate */
 	{ 0x00000547, 0x1818 },    /* R1351  - AIF2 Frame Ctrl 1 */
 	{ 0x00000548, 0x1818 },    /* R1352  - AIF2 Frame Ctrl 2 */
@@ -340,6 +342,7 @@ static const struct reg_default cs47l24_reg_default[] = {
 	{ 0x00000582, 0x0000 },    /* R1410  - AIF3 Rx Pin Ctrl */
 	{ 0x00000583, 0x0000 },    /* R1411  - AIF3 Rate Ctrl */
 	{ 0x00000584, 0x0000 },    /* R1412  - AIF3 Format */
+	{ 0x00000585, 0x0040 },    /* R1413  - AIF3 Tx BCLK Rate */
 	{ 0x00000586, 0x0040 },    /* R1414  - AIF3 Rx BCLK Rate */
 	{ 0x00000587, 0x1818 },    /* R1415  - AIF3 Frame Ctrl 1 */
 	{ 0x00000588, 0x1818 },    /* R1416  - AIF3 Frame Ctrl 2 */
@@ -923,6 +926,7 @@ static bool cs47l24_readable_register(struct device *dev, unsigned int reg)
 	case ARIZONA_AIF1_RX_PIN_CTRL:
 	case ARIZONA_AIF1_RATE_CTRL:
 	case ARIZONA_AIF1_FORMAT:
+	case ARIZONA_AIF1_TX_BCLK_RATE:
 	case ARIZONA_AIF1_RX_BCLK_RATE:
 	case ARIZONA_AIF1_FRAME_CTRL_1:
 	case ARIZONA_AIF1_FRAME_CTRL_2:
@@ -949,6 +953,7 @@ static bool cs47l24_readable_register(struct device *dev, unsigned int reg)
 	case ARIZONA_AIF2_RX_PIN_CTRL:
 	case ARIZONA_AIF2_RATE_CTRL:
 	case ARIZONA_AIF2_FORMAT:
+	case ARIZONA_AIF2_TX_BCLK_RATE:
 	case ARIZONA_AIF2_RX_BCLK_RATE:
 	case ARIZONA_AIF2_FRAME_CTRL_1:
 	case ARIZONA_AIF2_FRAME_CTRL_2:
@@ -971,6 +976,7 @@ static bool cs47l24_readable_register(struct device *dev, unsigned int reg)
 	case ARIZONA_AIF3_RX_PIN_CTRL:
 	case ARIZONA_AIF3_RATE_CTRL:
 	case ARIZONA_AIF3_FORMAT:
+	case ARIZONA_AIF3_TX_BCLK_RATE:
 	case ARIZONA_AIF3_RX_BCLK_RATE:
 	case ARIZONA_AIF3_FRAME_CTRL_1:
 	case ARIZONA_AIF3_FRAME_CTRL_2:

drivers/mfd/davinci_voicecodec.c

@@ -32,6 +32,7 @@
 #include <sound/pcm.h>
 
 #include <linux/mfd/davinci_voicecodec.h>
+#include <mach/hardware.h>
 
 static const struct regmap_config davinci_vc_regmap = {
 	.reg_bits = 32,

drivers/mfd/fsl-imx25-tsadc.c

@@ -187,6 +187,7 @@ static const struct of_device_id mx25_tsadc_ids[] = {
 	{ .compatible = "fsl,imx25-tsadc" },
 	{ /* Sentinel */ }
 };
+MODULE_DEVICE_TABLE(of, mx25_tsadc_ids);
 
 static struct platform_driver mx25_tsadc_driver = {
 	.driver = {

drivers/mfd/hi655x-pmic.c

@@ -169,6 +169,7 @@ static const struct of_device_id hi655x_pmic_match[] = {
 	{ .compatible = "hisilicon,hi655x-pmic", },
 	{},
 };
+MODULE_DEVICE_TABLE(of, hi655x_pmic_match);
 
 static struct platform_driver hi655x_pmic_driver = {
 	.driver	= {

drivers/mfd/intel-lpss-pci.c

@@ -41,6 +41,7 @@ static int intel_lpss_pci_probe(struct pci_dev *pdev,
 
 	/* Probably it is enough to set this for iDMA capable devices only */
 	pci_set_master(pdev);
+	pci_try_set_mwi(pdev);
 
 	ret = intel_lpss_probe(&pdev->dev, info);
 	if (ret)

drivers/mfd/intel_soc_pmic_bxtwc.c

@@ -519,7 +519,7 @@ static const struct acpi_device_id bxtwc_acpi_ids[] = {
 	{ "INT34D3", },
 	{ }
 };
-MODULE_DEVICE_TABLE(acpi, pmic_acpi_ids);
+MODULE_DEVICE_TABLE(acpi, bxtwc_acpi_ids);
 
 static struct platform_driver bxtwc_driver = {
 	.probe = bxtwc_probe,

drivers/mfd/lpc_ich.c

@@ -493,6 +493,7 @@ static struct lpc_ich_info lpc_chipset_info[] = {
 	[LPC_LPT] = {
 		.name = "Lynx Point",
 		.iTCO_version = 2,
+		.gpio_version = ICH_V5_GPIO,
 	},
 	[LPC_LPT_LP] = {
 		.name = "Lynx Point_LP",
@@ -530,6 +531,7 @@ static struct lpc_ich_info lpc_chipset_info[] = {
 	[LPC_9S] = {
 		.name = "9 Series",
 		.iTCO_version = 2,
+		.gpio_version = ICH_V5_GPIO,
 	},
 };
 

drivers/mfd/palmas.c

@@ -431,9 +431,6 @@ static void palmas_power_off(void)
 	unsigned int addr;
 	int ret, slave;
 
-	if (!palmas_dev)
-		return;
-
 	slave = PALMAS_BASE_TO_SLAVE(PALMAS_PMU_CONTROL_BASE);
 	addr = PALMAS_BASE_TO_REG(PALMAS_PMU_CONTROL_BASE, PALMAS_DEV_CTRL);
 

drivers/mfd/qcom-pm8xxx.c

@@ -39,6 +39,20 @@
 #define	SSBI_REG_ADDR_IRQ_CONFIG	(SSBI_REG_ADDR_IRQ_BASE + 7)
 #define	SSBI_REG_ADDR_IRQ_RT_STATUS	(SSBI_REG_ADDR_IRQ_BASE + 8)
 
+#define	PM8821_SSBI_REG_ADDR_IRQ_BASE	0x100
+#define	PM8821_SSBI_REG_ADDR_IRQ_MASTER0 (PM8821_SSBI_REG_ADDR_IRQ_BASE + 0x30)
+#define	PM8821_SSBI_REG_ADDR_IRQ_MASTER1 (PM8821_SSBI_REG_ADDR_IRQ_BASE + 0xb0)
+#define	PM8821_SSBI_REG(m, b, offset) \
+			((m == 0) ? \
+			(PM8821_SSBI_REG_ADDR_IRQ_MASTER0 + b + offset) : \
+			(PM8821_SSBI_REG_ADDR_IRQ_MASTER1 + b + offset))
+#define	PM8821_SSBI_ADDR_IRQ_ROOT(m, b)		PM8821_SSBI_REG(m, b, 0x0)
+#define	PM8821_SSBI_ADDR_IRQ_CLEAR(m, b)	PM8821_SSBI_REG(m, b, 0x01)
+#define	PM8821_SSBI_ADDR_IRQ_MASK(m, b)		PM8821_SSBI_REG(m, b, 0x08)
+#define	PM8821_SSBI_ADDR_IRQ_RT_STATUS(m, b)	PM8821_SSBI_REG(m, b, 0x0f)
+
+#define	PM8821_BLOCKS_PER_MASTER	7
+
 #define	PM_IRQF_LVL_SEL			0x01	/* level select */
 #define	PM_IRQF_MASK_FE			0x02	/* mask falling edge */
 #define	PM_IRQF_MASK_RE			0x04	/* mask rising edge */
@@ -54,6 +68,7 @@
 #define REG_HWREV_2		0x0E8  /* PMIC4 revision 2 */
 
 #define PM8XXX_NR_IRQS		256
+#define PM8821_NR_IRQS		112
 
 struct pm_irq_chip {
 	struct regmap		*regmap;
@@ -65,6 +80,12 @@ struct pm_irq_chip {
 	u8			config[0];
 };
 
+struct pm_irq_data {
+	int num_irqs;
+	const struct irq_domain_ops  *irq_domain_ops;
+	void (*irq_handler)(struct irq_desc *desc);
+};
+
 static int pm8xxx_read_block_irq(struct pm_irq_chip *chip, unsigned int bp,
 				 unsigned int *ip)
 {
@@ -182,6 +203,78 @@ static void pm8xxx_irq_handler(struct irq_desc *desc)
 	chained_irq_exit(irq_chip, desc);
 }
 
+static void pm8821_irq_block_handler(struct pm_irq_chip *chip,
+				     int master, int block)
+{
+	int pmirq, irq, i, ret;
+	unsigned int bits;
+
+	ret = regmap_read(chip->regmap,
+			  PM8821_SSBI_ADDR_IRQ_ROOT(master, block), &bits);
+	if (ret) {
+		pr_err("Reading block %d failed ret=%d", block, ret);
+		return;
+	}
+
+	/* Convert block offset to global block number */
+	block += (master * PM8821_BLOCKS_PER_MASTER) - 1;
+
+	/* Check IRQ bits */
+	for (i = 0; i < 8; i++) {
+		if (bits & BIT(i)) {
+			pmirq = block * 8 + i;
+			irq = irq_find_mapping(chip->irqdomain, pmirq);
+			generic_handle_irq(irq);
+		}
+	}
+}
+
+static inline void pm8821_irq_master_handler(struct pm_irq_chip *chip,
+					     int master, u8 master_val)
+{
+	int block;
+
+	for (block = 1; block < 8; block++)
+		if (master_val & BIT(block))
+			pm8821_irq_block_handler(chip, master, block);
+}
+
+static void pm8821_irq_handler(struct irq_desc *desc)
+{
+	struct pm_irq_chip *chip = irq_desc_get_handler_data(desc);
+	struct irq_chip *irq_chip = irq_desc_get_chip(desc);
+	unsigned int master;
+	int ret;
+
+	chained_irq_enter(irq_chip, desc);
+	ret = regmap_read(chip->regmap,
+			  PM8821_SSBI_REG_ADDR_IRQ_MASTER0, &master);
+	if (ret) {
+		pr_err("Failed to read master 0 ret=%d\n", ret);
+		goto done;
+	}
+
+	/* bits 1 through 7 marks the first 7 blocks in master 0 */
+	if (master & GENMASK(7, 1))
+		pm8821_irq_master_handler(chip, 0, master);
+
+	/* bit 0 marks if master 1 contains any bits */
+	if (!(master & BIT(0)))
+		goto done;
+
+	ret = regmap_read(chip->regmap,
+			  PM8821_SSBI_REG_ADDR_IRQ_MASTER1, &master);
+	if (ret) {
+		pr_err("Failed to read master 1 ret=%d\n", ret);
+		goto done;
+	}
+
+	pm8821_irq_master_handler(chip, 1, master);
+
+done:
+	chained_irq_exit(irq_chip, desc);
+}
+
 static void pm8xxx_irq_mask_ack(struct irq_data *d)
 {
 	struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
@@ -299,6 +392,104 @@ static const struct irq_domain_ops pm8xxx_irq_domain_ops = {
 	.map = pm8xxx_irq_domain_map,
 };
 
+static void pm8821_irq_mask_ack(struct irq_data *d)
+{
+	struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
+	unsigned int pmirq = irqd_to_hwirq(d);
+	u8 block, master;
+	int irq_bit, rc;
+
+	block = pmirq / 8;
+	master = block / PM8821_BLOCKS_PER_MASTER;
+	irq_bit = pmirq % 8;
+	block %= PM8821_BLOCKS_PER_MASTER;
+
+	rc = regmap_update_bits(chip->regmap,
+				PM8821_SSBI_ADDR_IRQ_MASK(master, block),
+				BIT(irq_bit), BIT(irq_bit));
+	if (rc) {
+		pr_err("Failed to mask IRQ:%d rc=%d\n", pmirq, rc);
+		return;
+	}
+
+	rc = regmap_update_bits(chip->regmap,
+				PM8821_SSBI_ADDR_IRQ_CLEAR(master, block),
+				BIT(irq_bit), BIT(irq_bit));
+	if (rc)
+		pr_err("Failed to CLEAR IRQ:%d rc=%d\n", pmirq, rc);
+}
+
+static void pm8821_irq_unmask(struct irq_data *d)
+{
+	struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
+	unsigned int pmirq = irqd_to_hwirq(d);
+	int irq_bit, rc;
+	u8 block, master;
+
+	block = pmirq / 8;
+	master = block / PM8821_BLOCKS_PER_MASTER;
+	irq_bit = pmirq % 8;
+	block %= PM8821_BLOCKS_PER_MASTER;
+
+	rc = regmap_update_bits(chip->regmap,
+				PM8821_SSBI_ADDR_IRQ_MASK(master, block),
+				BIT(irq_bit), ~BIT(irq_bit));
+	if (rc)
+		pr_err("Failed to read/write unmask IRQ:%d rc=%d\n", pmirq, rc);
+
+}
+
+static int pm8821_irq_get_irqchip_state(struct irq_data *d,
+					enum irqchip_irq_state which,
+					bool *state)
+{
+	struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
+	int rc, pmirq = irqd_to_hwirq(d);
+	u8 block, irq_bit, master;
+	unsigned int bits;
+
+	block = pmirq / 8;
+	master = block / PM8821_BLOCKS_PER_MASTER;
+	irq_bit = pmirq % 8;
+	block %= PM8821_BLOCKS_PER_MASTER;
+
+	rc = regmap_read(chip->regmap,
+		PM8821_SSBI_ADDR_IRQ_RT_STATUS(master, block), &bits);
+	if (rc) {
+		pr_err("Reading Status of IRQ %d failed rc=%d\n", pmirq, rc);
+		return rc;
+	}
+
+	*state = !!(bits & BIT(irq_bit));
+
+	return rc;
+}
+
+static struct irq_chip pm8821_irq_chip = {
+	.name		= "pm8821",
+	.irq_mask_ack	= pm8821_irq_mask_ack,
+	.irq_unmask	= pm8821_irq_unmask,
+	.irq_get_irqchip_state = pm8821_irq_get_irqchip_state,
+	.flags		= IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE,
+};
+
+static int pm8821_irq_domain_map(struct irq_domain *d, unsigned int irq,
+				   irq_hw_number_t hwirq)
+{
+	struct pm_irq_chip *chip = d->host_data;
+
+	irq_set_chip_and_handler(irq, &pm8821_irq_chip, handle_level_irq);
+	irq_set_chip_data(irq, chip);
+	irq_set_noprobe(irq);
+
+	return 0;
+}
+
+static const struct irq_domain_ops pm8821_irq_domain_ops = {
+	.xlate = irq_domain_xlate_twocell,
+	.map = pm8821_irq_domain_map,
+};
+
 static const struct regmap_config ssbi_regmap_config = {
 	.reg_bits = 16,
 	.val_bits = 8,
@@ -308,22 +499,41 @@ static const struct regmap_config ssbi_regmap_config = {
 	.reg_write = ssbi_reg_write
 };
 
+static const struct pm_irq_data pm8xxx_data = {
+	.num_irqs = PM8XXX_NR_IRQS,
+	.irq_domain_ops = &pm8xxx_irq_domain_ops,
+	.irq_handler = pm8xxx_irq_handler,
+};
+
+static const struct pm_irq_data pm8821_data = {
+	.num_irqs = PM8821_NR_IRQS,
+	.irq_domain_ops = &pm8821_irq_domain_ops,
+	.irq_handler = pm8821_irq_handler,
+};
+
 static const struct of_device_id pm8xxx_id_table[] = {
-	{ .compatible = "qcom,pm8018", },
-	{ .compatible = "qcom,pm8058", },
-	{ .compatible = "qcom,pm8921", },
+	{ .compatible = "qcom,pm8018", .data = &pm8xxx_data},
+	{ .compatible = "qcom,pm8058", .data = &pm8xxx_data},
+	{ .compatible = "qcom,pm8821", .data = &pm8821_data},
+	{ .compatible = "qcom,pm8921", .data = &pm8xxx_data},
 	{ }
 };
 MODULE_DEVICE_TABLE(of, pm8xxx_id_table);
 
 static int pm8xxx_probe(struct platform_device *pdev)
 {
+	const struct pm_irq_data *data;
 	struct regmap *regmap;
 	int irq, rc;
 	unsigned int val;
 	u32 rev;
 	struct pm_irq_chip *chip;
-	unsigned int nirqs = PM8XXX_NR_IRQS;
+
+	data = of_device_get_match_data(&pdev->dev);
+	if (!data) {
+		dev_err(&pdev->dev, "No matching driver data found\n");
+		return -EINVAL;
+	}
 
 	irq = platform_get_irq(pdev, 0);
 	if (irq < 0)
@@ -354,25 +564,26 @@ static int pm8xxx_probe(struct platform_device *pdev)
 	rev |= val << BITS_PER_BYTE;
 
 	chip = devm_kzalloc(&pdev->dev, sizeof(*chip) +
-					sizeof(chip->config[0]) * nirqs,
-					GFP_KERNEL);
+			    sizeof(chip->config[0]) * data->num_irqs,
+			    GFP_KERNEL);
 	if (!chip)
 		return -ENOMEM;
 
 	platform_set_drvdata(pdev, chip);
 	chip->regmap = regmap;
-	chip->num_irqs = nirqs;
+	chip->num_irqs = data->num_irqs;
 	chip->num_blocks = DIV_ROUND_UP(chip->num_irqs, 8);
 	chip->num_masters = DIV_ROUND_UP(chip->num_blocks, 8);
 	spin_lock_init(&chip->pm_irq_lock);
 
-	chip->irqdomain = irq_domain_add_linear(pdev->dev.of_node, nirqs,
-						&pm8xxx_irq_domain_ops,
+	chip->irqdomain = irq_domain_add_linear(pdev->dev.of_node,
+						data->num_irqs,
+						data->irq_domain_ops,
 						chip);
 	if (!chip->irqdomain)
 		return -ENODEV;
 
-	irq_set_chained_handler_and_data(irq, pm8xxx_irq_handler, chip);
+	irq_set_chained_handler_and_data(irq, data->irq_handler, chip);
 	irq_set_irq_wake(irq, 1);
 
 	rc = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);

drivers/mfd/rk808.c

@@ -290,6 +290,24 @@ static void rk808_device_shutdown(void)
 		dev_err(&rk808_i2c_client->dev, "power off error!\n");
 }
 
+static void rk818_device_shutdown(void)
+{
+	int ret;
+	struct rk808 *rk808 = i2c_get_clientdata(rk808_i2c_client);
+
+	if (!rk808) {
+		dev_warn(&rk808_i2c_client->dev,
+			 "have no rk818, so do nothing here\n");
+		return;
+	}
+
+	ret = regmap_update_bits(rk808->regmap,
+				 RK818_DEVCTRL_REG,
+				 DEV_OFF, DEV_OFF);
+	if (ret)
+		dev_err(&rk808_i2c_client->dev, "power off error!\n");
+}
+
 static const struct of_device_id rk808_of_match[] = {
 	{ .compatible = "rockchip,rk808" },
 	{ .compatible = "rockchip,rk818" },
@@ -304,6 +322,7 @@ static int rk808_probe(struct i2c_client *client,
 	struct rk808 *rk808;
 	const struct rk808_reg_data *pre_init_reg;
 	const struct mfd_cell *cells;
+	void (*pm_pwroff_fn)(void);
 	int nr_pre_init_regs;
 	int nr_cells;
 	int pm_off = 0;
@@ -331,6 +350,7 @@ static int rk808_probe(struct i2c_client *client,
 		nr_pre_init_regs = ARRAY_SIZE(rk808_pre_init_reg);
 		cells = rk808s;
 		nr_cells = ARRAY_SIZE(rk808s);
+		pm_pwroff_fn = rk808_device_shutdown;
 		break;
 	case RK818_ID:
 		rk808->regmap_cfg = &rk818_regmap_config;
@@ -339,6 +359,7 @@ static int rk808_probe(struct i2c_client *client,
 		nr_pre_init_regs = ARRAY_SIZE(rk818_pre_init_reg);
 		cells = rk818s;
 		nr_cells = ARRAY_SIZE(rk818s);
+		pm_pwroff_fn = rk818_device_shutdown;
 		break;
 	default:
 		dev_err(&client->dev, "Unsupported RK8XX ID %lu\n",
@@ -393,7 +414,7 @@ static int rk808_probe(struct i2c_client *client,
 				"rockchip,system-power-controller");
 	if (pm_off && !pm_power_off) {
 		rk808_i2c_client = client;
-		pm_power_off = rk808_device_shutdown;
+		pm_power_off = pm_pwroff_fn;
 	}
 
 	return 0;

drivers/mfd/rn5t618.c

@@ -87,6 +87,7 @@ static int rn5t618_restart(struct notifier_block *this,
 static const struct of_device_id rn5t618_of_match[] = {
 	{ .compatible = "ricoh,rn5t567", .data = (void *)RN5T567 },
 	{ .compatible = "ricoh,rn5t618", .data = (void *)RN5T618 },
+	{ .compatible = "ricoh,rc5t619", .data = (void *)RC5T619 },
 	{ }
 };
 MODULE_DEVICE_TABLE(of, rn5t618_of_match);

drivers/mfd/si476x-i2c.c

@@ -753,7 +753,7 @@ static int si476x_core_probe(struct i2c_client *client,
 				       ARRAY_SIZE(core->supplies),
 				       core->supplies);
 	if (rval) {
-		dev_err(&client->dev, "Failet to gett all of the regulators\n");
+		dev_err(&client->dev, "Failed to get all of the regulators\n");
 		goto free_gpio;
 	}
 

drivers/mfd/sun4i-gpadc.c

+/* ADC MFD core driver for sunxi platforms
+ *
+ * Copyright (c) 2016 Quentin Schulz <quentin.schulz@free-electrons.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/mfd/core.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/of_irq.h>
+#include <linux/regmap.h>
+
+#include <linux/mfd/sun4i-gpadc.h>
+
+#define ARCH_SUN4I_A10 0
+#define ARCH_SUN5I_A13 1
+#define ARCH_SUN6I_A31 2
+
+static struct resource adc_resources[] = {
+	DEFINE_RES_IRQ_NAMED(SUN4I_GPADC_IRQ_FIFO_DATA, "FIFO_DATA_PENDING"),
+	DEFINE_RES_IRQ_NAMED(SUN4I_GPADC_IRQ_TEMP_DATA, "TEMP_DATA_PENDING"),
+};
+
+static const struct regmap_irq sun4i_gpadc_regmap_irq[] = {
+	REGMAP_IRQ_REG(SUN4I_GPADC_IRQ_FIFO_DATA, 0,
+		       SUN4I_GPADC_INT_FIFOC_TP_DATA_IRQ_EN),
+	REGMAP_IRQ_REG(SUN4I_GPADC_IRQ_TEMP_DATA, 0,
+		       SUN4I_GPADC_INT_FIFOC_TEMP_IRQ_EN),
+};
+
+static const struct regmap_irq_chip sun4i_gpadc_regmap_irq_chip = {
+	.name = "sun4i_gpadc_irq_chip",
+	.status_base = SUN4I_GPADC_INT_FIFOS,
+	.ack_base = SUN4I_GPADC_INT_FIFOS,
+	.mask_base = SUN4I_GPADC_INT_FIFOC,
+	.init_ack_masked = true,
+	.mask_invert = true,
+	.irqs = sun4i_gpadc_regmap_irq,
+	.num_irqs = ARRAY_SIZE(sun4i_gpadc_regmap_irq),
+	.num_regs = 1,
+};
+
+static struct mfd_cell sun4i_gpadc_cells[] = {
+	{
+		.name	= "sun4i-a10-gpadc-iio",
+		.resources = adc_resources,
+		.num_resources = ARRAY_SIZE(adc_resources),
+	},
+	{ .name = "iio_hwmon" }
+};
+
+static struct mfd_cell sun5i_gpadc_cells[] = {
+	{
+		.name	= "sun5i-a13-gpadc-iio",
+		.resources = adc_resources,
+		.num_resources = ARRAY_SIZE(adc_resources),
+	},
+	{ .name = "iio_hwmon" },
+};
+
+static struct mfd_cell sun6i_gpadc_cells[] = {
+	{
+		.name	= "sun6i-a31-gpadc-iio",
+		.resources = adc_resources,
+		.num_resources = ARRAY_SIZE(adc_resources),
+	},
+	{ .name = "iio_hwmon" },
+};
+
+static const struct regmap_config sun4i_gpadc_regmap_config = {
+	.reg_bits = 32,
+	.val_bits = 32,
+	.reg_stride = 4,
+	.fast_io = true,
+};
+
+static const struct of_device_id sun4i_gpadc_of_match[] = {
+	{
+		.compatible = "allwinner,sun4i-a10-ts",
+		.data = (void *)ARCH_SUN4I_A10,
+	}, {
+		.compatible = "allwinner,sun5i-a13-ts",
+		.data = (void *)ARCH_SUN5I_A13,
+	}, {
+		.compatible = "allwinner,sun6i-a31-ts",
+		.data = (void *)ARCH_SUN6I_A31,
+	}, { /* sentinel */ }
+};
+
+MODULE_DEVICE_TABLE(of, sun4i_gpadc_of_match);
+
+static int sun4i_gpadc_probe(struct platform_device *pdev)
+{
+	struct sun4i_gpadc_dev *dev;
+	struct resource *mem;
+	const struct of_device_id *of_id;
+	const struct mfd_cell *cells;
+	unsigned int irq, size;
+	int ret;
+
+	of_id = of_match_node(sun4i_gpadc_of_match, pdev->dev.of_node);
+	if (!of_id)
+		return -EINVAL;
+
+	switch ((long)of_id->data) {
+	case ARCH_SUN4I_A10:
+		cells = sun4i_gpadc_cells;
+		size = ARRAY_SIZE(sun4i_gpadc_cells);
+		break;
+	case ARCH_SUN5I_A13:
+		cells = sun5i_gpadc_cells;
+		size = ARRAY_SIZE(sun5i_gpadc_cells);
+		break;
+	case ARCH_SUN6I_A31:
+		cells = sun6i_gpadc_cells;
+		size = ARRAY_SIZE(sun6i_gpadc_cells);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
+	if (!dev)
+		return -ENOMEM;
+
+	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	dev->base = devm_ioremap_resource(&pdev->dev, mem);
+	if (IS_ERR(dev->base))
+		return PTR_ERR(dev->base);
+
+	dev->dev = &pdev->dev;
+	dev_set_drvdata(dev->dev, dev);
+
+	dev->regmap = devm_regmap_init_mmio(dev->dev, dev->base,
+					    &sun4i_gpadc_regmap_config);
+	if (IS_ERR(dev->regmap)) {
+		ret = PTR_ERR(dev->regmap);
+		dev_err(&pdev->dev, "failed to init regmap: %d\n", ret);
+		return ret;
+	}
+
+	/* Disable all interrupts */
+	regmap_write(dev->regmap, SUN4I_GPADC_INT_FIFOC, 0);
+
+	irq = platform_get_irq(pdev, 0);
+	ret = devm_regmap_add_irq_chip(&pdev->dev, dev->regmap, irq,
+				       IRQF_ONESHOT, 0,
+				       &sun4i_gpadc_regmap_irq_chip,
+				       &dev->regmap_irqc);
+	if (ret) {
+		dev_err(&pdev->dev, "failed to add irq chip: %d\n", ret);
+		return ret;
+	}
+
+	ret = devm_mfd_add_devices(dev->dev, 0, cells, size, NULL, 0, NULL);
+	if (ret) {
+		dev_err(&pdev->dev, "failed to add MFD devices: %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static struct platform_driver sun4i_gpadc_driver = {
+	.driver = {
+		.name = "sun4i-gpadc",
+		.of_match_table = of_match_ptr(sun4i_gpadc_of_match),
+	},
+	.probe = sun4i_gpadc_probe,
+};
+
+module_platform_driver(sun4i_gpadc_driver);
+
+MODULE_DESCRIPTION("Allwinner sunxi platforms' GPADC MFD core driver");
+MODULE_AUTHOR("Quentin Schulz <quentin.schulz@free-electrons.com>");
+MODULE_LICENSE("GPL v2");

drivers/mfd/tc3589x.c

@@ -53,7 +53,7 @@ int tc3589x_reg_read(struct tc3589x *tc3589x, u8 reg)
 EXPORT_SYMBOL_GPL(tc3589x_reg_read);
 
 /**
- * tc3589x_reg_read() - write a single TC3589x register
+ * tc3589x_reg_write() - write a single TC3589x register
  * @tc3589x:	Device to write to
  * @reg:	Register to read
  * @data:	Value to write
@@ -118,7 +118,7 @@ EXPORT_SYMBOL_GPL(tc3589x_block_write);
  * @tc3589x:	Device to write to
  * @reg:	Register to write
  * @mask:	Mask of bits to set
- * @values:	Value to set
+ * @val:	Value to set
  */
 int tc3589x_set_bits(struct tc3589x *tc3589x, u8 reg, u8 mask, u8 val)
 {

drivers/mfd/tps65217.c

@@ -42,26 +42,6 @@ static struct resource pb_resources[] = {
 	DEFINE_RES_IRQ_NAMED(TPS65217_IRQ_PB, "PB"),
 };
 
-struct tps65217_irq {
-	int mask;
-	int interrupt;
-};
-
-static const struct tps65217_irq tps65217_irqs[] = {
-	[TPS65217_IRQ_PB] = {
-		.mask = TPS65217_INT_PBM,
-		.interrupt = TPS65217_INT_PBI,
-	},
-	[TPS65217_IRQ_AC] = {
-		.mask = TPS65217_INT_ACM,
-		.interrupt = TPS65217_INT_ACI,
-	},
-	[TPS65217_IRQ_USB] = {
-		.mask = TPS65217_INT_USBM,
-		.interrupt = TPS65217_INT_USBI,
-	},
-};
-
 static void tps65217_irq_lock(struct irq_data *data)
 {
 	struct tps65217 *tps = irq_data_get_irq_chip_data(data);
@@ -74,37 +54,32 @@ static void tps65217_irq_sync_unlock(struct irq_data *data)
 	struct tps65217 *tps = irq_data_get_irq_chip_data(data);
 	int ret;
 
-	ret = tps65217_reg_write(tps, TPS65217_REG_INT, tps->irq_mask,
-				TPS65217_PROTECT_NONE);
+	ret = tps65217_set_bits(tps, TPS65217_REG_INT, TPS65217_INT_MASK,
+				tps->irq_mask, TPS65217_PROTECT_NONE);
 	if (ret != 0)
 		dev_err(tps->dev, "Failed to sync IRQ masks\n");
 
 	mutex_unlock(&tps->irq_lock);
 }
 
-static inline const struct tps65217_irq *
-irq_to_tps65217_irq(struct tps65217 *tps, struct irq_data *data)
-{
-	return &tps65217_irqs[data->hwirq];
-}
-
 static void tps65217_irq_enable(struct irq_data *data)
 {
 	struct tps65217 *tps = irq_data_get_irq_chip_data(data);
-	const struct tps65217_irq *irq_data = irq_to_tps65217_irq(tps, data);
+	u8 mask = BIT(data->hwirq) << TPS65217_INT_SHIFT;
 
-	tps->irq_mask &= ~irq_data->mask;
+	tps->irq_mask &= ~mask;
 }
 
 static void tps65217_irq_disable(struct irq_data *data)
 {
 	struct tps65217 *tps = irq_data_get_irq_chip_data(data);
-	const struct tps65217_irq *irq_data = irq_to_tps65217_irq(tps, data);
+	u8 mask = BIT(data->hwirq) << TPS65217_INT_SHIFT;
 
-	tps->irq_mask |= irq_data->mask;
+	tps->irq_mask |= mask;
 }
 
 static struct irq_chip tps65217_irq_chip = {
+	.name			= "tps65217",
 	.irq_bus_lock		= tps65217_irq_lock,
 	.irq_bus_sync_unlock	= tps65217_irq_sync_unlock,
 	.irq_enable		= tps65217_irq_enable,
@@ -149,8 +124,8 @@ static irqreturn_t tps65217_irq_thread(int irq, void *data)
 		return IRQ_NONE;
 	}
 
-	for (i = 0; i < ARRAY_SIZE(tps65217_irqs); i++) {
-		if (status & tps65217_irqs[i].interrupt) {
+	for (i = 0; i < TPS65217_NUM_IRQ; i++) {
+		if (status & BIT(i)) {
 			handle_nested_irq(irq_find_mapping(tps->irq_domain, i));
 			handled = true;
 		}
@@ -188,10 +163,9 @@ static int tps65217_irq_init(struct tps65217 *tps, int irq)
 	tps->irq = irq;
 
 	/* Mask all interrupt sources */
-	tps->irq_mask = (TPS65217_INT_RESERVEDM | TPS65217_INT_PBM
-			| TPS65217_INT_ACM | TPS65217_INT_USBM);
-	tps65217_reg_write(tps, TPS65217_REG_INT, tps->irq_mask,
-			TPS65217_PROTECT_NONE);
+	tps->irq_mask = TPS65217_INT_MASK;
+	tps65217_set_bits(tps, TPS65217_REG_INT, TPS65217_INT_MASK,
+			  TPS65217_INT_MASK, TPS65217_PROTECT_NONE);
 
 	tps->irq_domain = irq_domain_add_linear(tps->dev->of_node,
 		TPS65217_NUM_IRQ, &tps65217_irq_domain_ops, tps);
@@ -209,6 +183,8 @@ static int tps65217_irq_init(struct tps65217 *tps, int irq)
 		return ret;
 	}
 
+	enable_irq_wake(irq);
+
 	return 0;
 }
 
@@ -424,6 +400,24 @@ static int tps65217_probe(struct i2c_client *client,
 	return 0;
 }
 
+static int tps65217_remove(struct i2c_client *client)
+{
+	struct tps65217 *tps = i2c_get_clientdata(client);
+	unsigned int virq;
+	int i;
+
+	for (i = 0; i < TPS65217_NUM_IRQ; i++) {
+		virq = irq_find_mapping(tps->irq_domain, i);
+		if (virq)
+			irq_dispose_mapping(virq);
+	}
+
+	irq_domain_remove(tps->irq_domain);
+	tps->irq_domain = NULL;
+
+	return 0;
+}
+
 static const struct i2c_device_id tps65217_id_table[] = {
 	{"tps65217", TPS65217},
 	{ /* sentinel */ }
@@ -437,6 +431,7 @@ static struct i2c_driver tps65217_driver = {
 	},
 	.id_table	= tps65217_id_table,
 	.probe		= tps65217_probe,
+	.remove		= tps65217_remove,
 };
 
 static int __init tps65217_init(void)

drivers/mfd/tps65218.c

@@ -33,19 +33,17 @@
 
 #define TPS65218_PASSWORD_REGS_UNLOCK   0x7D
 
-/**
- * tps65218_reg_read: Read a single tps65218 register.
- *
- * @tps: Device to read from.
- * @reg: Register to read.
- * @val: Contians the value
- */
-int tps65218_reg_read(struct tps65218 *tps, unsigned int reg,
-			unsigned int *val)
-{
-	return regmap_read(tps->regmap, reg, val);
-}
-EXPORT_SYMBOL_GPL(tps65218_reg_read);
+static const struct mfd_cell tps65218_cells[] = {
+	{
+		.name = "tps65218-pwrbutton",
+		.of_compatible = "ti,tps65218-pwrbutton",
+	},
+	{
+		.name = "tps65218-gpio",
+		.of_compatible = "ti,tps65218-gpio",
+	},
+	{ .name = "tps65218-regulator", },
+};
 
 /**
  * tps65218_reg_write: Write a single tps65218 register.
@@ -93,7 +91,7 @@ static int tps65218_update_bits(struct tps65218 *tps, unsigned int reg,
 	int ret;
 	unsigned int data;
 
-	ret = tps65218_reg_read(tps, reg, &data);
+	ret = regmap_read(tps->regmap, reg, &data);
 	if (ret) {
 		dev_err(tps->dev, "Read from reg 0x%x failed\n", reg);
 		return ret;
@@ -251,7 +249,7 @@ static int tps65218_probe(struct i2c_client *client,
 	if (ret < 0)
 		return ret;
 
-	ret = tps65218_reg_read(tps, TPS65218_REG_CHIPID, &chipid);
+	ret = regmap_read(tps->regmap, TPS65218_REG_CHIPID, &chipid);
 	if (ret) {
 		dev_err(tps->dev, "Failed to read chipid: %d\n", ret);
 		return ret;
@@ -259,8 +257,10 @@ static int tps65218_probe(struct i2c_client *client,
 
 	tps->rev = chipid & TPS65218_CHIPID_REV_MASK;
 
-	ret = of_platform_populate(client->dev.of_node, NULL, NULL,
-				   &client->dev);
+	ret = mfd_add_devices(tps->dev, PLATFORM_DEVID_AUTO, tps65218_cells,
+			      ARRAY_SIZE(tps65218_cells), NULL, 0,
+			      regmap_irq_get_domain(tps->irq_data));
+
 	if (ret < 0)
 		goto err_irq;
 

drivers/mfd/tps65912-core.c

@@ -77,6 +77,23 @@ static struct regmap_irq_chip tps65912_irq_chip = {
 	.init_ack_masked = true,
 };
 
+static const struct regmap_range tps65912_yes_ranges[] = {
+	regmap_reg_range(TPS65912_INT_STS, TPS65912_GPIO5),
+};
+
+static const struct regmap_access_table tps65912_volatile_table = {
+	.yes_ranges = tps65912_yes_ranges,
+	.n_yes_ranges = ARRAY_SIZE(tps65912_yes_ranges),
+};
+
+const struct regmap_config tps65912_regmap_config = {
+	.reg_bits = 8,
+	.val_bits = 8,
+	.cache_type = REGCACHE_RBTREE,
+	.volatile_table = &tps65912_volatile_table,
+};
+EXPORT_SYMBOL_GPL(tps65912_regmap_config);
+
 int tps65912_device_init(struct tps65912 *tps)
 {
 	int ret;

drivers/mfd/wm5102-tables.c

@@ -244,752 +244,752 @@ const struct regmap_irq_chip wm5102_irq = {
 };
 
 static const struct reg_default wm5102_reg_default[] = {
-	{ 0x00000008, 0x0019 },   /* R8     - Ctrl IF SPI CFG 1 */ 
-	{ 0x00000009, 0x0001 },   /* R9     - Ctrl IF I2C1 CFG 1 */ 
-	{ 0x00000020, 0x0000 },   /* R32    - Tone Generator 1 */ 
-	{ 0x00000021, 0x1000 },   /* R33    - Tone Generator 2 */ 
-	{ 0x00000022, 0x0000 },   /* R34    - Tone Generator 3 */ 
-	{ 0x00000023, 0x1000 },   /* R35    - Tone Generator 4 */ 
-	{ 0x00000024, 0x0000 },   /* R36    - Tone Generator 5 */ 
-	{ 0x00000030, 0x0000 },   /* R48    - PWM Drive 1 */ 
-	{ 0x00000031, 0x0100 },   /* R49    - PWM Drive 2 */ 
-	{ 0x00000032, 0x0100 },   /* R50    - PWM Drive 3 */ 
-	{ 0x00000040, 0x0000 },   /* R64    - Wake control */ 
-	{ 0x00000041, 0x0000 },   /* R65    - Sequence control */ 
-	{ 0x00000061, 0x01FF },   /* R97    - Sample Rate Sequence Select 1 */ 
-	{ 0x00000062, 0x01FF },   /* R98    - Sample Rate Sequence Select 2 */ 
-	{ 0x00000063, 0x01FF },   /* R99    - Sample Rate Sequence Select 3 */ 
-	{ 0x00000064, 0x01FF },   /* R100   - Sample Rate Sequence Select 4 */ 
+	{ 0x00000008, 0x0019 },   /* R8     - Ctrl IF SPI CFG 1 */
+	{ 0x00000009, 0x0001 },   /* R9     - Ctrl IF I2C1 CFG 1 */
+	{ 0x00000020, 0x0000 },   /* R32    - Tone Generator 1 */
+	{ 0x00000021, 0x1000 },   /* R33    - Tone Generator 2 */
+	{ 0x00000022, 0x0000 },   /* R34    - Tone Generator 3 */
+	{ 0x00000023, 0x1000 },   /* R35    - Tone Generator 4 */
+	{ 0x00000024, 0x0000 },   /* R36    - Tone Generator 5 */
+	{ 0x00000030, 0x0000 },   /* R48    - PWM Drive 1 */
+	{ 0x00000031, 0x0100 },   /* R49    - PWM Drive 2 */
+	{ 0x00000032, 0x0100 },   /* R50    - PWM Drive 3 */
+	{ 0x00000040, 0x0000 },   /* R64    - Wake control */
+	{ 0x00000041, 0x0000 },   /* R65    - Sequence control */
+	{ 0x00000061, 0x01FF },   /* R97    - Sample Rate Sequence Select 1 */
+	{ 0x00000062, 0x01FF },   /* R98    - Sample Rate Sequence Select 2 */
+	{ 0x00000063, 0x01FF },   /* R99    - Sample Rate Sequence Select 3 */
+	{ 0x00000064, 0x01FF },   /* R100   - Sample Rate Sequence Select 4 */
 	{ 0x00000066, 0x01FF },   /* R102   - Always On Triggers Sequence Select 1 */
 	{ 0x00000067, 0x01FF },   /* R103   - Always On Triggers Sequence Select 2 */
 	{ 0x00000068, 0x01FF },   /* R104   - Always On Triggers Sequence Select 3 */
 	{ 0x00000069, 0x01FF },   /* R105   - Always On Triggers Sequence Select 4 */
 	{ 0x0000006A, 0x01FF },   /* R106   - Always On Triggers Sequence Select 5 */
 	{ 0x0000006B, 0x01FF },   /* R107   - Always On Triggers Sequence Select 6 */
-	{ 0x00000070, 0x0000 },   /* R112   - Comfort Noise Generator */ 
-	{ 0x00000090, 0x0000 },   /* R144   - Haptics Control 1 */ 
-	{ 0x00000091, 0x7FFF },   /* R145   - Haptics Control 2 */ 
-	{ 0x00000092, 0x0000 },   /* R146   - Haptics phase 1 intensity */ 
-	{ 0x00000093, 0x0000 },   /* R147   - Haptics phase 1 duration */ 
-	{ 0x00000094, 0x0000 },   /* R148   - Haptics phase 2 intensity */ 
-	{ 0x00000095, 0x0000 },   /* R149   - Haptics phase 2 duration */ 
-	{ 0x00000096, 0x0000 },   /* R150   - Haptics phase 3 intensity */ 
-	{ 0x00000097, 0x0000 },   /* R151   - Haptics phase 3 duration */ 
+	{ 0x00000070, 0x0000 },   /* R112   - Comfort Noise Generator */
+	{ 0x00000090, 0x0000 },   /* R144   - Haptics Control 1 */
+	{ 0x00000091, 0x7FFF },   /* R145   - Haptics Control 2 */
+	{ 0x00000092, 0x0000 },   /* R146   - Haptics phase 1 intensity */
+	{ 0x00000093, 0x0000 },   /* R147   - Haptics phase 1 duration */
+	{ 0x00000094, 0x0000 },   /* R148   - Haptics phase 2 intensity */
+	{ 0x00000095, 0x0000 },   /* R149   - Haptics phase 2 duration */
+	{ 0x00000096, 0x0000 },   /* R150   - Haptics phase 3 intensity */
+	{ 0x00000097, 0x0000 },   /* R151   - Haptics phase 3 duration */
 	{ 0x00000100, 0x0002 },   /* R256   - Clock 32k 1 */
-	{ 0x00000101, 0x0304 },   /* R257   - System Clock 1 */ 
-	{ 0x00000102, 0x0011 },   /* R258   - Sample rate 1 */ 
-	{ 0x00000103, 0x0011 },   /* R259   - Sample rate 2 */ 
-	{ 0x00000104, 0x0011 },   /* R260   - Sample rate 3 */ 
-	{ 0x00000112, 0x0305 },   /* R274   - Async clock 1 */ 
-	{ 0x00000113, 0x0011 },   /* R275   - Async sample rate 1 */ 
+	{ 0x00000101, 0x0304 },   /* R257   - System Clock 1 */
+	{ 0x00000102, 0x0011 },   /* R258   - Sample rate 1 */
+	{ 0x00000103, 0x0011 },   /* R259   - Sample rate 2 */
+	{ 0x00000104, 0x0011 },   /* R260   - Sample rate 3 */
+	{ 0x00000112, 0x0305 },   /* R274   - Async clock 1 */
+	{ 0x00000113, 0x0011 },   /* R275   - Async sample rate 1 */
 	{ 0x00000114, 0x0011 },   /* R276   - Async sample rate 2 */
-	{ 0x00000149, 0x0000 },   /* R329   - Output system clock */ 
-	{ 0x0000014A, 0x0000 },   /* R330   - Output async clock */ 
-	{ 0x00000152, 0x0000 },   /* R338   - Rate Estimator 1 */ 
-	{ 0x00000153, 0x0000 },   /* R339   - Rate Estimator 2 */ 
-	{ 0x00000154, 0x0000 },   /* R340   - Rate Estimator 3 */ 
-	{ 0x00000155, 0x0000 },   /* R341   - Rate Estimator 4 */ 
-	{ 0x00000156, 0x0000 },   /* R342   - Rate Estimator 5 */ 
-	{ 0x00000161, 0x0000 },   /* R353   - Dynamic Frequency Scaling 1 */ 
+	{ 0x00000149, 0x0000 },   /* R329   - Output system clock */
+	{ 0x0000014A, 0x0000 },   /* R330   - Output async clock */
+	{ 0x00000152, 0x0000 },   /* R338   - Rate Estimator 1 */
+	{ 0x00000153, 0x0000 },   /* R339   - Rate Estimator 2 */
+	{ 0x00000154, 0x0000 },   /* R340   - Rate Estimator 3 */
+	{ 0x00000155, 0x0000 },   /* R341   - Rate Estimator 4 */
+	{ 0x00000156, 0x0000 },   /* R342   - Rate Estimator 5 */
+	{ 0x00000161, 0x0000 },   /* R353   - Dynamic Frequency Scaling 1 */
 	{ 0x00000171, 0x0000 },   /* R369   - FLL1 Control 1 */
-	{ 0x00000172, 0x0008 },   /* R370   - FLL1 Control 2 */ 
-	{ 0x00000173, 0x0018 },   /* R371   - FLL1 Control 3 */ 
-	{ 0x00000174, 0x007D },   /* R372   - FLL1 Control 4 */ 
-	{ 0x00000175, 0x0004 },   /* R373   - FLL1 Control 5 */ 
-	{ 0x00000176, 0x0000 },   /* R374   - FLL1 Control 6 */ 
+	{ 0x00000172, 0x0008 },   /* R370   - FLL1 Control 2 */
+	{ 0x00000173, 0x0018 },   /* R371   - FLL1 Control 3 */
+	{ 0x00000174, 0x007D },   /* R372   - FLL1 Control 4 */
+	{ 0x00000175, 0x0004 },   /* R373   - FLL1 Control 5 */
+	{ 0x00000176, 0x0000 },   /* R374   - FLL1 Control 6 */
 	{ 0x00000179, 0x0000 },   /* R377   - FLL1 Control 7 */
-	{ 0x00000181, 0x0000 },   /* R385   - FLL1 Synchroniser 1 */ 
-	{ 0x00000182, 0x0000 },   /* R386   - FLL1 Synchroniser 2 */ 
-	{ 0x00000183, 0x0000 },   /* R387   - FLL1 Synchroniser 3 */ 
-	{ 0x00000184, 0x0000 },   /* R388   - FLL1 Synchroniser 4 */ 
-	{ 0x00000185, 0x0000 },   /* R389   - FLL1 Synchroniser 5 */ 
-	{ 0x00000186, 0x0000 },   /* R390   - FLL1 Synchroniser 6 */ 
+	{ 0x00000181, 0x0000 },   /* R385   - FLL1 Synchroniser 1 */
+	{ 0x00000182, 0x0000 },   /* R386   - FLL1 Synchroniser 2 */
+	{ 0x00000183, 0x0000 },   /* R387   - FLL1 Synchroniser 3 */
+	{ 0x00000184, 0x0000 },   /* R388   - FLL1 Synchroniser 4 */
+	{ 0x00000185, 0x0000 },   /* R389   - FLL1 Synchroniser 5 */
+	{ 0x00000186, 0x0000 },   /* R390   - FLL1 Synchroniser 6 */
 	{ 0x00000187, 0x0001 },   /* R391   - FLL1 Synchroniser 7 */
-	{ 0x00000189, 0x0000 },   /* R393   - FLL1 Spread Spectrum */ 
-	{ 0x0000018A, 0x0004 },   /* R394   - FLL1 GPIO Clock */ 
-	{ 0x00000191, 0x0000 },   /* R401   - FLL2 Control 1 */ 
-	{ 0x00000192, 0x0008 },   /* R402   - FLL2 Control 2 */ 
-	{ 0x00000193, 0x0018 },   /* R403   - FLL2 Control 3 */ 
-	{ 0x00000194, 0x007D },   /* R404   - FLL2 Control 4 */ 
-	{ 0x00000195, 0x0004 },   /* R405   - FLL2 Control 5 */ 
-	{ 0x00000196, 0x0000 },   /* R406   - FLL2 Control 6 */ 
+	{ 0x00000189, 0x0000 },   /* R393   - FLL1 Spread Spectrum */
+	{ 0x0000018A, 0x0004 },   /* R394   - FLL1 GPIO Clock */
+	{ 0x00000191, 0x0000 },   /* R401   - FLL2 Control 1 */
+	{ 0x00000192, 0x0008 },   /* R402   - FLL2 Control 2 */
+	{ 0x00000193, 0x0018 },   /* R403   - FLL2 Control 3 */
+	{ 0x00000194, 0x007D },   /* R404   - FLL2 Control 4 */
+	{ 0x00000195, 0x0004 },   /* R405   - FLL2 Control 5 */
+	{ 0x00000196, 0x0000 },   /* R406   - FLL2 Control 6 */
 	{ 0x00000199, 0x0000 },   /* R409   - FLL2 Control 7 */
-	{ 0x000001A1, 0x0000 },   /* R417   - FLL2 Synchroniser 1 */ 
-	{ 0x000001A2, 0x0000 },   /* R418   - FLL2 Synchroniser 2 */ 
-	{ 0x000001A3, 0x0000 },   /* R419   - FLL2 Synchroniser 3 */ 
-	{ 0x000001A4, 0x0000 },   /* R420   - FLL2 Synchroniser 4 */ 
-	{ 0x000001A5, 0x0000 },   /* R421   - FLL2 Synchroniser 5 */ 
-	{ 0x000001A6, 0x0000 },   /* R422   - FLL2 Synchroniser 6 */ 
+	{ 0x000001A1, 0x0000 },   /* R417   - FLL2 Synchroniser 1 */
+	{ 0x000001A2, 0x0000 },   /* R418   - FLL2 Synchroniser 2 */
+	{ 0x000001A3, 0x0000 },   /* R419   - FLL2 Synchroniser 3 */
+	{ 0x000001A4, 0x0000 },   /* R420   - FLL2 Synchroniser 4 */
+	{ 0x000001A5, 0x0000 },   /* R421   - FLL2 Synchroniser 5 */
+	{ 0x000001A6, 0x0000 },   /* R422   - FLL2 Synchroniser 6 */
 	{ 0x000001A7, 0x0001 },   /* R423   - FLL2 Synchroniser 7 */
-	{ 0x000001A9, 0x0000 },   /* R425   - FLL2 Spread Spectrum */ 
-	{ 0x000001AA, 0x0004 },   /* R426   - FLL2 GPIO Clock */ 
-	{ 0x00000200, 0x0006 },   /* R512   - Mic Charge Pump 1 */ 
-	{ 0x00000210, 0x00D4 },   /* R528   - LDO1 Control 1 */ 
+	{ 0x000001A9, 0x0000 },   /* R425   - FLL2 Spread Spectrum */
+	{ 0x000001AA, 0x0004 },   /* R426   - FLL2 GPIO Clock */
+	{ 0x00000200, 0x0006 },   /* R512   - Mic Charge Pump 1 */
+	{ 0x00000210, 0x00D4 },   /* R528   - LDO1 Control 1 */
 	{ 0x00000212, 0x0000 },   /* R530   - LDO1 Control 2 */
-	{ 0x00000213, 0x0344 },   /* R531   - LDO2 Control 1 */ 
-	{ 0x00000218, 0x01A6 },   /* R536   - Mic Bias Ctrl 1 */ 
-	{ 0x00000219, 0x01A6 },   /* R537   - Mic Bias Ctrl 2 */ 
-	{ 0x0000021A, 0x01A6 },   /* R538   - Mic Bias Ctrl 3 */ 
-	{ 0x00000293, 0x0000 },   /* R659   - Accessory Detect Mode 1 */ 
-	{ 0x0000029B, 0x0020 },   /* R667   - Headphone Detect 1 */ 
+	{ 0x00000213, 0x0344 },   /* R531   - LDO2 Control 1 */
+	{ 0x00000218, 0x01A6 },   /* R536   - Mic Bias Ctrl 1 */
+	{ 0x00000219, 0x01A6 },   /* R537   - Mic Bias Ctrl 2 */
+	{ 0x0000021A, 0x01A6 },   /* R538   - Mic Bias Ctrl 3 */
+	{ 0x00000293, 0x0000 },   /* R659   - Accessory Detect Mode 1 */
+	{ 0x0000029B, 0x0020 },   /* R667   - Headphone Detect 1 */
 	{ 0x000002A2, 0x0000 },   /* R674   - Micd clamp control */
-	{ 0x000002A3, 0x1102 },   /* R675   - Mic Detect 1 */ 
-	{ 0x000002A4, 0x009F },   /* R676   - Mic Detect 2 */ 
+	{ 0x000002A3, 0x1102 },   /* R675   - Mic Detect 1 */
+	{ 0x000002A4, 0x009F },   /* R676   - Mic Detect 2 */
 	{ 0x000002A6, 0x3737 },   /* R678   - Mic Detect Level 1 */
 	{ 0x000002A7, 0x2C37 },   /* R679   - Mic Detect Level 2 */
 	{ 0x000002A8, 0x1422 },   /* R680   - Mic Detect Level 3 */
 	{ 0x000002A9, 0x030A },   /* R681   - Mic Detect Level 4 */
-	{ 0x000002C3, 0x0000 },   /* R707   - Mic noise mix control 1 */ 
-	{ 0x000002CB, 0x0000 },   /* R715   - Isolation control */ 
-	{ 0x000002D3, 0x0000 },   /* R723   - Jack detect analogue */ 
-	{ 0x00000300, 0x0000 },   /* R768   - Input Enables */ 
-	{ 0x00000308, 0x0000 },   /* R776   - Input Rate */ 
-	{ 0x00000309, 0x0022 },   /* R777   - Input Volume Ramp */ 
-	{ 0x00000310, 0x2080 },   /* R784   - IN1L Control */ 
-	{ 0x00000311, 0x0180 },   /* R785   - ADC Digital Volume 1L */ 
-	{ 0x00000312, 0x0000 },   /* R786   - DMIC1L Control */ 
-	{ 0x00000314, 0x0080 },   /* R788   - IN1R Control */ 
-	{ 0x00000315, 0x0180 },   /* R789   - ADC Digital Volume 1R */ 
-	{ 0x00000316, 0x0000 },   /* R790   - DMIC1R Control */ 
-	{ 0x00000318, 0x2080 },   /* R792   - IN2L Control */ 
-	{ 0x00000319, 0x0180 },   /* R793   - ADC Digital Volume 2L */ 
-	{ 0x0000031A, 0x0000 },   /* R794   - DMIC2L Control */ 
-	{ 0x0000031C, 0x0080 },   /* R796   - IN2R Control */ 
-	{ 0x0000031D, 0x0180 },   /* R797   - ADC Digital Volume 2R */ 
-	{ 0x0000031E, 0x0000 },   /* R798   - DMIC2R Control */ 
-	{ 0x00000320, 0x2080 },   /* R800   - IN3L Control */ 
-	{ 0x00000321, 0x0180 },   /* R801   - ADC Digital Volume 3L */ 
-	{ 0x00000322, 0x0000 },   /* R802   - DMIC3L Control */ 
-	{ 0x00000324, 0x0080 },   /* R804   - IN3R Control */ 
-	{ 0x00000325, 0x0180 },   /* R805   - ADC Digital Volume 3R */ 
-	{ 0x00000326, 0x0000 },   /* R806   - DMIC3R Control */ 
-	{ 0x00000400, 0x0000 },   /* R1024  - Output Enables 1 */ 
-	{ 0x00000408, 0x0000 },   /* R1032  - Output Rate 1 */ 
-	{ 0x00000409, 0x0022 },   /* R1033  - Output Volume Ramp */ 
+	{ 0x000002C3, 0x0000 },   /* R707   - Mic noise mix control 1 */
+	{ 0x000002CB, 0x0000 },   /* R715   - Isolation control */
+	{ 0x000002D3, 0x0000 },   /* R723   - Jack detect analogue */
+	{ 0x00000300, 0x0000 },   /* R768   - Input Enables */
+	{ 0x00000308, 0x0000 },   /* R776   - Input Rate */
+	{ 0x00000309, 0x0022 },   /* R777   - Input Volume Ramp */
+	{ 0x00000310, 0x2080 },   /* R784   - IN1L Control */
+	{ 0x00000311, 0x0180 },   /* R785   - ADC Digital Volume 1L */
+	{ 0x00000312, 0x0000 },   /* R786   - DMIC1L Control */
+	{ 0x00000314, 0x0080 },   /* R788   - IN1R Control */
+	{ 0x00000315, 0x0180 },   /* R789   - ADC Digital Volume 1R */
+	{ 0x00000316, 0x0000 },   /* R790   - DMIC1R Control */
+	{ 0x00000318, 0x2080 },   /* R792   - IN2L Control */
+	{ 0x00000319, 0x0180 },   /* R793   - ADC Digital Volume 2L */
+	{ 0x0000031A, 0x0000 },   /* R794   - DMIC2L Control */
+	{ 0x0000031C, 0x0080 },   /* R796   - IN2R Control */
+	{ 0x0000031D, 0x0180 },   /* R797   - ADC Digital Volume 2R */
+	{ 0x0000031E, 0x0000 },   /* R798   - DMIC2R Control */
+	{ 0x00000320, 0x2080 },   /* R800   - IN3L Control */
+	{ 0x00000321, 0x0180 },   /* R801   - ADC Digital Volume 3L */
+	{ 0x00000322, 0x0000 },   /* R802   - DMIC3L Control */
+	{ 0x00000324, 0x0080 },   /* R804   - IN3R Control */
+	{ 0x00000325, 0x0180 },   /* R805   - ADC Digital Volume 3R */
+	{ 0x00000326, 0x0000 },   /* R806   - DMIC3R Control */
+	{ 0x00000400, 0x0000 },   /* R1024  - Output Enables 1 */
+	{ 0x00000408, 0x0000 },   /* R1032  - Output Rate 1 */
+	{ 0x00000409, 0x0022 },   /* R1033  - Output Volume Ramp */
 	{ 0x00000410, 0x6080 },   /* R1040  - Output Path Config 1L */
-	{ 0x00000411, 0x0180 },   /* R1041  - DAC Digital Volume 1L */ 
+	{ 0x00000411, 0x0180 },   /* R1041  - DAC Digital Volume 1L */
 	{ 0x00000412, 0x0081 },   /* R1042  - DAC Volume Limit 1L */
-	{ 0x00000413, 0x0001 },   /* R1043  - Noise Gate Select 1L */ 
-	{ 0x00000414, 0x0080 },   /* R1044  - Output Path Config 1R */ 
-	{ 0x00000415, 0x0180 },   /* R1045  - DAC Digital Volume 1R */ 
+	{ 0x00000413, 0x0001 },   /* R1043  - Noise Gate Select 1L */
+	{ 0x00000414, 0x0080 },   /* R1044  - Output Path Config 1R */
+	{ 0x00000415, 0x0180 },   /* R1045  - DAC Digital Volume 1R */
 	{ 0x00000416, 0x0081 },   /* R1046  - DAC Volume Limit 1R */
-	{ 0x00000417, 0x0002 },   /* R1047  - Noise Gate Select 1R */ 
+	{ 0x00000417, 0x0002 },   /* R1047  - Noise Gate Select 1R */
 	{ 0x00000418, 0xA080 },   /* R1048  - Output Path Config 2L */
-	{ 0x00000419, 0x0180 },   /* R1049  - DAC Digital Volume 2L */ 
+	{ 0x00000419, 0x0180 },   /* R1049  - DAC Digital Volume 2L */
 	{ 0x0000041A, 0x0081 },   /* R1050  - DAC Volume Limit 2L */
-	{ 0x0000041B, 0x0004 },   /* R1051  - Noise Gate Select 2L */ 
-	{ 0x0000041C, 0x0080 },   /* R1052  - Output Path Config 2R */ 
-	{ 0x0000041D, 0x0180 },   /* R1053  - DAC Digital Volume 2R */ 
+	{ 0x0000041B, 0x0004 },   /* R1051  - Noise Gate Select 2L */
+	{ 0x0000041C, 0x0080 },   /* R1052  - Output Path Config 2R */
+	{ 0x0000041D, 0x0180 },   /* R1053  - DAC Digital Volume 2R */
 	{ 0x0000041E, 0x0081 },   /* R1054  - DAC Volume Limit 2R */
-	{ 0x0000041F, 0x0008 },   /* R1055  - Noise Gate Select 2R */ 
+	{ 0x0000041F, 0x0008 },   /* R1055  - Noise Gate Select 2R */
 	{ 0x00000420, 0xA080 },   /* R1056  - Output Path Config 3L */
-	{ 0x00000421, 0x0180 },   /* R1057  - DAC Digital Volume 3L */ 
+	{ 0x00000421, 0x0180 },   /* R1057  - DAC Digital Volume 3L */
 	{ 0x00000422, 0x0081 },   /* R1058  - DAC Volume Limit 3L */
-	{ 0x00000423, 0x0010 },   /* R1059  - Noise Gate Select 3L */ 
+	{ 0x00000423, 0x0010 },   /* R1059  - Noise Gate Select 3L */
 	{ 0x00000428, 0xE000 },   /* R1064  - Output Path Config 4L */
-	{ 0x00000429, 0x0180 },   /* R1065  - DAC Digital Volume 4L */ 
+	{ 0x00000429, 0x0180 },   /* R1065  - DAC Digital Volume 4L */
 	{ 0x0000042A, 0x0081 },   /* R1066  - Out Volume 4L */
-	{ 0x0000042B, 0x0040 },   /* R1067  - Noise Gate Select 4L */ 
-	{ 0x0000042D, 0x0180 },   /* R1069  - DAC Digital Volume 4R */ 
+	{ 0x0000042B, 0x0040 },   /* R1067  - Noise Gate Select 4L */
+	{ 0x0000042D, 0x0180 },   /* R1069  - DAC Digital Volume 4R */
 	{ 0x0000042E, 0x0081 },   /* R1070  - Out Volume 4R */
-	{ 0x0000042F, 0x0080 },   /* R1071  - Noise Gate Select 4R */ 
-	{ 0x00000430, 0x0000 },   /* R1072  - Output Path Config 5L */ 
-	{ 0x00000431, 0x0180 },   /* R1073  - DAC Digital Volume 5L */ 
+	{ 0x0000042F, 0x0080 },   /* R1071  - Noise Gate Select 4R */
+	{ 0x00000430, 0x0000 },   /* R1072  - Output Path Config 5L */
+	{ 0x00000431, 0x0180 },   /* R1073  - DAC Digital Volume 5L */
 	{ 0x00000432, 0x0081 },   /* R1074  - DAC Volume Limit 5L */
-	{ 0x00000433, 0x0100 },   /* R1075  - Noise Gate Select 5L */ 
-	{ 0x00000435, 0x0180 },   /* R1077  - DAC Digital Volume 5R */ 
+	{ 0x00000433, 0x0100 },   /* R1075  - Noise Gate Select 5L */
+	{ 0x00000435, 0x0180 },   /* R1077  - DAC Digital Volume 5R */
 	{ 0x00000436, 0x0081 },   /* R1078  - DAC Volume Limit 5R */
 	{ 0x00000437, 0x0200 },   /* R1079  - Noise Gate Select 5R */
 	{ 0x00000440, 0x0FFF },   /* R1088  - DRE Enable */
 	{ 0x00000442, 0x3F0A },   /* R1090  - DRE Control 2 */
 	{ 0x00000443, 0xDC1F },   /* R1090  - DRE Control 3 */
-	{ 0x00000450, 0x0000 },   /* R1104  - DAC AEC Control 1 */ 
+	{ 0x00000450, 0x0000 },   /* R1104  - DAC AEC Control 1 */
 	{ 0x00000458, 0x000B },   /* R1112  - Noise Gate Control */
-	{ 0x00000490, 0x0069 },   /* R1168  - PDM SPK1 CTRL 1 */ 
-	{ 0x00000491, 0x0000 },   /* R1169  - PDM SPK1 CTRL 2 */ 
-	{ 0x00000500, 0x000C },   /* R1280  - AIF1 BCLK Ctrl */ 
-	{ 0x00000501, 0x0008 },   /* R1281  - AIF1 Tx Pin Ctrl */ 
-	{ 0x00000502, 0x0000 },   /* R1282  - AIF1 Rx Pin Ctrl */ 
-	{ 0x00000503, 0x0000 },   /* R1283  - AIF1 Rate Ctrl */ 
-	{ 0x00000504, 0x0000 },   /* R1284  - AIF1 Format */ 
-	{ 0x00000505, 0x0040 },   /* R1285  - AIF1 Tx BCLK Rate */ 
-	{ 0x00000506, 0x0040 },   /* R1286  - AIF1 Rx BCLK Rate */ 
-	{ 0x00000507, 0x1818 },   /* R1287  - AIF1 Frame Ctrl 1 */ 
-	{ 0x00000508, 0x1818 },   /* R1288  - AIF1 Frame Ctrl 2 */ 
-	{ 0x00000509, 0x0000 },   /* R1289  - AIF1 Frame Ctrl 3 */ 
-	{ 0x0000050A, 0x0001 },   /* R1290  - AIF1 Frame Ctrl 4 */ 
-	{ 0x0000050B, 0x0002 },   /* R1291  - AIF1 Frame Ctrl 5 */ 
-	{ 0x0000050C, 0x0003 },   /* R1292  - AIF1 Frame Ctrl 6 */ 
-	{ 0x0000050D, 0x0004 },   /* R1293  - AIF1 Frame Ctrl 7 */ 
-	{ 0x0000050E, 0x0005 },   /* R1294  - AIF1 Frame Ctrl 8 */ 
-	{ 0x0000050F, 0x0006 },   /* R1295  - AIF1 Frame Ctrl 9 */ 
-	{ 0x00000510, 0x0007 },   /* R1296  - AIF1 Frame Ctrl 10 */ 
-	{ 0x00000511, 0x0000 },   /* R1297  - AIF1 Frame Ctrl 11 */ 
-	{ 0x00000512, 0x0001 },   /* R1298  - AIF1 Frame Ctrl 12 */ 
-	{ 0x00000513, 0x0002 },   /* R1299  - AIF1 Frame Ctrl 13 */ 
-	{ 0x00000514, 0x0003 },   /* R1300  - AIF1 Frame Ctrl 14 */ 
-	{ 0x00000515, 0x0004 },   /* R1301  - AIF1 Frame Ctrl 15 */ 
-	{ 0x00000516, 0x0005 },   /* R1302  - AIF1 Frame Ctrl 16 */ 
-	{ 0x00000517, 0x0006 },   /* R1303  - AIF1 Frame Ctrl 17 */ 
-	{ 0x00000518, 0x0007 },   /* R1304  - AIF1 Frame Ctrl 18 */ 
-	{ 0x00000519, 0x0000 },   /* R1305  - AIF1 Tx Enables */ 
-	{ 0x0000051A, 0x0000 },   /* R1306  - AIF1 Rx Enables */ 
-	{ 0x00000540, 0x000C },   /* R1344  - AIF2 BCLK Ctrl */ 
-	{ 0x00000541, 0x0008 },   /* R1345  - AIF2 Tx Pin Ctrl */ 
-	{ 0x00000542, 0x0000 },   /* R1346  - AIF2 Rx Pin Ctrl */ 
-	{ 0x00000543, 0x0000 },   /* R1347  - AIF2 Rate Ctrl */ 
-	{ 0x00000544, 0x0000 },   /* R1348  - AIF2 Format */ 
-	{ 0x00000545, 0x0040 },   /* R1349  - AIF2 Tx BCLK Rate */ 
-	{ 0x00000546, 0x0040 },   /* R1350  - AIF2 Rx BCLK Rate */ 
-	{ 0x00000547, 0x1818 },   /* R1351  - AIF2 Frame Ctrl 1 */ 
-	{ 0x00000548, 0x1818 },   /* R1352  - AIF2 Frame Ctrl 2 */ 
-	{ 0x00000549, 0x0000 },   /* R1353  - AIF2 Frame Ctrl 3 */ 
-	{ 0x0000054A, 0x0001 },   /* R1354  - AIF2 Frame Ctrl 4 */ 
-	{ 0x00000551, 0x0000 },   /* R1361  - AIF2 Frame Ctrl 11 */ 
-	{ 0x00000552, 0x0001 },   /* R1362  - AIF2 Frame Ctrl 12 */ 
-	{ 0x00000559, 0x0000 },   /* R1369  - AIF2 Tx Enables */ 
-	{ 0x0000055A, 0x0000 },   /* R1370  - AIF2 Rx Enables */ 
-	{ 0x00000580, 0x000C },   /* R1408  - AIF3 BCLK Ctrl */ 
-	{ 0x00000581, 0x0008 },   /* R1409  - AIF3 Tx Pin Ctrl */ 
-	{ 0x00000582, 0x0000 },   /* R1410  - AIF3 Rx Pin Ctrl */ 
-	{ 0x00000583, 0x0000 },   /* R1411  - AIF3 Rate Ctrl */ 
-	{ 0x00000584, 0x0000 },   /* R1412  - AIF3 Format */ 
-	{ 0x00000585, 0x0040 },   /* R1413  - AIF3 Tx BCLK Rate */ 
-	{ 0x00000586, 0x0040 },   /* R1414  - AIF3 Rx BCLK Rate */ 
-	{ 0x00000587, 0x1818 },   /* R1415  - AIF3 Frame Ctrl 1 */ 
-	{ 0x00000588, 0x1818 },   /* R1416  - AIF3 Frame Ctrl 2 */ 
-	{ 0x00000589, 0x0000 },   /* R1417  - AIF3 Frame Ctrl 3 */ 
-	{ 0x0000058A, 0x0001 },   /* R1418  - AIF3 Frame Ctrl 4 */ 
-	{ 0x00000591, 0x0000 },   /* R1425  - AIF3 Frame Ctrl 11 */ 
-	{ 0x00000592, 0x0001 },   /* R1426  - AIF3 Frame Ctrl 12 */ 
-	{ 0x00000599, 0x0000 },   /* R1433  - AIF3 Tx Enables */ 
-	{ 0x0000059A, 0x0000 },   /* R1434  - AIF3 Rx Enables */ 
-	{ 0x000005E3, 0x0004 },   /* R1507  - SLIMbus Framer Ref Gear */ 
-	{ 0x000005E5, 0x0000 },   /* R1509  - SLIMbus Rates 1 */ 
-	{ 0x000005E6, 0x0000 },   /* R1510  - SLIMbus Rates 2 */ 
-	{ 0x000005E7, 0x0000 },   /* R1511  - SLIMbus Rates 3 */ 
-	{ 0x000005E8, 0x0000 },   /* R1512  - SLIMbus Rates 4 */ 
-	{ 0x000005E9, 0x0000 },   /* R1513  - SLIMbus Rates 5 */ 
-	{ 0x000005EA, 0x0000 },   /* R1514  - SLIMbus Rates 6 */ 
-	{ 0x000005EB, 0x0000 },   /* R1515  - SLIMbus Rates 7 */ 
-	{ 0x000005EC, 0x0000 },   /* R1516  - SLIMbus Rates 8 */ 
-	{ 0x000005F5, 0x0000 },   /* R1525  - SLIMbus RX Channel Enable */ 
-	{ 0x000005F6, 0x0000 },   /* R1526  - SLIMbus TX Channel Enable */ 
-	{ 0x00000640, 0x0000 },   /* R1600  - PWM1MIX Input 1 Source */ 
-	{ 0x00000641, 0x0080 },   /* R1601  - PWM1MIX Input 1 Volume */ 
-	{ 0x00000642, 0x0000 },   /* R1602  - PWM1MIX Input 2 Source */ 
-	{ 0x00000643, 0x0080 },   /* R1603  - PWM1MIX Input 2 Volume */ 
-	{ 0x00000644, 0x0000 },   /* R1604  - PWM1MIX Input 3 Source */ 
-	{ 0x00000645, 0x0080 },   /* R1605  - PWM1MIX Input 3 Volume */ 
-	{ 0x00000646, 0x0000 },   /* R1606  - PWM1MIX Input 4 Source */ 
-	{ 0x00000647, 0x0080 },   /* R1607  - PWM1MIX Input 4 Volume */ 
-	{ 0x00000648, 0x0000 },   /* R1608  - PWM2MIX Input 1 Source */ 
-	{ 0x00000649, 0x0080 },   /* R1609  - PWM2MIX Input 1 Volume */ 
-	{ 0x0000064A, 0x0000 },   /* R1610  - PWM2MIX Input 2 Source */ 
-	{ 0x0000064B, 0x0080 },   /* R1611  - PWM2MIX Input 2 Volume */ 
-	{ 0x0000064C, 0x0000 },   /* R1612  - PWM2MIX Input 3 Source */ 
-	{ 0x0000064D, 0x0080 },   /* R1613  - PWM2MIX Input 3 Volume */ 
-	{ 0x0000064E, 0x0000 },   /* R1614  - PWM2MIX Input 4 Source */ 
-	{ 0x0000064F, 0x0080 },   /* R1615  - PWM2MIX Input 4 Volume */ 
-	{ 0x00000660, 0x0000 },   /* R1632  - MICMIX Input 1 Source */ 
-	{ 0x00000661, 0x0080 },   /* R1633  - MICMIX Input 1 Volume */ 
-	{ 0x00000662, 0x0000 },   /* R1634  - MICMIX Input 2 Source */ 
-	{ 0x00000663, 0x0080 },   /* R1635  - MICMIX Input 2 Volume */ 
-	{ 0x00000664, 0x0000 },   /* R1636  - MICMIX Input 3 Source */ 
-	{ 0x00000665, 0x0080 },   /* R1637  - MICMIX Input 3 Volume */ 
-	{ 0x00000666, 0x0000 },   /* R1638  - MICMIX Input 4 Source */ 
-	{ 0x00000667, 0x0080 },   /* R1639  - MICMIX Input 4 Volume */ 
-	{ 0x00000668, 0x0000 },   /* R1640  - NOISEMIX Input 1 Source */ 
-	{ 0x00000669, 0x0080 },   /* R1641  - NOISEMIX Input 1 Volume */ 
-	{ 0x0000066A, 0x0000 },   /* R1642  - NOISEMIX Input 2 Source */ 
-	{ 0x0000066B, 0x0080 },   /* R1643  - NOISEMIX Input 2 Volume */ 
-	{ 0x0000066C, 0x0000 },   /* R1644  - NOISEMIX Input 3 Source */ 
-	{ 0x0000066D, 0x0080 },   /* R1645  - NOISEMIX Input 3 Volume */ 
-	{ 0x0000066E, 0x0000 },   /* R1646  - NOISEMIX Input 4 Source */ 
-	{ 0x0000066F, 0x0080 },   /* R1647  - NOISEMIX Input 4 Volume */ 
-	{ 0x00000680, 0x0000 },   /* R1664  - OUT1LMIX Input 1 Source */ 
-	{ 0x00000681, 0x0080 },   /* R1665  - OUT1LMIX Input 1 Volume */ 
-	{ 0x00000682, 0x0000 },   /* R1666  - OUT1LMIX Input 2 Source */ 
-	{ 0x00000683, 0x0080 },   /* R1667  - OUT1LMIX Input 2 Volume */ 
-	{ 0x00000684, 0x0000 },   /* R1668  - OUT1LMIX Input 3 Source */ 
-	{ 0x00000685, 0x0080 },   /* R1669  - OUT1LMIX Input 3 Volume */ 
-	{ 0x00000686, 0x0000 },   /* R1670  - OUT1LMIX Input 4 Source */ 
-	{ 0x00000687, 0x0080 },   /* R1671  - OUT1LMIX Input 4 Volume */ 
-	{ 0x00000688, 0x0000 },   /* R1672  - OUT1RMIX Input 1 Source */ 
-	{ 0x00000689, 0x0080 },   /* R1673  - OUT1RMIX Input 1 Volume */ 
-	{ 0x0000068A, 0x0000 },   /* R1674  - OUT1RMIX Input 2 Source */ 
-	{ 0x0000068B, 0x0080 },   /* R1675  - OUT1RMIX Input 2 Volume */ 
-	{ 0x0000068C, 0x0000 },   /* R1676  - OUT1RMIX Input 3 Source */ 
-	{ 0x0000068D, 0x0080 },   /* R1677  - OUT1RMIX Input 3 Volume */ 
-	{ 0x0000068E, 0x0000 },   /* R1678  - OUT1RMIX Input 4 Source */ 
-	{ 0x0000068F, 0x0080 },   /* R1679  - OUT1RMIX Input 4 Volume */ 
-	{ 0x00000690, 0x0000 },   /* R1680  - OUT2LMIX Input 1 Source */ 
-	{ 0x00000691, 0x0080 },   /* R1681  - OUT2LMIX Input 1 Volume */ 
-	{ 0x00000692, 0x0000 },   /* R1682  - OUT2LMIX Input 2 Source */ 
-	{ 0x00000693, 0x0080 },   /* R1683  - OUT2LMIX Input 2 Volume */ 
-	{ 0x00000694, 0x0000 },   /* R1684  - OUT2LMIX Input 3 Source */ 
-	{ 0x00000695, 0x0080 },   /* R1685  - OUT2LMIX Input 3 Volume */ 
-	{ 0x00000696, 0x0000 },   /* R1686  - OUT2LMIX Input 4 Source */ 
-	{ 0x00000697, 0x0080 },   /* R1687  - OUT2LMIX Input 4 Volume */ 
-	{ 0x00000698, 0x0000 },   /* R1688  - OUT2RMIX Input 1 Source */ 
-	{ 0x00000699, 0x0080 },   /* R1689  - OUT2RMIX Input 1 Volume */ 
-	{ 0x0000069A, 0x0000 },   /* R1690  - OUT2RMIX Input 2 Source */ 
-	{ 0x0000069B, 0x0080 },   /* R1691  - OUT2RMIX Input 2 Volume */ 
-	{ 0x0000069C, 0x0000 },   /* R1692  - OUT2RMIX Input 3 Source */ 
-	{ 0x0000069D, 0x0080 },   /* R1693  - OUT2RMIX Input 3 Volume */ 
-	{ 0x0000069E, 0x0000 },   /* R1694  - OUT2RMIX Input 4 Source */ 
-	{ 0x0000069F, 0x0080 },   /* R1695  - OUT2RMIX Input 4 Volume */ 
-	{ 0x000006A0, 0x0000 },   /* R1696  - OUT3LMIX Input 1 Source */ 
-	{ 0x000006A1, 0x0080 },   /* R1697  - OUT3LMIX Input 1 Volume */ 
-	{ 0x000006A2, 0x0000 },   /* R1698  - OUT3LMIX Input 2 Source */ 
-	{ 0x000006A3, 0x0080 },   /* R1699  - OUT3LMIX Input 2 Volume */ 
-	{ 0x000006A4, 0x0000 },   /* R1700  - OUT3LMIX Input 3 Source */ 
-	{ 0x000006A5, 0x0080 },   /* R1701  - OUT3LMIX Input 3 Volume */ 
-	{ 0x000006A6, 0x0000 },   /* R1702  - OUT3LMIX Input 4 Source */ 
-	{ 0x000006A7, 0x0080 },   /* R1703  - OUT3LMIX Input 4 Volume */ 
-	{ 0x000006B0, 0x0000 },   /* R1712  - OUT4LMIX Input 1 Source */ 
-	{ 0x000006B1, 0x0080 },   /* R1713  - OUT4LMIX Input 1 Volume */ 
-	{ 0x000006B2, 0x0000 },   /* R1714  - OUT4LMIX Input 2 Source */ 
-	{ 0x000006B3, 0x0080 },   /* R1715  - OUT4LMIX Input 2 Volume */ 
-	{ 0x000006B4, 0x0000 },   /* R1716  - OUT4LMIX Input 3 Source */ 
-	{ 0x000006B5, 0x0080 },   /* R1717  - OUT4LMIX Input 3 Volume */ 
-	{ 0x000006B6, 0x0000 },   /* R1718  - OUT4LMIX Input 4 Source */ 
-	{ 0x000006B7, 0x0080 },   /* R1719  - OUT4LMIX Input 4 Volume */ 
-	{ 0x000006B8, 0x0000 },   /* R1720  - OUT4RMIX Input 1 Source */ 
-	{ 0x000006B9, 0x0080 },   /* R1721  - OUT4RMIX Input 1 Volume */ 
-	{ 0x000006BA, 0x0000 },   /* R1722  - OUT4RMIX Input 2 Source */ 
-	{ 0x000006BB, 0x0080 },   /* R1723  - OUT4RMIX Input 2 Volume */ 
-	{ 0x000006BC, 0x0000 },   /* R1724  - OUT4RMIX Input 3 Source */ 
-	{ 0x000006BD, 0x0080 },   /* R1725  - OUT4RMIX Input 3 Volume */ 
-	{ 0x000006BE, 0x0000 },   /* R1726  - OUT4RMIX Input 4 Source */ 
-	{ 0x000006BF, 0x0080 },   /* R1727  - OUT4RMIX Input 4 Volume */ 
-	{ 0x000006C0, 0x0000 },   /* R1728  - OUT5LMIX Input 1 Source */ 
-	{ 0x000006C1, 0x0080 },   /* R1729  - OUT5LMIX Input 1 Volume */ 
-	{ 0x000006C2, 0x0000 },   /* R1730  - OUT5LMIX Input 2 Source */ 
-	{ 0x000006C3, 0x0080 },   /* R1731  - OUT5LMIX Input 2 Volume */ 
-	{ 0x000006C4, 0x0000 },   /* R1732  - OUT5LMIX Input 3 Source */ 
-	{ 0x000006C5, 0x0080 },   /* R1733  - OUT5LMIX Input 3 Volume */ 
-	{ 0x000006C6, 0x0000 },   /* R1734  - OUT5LMIX Input 4 Source */ 
-	{ 0x000006C7, 0x0080 },   /* R1735  - OUT5LMIX Input 4 Volume */ 
-	{ 0x000006C8, 0x0000 },   /* R1736  - OUT5RMIX Input 1 Source */ 
-	{ 0x000006C9, 0x0080 },   /* R1737  - OUT5RMIX Input 1 Volume */ 
-	{ 0x000006CA, 0x0000 },   /* R1738  - OUT5RMIX Input 2 Source */ 
-	{ 0x000006CB, 0x0080 },   /* R1739  - OUT5RMIX Input 2 Volume */ 
-	{ 0x000006CC, 0x0000 },   /* R1740  - OUT5RMIX Input 3 Source */ 
-	{ 0x000006CD, 0x0080 },   /* R1741  - OUT5RMIX Input 3 Volume */ 
-	{ 0x000006CE, 0x0000 },   /* R1742  - OUT5RMIX Input 4 Source */ 
-	{ 0x000006CF, 0x0080 },   /* R1743  - OUT5RMIX Input 4 Volume */ 
-	{ 0x00000700, 0x0000 },   /* R1792  - AIF1TX1MIX Input 1 Source */ 
-	{ 0x00000701, 0x0080 },   /* R1793  - AIF1TX1MIX Input 1 Volume */ 
-	{ 0x00000702, 0x0000 },   /* R1794  - AIF1TX1MIX Input 2 Source */ 
-	{ 0x00000703, 0x0080 },   /* R1795  - AIF1TX1MIX Input 2 Volume */ 
-	{ 0x00000704, 0x0000 },   /* R1796  - AIF1TX1MIX Input 3 Source */ 
-	{ 0x00000705, 0x0080 },   /* R1797  - AIF1TX1MIX Input 3 Volume */ 
-	{ 0x00000706, 0x0000 },   /* R1798  - AIF1TX1MIX Input 4 Source */ 
-	{ 0x00000707, 0x0080 },   /* R1799  - AIF1TX1MIX Input 4 Volume */ 
-	{ 0x00000708, 0x0000 },   /* R1800  - AIF1TX2MIX Input 1 Source */ 
-	{ 0x00000709, 0x0080 },   /* R1801  - AIF1TX2MIX Input 1 Volume */ 
-	{ 0x0000070A, 0x0000 },   /* R1802  - AIF1TX2MIX Input 2 Source */ 
-	{ 0x0000070B, 0x0080 },   /* R1803  - AIF1TX2MIX Input 2 Volume */ 
-	{ 0x0000070C, 0x0000 },   /* R1804  - AIF1TX2MIX Input 3 Source */ 
-	{ 0x0000070D, 0x0080 },   /* R1805  - AIF1TX2MIX Input 3 Volume */ 
-	{ 0x0000070E, 0x0000 },   /* R1806  - AIF1TX2MIX Input 4 Source */ 
-	{ 0x0000070F, 0x0080 },   /* R1807  - AIF1TX2MIX Input 4 Volume */ 
-	{ 0x00000710, 0x0000 },   /* R1808  - AIF1TX3MIX Input 1 Source */ 
-	{ 0x00000711, 0x0080 },   /* R1809  - AIF1TX3MIX Input 1 Volume */ 
-	{ 0x00000712, 0x0000 },   /* R1810  - AIF1TX3MIX Input 2 Source */ 
-	{ 0x00000713, 0x0080 },   /* R1811  - AIF1TX3MIX Input 2 Volume */ 
-	{ 0x00000714, 0x0000 },   /* R1812  - AIF1TX3MIX Input 3 Source */ 
-	{ 0x00000715, 0x0080 },   /* R1813  - AIF1TX3MIX Input 3 Volume */ 
-	{ 0x00000716, 0x0000 },   /* R1814  - AIF1TX3MIX Input 4 Source */ 
-	{ 0x00000717, 0x0080 },   /* R1815  - AIF1TX3MIX Input 4 Volume */ 
-	{ 0x00000718, 0x0000 },   /* R1816  - AIF1TX4MIX Input 1 Source */ 
-	{ 0x00000719, 0x0080 },   /* R1817  - AIF1TX4MIX Input 1 Volume */ 
-	{ 0x0000071A, 0x0000 },   /* R1818  - AIF1TX4MIX Input 2 Source */ 
-	{ 0x0000071B, 0x0080 },   /* R1819  - AIF1TX4MIX Input 2 Volume */ 
-	{ 0x0000071C, 0x0000 },   /* R1820  - AIF1TX4MIX Input 3 Source */ 
-	{ 0x0000071D, 0x0080 },   /* R1821  - AIF1TX4MIX Input 3 Volume */ 
-	{ 0x0000071E, 0x0000 },   /* R1822  - AIF1TX4MIX Input 4 Source */ 
-	{ 0x0000071F, 0x0080 },   /* R1823  - AIF1TX4MIX Input 4 Volume */ 
-	{ 0x00000720, 0x0000 },   /* R1824  - AIF1TX5MIX Input 1 Source */ 
-	{ 0x00000721, 0x0080 },   /* R1825  - AIF1TX5MIX Input 1 Volume */ 
-	{ 0x00000722, 0x0000 },   /* R1826  - AIF1TX5MIX Input 2 Source */ 
-	{ 0x00000723, 0x0080 },   /* R1827  - AIF1TX5MIX Input 2 Volume */ 
-	{ 0x00000724, 0x0000 },   /* R1828  - AIF1TX5MIX Input 3 Source */ 
-	{ 0x00000725, 0x0080 },   /* R1829  - AIF1TX5MIX Input 3 Volume */ 
-	{ 0x00000726, 0x0000 },   /* R1830  - AIF1TX5MIX Input 4 Source */ 
-	{ 0x00000727, 0x0080 },   /* R1831  - AIF1TX5MIX Input 4 Volume */ 
-	{ 0x00000728, 0x0000 },   /* R1832  - AIF1TX6MIX Input 1 Source */ 
-	{ 0x00000729, 0x0080 },   /* R1833  - AIF1TX6MIX Input 1 Volume */ 
-	{ 0x0000072A, 0x0000 },   /* R1834  - AIF1TX6MIX Input 2 Source */ 
-	{ 0x0000072B, 0x0080 },   /* R1835  - AIF1TX6MIX Input 2 Volume */ 
-	{ 0x0000072C, 0x0000 },   /* R1836  - AIF1TX6MIX Input 3 Source */ 
-	{ 0x0000072D, 0x0080 },   /* R1837  - AIF1TX6MIX Input 3 Volume */ 
-	{ 0x0000072E, 0x0000 },   /* R1838  - AIF1TX6MIX Input 4 Source */ 
-	{ 0x0000072F, 0x0080 },   /* R1839  - AIF1TX6MIX Input 4 Volume */ 
-	{ 0x00000730, 0x0000 },   /* R1840  - AIF1TX7MIX Input 1 Source */ 
-	{ 0x00000731, 0x0080 },   /* R1841  - AIF1TX7MIX Input 1 Volume */ 
-	{ 0x00000732, 0x0000 },   /* R1842  - AIF1TX7MIX Input 2 Source */ 
-	{ 0x00000733, 0x0080 },   /* R1843  - AIF1TX7MIX Input 2 Volume */ 
-	{ 0x00000734, 0x0000 },   /* R1844  - AIF1TX7MIX Input 3 Source */ 
-	{ 0x00000735, 0x0080 },   /* R1845  - AIF1TX7MIX Input 3 Volume */ 
-	{ 0x00000736, 0x0000 },   /* R1846  - AIF1TX7MIX Input 4 Source */ 
-	{ 0x00000737, 0x0080 },   /* R1847  - AIF1TX7MIX Input 4 Volume */ 
-	{ 0x00000738, 0x0000 },   /* R1848  - AIF1TX8MIX Input 1 Source */ 
-	{ 0x00000739, 0x0080 },   /* R1849  - AIF1TX8MIX Input 1 Volume */ 
-	{ 0x0000073A, 0x0000 },   /* R1850  - AIF1TX8MIX Input 2 Source */ 
-	{ 0x0000073B, 0x0080 },   /* R1851  - AIF1TX8MIX Input 2 Volume */ 
-	{ 0x0000073C, 0x0000 },   /* R1852  - AIF1TX8MIX Input 3 Source */ 
-	{ 0x0000073D, 0x0080 },   /* R1853  - AIF1TX8MIX Input 3 Volume */ 
-	{ 0x0000073E, 0x0000 },   /* R1854  - AIF1TX8MIX Input 4 Source */ 
-	{ 0x0000073F, 0x0080 },   /* R1855  - AIF1TX8MIX Input 4 Volume */ 
-	{ 0x00000740, 0x0000 },   /* R1856  - AIF2TX1MIX Input 1 Source */ 
-	{ 0x00000741, 0x0080 },   /* R1857  - AIF2TX1MIX Input 1 Volume */ 
-	{ 0x00000742, 0x0000 },   /* R1858  - AIF2TX1MIX Input 2 Source */ 
-	{ 0x00000743, 0x0080 },   /* R1859  - AIF2TX1MIX Input 2 Volume */ 
-	{ 0x00000744, 0x0000 },   /* R1860  - AIF2TX1MIX Input 3 Source */ 
-	{ 0x00000745, 0x0080 },   /* R1861  - AIF2TX1MIX Input 3 Volume */ 
-	{ 0x00000746, 0x0000 },   /* R1862  - AIF2TX1MIX Input 4 Source */ 
-	{ 0x00000747, 0x0080 },   /* R1863  - AIF2TX1MIX Input 4 Volume */ 
-	{ 0x00000748, 0x0000 },   /* R1864  - AIF2TX2MIX Input 1 Source */ 
-	{ 0x00000749, 0x0080 },   /* R1865  - AIF2TX2MIX Input 1 Volume */ 
-	{ 0x0000074A, 0x0000 },   /* R1866  - AIF2TX2MIX Input 2 Source */ 
-	{ 0x0000074B, 0x0080 },   /* R1867  - AIF2TX2MIX Input 2 Volume */ 
-	{ 0x0000074C, 0x0000 },   /* R1868  - AIF2TX2MIX Input 3 Source */ 
-	{ 0x0000074D, 0x0080 },   /* R1869  - AIF2TX2MIX Input 3 Volume */ 
-	{ 0x0000074E, 0x0000 },   /* R1870  - AIF2TX2MIX Input 4 Source */ 
-	{ 0x0000074F, 0x0080 },   /* R1871  - AIF2TX2MIX Input 4 Volume */ 
-	{ 0x00000780, 0x0000 },   /* R1920  - AIF3TX1MIX Input 1 Source */ 
-	{ 0x00000781, 0x0080 },   /* R1921  - AIF3TX1MIX Input 1 Volume */ 
-	{ 0x00000782, 0x0000 },   /* R1922  - AIF3TX1MIX Input 2 Source */ 
-	{ 0x00000783, 0x0080 },   /* R1923  - AIF3TX1MIX Input 2 Volume */ 
-	{ 0x00000784, 0x0000 },   /* R1924  - AIF3TX1MIX Input 3 Source */ 
-	{ 0x00000785, 0x0080 },   /* R1925  - AIF3TX1MIX Input 3 Volume */ 
-	{ 0x00000786, 0x0000 },   /* R1926  - AIF3TX1MIX Input 4 Source */ 
-	{ 0x00000787, 0x0080 },   /* R1927  - AIF3TX1MIX Input 4 Volume */ 
-	{ 0x00000788, 0x0000 },   /* R1928  - AIF3TX2MIX Input 1 Source */ 
-	{ 0x00000789, 0x0080 },   /* R1929  - AIF3TX2MIX Input 1 Volume */ 
-	{ 0x0000078A, 0x0000 },   /* R1930  - AIF3TX2MIX Input 2 Source */ 
-	{ 0x0000078B, 0x0080 },   /* R1931  - AIF3TX2MIX Input 2 Volume */ 
-	{ 0x0000078C, 0x0000 },   /* R1932  - AIF3TX2MIX Input 3 Source */ 
-	{ 0x0000078D, 0x0080 },   /* R1933  - AIF3TX2MIX Input 3 Volume */ 
-	{ 0x0000078E, 0x0000 },   /* R1934  - AIF3TX2MIX Input 4 Source */ 
-	{ 0x0000078F, 0x0080 },   /* R1935  - AIF3TX2MIX Input 4 Volume */ 
-	{ 0x000007C0, 0x0000 },   /* R1984  - SLIMTX1MIX Input 1 Source */ 
-	{ 0x000007C1, 0x0080 },   /* R1985  - SLIMTX1MIX Input 1 Volume */ 
-	{ 0x000007C2, 0x0000 },   /* R1986  - SLIMTX1MIX Input 2 Source */ 
-	{ 0x000007C3, 0x0080 },   /* R1987  - SLIMTX1MIX Input 2 Volume */ 
-	{ 0x000007C4, 0x0000 },   /* R1988  - SLIMTX1MIX Input 3 Source */ 
-	{ 0x000007C5, 0x0080 },   /* R1989  - SLIMTX1MIX Input 3 Volume */ 
-	{ 0x000007C6, 0x0000 },   /* R1990  - SLIMTX1MIX Input 4 Source */ 
-	{ 0x000007C7, 0x0080 },   /* R1991  - SLIMTX1MIX Input 4 Volume */ 
-	{ 0x000007C8, 0x0000 },   /* R1992  - SLIMTX2MIX Input 1 Source */ 
-	{ 0x000007C9, 0x0080 },   /* R1993  - SLIMTX2MIX Input 1 Volume */ 
-	{ 0x000007CA, 0x0000 },   /* R1994  - SLIMTX2MIX Input 2 Source */ 
-	{ 0x000007CB, 0x0080 },   /* R1995  - SLIMTX2MIX Input 2 Volume */ 
-	{ 0x000007CC, 0x0000 },   /* R1996  - SLIMTX2MIX Input 3 Source */ 
-	{ 0x000007CD, 0x0080 },   /* R1997  - SLIMTX2MIX Input 3 Volume */ 
-	{ 0x000007CE, 0x0000 },   /* R1998  - SLIMTX2MIX Input 4 Source */ 
-	{ 0x000007CF, 0x0080 },   /* R1999  - SLIMTX2MIX Input 4 Volume */ 
-	{ 0x000007D0, 0x0000 },   /* R2000  - SLIMTX3MIX Input 1 Source */ 
-	{ 0x000007D1, 0x0080 },   /* R2001  - SLIMTX3MIX Input 1 Volume */ 
-	{ 0x000007D2, 0x0000 },   /* R2002  - SLIMTX3MIX Input 2 Source */ 
-	{ 0x000007D3, 0x0080 },   /* R2003  - SLIMTX3MIX Input 2 Volume */ 
-	{ 0x000007D4, 0x0000 },   /* R2004  - SLIMTX3MIX Input 3 Source */ 
-	{ 0x000007D5, 0x0080 },   /* R2005  - SLIMTX3MIX Input 3 Volume */ 
-	{ 0x000007D6, 0x0000 },   /* R2006  - SLIMTX3MIX Input 4 Source */ 
-	{ 0x000007D7, 0x0080 },   /* R2007  - SLIMTX3MIX Input 4 Volume */ 
-	{ 0x000007D8, 0x0000 },   /* R2008  - SLIMTX4MIX Input 1 Source */ 
-	{ 0x000007D9, 0x0080 },   /* R2009  - SLIMTX4MIX Input 1 Volume */ 
-	{ 0x000007DA, 0x0000 },   /* R2010  - SLIMTX4MIX Input 2 Source */ 
-	{ 0x000007DB, 0x0080 },   /* R2011  - SLIMTX4MIX Input 2 Volume */ 
-	{ 0x000007DC, 0x0000 },   /* R2012  - SLIMTX4MIX Input 3 Source */ 
-	{ 0x000007DD, 0x0080 },   /* R2013  - SLIMTX4MIX Input 3 Volume */ 
-	{ 0x000007DE, 0x0000 },   /* R2014  - SLIMTX4MIX Input 4 Source */ 
-	{ 0x000007DF, 0x0080 },   /* R2015  - SLIMTX4MIX Input 4 Volume */ 
-	{ 0x000007E0, 0x0000 },   /* R2016  - SLIMTX5MIX Input 1 Source */ 
-	{ 0x000007E1, 0x0080 },   /* R2017  - SLIMTX5MIX Input 1 Volume */ 
-	{ 0x000007E2, 0x0000 },   /* R2018  - SLIMTX5MIX Input 2 Source */ 
-	{ 0x000007E3, 0x0080 },   /* R2019  - SLIMTX5MIX Input 2 Volume */ 
-	{ 0x000007E4, 0x0000 },   /* R2020  - SLIMTX5MIX Input 3 Source */ 
-	{ 0x000007E5, 0x0080 },   /* R2021  - SLIMTX5MIX Input 3 Volume */ 
-	{ 0x000007E6, 0x0000 },   /* R2022  - SLIMTX5MIX Input 4 Source */ 
-	{ 0x000007E7, 0x0080 },   /* R2023  - SLIMTX5MIX Input 4 Volume */ 
-	{ 0x000007E8, 0x0000 },   /* R2024  - SLIMTX6MIX Input 1 Source */ 
-	{ 0x000007E9, 0x0080 },   /* R2025  - SLIMTX6MIX Input 1 Volume */ 
-	{ 0x000007EA, 0x0000 },   /* R2026  - SLIMTX6MIX Input 2 Source */ 
-	{ 0x000007EB, 0x0080 },   /* R2027  - SLIMTX6MIX Input 2 Volume */ 
-	{ 0x000007EC, 0x0000 },   /* R2028  - SLIMTX6MIX Input 3 Source */ 
-	{ 0x000007ED, 0x0080 },   /* R2029  - SLIMTX6MIX Input 3 Volume */ 
-	{ 0x000007EE, 0x0000 },   /* R2030  - SLIMTX6MIX Input 4 Source */ 
-	{ 0x000007EF, 0x0080 },   /* R2031  - SLIMTX6MIX Input 4 Volume */ 
-	{ 0x000007F0, 0x0000 },   /* R2032  - SLIMTX7MIX Input 1 Source */ 
-	{ 0x000007F1, 0x0080 },   /* R2033  - SLIMTX7MIX Input 1 Volume */ 
-	{ 0x000007F2, 0x0000 },   /* R2034  - SLIMTX7MIX Input 2 Source */ 
-	{ 0x000007F3, 0x0080 },   /* R2035  - SLIMTX7MIX Input 2 Volume */ 
-	{ 0x000007F4, 0x0000 },   /* R2036  - SLIMTX7MIX Input 3 Source */ 
-	{ 0x000007F5, 0x0080 },   /* R2037  - SLIMTX7MIX Input 3 Volume */ 
-	{ 0x000007F6, 0x0000 },   /* R2038  - SLIMTX7MIX Input 4 Source */ 
-	{ 0x000007F7, 0x0080 },   /* R2039  - SLIMTX7MIX Input 4 Volume */ 
-	{ 0x000007F8, 0x0000 },   /* R2040  - SLIMTX8MIX Input 1 Source */ 
-	{ 0x000007F9, 0x0080 },   /* R2041  - SLIMTX8MIX Input 1 Volume */ 
-	{ 0x000007FA, 0x0000 },   /* R2042  - SLIMTX8MIX Input 2 Source */ 
-	{ 0x000007FB, 0x0080 },   /* R2043  - SLIMTX8MIX Input 2 Volume */ 
-	{ 0x000007FC, 0x0000 },   /* R2044  - SLIMTX8MIX Input 3 Source */ 
-	{ 0x000007FD, 0x0080 },   /* R2045  - SLIMTX8MIX Input 3 Volume */ 
-	{ 0x000007FE, 0x0000 },   /* R2046  - SLIMTX8MIX Input 4 Source */ 
-	{ 0x000007FF, 0x0080 },   /* R2047  - SLIMTX8MIX Input 4 Volume */ 
-	{ 0x00000880, 0x0000 },   /* R2176  - EQ1MIX Input 1 Source */ 
-	{ 0x00000881, 0x0080 },   /* R2177  - EQ1MIX Input 1 Volume */ 
-	{ 0x00000882, 0x0000 },   /* R2178  - EQ1MIX Input 2 Source */ 
-	{ 0x00000883, 0x0080 },   /* R2179  - EQ1MIX Input 2 Volume */ 
-	{ 0x00000884, 0x0000 },   /* R2180  - EQ1MIX Input 3 Source */ 
-	{ 0x00000885, 0x0080 },   /* R2181  - EQ1MIX Input 3 Volume */ 
-	{ 0x00000886, 0x0000 },   /* R2182  - EQ1MIX Input 4 Source */ 
-	{ 0x00000887, 0x0080 },   /* R2183  - EQ1MIX Input 4 Volume */ 
-	{ 0x00000888, 0x0000 },   /* R2184  - EQ2MIX Input 1 Source */ 
-	{ 0x00000889, 0x0080 },   /* R2185  - EQ2MIX Input 1 Volume */ 
-	{ 0x0000088A, 0x0000 },   /* R2186  - EQ2MIX Input 2 Source */ 
-	{ 0x0000088B, 0x0080 },   /* R2187  - EQ2MIX Input 2 Volume */ 
-	{ 0x0000088C, 0x0000 },   /* R2188  - EQ2MIX Input 3 Source */ 
-	{ 0x0000088D, 0x0080 },   /* R2189  - EQ2MIX Input 3 Volume */ 
-	{ 0x0000088E, 0x0000 },   /* R2190  - EQ2MIX Input 4 Source */ 
-	{ 0x0000088F, 0x0080 },   /* R2191  - EQ2MIX Input 4 Volume */ 
-	{ 0x00000890, 0x0000 },   /* R2192  - EQ3MIX Input 1 Source */ 
-	{ 0x00000891, 0x0080 },   /* R2193  - EQ3MIX Input 1 Volume */ 
-	{ 0x00000892, 0x0000 },   /* R2194  - EQ3MIX Input 2 Source */ 
-	{ 0x00000893, 0x0080 },   /* R2195  - EQ3MIX Input 2 Volume */ 
-	{ 0x00000894, 0x0000 },   /* R2196  - EQ3MIX Input 3 Source */ 
-	{ 0x00000895, 0x0080 },   /* R2197  - EQ3MIX Input 3 Volume */ 
-	{ 0x00000896, 0x0000 },   /* R2198  - EQ3MIX Input 4 Source */ 
-	{ 0x00000897, 0x0080 },   /* R2199  - EQ3MIX Input 4 Volume */ 
-	{ 0x00000898, 0x0000 },   /* R2200  - EQ4MIX Input 1 Source */ 
-	{ 0x00000899, 0x0080 },   /* R2201  - EQ4MIX Input 1 Volume */ 
-	{ 0x0000089A, 0x0000 },   /* R2202  - EQ4MIX Input 2 Source */ 
-	{ 0x0000089B, 0x0080 },   /* R2203  - EQ4MIX Input 2 Volume */ 
-	{ 0x0000089C, 0x0000 },   /* R2204  - EQ4MIX Input 3 Source */ 
-	{ 0x0000089D, 0x0080 },   /* R2205  - EQ4MIX Input 3 Volume */ 
-	{ 0x0000089E, 0x0000 },   /* R2206  - EQ4MIX Input 4 Source */ 
-	{ 0x0000089F, 0x0080 },   /* R2207  - EQ4MIX Input 4 Volume */ 
-	{ 0x000008C0, 0x0000 },   /* R2240  - DRC1LMIX Input 1 Source */ 
-	{ 0x000008C1, 0x0080 },   /* R2241  - DRC1LMIX Input 1 Volume */ 
-	{ 0x000008C2, 0x0000 },   /* R2242  - DRC1LMIX Input 2 Source */ 
-	{ 0x000008C3, 0x0080 },   /* R2243  - DRC1LMIX Input 2 Volume */ 
-	{ 0x000008C4, 0x0000 },   /* R2244  - DRC1LMIX Input 3 Source */ 
-	{ 0x000008C5, 0x0080 },   /* R2245  - DRC1LMIX Input 3 Volume */ 
-	{ 0x000008C6, 0x0000 },   /* R2246  - DRC1LMIX Input 4 Source */ 
-	{ 0x000008C7, 0x0080 },   /* R2247  - DRC1LMIX Input 4 Volume */ 
-	{ 0x000008C8, 0x0000 },   /* R2248  - DRC1RMIX Input 1 Source */ 
-	{ 0x000008C9, 0x0080 },   /* R2249  - DRC1RMIX Input 1 Volume */ 
-	{ 0x000008CA, 0x0000 },   /* R2250  - DRC1RMIX Input 2 Source */ 
-	{ 0x000008CB, 0x0080 },   /* R2251  - DRC1RMIX Input 2 Volume */ 
-	{ 0x000008CC, 0x0000 },   /* R2252  - DRC1RMIX Input 3 Source */ 
-	{ 0x000008CD, 0x0080 },   /* R2253  - DRC1RMIX Input 3 Volume */ 
-	{ 0x000008CE, 0x0000 },   /* R2254  - DRC1RMIX Input 4 Source */ 
-	{ 0x000008CF, 0x0080 },   /* R2255  - DRC1RMIX Input 4 Volume */ 
-	{ 0x00000900, 0x0000 },   /* R2304  - HPLP1MIX Input 1 Source */ 
-	{ 0x00000901, 0x0080 },   /* R2305  - HPLP1MIX Input 1 Volume */ 
-	{ 0x00000902, 0x0000 },   /* R2306  - HPLP1MIX Input 2 Source */ 
-	{ 0x00000903, 0x0080 },   /* R2307  - HPLP1MIX Input 2 Volume */ 
-	{ 0x00000904, 0x0000 },   /* R2308  - HPLP1MIX Input 3 Source */ 
-	{ 0x00000905, 0x0080 },   /* R2309  - HPLP1MIX Input 3 Volume */ 
-	{ 0x00000906, 0x0000 },   /* R2310  - HPLP1MIX Input 4 Source */ 
-	{ 0x00000907, 0x0080 },   /* R2311  - HPLP1MIX Input 4 Volume */ 
-	{ 0x00000908, 0x0000 },   /* R2312  - HPLP2MIX Input 1 Source */ 
-	{ 0x00000909, 0x0080 },   /* R2313  - HPLP2MIX Input 1 Volume */ 
-	{ 0x0000090A, 0x0000 },   /* R2314  - HPLP2MIX Input 2 Source */ 
-	{ 0x0000090B, 0x0080 },   /* R2315  - HPLP2MIX Input 2 Volume */ 
-	{ 0x0000090C, 0x0000 },   /* R2316  - HPLP2MIX Input 3 Source */ 
-	{ 0x0000090D, 0x0080 },   /* R2317  - HPLP2MIX Input 3 Volume */ 
-	{ 0x0000090E, 0x0000 },   /* R2318  - HPLP2MIX Input 4 Source */ 
-	{ 0x0000090F, 0x0080 },   /* R2319  - HPLP2MIX Input 4 Volume */ 
-	{ 0x00000910, 0x0000 },   /* R2320  - HPLP3MIX Input 1 Source */ 
-	{ 0x00000911, 0x0080 },   /* R2321  - HPLP3MIX Input 1 Volume */ 
-	{ 0x00000912, 0x0000 },   /* R2322  - HPLP3MIX Input 2 Source */ 
-	{ 0x00000913, 0x0080 },   /* R2323  - HPLP3MIX Input 2 Volume */ 
-	{ 0x00000914, 0x0000 },   /* R2324  - HPLP3MIX Input 3 Source */ 
-	{ 0x00000915, 0x0080 },   /* R2325  - HPLP3MIX Input 3 Volume */ 
-	{ 0x00000916, 0x0000 },   /* R2326  - HPLP3MIX Input 4 Source */ 
-	{ 0x00000917, 0x0080 },   /* R2327  - HPLP3MIX Input 4 Volume */ 
-	{ 0x00000918, 0x0000 },   /* R2328  - HPLP4MIX Input 1 Source */ 
-	{ 0x00000919, 0x0080 },   /* R2329  - HPLP4MIX Input 1 Volume */ 
-	{ 0x0000091A, 0x0000 },   /* R2330  - HPLP4MIX Input 2 Source */ 
-	{ 0x0000091B, 0x0080 },   /* R2331  - HPLP4MIX Input 2 Volume */ 
-	{ 0x0000091C, 0x0000 },   /* R2332  - HPLP4MIX Input 3 Source */ 
-	{ 0x0000091D, 0x0080 },   /* R2333  - HPLP4MIX Input 3 Volume */ 
-	{ 0x0000091E, 0x0000 },   /* R2334  - HPLP4MIX Input 4 Source */ 
-	{ 0x0000091F, 0x0080 },   /* R2335  - HPLP4MIX Input 4 Volume */ 
-	{ 0x00000940, 0x0000 },   /* R2368  - DSP1LMIX Input 1 Source */ 
-	{ 0x00000941, 0x0080 },   /* R2369  - DSP1LMIX Input 1 Volume */ 
-	{ 0x00000942, 0x0000 },   /* R2370  - DSP1LMIX Input 2 Source */ 
-	{ 0x00000943, 0x0080 },   /* R2371  - DSP1LMIX Input 2 Volume */ 
-	{ 0x00000944, 0x0000 },   /* R2372  - DSP1LMIX Input 3 Source */ 
-	{ 0x00000945, 0x0080 },   /* R2373  - DSP1LMIX Input 3 Volume */ 
-	{ 0x00000946, 0x0000 },   /* R2374  - DSP1LMIX Input 4 Source */ 
-	{ 0x00000947, 0x0080 },   /* R2375  - DSP1LMIX Input 4 Volume */ 
-	{ 0x00000948, 0x0000 },   /* R2376  - DSP1RMIX Input 1 Source */ 
-	{ 0x00000949, 0x0080 },   /* R2377  - DSP1RMIX Input 1 Volume */ 
-	{ 0x0000094A, 0x0000 },   /* R2378  - DSP1RMIX Input 2 Source */ 
-	{ 0x0000094B, 0x0080 },   /* R2379  - DSP1RMIX Input 2 Volume */ 
-	{ 0x0000094C, 0x0000 },   /* R2380  - DSP1RMIX Input 3 Source */ 
-	{ 0x0000094D, 0x0080 },   /* R2381  - DSP1RMIX Input 3 Volume */ 
-	{ 0x0000094E, 0x0000 },   /* R2382  - DSP1RMIX Input 4 Source */ 
-	{ 0x0000094F, 0x0080 },   /* R2383  - DSP1RMIX Input 4 Volume */ 
-	{ 0x00000950, 0x0000 },   /* R2384  - DSP1AUX1MIX Input 1 Source */ 
-	{ 0x00000958, 0x0000 },   /* R2392  - DSP1AUX2MIX Input 1 Source */ 
-	{ 0x00000960, 0x0000 },   /* R2400  - DSP1AUX3MIX Input 1 Source */ 
-	{ 0x00000968, 0x0000 },   /* R2408  - DSP1AUX4MIX Input 1 Source */ 
-	{ 0x00000970, 0x0000 },   /* R2416  - DSP1AUX5MIX Input 1 Source */ 
-	{ 0x00000978, 0x0000 },   /* R2424  - DSP1AUX6MIX Input 1 Source */ 
-	{ 0x00000A80, 0x0000 },   /* R2688  - ASRC1LMIX Input 1 Source */ 
-	{ 0x00000A88, 0x0000 },   /* R2696  - ASRC1RMIX Input 1 Source */ 
-	{ 0x00000A90, 0x0000 },   /* R2704  - ASRC2LMIX Input 1 Source */ 
-	{ 0x00000A98, 0x0000 },   /* R2712  - ASRC2RMIX Input 1 Source */ 
-	{ 0x00000B00, 0x0000 },   /* R2816  - ISRC1DEC1MIX Input 1 Source */ 
-	{ 0x00000B08, 0x0000 },   /* R2824  - ISRC1DEC2MIX Input 1 Source */ 
-	{ 0x00000B20, 0x0000 },   /* R2848  - ISRC1INT1MIX Input 1 Source */ 
-	{ 0x00000B28, 0x0000 },   /* R2856  - ISRC1INT2MIX Input 1 Source */ 
-	{ 0x00000B40, 0x0000 },   /* R2880  - ISRC2DEC1MIX Input 1 Source */ 
-	{ 0x00000B48, 0x0000 },   /* R2888  - ISRC2DEC2MIX Input 1 Source */ 
-	{ 0x00000B60, 0x0000 },   /* R2912  - ISRC2INT1MIX Input 1 Source */ 
-	{ 0x00000B68, 0x0000 },   /* R2920  - ISRC2INT2MIX Input 1 Source */ 
-	{ 0x00000C00, 0xA101 },   /* R3072  - GPIO1 CTRL */ 
-	{ 0x00000C01, 0xA101 },   /* R3073  - GPIO2 CTRL */ 
-	{ 0x00000C02, 0xA101 },   /* R3074  - GPIO3 CTRL */ 
-	{ 0x00000C03, 0xA101 },   /* R3075  - GPIO4 CTRL */ 
-	{ 0x00000C04, 0xA101 },   /* R3076  - GPIO5 CTRL */ 
-	{ 0x00000C0F, 0x0400 },   /* R3087  - IRQ CTRL 1 */ 
-	{ 0x00000C10, 0x1000 },   /* R3088  - GPIO Debounce Config */ 
-	{ 0x00000C20, 0x8002 },   /* R3104  - Misc Pad Ctrl 1 */ 
+	{ 0x00000490, 0x0069 },   /* R1168  - PDM SPK1 CTRL 1 */
+	{ 0x00000491, 0x0000 },   /* R1169  - PDM SPK1 CTRL 2 */
+	{ 0x00000500, 0x000C },   /* R1280  - AIF1 BCLK Ctrl */
+	{ 0x00000501, 0x0008 },   /* R1281  - AIF1 Tx Pin Ctrl */
+	{ 0x00000502, 0x0000 },   /* R1282  - AIF1 Rx Pin Ctrl */
+	{ 0x00000503, 0x0000 },   /* R1283  - AIF1 Rate Ctrl */
+	{ 0x00000504, 0x0000 },   /* R1284  - AIF1 Format */
+	{ 0x00000505, 0x0040 },   /* R1285  - AIF1 Tx BCLK Rate */
+	{ 0x00000506, 0x0040 },   /* R1286  - AIF1 Rx BCLK Rate */
+	{ 0x00000507, 0x1818 },   /* R1287  - AIF1 Frame Ctrl 1 */
+	{ 0x00000508, 0x1818 },   /* R1288  - AIF1 Frame Ctrl 2 */
+	{ 0x00000509, 0x0000 },   /* R1289  - AIF1 Frame Ctrl 3 */
+	{ 0x0000050A, 0x0001 },   /* R1290  - AIF1 Frame Ctrl 4 */
+	{ 0x0000050B, 0x0002 },   /* R1291  - AIF1 Frame Ctrl 5 */
+	{ 0x0000050C, 0x0003 },   /* R1292  - AIF1 Frame Ctrl 6 */
+	{ 0x0000050D, 0x0004 },   /* R1293  - AIF1 Frame Ctrl 7 */
+	{ 0x0000050E, 0x0005 },   /* R1294  - AIF1 Frame Ctrl 8 */
+	{ 0x0000050F, 0x0006 },   /* R1295  - AIF1 Frame Ctrl 9 */
+	{ 0x00000510, 0x0007 },   /* R1296  - AIF1 Frame Ctrl 10 */
+	{ 0x00000511, 0x0000 },   /* R1297  - AIF1 Frame Ctrl 11 */
+	{ 0x00000512, 0x0001 },   /* R1298  - AIF1 Frame Ctrl 12 */
+	{ 0x00000513, 0x0002 },   /* R1299  - AIF1 Frame Ctrl 13 */
+	{ 0x00000514, 0x0003 },   /* R1300  - AIF1 Frame Ctrl 14 */
+	{ 0x00000515, 0x0004 },   /* R1301  - AIF1 Frame Ctrl 15 */
+	{ 0x00000516, 0x0005 },   /* R1302  - AIF1 Frame Ctrl 16 */
+	{ 0x00000517, 0x0006 },   /* R1303  - AIF1 Frame Ctrl 17 */
+	{ 0x00000518, 0x0007 },   /* R1304  - AIF1 Frame Ctrl 18 */
+	{ 0x00000519, 0x0000 },   /* R1305  - AIF1 Tx Enables */
+	{ 0x0000051A, 0x0000 },   /* R1306  - AIF1 Rx Enables */
+	{ 0x00000540, 0x000C },   /* R1344  - AIF2 BCLK Ctrl */
+	{ 0x00000541, 0x0008 },   /* R1345  - AIF2 Tx Pin Ctrl */
+	{ 0x00000542, 0x0000 },   /* R1346  - AIF2 Rx Pin Ctrl */
+	{ 0x00000543, 0x0000 },   /* R1347  - AIF2 Rate Ctrl */
+	{ 0x00000544, 0x0000 },   /* R1348  - AIF2 Format */
+	{ 0x00000545, 0x0040 },   /* R1349  - AIF2 Tx BCLK Rate */
+	{ 0x00000546, 0x0040 },   /* R1350  - AIF2 Rx BCLK Rate */
+	{ 0x00000547, 0x1818 },   /* R1351  - AIF2 Frame Ctrl 1 */
+	{ 0x00000548, 0x1818 },   /* R1352  - AIF2 Frame Ctrl 2 */
+	{ 0x00000549, 0x0000 },   /* R1353  - AIF2 Frame Ctrl 3 */
+	{ 0x0000054A, 0x0001 },   /* R1354  - AIF2 Frame Ctrl 4 */
+	{ 0x00000551, 0x0000 },   /* R1361  - AIF2 Frame Ctrl 11 */
+	{ 0x00000552, 0x0001 },   /* R1362  - AIF2 Frame Ctrl 12 */
+	{ 0x00000559, 0x0000 },   /* R1369  - AIF2 Tx Enables */
+	{ 0x0000055A, 0x0000 },   /* R1370  - AIF2 Rx Enables */
+	{ 0x00000580, 0x000C },   /* R1408  - AIF3 BCLK Ctrl */
+	{ 0x00000581, 0x0008 },   /* R1409  - AIF3 Tx Pin Ctrl */
+	{ 0x00000582, 0x0000 },   /* R1410  - AIF3 Rx Pin Ctrl */
+	{ 0x00000583, 0x0000 },   /* R1411  - AIF3 Rate Ctrl */
+	{ 0x00000584, 0x0000 },   /* R1412  - AIF3 Format */
+	{ 0x00000585, 0x0040 },   /* R1413  - AIF3 Tx BCLK Rate */
+	{ 0x00000586, 0x0040 },   /* R1414  - AIF3 Rx BCLK Rate */
+	{ 0x00000587, 0x1818 },   /* R1415  - AIF3 Frame Ctrl 1 */
+	{ 0x00000588, 0x1818 },   /* R1416  - AIF3 Frame Ctrl 2 */
+	{ 0x00000589, 0x0000 },   /* R1417  - AIF3 Frame Ctrl 3 */
+	{ 0x0000058A, 0x0001 },   /* R1418  - AIF3 Frame Ctrl 4 */
+	{ 0x00000591, 0x0000 },   /* R1425  - AIF3 Frame Ctrl 11 */
+	{ 0x00000592, 0x0001 },   /* R1426  - AIF3 Frame Ctrl 12 */
+	{ 0x00000599, 0x0000 },   /* R1433  - AIF3 Tx Enables */
+	{ 0x0000059A, 0x0000 },   /* R1434  - AIF3 Rx Enables */
+	{ 0x000005E3, 0x0004 },   /* R1507  - SLIMbus Framer Ref Gear */
+	{ 0x000005E5, 0x0000 },   /* R1509  - SLIMbus Rates 1 */
+	{ 0x000005E6, 0x0000 },   /* R1510  - SLIMbus Rates 2 */
+	{ 0x000005E7, 0x0000 },   /* R1511  - SLIMbus Rates 3 */
+	{ 0x000005E8, 0x0000 },   /* R1512  - SLIMbus Rates 4 */
+	{ 0x000005E9, 0x0000 },   /* R1513  - SLIMbus Rates 5 */
+	{ 0x000005EA, 0x0000 },   /* R1514  - SLIMbus Rates 6 */
+	{ 0x000005EB, 0x0000 },   /* R1515  - SLIMbus Rates 7 */
+	{ 0x000005EC, 0x0000 },   /* R1516  - SLIMbus Rates 8 */
+	{ 0x000005F5, 0x0000 },   /* R1525  - SLIMbus RX Channel Enable */
+	{ 0x000005F6, 0x0000 },   /* R1526  - SLIMbus TX Channel Enable */
+	{ 0x00000640, 0x0000 },   /* R1600  - PWM1MIX Input 1 Source */
+	{ 0x00000641, 0x0080 },   /* R1601  - PWM1MIX Input 1 Volume */
+	{ 0x00000642, 0x0000 },   /* R1602  - PWM1MIX Input 2 Source */
+	{ 0x00000643, 0x0080 },   /* R1603  - PWM1MIX Input 2 Volume */
+	{ 0x00000644, 0x0000 },   /* R1604  - PWM1MIX Input 3 Source */
+	{ 0x00000645, 0x0080 },   /* R1605  - PWM1MIX Input 3 Volume */
+	{ 0x00000646, 0x0000 },   /* R1606  - PWM1MIX Input 4 Source */
+	{ 0x00000647, 0x0080 },   /* R1607  - PWM1MIX Input 4 Volume */
+	{ 0x00000648, 0x0000 },   /* R1608  - PWM2MIX Input 1 Source */
+	{ 0x00000649, 0x0080 },   /* R1609  - PWM2MIX Input 1 Volume */
+	{ 0x0000064A, 0x0000 },   /* R1610  - PWM2MIX Input 2 Source */
+	{ 0x0000064B, 0x0080 },   /* R1611  - PWM2MIX Input 2 Volume */
+	{ 0x0000064C, 0x0000 },   /* R1612  - PWM2MIX Input 3 Source */
+	{ 0x0000064D, 0x0080 },   /* R1613  - PWM2MIX Input 3 Volume */
+	{ 0x0000064E, 0x0000 },   /* R1614  - PWM2MIX Input 4 Source */
+	{ 0x0000064F, 0x0080 },   /* R1615  - PWM2MIX Input 4 Volume */
+	{ 0x00000660, 0x0000 },   /* R1632  - MICMIX Input 1 Source */
+	{ 0x00000661, 0x0080 },   /* R1633  - MICMIX Input 1 Volume */
+	{ 0x00000662, 0x0000 },   /* R1634  - MICMIX Input 2 Source */
+	{ 0x00000663, 0x0080 },   /* R1635  - MICMIX Input 2 Volume */
+	{ 0x00000664, 0x0000 },   /* R1636  - MICMIX Input 3 Source */
+	{ 0x00000665, 0x0080 },   /* R1637  - MICMIX Input 3 Volume */
+	{ 0x00000666, 0x0000 },   /* R1638  - MICMIX Input 4 Source */
+	{ 0x00000667, 0x0080 },   /* R1639  - MICMIX Input 4 Volume */
+	{ 0x00000668, 0x0000 },   /* R1640  - NOISEMIX Input 1 Source */
+	{ 0x00000669, 0x0080 },   /* R1641  - NOISEMIX Input 1 Volume */
+	{ 0x0000066A, 0x0000 },   /* R1642  - NOISEMIX Input 2 Source */
+	{ 0x0000066B, 0x0080 },   /* R1643  - NOISEMIX Input 2 Volume */
+	{ 0x0000066C, 0x0000 },   /* R1644  - NOISEMIX Input 3 Source */
+	{ 0x0000066D, 0x0080 },   /* R1645  - NOISEMIX Input 3 Volume */
+	{ 0x0000066E, 0x0000 },   /* R1646  - NOISEMIX Input 4 Source */
+	{ 0x0000066F, 0x0080 },   /* R1647  - NOISEMIX Input 4 Volume */
+	{ 0x00000680, 0x0000 },   /* R1664  - OUT1LMIX Input 1 Source */
+	{ 0x00000681, 0x0080 },   /* R1665  - OUT1LMIX Input 1 Volume */
+	{ 0x00000682, 0x0000 },   /* R1666  - OUT1LMIX Input 2 Source */
+	{ 0x00000683, 0x0080 },   /* R1667  - OUT1LMIX Input 2 Volume */
+	{ 0x00000684, 0x0000 },   /* R1668  - OUT1LMIX Input 3 Source */
+	{ 0x00000685, 0x0080 },   /* R1669  - OUT1LMIX Input 3 Volume */
+	{ 0x00000686, 0x0000 },   /* R1670  - OUT1LMIX Input 4 Source */
+	{ 0x00000687, 0x0080 },   /* R1671  - OUT1LMIX Input 4 Volume */
+	{ 0x00000688, 0x0000 },   /* R1672  - OUT1RMIX Input 1 Source */
+	{ 0x00000689, 0x0080 },   /* R1673  - OUT1RMIX Input 1 Volume */
+	{ 0x0000068A, 0x0000 },   /* R1674  - OUT1RMIX Input 2 Source */
+	{ 0x0000068B, 0x0080 },   /* R1675  - OUT1RMIX Input 2 Volume */
+	{ 0x0000068C, 0x0000 },   /* R1676  - OUT1RMIX Input 3 Source */
+	{ 0x0000068D, 0x0080 },   /* R1677  - OUT1RMIX Input 3 Volume */
+	{ 0x0000068E, 0x0000 },   /* R1678  - OUT1RMIX Input 4 Source */
+	{ 0x0000068F, 0x0080 },   /* R1679  - OUT1RMIX Input 4 Volume */
+	{ 0x00000690, 0x0000 },   /* R1680  - OUT2LMIX Input 1 Source */
+	{ 0x00000691, 0x0080 },   /* R1681  - OUT2LMIX Input 1 Volume */
+	{ 0x00000692, 0x0000 },   /* R1682  - OUT2LMIX Input 2 Source */
+	{ 0x00000693, 0x0080 },   /* R1683  - OUT2LMIX Input 2 Volume */
+	{ 0x00000694, 0x0000 },   /* R1684  - OUT2LMIX Input 3 Source */
+	{ 0x00000695, 0x0080 },   /* R1685  - OUT2LMIX Input 3 Volume */
+	{ 0x00000696, 0x0000 },   /* R1686  - OUT2LMIX Input 4 Source */
+	{ 0x00000697, 0x0080 },   /* R1687  - OUT2LMIX Input 4 Volume */
+	{ 0x00000698, 0x0000 },   /* R1688  - OUT2RMIX Input 1 Source */
+	{ 0x00000699, 0x0080 },   /* R1689  - OUT2RMIX Input 1 Volume */
+	{ 0x0000069A, 0x0000 },   /* R1690  - OUT2RMIX Input 2 Source */
+	{ 0x0000069B, 0x0080 },   /* R1691  - OUT2RMIX Input 2 Volume */
+	{ 0x0000069C, 0x0000 },   /* R1692  - OUT2RMIX Input 3 Source */
+	{ 0x0000069D, 0x0080 },   /* R1693  - OUT2RMIX Input 3 Volume */
+	{ 0x0000069E, 0x0000 },   /* R1694  - OUT2RMIX Input 4 Source */
+	{ 0x0000069F, 0x0080 },   /* R1695  - OUT2RMIX Input 4 Volume */
+	{ 0x000006A0, 0x0000 },   /* R1696  - OUT3LMIX Input 1 Source */
+	{ 0x000006A1, 0x0080 },   /* R1697  - OUT3LMIX Input 1 Volume */
+	{ 0x000006A2, 0x0000 },   /* R1698  - OUT3LMIX Input 2 Source */
+	{ 0x000006A3, 0x0080 },   /* R1699  - OUT3LMIX Input 2 Volume */
+	{ 0x000006A4, 0x0000 },   /* R1700  - OUT3LMIX Input 3 Source */
+	{ 0x000006A5, 0x0080 },   /* R1701  - OUT3LMIX Input 3 Volume */
+	{ 0x000006A6, 0x0000 },   /* R1702  - OUT3LMIX Input 4 Source */
+	{ 0x000006A7, 0x0080 },   /* R1703  - OUT3LMIX Input 4 Volume */
+	{ 0x000006B0, 0x0000 },   /* R1712  - OUT4LMIX Input 1 Source */
+	{ 0x000006B1, 0x0080 },   /* R1713  - OUT4LMIX Input 1 Volume */
+	{ 0x000006B2, 0x0000 },   /* R1714  - OUT4LMIX Input 2 Source */
+	{ 0x000006B3, 0x0080 },   /* R1715  - OUT4LMIX Input 2 Volume */
+	{ 0x000006B4, 0x0000 },   /* R1716  - OUT4LMIX Input 3 Source */
+	{ 0x000006B5, 0x0080 },   /* R1717  - OUT4LMIX Input 3 Volume */
+	{ 0x000006B6, 0x0000 },   /* R1718  - OUT4LMIX Input 4 Source */
+	{ 0x000006B7, 0x0080 },   /* R1719  - OUT4LMIX Input 4 Volume */
+	{ 0x000006B8, 0x0000 },   /* R1720  - OUT4RMIX Input 1 Source */
+	{ 0x000006B9, 0x0080 },   /* R1721  - OUT4RMIX Input 1 Volume */
+	{ 0x000006BA, 0x0000 },   /* R1722  - OUT4RMIX Input 2 Source */
+	{ 0x000006BB, 0x0080 },   /* R1723  - OUT4RMIX Input 2 Volume */
+	{ 0x000006BC, 0x0000 },   /* R1724  - OUT4RMIX Input 3 Source */
+	{ 0x000006BD, 0x0080 },   /* R1725  - OUT4RMIX Input 3 Volume */
+	{ 0x000006BE, 0x0000 },   /* R1726  - OUT4RMIX Input 4 Source */
+	{ 0x000006BF, 0x0080 },   /* R1727  - OUT4RMIX Input 4 Volume */
+	{ 0x000006C0, 0x0000 },   /* R1728  - OUT5LMIX Input 1 Source */
+	{ 0x000006C1, 0x0080 },   /* R1729  - OUT5LMIX Input 1 Volume */
+	{ 0x000006C2, 0x0000 },   /* R1730  - OUT5LMIX Input 2 Source */
+	{ 0x000006C3, 0x0080 },   /* R1731  - OUT5LMIX Input 2 Volume */
+	{ 0x000006C4, 0x0000 },   /* R1732  - OUT5LMIX Input 3 Source */
+	{ 0x000006C5, 0x0080 },   /* R1733  - OUT5LMIX Input 3 Volume */
+	{ 0x000006C6, 0x0000 },   /* R1734  - OUT5LMIX Input 4 Source */
+	{ 0x000006C7, 0x0080 },   /* R1735  - OUT5LMIX Input 4 Volume */
+	{ 0x000006C8, 0x0000 },   /* R1736  - OUT5RMIX Input 1 Source */
+	{ 0x000006C9, 0x0080 },   /* R1737  - OUT5RMIX Input 1 Volume */
+	{ 0x000006CA, 0x0000 },   /* R1738  - OUT5RMIX Input 2 Source */
+	{ 0x000006CB, 0x0080 },   /* R1739  - OUT5RMIX Input 2 Volume */
+	{ 0x000006CC, 0x0000 },   /* R1740  - OUT5RMIX Input 3 Source */
+	{ 0x000006CD, 0x0080 },   /* R1741  - OUT5RMIX Input 3 Volume */
+	{ 0x000006CE, 0x0000 },   /* R1742  - OUT5RMIX Input 4 Source */
+	{ 0x000006CF, 0x0080 },   /* R1743  - OUT5RMIX Input 4 Volume */
+	{ 0x00000700, 0x0000 },   /* R1792  - AIF1TX1MIX Input 1 Source */
+	{ 0x00000701, 0x0080 },   /* R1793  - AIF1TX1MIX Input 1 Volume */
+	{ 0x00000702, 0x0000 },   /* R1794  - AIF1TX1MIX Input 2 Source */
+	{ 0x00000703, 0x0080 },   /* R1795  - AIF1TX1MIX Input 2 Volume */
+	{ 0x00000704, 0x0000 },   /* R1796  - AIF1TX1MIX Input 3 Source */
+	{ 0x00000705, 0x0080 },   /* R1797  - AIF1TX1MIX Input 3 Volume */
+	{ 0x00000706, 0x0000 },   /* R1798  - AIF1TX1MIX Input 4 Source */
+	{ 0x00000707, 0x0080 },   /* R1799  - AIF1TX1MIX Input 4 Volume */
+	{ 0x00000708, 0x0000 },   /* R1800  - AIF1TX2MIX Input 1 Source */
+	{ 0x00000709, 0x0080 },   /* R1801  - AIF1TX2MIX Input 1 Volume */
+	{ 0x0000070A, 0x0000 },   /* R1802  - AIF1TX2MIX Input 2 Source */
+	{ 0x0000070B, 0x0080 },   /* R1803  - AIF1TX2MIX Input 2 Volume */
+	{ 0x0000070C, 0x0000 },   /* R1804  - AIF1TX2MIX Input 3 Source */
+	{ 0x0000070D, 0x0080 },   /* R1805  - AIF1TX2MIX Input 3 Volume */
+	{ 0x0000070E, 0x0000 },   /* R1806  - AIF1TX2MIX Input 4 Source */
+	{ 0x0000070F, 0x0080 },   /* R1807  - AIF1TX2MIX Input 4 Volume */
+	{ 0x00000710, 0x0000 },   /* R1808  - AIF1TX3MIX Input 1 Source */
+	{ 0x00000711, 0x0080 },   /* R1809  - AIF1TX3MIX Input 1 Volume */
+	{ 0x00000712, 0x0000 },   /* R1810  - AIF1TX3MIX Input 2 Source */
+	{ 0x00000713, 0x0080 },   /* R1811  - AIF1TX3MIX Input 2 Volume */
+	{ 0x00000714, 0x0000 },   /* R1812  - AIF1TX3MIX Input 3 Source */
+	{ 0x00000715, 0x0080 },   /* R1813  - AIF1TX3MIX Input 3 Volume */
+	{ 0x00000716, 0x0000 },   /* R1814  - AIF1TX3MIX Input 4 Source */
+	{ 0x00000717, 0x0080 },   /* R1815  - AIF1TX3MIX Input 4 Volume */
+	{ 0x00000718, 0x0000 },   /* R1816  - AIF1TX4MIX Input 1 Source */
+	{ 0x00000719, 0x0080 },   /* R1817  - AIF1TX4MIX Input 1 Volume */
+	{ 0x0000071A, 0x0000 },   /* R1818  - AIF1TX4MIX Input 2 Source */
+	{ 0x0000071B, 0x0080 },   /* R1819  - AIF1TX4MIX Input 2 Volume */
+	{ 0x0000071C, 0x0000 },   /* R1820  - AIF1TX4MIX Input 3 Source */
+	{ 0x0000071D, 0x0080 },   /* R1821  - AIF1TX4MIX Input 3 Volume */
+	{ 0x0000071E, 0x0000 },   /* R1822  - AIF1TX4MIX Input 4 Source */
+	{ 0x0000071F, 0x0080 },   /* R1823  - AIF1TX4MIX Input 4 Volume */
+	{ 0x00000720, 0x0000 },   /* R1824  - AIF1TX5MIX Input 1 Source */
+	{ 0x00000721, 0x0080 },   /* R1825  - AIF1TX5MIX Input 1 Volume */
+	{ 0x00000722, 0x0000 },   /* R1826  - AIF1TX5MIX Input 2 Source */
+	{ 0x00000723, 0x0080 },   /* R1827  - AIF1TX5MIX Input 2 Volume */
+	{ 0x00000724, 0x0000 },   /* R1828  - AIF1TX5MIX Input 3 Source */
+	{ 0x00000725, 0x0080 },   /* R1829  - AIF1TX5MIX Input 3 Volume */
+	{ 0x00000726, 0x0000 },   /* R1830  - AIF1TX5MIX Input 4 Source */
+	{ 0x00000727, 0x0080 },   /* R1831  - AIF1TX5MIX Input 4 Volume */
+	{ 0x00000728, 0x0000 },   /* R1832  - AIF1TX6MIX Input 1 Source */
+	{ 0x00000729, 0x0080 },   /* R1833  - AIF1TX6MIX Input 1 Volume */
+	{ 0x0000072A, 0x0000 },   /* R1834  - AIF1TX6MIX Input 2 Source */
+	{ 0x0000072B, 0x0080 },   /* R1835  - AIF1TX6MIX Input 2 Volume */
+	{ 0x0000072C, 0x0000 },   /* R1836  - AIF1TX6MIX Input 3 Source */
+	{ 0x0000072D, 0x0080 },   /* R1837  - AIF1TX6MIX Input 3 Volume */
+	{ 0x0000072E, 0x0000 },   /* R1838  - AIF1TX6MIX Input 4 Source */
+	{ 0x0000072F, 0x0080 },   /* R1839  - AIF1TX6MIX Input 4 Volume */
+	{ 0x00000730, 0x0000 },   /* R1840  - AIF1TX7MIX Input 1 Source */
+	{ 0x00000731, 0x0080 },   /* R1841  - AIF1TX7MIX Input 1 Volume */
+	{ 0x00000732, 0x0000 },   /* R1842  - AIF1TX7MIX Input 2 Source */
+	{ 0x00000733, 0x0080 },   /* R1843  - AIF1TX7MIX Input 2 Volume */
+	{ 0x00000734, 0x0000 },   /* R1844  - AIF1TX7MIX Input 3 Source */
+	{ 0x00000735, 0x0080 },   /* R1845  - AIF1TX7MIX Input 3 Volume */
+	{ 0x00000736, 0x0000 },   /* R1846  - AIF1TX7MIX Input 4 Source */
+	{ 0x00000737, 0x0080 },   /* R1847  - AIF1TX7MIX Input 4 Volume */
+	{ 0x00000738, 0x0000 },   /* R1848  - AIF1TX8MIX Input 1 Source */
+	{ 0x00000739, 0x0080 },   /* R1849  - AIF1TX8MIX Input 1 Volume */
+	{ 0x0000073A, 0x0000 },   /* R1850  - AIF1TX8MIX Input 2 Source */
+	{ 0x0000073B, 0x0080 },   /* R1851  - AIF1TX8MIX Input 2 Volume */
+	{ 0x0000073C, 0x0000 },   /* R1852  - AIF1TX8MIX Input 3 Source */
+	{ 0x0000073D, 0x0080 },   /* R1853  - AIF1TX8MIX Input 3 Volume */
+	{ 0x0000073E, 0x0000 },   /* R1854  - AIF1TX8MIX Input 4 Source */
+	{ 0x0000073F, 0x0080 },   /* R1855  - AIF1TX8MIX Input 4 Volume */
+	{ 0x00000740, 0x0000 },   /* R1856  - AIF2TX1MIX Input 1 Source */
+	{ 0x00000741, 0x0080 },   /* R1857  - AIF2TX1MIX Input 1 Volume */
+	{ 0x00000742, 0x0000 },   /* R1858  - AIF2TX1MIX Input 2 Source */
+	{ 0x00000743, 0x0080 },   /* R1859  - AIF2TX1MIX Input 2 Volume */
+	{ 0x00000744, 0x0000 },   /* R1860  - AIF2TX1MIX Input 3 Source */
+	{ 0x00000745, 0x0080 },   /* R1861  - AIF2TX1MIX Input 3 Volume */
+	{ 0x00000746, 0x0000 },   /* R1862  - AIF2TX1MIX Input 4 Source */
+	{ 0x00000747, 0x0080 },   /* R1863  - AIF2TX1MIX Input 4 Volume */
+	{ 0x00000748, 0x0000 },   /* R1864  - AIF2TX2MIX Input 1 Source */
+	{ 0x00000749, 0x0080 },   /* R1865  - AIF2TX2MIX Input 1 Volume */
+	{ 0x0000074A, 0x0000 },   /* R1866  - AIF2TX2MIX Input 2 Source */
+	{ 0x0000074B, 0x0080 },   /* R1867  - AIF2TX2MIX Input 2 Volume */
+	{ 0x0000074C, 0x0000 },   /* R1868  - AIF2TX2MIX Input 3 Source */
+	{ 0x0000074D, 0x0080 },   /* R1869  - AIF2TX2MIX Input 3 Volume */
+	{ 0x0000074E, 0x0000 },   /* R1870  - AIF2TX2MIX Input 4 Source */
+	{ 0x0000074F, 0x0080 },   /* R1871  - AIF2TX2MIX Input 4 Volume */
+	{ 0x00000780, 0x0000 },   /* R1920  - AIF3TX1MIX Input 1 Source */
+	{ 0x00000781, 0x0080 },   /* R1921  - AIF3TX1MIX Input 1 Volume */
+	{ 0x00000782, 0x0000 },   /* R1922  - AIF3TX1MIX Input 2 Source */
+	{ 0x00000783, 0x0080 },   /* R1923  - AIF3TX1MIX Input 2 Volume */
+	{ 0x00000784, 0x0000 },   /* R1924  - AIF3TX1MIX Input 3 Source */
+	{ 0x00000785, 0x0080 },   /* R1925  - AIF3TX1MIX Input 3 Volume */
+	{ 0x00000786, 0x0000 },   /* R1926  - AIF3TX1MIX Input 4 Source */
+	{ 0x00000787, 0x0080 },   /* R1927  - AIF3TX1MIX Input 4 Volume */
+	{ 0x00000788, 0x0000 },   /* R1928  - AIF3TX2MIX Input 1 Source */
+	{ 0x00000789, 0x0080 },   /* R1929  - AIF3TX2MIX Input 1 Volume */
+	{ 0x0000078A, 0x0000 },   /* R1930  - AIF3TX2MIX Input 2 Source */
+	{ 0x0000078B, 0x0080 },   /* R1931  - AIF3TX2MIX Input 2 Volume */
+	{ 0x0000078C, 0x0000 },   /* R1932  - AIF3TX2MIX Input 3 Source */
+	{ 0x0000078D, 0x0080 },   /* R1933  - AIF3TX2MIX Input 3 Volume */
+	{ 0x0000078E, 0x0000 },   /* R1934  - AIF3TX2MIX Input 4 Source */
+	{ 0x0000078F, 0x0080 },   /* R1935  - AIF3TX2MIX Input 4 Volume */
+	{ 0x000007C0, 0x0000 },   /* R1984  - SLIMTX1MIX Input 1 Source */
+	{ 0x000007C1, 0x0080 },   /* R1985  - SLIMTX1MIX Input 1 Volume */
+	{ 0x000007C2, 0x0000 },   /* R1986  - SLIMTX1MIX Input 2 Source */
+	{ 0x000007C3, 0x0080 },   /* R1987  - SLIMTX1MIX Input 2 Volume */
+	{ 0x000007C4, 0x0000 },   /* R1988  - SLIMTX1MIX Input 3 Source */
+	{ 0x000007C5, 0x0080 },   /* R1989  - SLIMTX1MIX Input 3 Volume */
+	{ 0x000007C6, 0x0000 },   /* R1990  - SLIMTX1MIX Input 4 Source */
+	{ 0x000007C7, 0x0080 },   /* R1991  - SLIMTX1MIX Input 4 Volume */
+	{ 0x000007C8, 0x0000 },   /* R1992  - SLIMTX2MIX Input 1 Source */
+	{ 0x000007C9, 0x0080 },   /* R1993  - SLIMTX2MIX Input 1 Volume */
+	{ 0x000007CA, 0x0000 },   /* R1994  - SLIMTX2MIX Input 2 Source */
+	{ 0x000007CB, 0x0080 },   /* R1995  - SLIMTX2MIX Input 2 Volume */
+	{ 0x000007CC, 0x0000 },   /* R1996  - SLIMTX2MIX Input 3 Source */
+	{ 0x000007CD, 0x0080 },   /* R1997  - SLIMTX2MIX Input 3 Volume */
+	{ 0x000007CE, 0x0000 },   /* R1998  - SLIMTX2MIX Input 4 Source */
+	{ 0x000007CF, 0x0080 },   /* R1999  - SLIMTX2MIX Input 4 Volume */
+	{ 0x000007D0, 0x0000 },   /* R2000  - SLIMTX3MIX Input 1 Source */
+	{ 0x000007D1, 0x0080 },   /* R2001  - SLIMTX3MIX Input 1 Volume */
+	{ 0x000007D2, 0x0000 },   /* R2002  - SLIMTX3MIX Input 2 Source */
+	{ 0x000007D3, 0x0080 },   /* R2003  - SLIMTX3MIX Input 2 Volume */
+	{ 0x000007D4, 0x0000 },   /* R2004  - SLIMTX3MIX Input 3 Source */
+	{ 0x000007D5, 0x0080 },   /* R2005  - SLIMTX3MIX Input 3 Volume */
+	{ 0x000007D6, 0x0000 },   /* R2006  - SLIMTX3MIX Input 4 Source */
+	{ 0x000007D7, 0x0080 },   /* R2007  - SLIMTX3MIX Input 4 Volume */
+	{ 0x000007D8, 0x0000 },   /* R2008  - SLIMTX4MIX Input 1 Source */
+	{ 0x000007D9, 0x0080 },   /* R2009  - SLIMTX4MIX Input 1 Volume */
+	{ 0x000007DA, 0x0000 },   /* R2010  - SLIMTX4MIX Input 2 Source */
+	{ 0x000007DB, 0x0080 },   /* R2011  - SLIMTX4MIX Input 2 Volume */
+	{ 0x000007DC, 0x0000 },   /* R2012  - SLIMTX4MIX Input 3 Source */
+	{ 0x000007DD, 0x0080 },   /* R2013  - SLIMTX4MIX Input 3 Volume */
+	{ 0x000007DE, 0x0000 },   /* R2014  - SLIMTX4MIX Input 4 Source */
+	{ 0x000007DF, 0x0080 },   /* R2015  - SLIMTX4MIX Input 4 Volume */
+	{ 0x000007E0, 0x0000 },   /* R2016  - SLIMTX5MIX Input 1 Source */
+	{ 0x000007E1, 0x0080 },   /* R2017  - SLIMTX5MIX Input 1 Volume */
+	{ 0x000007E2, 0x0000 },   /* R2018  - SLIMTX5MIX Input 2 Source */
+	{ 0x000007E3, 0x0080 },   /* R2019  - SLIMTX5MIX Input 2 Volume */
+	{ 0x000007E4, 0x0000 },   /* R2020  - SLIMTX5MIX Input 3 Source */
+	{ 0x000007E5, 0x0080 },   /* R2021  - SLIMTX5MIX Input 3 Volume */
+	{ 0x000007E6, 0x0000 },   /* R2022  - SLIMTX5MIX Input 4 Source */
+	{ 0x000007E7, 0x0080 },   /* R2023  - SLIMTX5MIX Input 4 Volume */
+	{ 0x000007E8, 0x0000 },   /* R2024  - SLIMTX6MIX Input 1 Source */
+	{ 0x000007E9, 0x0080 },   /* R2025  - SLIMTX6MIX Input 1 Volume */
+	{ 0x000007EA, 0x0000 },   /* R2026  - SLIMTX6MIX Input 2 Source */
+	{ 0x000007EB, 0x0080 },   /* R2027  - SLIMTX6MIX Input 2 Volume */
+	{ 0x000007EC, 0x0000 },   /* R2028  - SLIMTX6MIX Input 3 Source */
+	{ 0x000007ED, 0x0080 },   /* R2029  - SLIMTX6MIX Input 3 Volume */
+	{ 0x000007EE, 0x0000 },   /* R2030  - SLIMTX6MIX Input 4 Source */
+	{ 0x000007EF, 0x0080 },   /* R2031  - SLIMTX6MIX Input 4 Volume */
+	{ 0x000007F0, 0x0000 },   /* R2032  - SLIMTX7MIX Input 1 Source */
+	{ 0x000007F1, 0x0080 },   /* R2033  - SLIMTX7MIX Input 1 Volume */
+	{ 0x000007F2, 0x0000 },   /* R2034  - SLIMTX7MIX Input 2 Source */
+	{ 0x000007F3, 0x0080 },   /* R2035  - SLIMTX7MIX Input 2 Volume */
+	{ 0x000007F4, 0x0000 },   /* R2036  - SLIMTX7MIX Input 3 Source */
+	{ 0x000007F5, 0x0080 },   /* R2037  - SLIMTX7MIX Input 3 Volume */
+	{ 0x000007F6, 0x0000 },   /* R2038  - SLIMTX7MIX Input 4 Source */
+	{ 0x000007F7, 0x0080 },   /* R2039  - SLIMTX7MIX Input 4 Volume */
+	{ 0x000007F8, 0x0000 },   /* R2040  - SLIMTX8MIX Input 1 Source */
+	{ 0x000007F9, 0x0080 },   /* R2041  - SLIMTX8MIX Input 1 Volume */
+	{ 0x000007FA, 0x0000 },   /* R2042  - SLIMTX8MIX Input 2 Source */
+	{ 0x000007FB, 0x0080 },   /* R2043  - SLIMTX8MIX Input 2 Volume */
+	{ 0x000007FC, 0x0000 },   /* R2044  - SLIMTX8MIX Input 3 Source */
+	{ 0x000007FD, 0x0080 },   /* R2045  - SLIMTX8MIX Input 3 Volume */
+	{ 0x000007FE, 0x0000 },   /* R2046  - SLIMTX8MIX Input 4 Source */
+	{ 0x000007FF, 0x0080 },   /* R2047  - SLIMTX8MIX Input 4 Volume */
+	{ 0x00000880, 0x0000 },   /* R2176  - EQ1MIX Input 1 Source */
+	{ 0x00000881, 0x0080 },   /* R2177  - EQ1MIX Input 1 Volume */
+	{ 0x00000882, 0x0000 },   /* R2178  - EQ1MIX Input 2 Source */
+	{ 0x00000883, 0x0080 },   /* R2179  - EQ1MIX Input 2 Volume */
+	{ 0x00000884, 0x0000 },   /* R2180  - EQ1MIX Input 3 Source */
+	{ 0x00000885, 0x0080 },   /* R2181  - EQ1MIX Input 3 Volume */
+	{ 0x00000886, 0x0000 },   /* R2182  - EQ1MIX Input 4 Source */
+	{ 0x00000887, 0x0080 },   /* R2183  - EQ1MIX Input 4 Volume */
+	{ 0x00000888, 0x0000 },   /* R2184  - EQ2MIX Input 1 Source */
+	{ 0x00000889, 0x0080 },   /* R2185  - EQ2MIX Input 1 Volume */
+	{ 0x0000088A, 0x0000 },   /* R2186  - EQ2MIX Input 2 Source */
+	{ 0x0000088B, 0x0080 },   /* R2187  - EQ2MIX Input 2 Volume */
+	{ 0x0000088C, 0x0000 },   /* R2188  - EQ2MIX Input 3 Source */
+	{ 0x0000088D, 0x0080 },   /* R2189  - EQ2MIX Input 3 Volume */
+	{ 0x0000088E, 0x0000 },   /* R2190  - EQ2MIX Input 4 Source */
+	{ 0x0000088F, 0x0080 },   /* R2191  - EQ2MIX Input 4 Volume */
+	{ 0x00000890, 0x0000 },   /* R2192  - EQ3MIX Input 1 Source */
+	{ 0x00000891, 0x0080 },   /* R2193  - EQ3MIX Input 1 Volume */
+	{ 0x00000892, 0x0000 },   /* R2194  - EQ3MIX Input 2 Source */
+	{ 0x00000893, 0x0080 },   /* R2195  - EQ3MIX Input 2 Volume */
+	{ 0x00000894, 0x0000 },   /* R2196  - EQ3MIX Input 3 Source */
+	{ 0x00000895, 0x0080 },   /* R2197  - EQ3MIX Input 3 Volume */
+	{ 0x00000896, 0x0000 },   /* R2198  - EQ3MIX Input 4 Source */
+	{ 0x00000897, 0x0080 },   /* R2199  - EQ3MIX Input 4 Volume */
+	{ 0x00000898, 0x0000 },   /* R2200  - EQ4MIX Input 1 Source */
+	{ 0x00000899, 0x0080 },   /* R2201  - EQ4MIX Input 1 Volume */
+	{ 0x0000089A, 0x0000 },   /* R2202  - EQ4MIX Input 2 Source */
+	{ 0x0000089B, 0x0080 },   /* R2203  - EQ4MIX Input 2 Volume */
+	{ 0x0000089C, 0x0000 },   /* R2204  - EQ4MIX Input 3 Source */
+	{ 0x0000089D, 0x0080 },   /* R2205  - EQ4MIX Input 3 Volume */
+	{ 0x0000089E, 0x0000 },   /* R2206  - EQ4MIX Input 4 Source */
+	{ 0x0000089F, 0x0080 },   /* R2207  - EQ4MIX Input 4 Volume */
+	{ 0x000008C0, 0x0000 },   /* R2240  - DRC1LMIX Input 1 Source */
+	{ 0x000008C1, 0x0080 },   /* R2241  - DRC1LMIX Input 1 Volume */
+	{ 0x000008C2, 0x0000 },   /* R2242  - DRC1LMIX Input 2 Source */
+	{ 0x000008C3, 0x0080 },   /* R2243  - DRC1LMIX Input 2 Volume */
+	{ 0x000008C4, 0x0000 },   /* R2244  - DRC1LMIX Input 3 Source */
+	{ 0x000008C5, 0x0080 },   /* R2245  - DRC1LMIX Input 3 Volume */
+	{ 0x000008C6, 0x0000 },   /* R2246  - DRC1LMIX Input 4 Source */
+	{ 0x000008C7, 0x0080 },   /* R2247  - DRC1LMIX Input 4 Volume */
+	{ 0x000008C8, 0x0000 },   /* R2248  - DRC1RMIX Input 1 Source */
+	{ 0x000008C9, 0x0080 },   /* R2249  - DRC1RMIX Input 1 Volume */
+	{ 0x000008CA, 0x0000 },   /* R2250  - DRC1RMIX Input 2 Source */
+	{ 0x000008CB, 0x0080 },   /* R2251  - DRC1RMIX Input 2 Volume */
+	{ 0x000008CC, 0x0000 },   /* R2252  - DRC1RMIX Input 3 Source */
+	{ 0x000008CD, 0x0080 },   /* R2253  - DRC1RMIX Input 3 Volume */
+	{ 0x000008CE, 0x0000 },   /* R2254  - DRC1RMIX Input 4 Source */
+	{ 0x000008CF, 0x0080 },   /* R2255  - DRC1RMIX Input 4 Volume */
+	{ 0x00000900, 0x0000 },   /* R2304  - HPLP1MIX Input 1 Source */
+	{ 0x00000901, 0x0080 },   /* R2305  - HPLP1MIX Input 1 Volume */
+	{ 0x00000902, 0x0000 },   /* R2306  - HPLP1MIX Input 2 Source */
+	{ 0x00000903, 0x0080 },   /* R2307  - HPLP1MIX Input 2 Volume */
+	{ 0x00000904, 0x0000 },   /* R2308  - HPLP1MIX Input 3 Source */
+	{ 0x00000905, 0x0080 },   /* R2309  - HPLP1MIX Input 3 Volume */
+	{ 0x00000906, 0x0000 },   /* R2310  - HPLP1MIX Input 4 Source */
+	{ 0x00000907, 0x0080 },   /* R2311  - HPLP1MIX Input 4 Volume */
+	{ 0x00000908, 0x0000 },   /* R2312  - HPLP2MIX Input 1 Source */
+	{ 0x00000909, 0x0080 },   /* R2313  - HPLP2MIX Input 1 Volume */
+	{ 0x0000090A, 0x0000 },   /* R2314  - HPLP2MIX Input 2 Source */
+	{ 0x0000090B, 0x0080 },   /* R2315  - HPLP2MIX Input 2 Volume */
+	{ 0x0000090C, 0x0000 },   /* R2316  - HPLP2MIX Input 3 Source */
+	{ 0x0000090D, 0x0080 },   /* R2317  - HPLP2MIX Input 3 Volume */
+	{ 0x0000090E, 0x0000 },   /* R2318  - HPLP2MIX Input 4 Source */
+	{ 0x0000090F, 0x0080 },   /* R2319  - HPLP2MIX Input 4 Volume */
+	{ 0x00000910, 0x0000 },   /* R2320  - HPLP3MIX Input 1 Source */
+	{ 0x00000911, 0x0080 },   /* R2321  - HPLP3MIX Input 1 Volume */
+	{ 0x00000912, 0x0000 },   /* R2322  - HPLP3MIX Input 2 Source */
+	{ 0x00000913, 0x0080 },   /* R2323  - HPLP3MIX Input 2 Volume */
+	{ 0x00000914, 0x0000 },   /* R2324  - HPLP3MIX Input 3 Source */
+	{ 0x00000915, 0x0080 },   /* R2325  - HPLP3MIX Input 3 Volume */
+	{ 0x00000916, 0x0000 },   /* R2326  - HPLP3MIX Input 4 Source */
+	{ 0x00000917, 0x0080 },   /* R2327  - HPLP3MIX Input 4 Volume */
+	{ 0x00000918, 0x0000 },   /* R2328  - HPLP4MIX Input 1 Source */
+	{ 0x00000919, 0x0080 },   /* R2329  - HPLP4MIX Input 1 Volume */
+	{ 0x0000091A, 0x0000 },   /* R2330  - HPLP4MIX Input 2 Source */
+	{ 0x0000091B, 0x0080 },   /* R2331  - HPLP4MIX Input 2 Volume */
+	{ 0x0000091C, 0x0000 },   /* R2332  - HPLP4MIX Input 3 Source */
+	{ 0x0000091D, 0x0080 },   /* R2333  - HPLP4MIX Input 3 Volume */
+	{ 0x0000091E, 0x0000 },   /* R2334  - HPLP4MIX Input 4 Source */
+	{ 0x0000091F, 0x0080 },   /* R2335  - HPLP4MIX Input 4 Volume */
+	{ 0x00000940, 0x0000 },   /* R2368  - DSP1LMIX Input 1 Source */
+	{ 0x00000941, 0x0080 },   /* R2369  - DSP1LMIX Input 1 Volume */
+	{ 0x00000942, 0x0000 },   /* R2370  - DSP1LMIX Input 2 Source */
+	{ 0x00000943, 0x0080 },   /* R2371  - DSP1LMIX Input 2 Volume */
+	{ 0x00000944, 0x0000 },   /* R2372  - DSP1LMIX Input 3 Source */
+	{ 0x00000945, 0x0080 },   /* R2373  - DSP1LMIX Input 3 Volume */
+	{ 0x00000946, 0x0000 },   /* R2374  - DSP1LMIX Input 4 Source */
+	{ 0x00000947, 0x0080 },   /* R2375  - DSP1LMIX Input 4 Volume */
+	{ 0x00000948, 0x0000 },   /* R2376  - DSP1RMIX Input 1 Source */
+	{ 0x00000949, 0x0080 },   /* R2377  - DSP1RMIX Input 1 Volume */
+	{ 0x0000094A, 0x0000 },   /* R2378  - DSP1RMIX Input 2 Source */
+	{ 0x0000094B, 0x0080 },   /* R2379  - DSP1RMIX Input 2 Volume */
+	{ 0x0000094C, 0x0000 },   /* R2380  - DSP1RMIX Input 3 Source */
+	{ 0x0000094D, 0x0080 },   /* R2381  - DSP1RMIX Input 3 Volume */
+	{ 0x0000094E, 0x0000 },   /* R2382  - DSP1RMIX Input 4 Source */
+	{ 0x0000094F, 0x0080 },   /* R2383  - DSP1RMIX Input 4 Volume */
+	{ 0x00000950, 0x0000 },   /* R2384  - DSP1AUX1MIX Input 1 Source */
+	{ 0x00000958, 0x0000 },   /* R2392  - DSP1AUX2MIX Input 1 Source */
+	{ 0x00000960, 0x0000 },   /* R2400  - DSP1AUX3MIX Input 1 Source */
+	{ 0x00000968, 0x0000 },   /* R2408  - DSP1AUX4MIX Input 1 Source */
+	{ 0x00000970, 0x0000 },   /* R2416  - DSP1AUX5MIX Input 1 Source */
+	{ 0x00000978, 0x0000 },   /* R2424  - DSP1AUX6MIX Input 1 Source */
+	{ 0x00000A80, 0x0000 },   /* R2688  - ASRC1LMIX Input 1 Source */
+	{ 0x00000A88, 0x0000 },   /* R2696  - ASRC1RMIX Input 1 Source */
+	{ 0x00000A90, 0x0000 },   /* R2704  - ASRC2LMIX Input 1 Source */
+	{ 0x00000A98, 0x0000 },   /* R2712  - ASRC2RMIX Input 1 Source */
+	{ 0x00000B00, 0x0000 },   /* R2816  - ISRC1DEC1MIX Input 1 Source */
+	{ 0x00000B08, 0x0000 },   /* R2824  - ISRC1DEC2MIX Input 1 Source */
+	{ 0x00000B20, 0x0000 },   /* R2848  - ISRC1INT1MIX Input 1 Source */
+	{ 0x00000B28, 0x0000 },   /* R2856  - ISRC1INT2MIX Input 1 Source */
+	{ 0x00000B40, 0x0000 },   /* R2880  - ISRC2DEC1MIX Input 1 Source */
+	{ 0x00000B48, 0x0000 },   /* R2888  - ISRC2DEC2MIX Input 1 Source */
+	{ 0x00000B60, 0x0000 },   /* R2912  - ISRC2INT1MIX Input 1 Source */
+	{ 0x00000B68, 0x0000 },   /* R2920  - ISRC2INT2MIX Input 1 Source */
+	{ 0x00000C00, 0xA101 },   /* R3072  - GPIO1 CTRL */
+	{ 0x00000C01, 0xA101 },   /* R3073  - GPIO2 CTRL */
+	{ 0x00000C02, 0xA101 },   /* R3074  - GPIO3 CTRL */
+	{ 0x00000C03, 0xA101 },   /* R3075  - GPIO4 CTRL */
+	{ 0x00000C04, 0xA101 },   /* R3076  - GPIO5 CTRL */
+	{ 0x00000C0F, 0x0400 },   /* R3087  - IRQ CTRL 1 */
+	{ 0x00000C10, 0x1000 },   /* R3088  - GPIO Debounce Config */
+	{ 0x00000C20, 0x8002 },   /* R3104  - Misc Pad Ctrl 1 */
 	{ 0x00000C21, 0x0001 },   /* R3105  - Misc Pad Ctrl 2 */
-	{ 0x00000C22, 0x0000 },   /* R3106  - Misc Pad Ctrl 3 */ 
-	{ 0x00000C23, 0x0000 },   /* R3107  - Misc Pad Ctrl 4 */ 
-	{ 0x00000C24, 0x0000 },   /* R3108  - Misc Pad Ctrl 5 */ 
-	{ 0x00000C25, 0x0000 },   /* R3109  - Misc Pad Ctrl 6 */ 
-	{ 0x00000D08, 0xFFFF },   /* R3336  - Interrupt Status 1 Mask */ 
-	{ 0x00000D09, 0xFFFF },   /* R3337  - Interrupt Status 2 Mask */ 
-	{ 0x00000D0A, 0xFFFF },   /* R3338  - Interrupt Status 3 Mask */ 
-	{ 0x00000D0B, 0xFFFF },   /* R3339  - Interrupt Status 4 Mask */ 
-	{ 0x00000D0C, 0xFEFF },   /* R3340  - Interrupt Status 5 Mask */ 
-	{ 0x00000D0F, 0x0000 },   /* R3343  - Interrupt Control */ 
-	{ 0x00000D18, 0xFFFF },   /* R3352  - IRQ2 Status 1 Mask */ 
-	{ 0x00000D19, 0xFFFF },   /* R3353  - IRQ2 Status 2 Mask */ 
-	{ 0x00000D1A, 0xFFFF },   /* R3354  - IRQ2 Status 3 Mask */ 
-	{ 0x00000D1B, 0xFFFF },   /* R3355  - IRQ2 Status 4 Mask */ 
-	{ 0x00000D1C, 0xFFFF },   /* R3356  - IRQ2 Status 5 Mask */ 
-	{ 0x00000D1F, 0x0000 },   /* R3359  - IRQ2 Control */ 
+	{ 0x00000C22, 0x0000 },   /* R3106  - Misc Pad Ctrl 3 */
+	{ 0x00000C23, 0x0000 },   /* R3107  - Misc Pad Ctrl 4 */
+	{ 0x00000C24, 0x0000 },   /* R3108  - Misc Pad Ctrl 5 */
+	{ 0x00000C25, 0x0000 },   /* R3109  - Misc Pad Ctrl 6 */
+	{ 0x00000D08, 0xFFFF },   /* R3336  - Interrupt Status 1 Mask */
+	{ 0x00000D09, 0xFFFF },   /* R3337  - Interrupt Status 2 Mask */
+	{ 0x00000D0A, 0xFFFF },   /* R3338  - Interrupt Status 3 Mask */
+	{ 0x00000D0B, 0xFFFF },   /* R3339  - Interrupt Status 4 Mask */
+	{ 0x00000D0C, 0xFEFF },   /* R3340  - Interrupt Status 5 Mask */
+	{ 0x00000D0F, 0x0000 },   /* R3343  - Interrupt Control */
+	{ 0x00000D18, 0xFFFF },   /* R3352  - IRQ2 Status 1 Mask */
+	{ 0x00000D19, 0xFFFF },   /* R3353  - IRQ2 Status 2 Mask */
+	{ 0x00000D1A, 0xFFFF },   /* R3354  - IRQ2 Status 3 Mask */
+	{ 0x00000D1B, 0xFFFF },   /* R3355  - IRQ2 Status 4 Mask */
+	{ 0x00000D1C, 0xFFFF },   /* R3356  - IRQ2 Status 5 Mask */
+	{ 0x00000D1F, 0x0000 },   /* R3359  - IRQ2 Control */
 	{ 0x00000D41, 0x0000 },   /* R3393  - ADSP2 IRQ0 */
-	{ 0x00000D53, 0xFFFF },   /* R3411  - AOD IRQ Mask IRQ1 */ 
-	{ 0x00000D54, 0xFFFF },   /* R3412  - AOD IRQ Mask IRQ2 */ 
-	{ 0x00000D56, 0x0000 },   /* R3414  - Jack detect debounce */ 
-	{ 0x00000E00, 0x0000 },   /* R3584  - FX_Ctrl1 */ 
-	{ 0x00000E10, 0x6318 },   /* R3600  - EQ1_1 */ 
-	{ 0x00000E11, 0x6300 },   /* R3601  - EQ1_2 */ 
-	{ 0x00000E12, 0x0FC8 },   /* R3602  - EQ1_3 */ 
-	{ 0x00000E13, 0x03FE },   /* R3603  - EQ1_4 */ 
-	{ 0x00000E14, 0x00E0 },   /* R3604  - EQ1_5 */ 
-	{ 0x00000E15, 0x1EC4 },   /* R3605  - EQ1_6 */ 
-	{ 0x00000E16, 0xF136 },   /* R3606  - EQ1_7 */ 
-	{ 0x00000E17, 0x0409 },   /* R3607  - EQ1_8 */ 
-	{ 0x00000E18, 0x04CC },   /* R3608  - EQ1_9 */ 
-	{ 0x00000E19, 0x1C9B },   /* R3609  - EQ1_10 */ 
-	{ 0x00000E1A, 0xF337 },   /* R3610  - EQ1_11 */ 
-	{ 0x00000E1B, 0x040B },   /* R3611  - EQ1_12 */ 
-	{ 0x00000E1C, 0x0CBB },   /* R3612  - EQ1_13 */ 
-	{ 0x00000E1D, 0x16F8 },   /* R3613  - EQ1_14 */ 
-	{ 0x00000E1E, 0xF7D9 },   /* R3614  - EQ1_15 */ 
-	{ 0x00000E1F, 0x040A },   /* R3615  - EQ1_16 */ 
-	{ 0x00000E20, 0x1F14 },   /* R3616  - EQ1_17 */ 
-	{ 0x00000E21, 0x058C },   /* R3617  - EQ1_18 */ 
-	{ 0x00000E22, 0x0563 },   /* R3618  - EQ1_19 */ 
-	{ 0x00000E23, 0x4000 },   /* R3619  - EQ1_20 */ 
-	{ 0x00000E24, 0x0B75 },   /* R3620  - EQ1_21 */ 
-	{ 0x00000E26, 0x6318 },   /* R3622  - EQ2_1 */ 
-	{ 0x00000E27, 0x6300 },   /* R3623  - EQ2_2 */ 
-	{ 0x00000E28, 0x0FC8 },   /* R3624  - EQ2_3 */ 
-	{ 0x00000E29, 0x03FE },   /* R3625  - EQ2_4 */ 
-	{ 0x00000E2A, 0x00E0 },   /* R3626  - EQ2_5 */ 
-	{ 0x00000E2B, 0x1EC4 },   /* R3627  - EQ2_6 */ 
-	{ 0x00000E2C, 0xF136 },   /* R3628  - EQ2_7 */ 
-	{ 0x00000E2D, 0x0409 },   /* R3629  - EQ2_8 */ 
-	{ 0x00000E2E, 0x04CC },   /* R3630  - EQ2_9 */ 
-	{ 0x00000E2F, 0x1C9B },   /* R3631  - EQ2_10 */ 
-	{ 0x00000E30, 0xF337 },   /* R3632  - EQ2_11 */ 
-	{ 0x00000E31, 0x040B },   /* R3633  - EQ2_12 */ 
-	{ 0x00000E32, 0x0CBB },   /* R3634  - EQ2_13 */ 
-	{ 0x00000E33, 0x16F8 },   /* R3635  - EQ2_14 */ 
-	{ 0x00000E34, 0xF7D9 },   /* R3636  - EQ2_15 */ 
-	{ 0x00000E35, 0x040A },   /* R3637  - EQ2_16 */ 
-	{ 0x00000E36, 0x1F14 },   /* R3638  - EQ2_17 */ 
-	{ 0x00000E37, 0x058C },   /* R3639  - EQ2_18 */ 
-	{ 0x00000E38, 0x0563 },   /* R3640  - EQ2_19 */ 
-	{ 0x00000E39, 0x4000 },   /* R3641  - EQ2_20 */ 
-	{ 0x00000E3A, 0x0B75 },   /* R3642  - EQ2_21 */ 
-	{ 0x00000E3C, 0x6318 },   /* R3644  - EQ3_1 */ 
-	{ 0x00000E3D, 0x6300 },   /* R3645  - EQ3_2 */ 
-	{ 0x00000E3E, 0x0FC8 },   /* R3646  - EQ3_3 */ 
-	{ 0x00000E3F, 0x03FE },   /* R3647  - EQ3_4 */ 
-	{ 0x00000E40, 0x00E0 },   /* R3648  - EQ3_5 */ 
-	{ 0x00000E41, 0x1EC4 },   /* R3649  - EQ3_6 */ 
-	{ 0x00000E42, 0xF136 },   /* R3650  - EQ3_7 */ 
-	{ 0x00000E43, 0x0409 },   /* R3651  - EQ3_8 */ 
-	{ 0x00000E44, 0x04CC },   /* R3652  - EQ3_9 */ 
-	{ 0x00000E45, 0x1C9B },   /* R3653  - EQ3_10 */ 
-	{ 0x00000E46, 0xF337 },   /* R3654  - EQ3_11 */ 
-	{ 0x00000E47, 0x040B },   /* R3655  - EQ3_12 */ 
-	{ 0x00000E48, 0x0CBB },   /* R3656  - EQ3_13 */ 
-	{ 0x00000E49, 0x16F8 },   /* R3657  - EQ3_14 */ 
-	{ 0x00000E4A, 0xF7D9 },   /* R3658  - EQ3_15 */ 
-	{ 0x00000E4B, 0x040A },   /* R3659  - EQ3_16 */ 
-	{ 0x00000E4C, 0x1F14 },   /* R3660  - EQ3_17 */ 
-	{ 0x00000E4D, 0x058C },   /* R3661  - EQ3_18 */ 
-	{ 0x00000E4E, 0x0563 },   /* R3662  - EQ3_19 */ 
-	{ 0x00000E4F, 0x4000 },   /* R3663  - EQ3_20 */ 
-	{ 0x00000E50, 0x0B75 },   /* R3664  - EQ3_21 */ 
-	{ 0x00000E52, 0x6318 },   /* R3666  - EQ4_1 */ 
-	{ 0x00000E53, 0x6300 },   /* R3667  - EQ4_2 */ 
-	{ 0x00000E54, 0x0FC8 },   /* R3668  - EQ4_3 */ 
-	{ 0x00000E55, 0x03FE },   /* R3669  - EQ4_4 */ 
-	{ 0x00000E56, 0x00E0 },   /* R3670  - EQ4_5 */ 
-	{ 0x00000E57, 0x1EC4 },   /* R3671  - EQ4_6 */ 
-	{ 0x00000E58, 0xF136 },   /* R3672  - EQ4_7 */ 
-	{ 0x00000E59, 0x0409 },   /* R3673  - EQ4_8 */ 
-	{ 0x00000E5A, 0x04CC },   /* R3674  - EQ4_9 */ 
-	{ 0x00000E5B, 0x1C9B },   /* R3675  - EQ4_10 */ 
-	{ 0x00000E5C, 0xF337 },   /* R3676  - EQ4_11 */ 
-	{ 0x00000E5D, 0x040B },   /* R3677  - EQ4_12 */ 
-	{ 0x00000E5E, 0x0CBB },   /* R3678  - EQ4_13 */ 
-	{ 0x00000E5F, 0x16F8 },   /* R3679  - EQ4_14 */ 
-	{ 0x00000E60, 0xF7D9 },   /* R3680  - EQ4_15 */ 
-	{ 0x00000E61, 0x040A },   /* R3681  - EQ4_16 */ 
-	{ 0x00000E62, 0x1F14 },   /* R3682  - EQ4_17 */ 
-	{ 0x00000E63, 0x058C },   /* R3683  - EQ4_18 */ 
-	{ 0x00000E64, 0x0563 },   /* R3684  - EQ4_19 */ 
-	{ 0x00000E65, 0x4000 },   /* R3685  - EQ4_20 */ 
-	{ 0x00000E66, 0x0B75 },   /* R3686  - EQ4_21 */ 
-	{ 0x00000E80, 0x0018 },   /* R3712  - DRC1 ctrl1 */ 
-	{ 0x00000E81, 0x0933 },   /* R3713  - DRC1 ctrl2 */ 
-	{ 0x00000E82, 0x0018 },   /* R3714  - DRC1 ctrl3 */ 
-	{ 0x00000E83, 0x0000 },   /* R3715  - DRC1 ctrl4 */ 
-	{ 0x00000E84, 0x0000 },   /* R3716  - DRC1 ctrl5 */ 
-	{ 0x00000EC0, 0x0000 },   /* R3776  - HPLPF1_1 */ 
-	{ 0x00000EC1, 0x0000 },   /* R3777  - HPLPF1_2 */ 
-	{ 0x00000EC4, 0x0000 },   /* R3780  - HPLPF2_1 */ 
-	{ 0x00000EC5, 0x0000 },   /* R3781  - HPLPF2_2 */ 
-	{ 0x00000EC8, 0x0000 },   /* R3784  - HPLPF3_1 */ 
-	{ 0x00000EC9, 0x0000 },   /* R3785  - HPLPF3_2 */ 
-	{ 0x00000ECC, 0x0000 },   /* R3788  - HPLPF4_1 */ 
-	{ 0x00000ECD, 0x0000 },   /* R3789  - HPLPF4_2 */ 
-	{ 0x00000EE0, 0x0000 },   /* R3808  - ASRC_ENABLE */ 
-	{ 0x00000EE2, 0x0000 },   /* R3810  - ASRC_RATE1 */ 
+	{ 0x00000D53, 0xFFFF },   /* R3411  - AOD IRQ Mask IRQ1 */
+	{ 0x00000D54, 0xFFFF },   /* R3412  - AOD IRQ Mask IRQ2 */
+	{ 0x00000D56, 0x0000 },   /* R3414  - Jack detect debounce */
+	{ 0x00000E00, 0x0000 },   /* R3584  - FX_Ctrl1 */
+	{ 0x00000E10, 0x6318 },   /* R3600  - EQ1_1 */
+	{ 0x00000E11, 0x6300 },   /* R3601  - EQ1_2 */
+	{ 0x00000E12, 0x0FC8 },   /* R3602  - EQ1_3 */
+	{ 0x00000E13, 0x03FE },   /* R3603  - EQ1_4 */
+	{ 0x00000E14, 0x00E0 },   /* R3604  - EQ1_5 */
+	{ 0x00000E15, 0x1EC4 },   /* R3605  - EQ1_6 */
+	{ 0x00000E16, 0xF136 },   /* R3606  - EQ1_7 */
+	{ 0x00000E17, 0x0409 },   /* R3607  - EQ1_8 */
+	{ 0x00000E18, 0x04CC },   /* R3608  - EQ1_9 */
+	{ 0x00000E19, 0x1C9B },   /* R3609  - EQ1_10 */
+	{ 0x00000E1A, 0xF337 },   /* R3610  - EQ1_11 */
+	{ 0x00000E1B, 0x040B },   /* R3611  - EQ1_12 */
+	{ 0x00000E1C, 0x0CBB },   /* R3612  - EQ1_13 */
+	{ 0x00000E1D, 0x16F8 },   /* R3613  - EQ1_14 */
+	{ 0x00000E1E, 0xF7D9 },   /* R3614  - EQ1_15 */
+	{ 0x00000E1F, 0x040A },   /* R3615  - EQ1_16 */
+	{ 0x00000E20, 0x1F14 },   /* R3616  - EQ1_17 */
+	{ 0x00000E21, 0x058C },   /* R3617  - EQ1_18 */
+	{ 0x00000E22, 0x0563 },   /* R3618  - EQ1_19 */
+	{ 0x00000E23, 0x4000 },   /* R3619  - EQ1_20 */
+	{ 0x00000E24, 0x0B75 },   /* R3620  - EQ1_21 */
+	{ 0x00000E26, 0x6318 },   /* R3622  - EQ2_1 */
+	{ 0x00000E27, 0x6300 },   /* R3623  - EQ2_2 */
+	{ 0x00000E28, 0x0FC8 },   /* R3624  - EQ2_3 */
+	{ 0x00000E29, 0x03FE },   /* R3625  - EQ2_4 */
+	{ 0x00000E2A, 0x00E0 },   /* R3626  - EQ2_5 */
+	{ 0x00000E2B, 0x1EC4 },   /* R3627  - EQ2_6 */
+	{ 0x00000E2C, 0xF136 },   /* R3628  - EQ2_7 */
+	{ 0x00000E2D, 0x0409 },   /* R3629  - EQ2_8 */
+	{ 0x00000E2E, 0x04CC },   /* R3630  - EQ2_9 */
+	{ 0x00000E2F, 0x1C9B },   /* R3631  - EQ2_10 */
+	{ 0x00000E30, 0xF337 },   /* R3632  - EQ2_11 */
+	{ 0x00000E31, 0x040B },   /* R3633  - EQ2_12 */
+	{ 0x00000E32, 0x0CBB },   /* R3634  - EQ2_13 */
+	{ 0x00000E33, 0x16F8 },   /* R3635  - EQ2_14 */
+	{ 0x00000E34, 0xF7D9 },   /* R3636  - EQ2_15 */
+	{ 0x00000E35, 0x040A },   /* R3637  - EQ2_16 */
+	{ 0x00000E36, 0x1F14 },   /* R3638  - EQ2_17 */
+	{ 0x00000E37, 0x058C },   /* R3639  - EQ2_18 */
+	{ 0x00000E38, 0x0563 },   /* R3640  - EQ2_19 */
+	{ 0x00000E39, 0x4000 },   /* R3641  - EQ2_20 */
+	{ 0x00000E3A, 0x0B75 },   /* R3642  - EQ2_21 */
+	{ 0x00000E3C, 0x6318 },   /* R3644  - EQ3_1 */
+	{ 0x00000E3D, 0x6300 },   /* R3645  - EQ3_2 */
+	{ 0x00000E3E, 0x0FC8 },   /* R3646  - EQ3_3 */
+	{ 0x00000E3F, 0x03FE },   /* R3647  - EQ3_4 */
+	{ 0x00000E40, 0x00E0 },   /* R3648  - EQ3_5 */
+	{ 0x00000E41, 0x1EC4 },   /* R3649  - EQ3_6 */
+	{ 0x00000E42, 0xF136 },   /* R3650  - EQ3_7 */
+	{ 0x00000E43, 0x0409 },   /* R3651  - EQ3_8 */
+	{ 0x00000E44, 0x04CC },   /* R3652  - EQ3_9 */
+	{ 0x00000E45, 0x1C9B },   /* R3653  - EQ3_10 */
+	{ 0x00000E46, 0xF337 },   /* R3654  - EQ3_11 */
+	{ 0x00000E47, 0x040B },   /* R3655  - EQ3_12 */
+	{ 0x00000E48, 0x0CBB },   /* R3656  - EQ3_13 */
+	{ 0x00000E49, 0x16F8 },   /* R3657  - EQ3_14 */
+	{ 0x00000E4A, 0xF7D9 },   /* R3658  - EQ3_15 */
+	{ 0x00000E4B, 0x040A },   /* R3659  - EQ3_16 */
+	{ 0x00000E4C, 0x1F14 },   /* R3660  - EQ3_17 */
+	{ 0x00000E4D, 0x058C },   /* R3661  - EQ3_18 */
+	{ 0x00000E4E, 0x0563 },   /* R3662  - EQ3_19 */
+	{ 0x00000E4F, 0x4000 },   /* R3663  - EQ3_20 */
+	{ 0x00000E50, 0x0B75 },   /* R3664  - EQ3_21 */
+	{ 0x00000E52, 0x6318 },   /* R3666  - EQ4_1 */
+	{ 0x00000E53, 0x6300 },   /* R3667  - EQ4_2 */
+	{ 0x00000E54, 0x0FC8 },   /* R3668  - EQ4_3 */
+	{ 0x00000E55, 0x03FE },   /* R3669  - EQ4_4 */
+	{ 0x00000E56, 0x00E0 },   /* R3670  - EQ4_5 */
+	{ 0x00000E57, 0x1EC4 },   /* R3671  - EQ4_6 */
+	{ 0x00000E58, 0xF136 },   /* R3672  - EQ4_7 */
+	{ 0x00000E59, 0x0409 },   /* R3673  - EQ4_8 */
+	{ 0x00000E5A, 0x04CC },   /* R3674  - EQ4_9 */
+	{ 0x00000E5B, 0x1C9B },   /* R3675  - EQ4_10 */
+	{ 0x00000E5C, 0xF337 },   /* R3676  - EQ4_11 */
+	{ 0x00000E5D, 0x040B },   /* R3677  - EQ4_12 */
+	{ 0x00000E5E, 0x0CBB },   /* R3678  - EQ4_13 */
+	{ 0x00000E5F, 0x16F8 },   /* R3679  - EQ4_14 */
+	{ 0x00000E60, 0xF7D9 },   /* R3680  - EQ4_15 */
+	{ 0x00000E61, 0x040A },   /* R3681  - EQ4_16 */
+	{ 0x00000E62, 0x1F14 },   /* R3682  - EQ4_17 */
+	{ 0x00000E63, 0x058C },   /* R3683  - EQ4_18 */
+	{ 0x00000E64, 0x0563 },   /* R3684  - EQ4_19 */
+	{ 0x00000E65, 0x4000 },   /* R3685  - EQ4_20 */
+	{ 0x00000E66, 0x0B75 },   /* R3686  - EQ4_21 */
+	{ 0x00000E80, 0x0018 },   /* R3712  - DRC1 ctrl1 */
+	{ 0x00000E81, 0x0933 },   /* R3713  - DRC1 ctrl2 */
+	{ 0x00000E82, 0x0018 },   /* R3714  - DRC1 ctrl3 */
+	{ 0x00000E83, 0x0000 },   /* R3715  - DRC1 ctrl4 */
+	{ 0x00000E84, 0x0000 },   /* R3716  - DRC1 ctrl5 */
+	{ 0x00000EC0, 0x0000 },   /* R3776  - HPLPF1_1 */
+	{ 0x00000EC1, 0x0000 },   /* R3777  - HPLPF1_2 */
+	{ 0x00000EC4, 0x0000 },   /* R3780  - HPLPF2_1 */
+	{ 0x00000EC5, 0x0000 },   /* R3781  - HPLPF2_2 */
+	{ 0x00000EC8, 0x0000 },   /* R3784  - HPLPF3_1 */
+	{ 0x00000EC9, 0x0000 },   /* R3785  - HPLPF3_2 */
+	{ 0x00000ECC, 0x0000 },   /* R3788  - HPLPF4_1 */
+	{ 0x00000ECD, 0x0000 },   /* R3789  - HPLPF4_2 */
+	{ 0x00000EE0, 0x0000 },   /* R3808  - ASRC_ENABLE */
+	{ 0x00000EE2, 0x0000 },   /* R3810  - ASRC_RATE1 */
 	{ 0x00000EE3, 0x4000 },   /* R3811  - ASRC_RATE2 */
-	{ 0x00000EF0, 0x0000 },   /* R3824  - ISRC 1 CTRL 1 */ 
-	{ 0x00000EF1, 0x0000 },   /* R3825  - ISRC 1 CTRL 2 */ 
-	{ 0x00000EF2, 0x0000 },   /* R3826  - ISRC 1 CTRL 3 */ 
-	{ 0x00000EF3, 0x0000 },   /* R3827  - ISRC 2 CTRL 1 */ 
-	{ 0x00000EF4, 0x0000 },   /* R3828  - ISRC 2 CTRL 2 */ 
-	{ 0x00000EF5, 0x0000 },   /* R3829  - ISRC 2 CTRL 3 */ 
-	{ 0x00001100, 0x0010 },   /* R4352  - DSP1 Control 1 */ 
+	{ 0x00000EF0, 0x0000 },   /* R3824  - ISRC 1 CTRL 1 */
+	{ 0x00000EF1, 0x0000 },   /* R3825  - ISRC 1 CTRL 2 */
+	{ 0x00000EF2, 0x0000 },   /* R3826  - ISRC 1 CTRL 3 */
+	{ 0x00000EF3, 0x0000 },   /* R3827  - ISRC 2 CTRL 1 */
+	{ 0x00000EF4, 0x0000 },   /* R3828  - ISRC 2 CTRL 2 */
+	{ 0x00000EF5, 0x0000 },   /* R3829  - ISRC 2 CTRL 3 */
+	{ 0x00001100, 0x0010 },   /* R4352  - DSP1 Control 1 */
 };
 
 static bool wm5102_readable_register(struct device *dev, unsigned int reg)

drivers/mfd/wm8994-core.c

@@ -406,8 +406,7 @@ static int wm8994_device_init(struct wm8994 *wm8994, int irq)
 		goto err;
 	}
 
-	ret = regulator_bulk_enable(wm8994->num_supplies,
-				    wm8994->supplies);
+	ret = regulator_bulk_enable(wm8994->num_supplies, wm8994->supplies);
 	if (ret != 0) {
 		dev_err(wm8994->dev, "Failed to enable supplies: %d\n", ret);
 		goto err_regulator_free;
@@ -612,8 +611,7 @@ static void wm8994_device_exit(struct wm8994 *wm8994)
 {
 	pm_runtime_disable(wm8994->dev);
 	wm8994_irq_exit(wm8994);
-	regulator_bulk_disable(wm8994->num_supplies,
-			       wm8994->supplies);
+	regulator_bulk_disable(wm8994->num_supplies, wm8994->supplies);
 	regulator_bulk_free(wm8994->num_supplies, wm8994->supplies);
 	mfd_remove_devices(wm8994->dev);
 }

drivers/regulator/tps65218-regulator.c

@@ -22,6 +22,7 @@
 #include <linux/err.h>
 #include <linux/platform_device.h>
 #include <linux/of_device.h>
+#include <linux/regmap.h>
 #include <linux/regulator/of_regulator.h>
 #include <linux/regulator/driver.h>
 #include <linux/regulator/machine.h>
@@ -30,10 +31,11 @@
 enum tps65218_regulators { DCDC1, DCDC2, DCDC3, DCDC4,
 			   DCDC5, DCDC6, LDO1, LS3 };
 
-#define TPS65218_REGULATOR(_name, _id, _type, _ops, _n, _vr, _vm, _er, _em, \
-			   _cr, _cm, _lr, _nlr, _delay, _fuv, _sr, _sm)	\
+#define TPS65218_REGULATOR(_name, _of, _id, _type, _ops, _n, _vr, _vm, _er, \
+			   _em, _cr, _cm, _lr, _nlr, _delay, _fuv, _sr, _sm) \
 	{							\
 		.name			= _name,		\
+		.of_match		= _of,			\
 		.id			= _id,			\
 		.ops			= &_ops,		\
 		.n_voltages		= _n,			\
@@ -54,14 +56,6 @@ enum tps65218_regulators { DCDC1, DCDC2, DCDC3, DCDC4,
 		.bypass_mask	= _sm,				\
 	}							\
 
-#define TPS65218_INFO(_id, _nm, _min, _max)	\
-	[_id] = {					\
-		.id		= _id,			\
-		.name		= _nm,			\
-		.min_uV		= _min,			\
-		.max_uV		= _max,			\
-	}
-
 static const struct regulator_linear_range dcdc1_dcdc2_ranges[] = {
 	REGULATOR_LINEAR_RANGE(850000, 0x0, 0x32, 10000),
 	REGULATOR_LINEAR_RANGE(1375000, 0x33, 0x3f, 25000),
@@ -77,36 +71,6 @@ static const struct regulator_linear_range dcdc4_ranges[] = {
 	REGULATOR_LINEAR_RANGE(1600000, 0x10, 0x34, 50000),
 };
 
-static struct tps_info tps65218_pmic_regs[] = {
-	TPS65218_INFO(DCDC1, "DCDC1", 850000, 1675000),
-	TPS65218_INFO(DCDC2, "DCDC2", 850000, 1675000),
-	TPS65218_INFO(DCDC3, "DCDC3", 900000, 3400000),
-	TPS65218_INFO(DCDC4, "DCDC4", 1175000, 3400000),
-	TPS65218_INFO(DCDC5, "DCDC5", 1000000, 1000000),
-	TPS65218_INFO(DCDC6, "DCDC6", 1800000, 1800000),
-	TPS65218_INFO(LDO1, "LDO1", 900000, 3400000),
-	TPS65218_INFO(LS3, "LS3", -1, -1),
-};
-
-#define TPS65218_OF_MATCH(comp, label) \
-	{ \
-		.compatible = comp, \
-		.data = &label, \
-	}
-
-static const struct of_device_id tps65218_of_match[] = {
-	TPS65218_OF_MATCH("ti,tps65218-dcdc1", tps65218_pmic_regs[DCDC1]),
-	TPS65218_OF_MATCH("ti,tps65218-dcdc2", tps65218_pmic_regs[DCDC2]),
-	TPS65218_OF_MATCH("ti,tps65218-dcdc3", tps65218_pmic_regs[DCDC3]),
-	TPS65218_OF_MATCH("ti,tps65218-dcdc4", tps65218_pmic_regs[DCDC4]),
-	TPS65218_OF_MATCH("ti,tps65218-dcdc5", tps65218_pmic_regs[DCDC5]),
-	TPS65218_OF_MATCH("ti,tps65218-dcdc6", tps65218_pmic_regs[DCDC6]),
-	TPS65218_OF_MATCH("ti,tps65218-ldo1", tps65218_pmic_regs[LDO1]),
-	TPS65218_OF_MATCH("ti,tps65218-ls3", tps65218_pmic_regs[LS3]),
-	{ }
-};
-MODULE_DEVICE_TABLE(of, tps65218_of_match);
-
 static int tps65218_pmic_set_voltage_sel(struct regulator_dev *dev,
 					 unsigned selector)
 {
@@ -188,7 +152,7 @@ static int tps65218_pmic_set_suspend_disable(struct regulator_dev *dev)
 	if (rid == TPS65218_DCDC_3 && tps->rev == TPS65218_REV_2_1)
 		return 0;
 
-	if (!tps->info[rid]->strobe) {
+	if (!tps->strobes[rid]) {
 		if (rid == TPS65218_DCDC_3)
 			tps->info[rid]->strobe = 3;
 		else
@@ -197,8 +161,7 @@ static int tps65218_pmic_set_suspend_disable(struct regulator_dev *dev)
 
 	return tps65218_set_bits(tps, dev->desc->bypass_reg,
 				 dev->desc->bypass_mask,
-				 tps->info[rid]->strobe,
-				 TPS65218_PROTECT_L1);
+				 tps->strobes[rid], TPS65218_PROTECT_L1);
 }
 
 /* Operations permitted on DCDC1, DCDC2 */
@@ -272,7 +235,7 @@ static int tps65218_pmic_get_current_limit(struct regulator_dev *dev)
 	unsigned int index;
 	struct tps65218 *tps = rdev_get_drvdata(dev);
 
-	retval = tps65218_reg_read(tps, dev->desc->csel_reg, &index);
+	retval = regmap_read(tps->regmap, dev->desc->csel_reg, &index);
 	if (retval < 0)
 		return retval;
 
@@ -300,104 +263,104 @@ static struct regulator_ops tps65218_dcdc56_pmic_ops = {
 };
 
 static const struct regulator_desc regulators[] = {
-	TPS65218_REGULATOR("DCDC1", TPS65218_DCDC_1, REGULATOR_VOLTAGE,
-			   tps65218_dcdc12_ops, 64, TPS65218_REG_CONTROL_DCDC1,
+	TPS65218_REGULATOR("DCDC1", "regulator-dcdc1", TPS65218_DCDC_1,
+			   REGULATOR_VOLTAGE, tps65218_dcdc12_ops, 64,
+			   TPS65218_REG_CONTROL_DCDC1,
 			   TPS65218_CONTROL_DCDC1_MASK, TPS65218_REG_ENABLE1,
 			   TPS65218_ENABLE1_DC1_EN, 0, 0, dcdc1_dcdc2_ranges,
 			   2, 4000, 0, TPS65218_REG_SEQ3,
 			   TPS65218_SEQ3_DC1_SEQ_MASK),
-	TPS65218_REGULATOR("DCDC2", TPS65218_DCDC_2, REGULATOR_VOLTAGE,
-			   tps65218_dcdc12_ops, 64, TPS65218_REG_CONTROL_DCDC2,
+	TPS65218_REGULATOR("DCDC2", "regulator-dcdc2", TPS65218_DCDC_2,
+			   REGULATOR_VOLTAGE, tps65218_dcdc12_ops, 64,
+			   TPS65218_REG_CONTROL_DCDC2,
 			   TPS65218_CONTROL_DCDC2_MASK, TPS65218_REG_ENABLE1,
 			   TPS65218_ENABLE1_DC2_EN, 0, 0, dcdc1_dcdc2_ranges,
 			   2, 4000, 0, TPS65218_REG_SEQ3,
 			   TPS65218_SEQ3_DC2_SEQ_MASK),
-	TPS65218_REGULATOR("DCDC3", TPS65218_DCDC_3, REGULATOR_VOLTAGE,
-			   tps65218_ldo1_dcdc34_ops, 64,
+	TPS65218_REGULATOR("DCDC3", "regulator-dcdc3", TPS65218_DCDC_3,
+			   REGULATOR_VOLTAGE, tps65218_ldo1_dcdc34_ops, 64,
 			   TPS65218_REG_CONTROL_DCDC3,
 			   TPS65218_CONTROL_DCDC3_MASK, TPS65218_REG_ENABLE1,
 			   TPS65218_ENABLE1_DC3_EN, 0, 0, ldo1_dcdc3_ranges, 2,
 			   0, 0, TPS65218_REG_SEQ4, TPS65218_SEQ4_DC3_SEQ_MASK),
-	TPS65218_REGULATOR("DCDC4", TPS65218_DCDC_4, REGULATOR_VOLTAGE,
-			   tps65218_ldo1_dcdc34_ops, 53,
+	TPS65218_REGULATOR("DCDC4", "regulator-dcdc4", TPS65218_DCDC_4,
+			   REGULATOR_VOLTAGE, tps65218_ldo1_dcdc34_ops, 53,
 			   TPS65218_REG_CONTROL_DCDC4,
 			   TPS65218_CONTROL_DCDC4_MASK, TPS65218_REG_ENABLE1,
 			   TPS65218_ENABLE1_DC4_EN, 0, 0, dcdc4_ranges, 2,
 			   0, 0, TPS65218_REG_SEQ4, TPS65218_SEQ4_DC4_SEQ_MASK),
-	TPS65218_REGULATOR("DCDC5", TPS65218_DCDC_5, REGULATOR_VOLTAGE,
-			   tps65218_dcdc56_pmic_ops, 1, -1, -1,
-			   TPS65218_REG_ENABLE1, TPS65218_ENABLE1_DC5_EN, 0, 0,
-			   NULL, 0, 0, 1000000, TPS65218_REG_SEQ5,
+	TPS65218_REGULATOR("DCDC5", "regulator-dcdc5", TPS65218_DCDC_5,
+			   REGULATOR_VOLTAGE, tps65218_dcdc56_pmic_ops, 1, -1,
+			   -1, TPS65218_REG_ENABLE1, TPS65218_ENABLE1_DC5_EN, 0,
+			   0, NULL, 0, 0, 1000000, TPS65218_REG_SEQ5,
 			   TPS65218_SEQ5_DC5_SEQ_MASK),
-	TPS65218_REGULATOR("DCDC6", TPS65218_DCDC_6, REGULATOR_VOLTAGE,
-			   tps65218_dcdc56_pmic_ops, 1, -1, -1,
-			   TPS65218_REG_ENABLE1, TPS65218_ENABLE1_DC6_EN, 0, 0,
-			   NULL, 0, 0, 1800000, TPS65218_REG_SEQ5,
+	TPS65218_REGULATOR("DCDC6", "regulator-dcdc6", TPS65218_DCDC_6,
+			   REGULATOR_VOLTAGE, tps65218_dcdc56_pmic_ops, 1, -1,
+			   -1, TPS65218_REG_ENABLE1, TPS65218_ENABLE1_DC6_EN, 0,
+			   0, NULL, 0, 0, 1800000, TPS65218_REG_SEQ5,
 			   TPS65218_SEQ5_DC6_SEQ_MASK),
-	TPS65218_REGULATOR("LDO1", TPS65218_LDO_1, REGULATOR_VOLTAGE,
-			   tps65218_ldo1_dcdc34_ops, 64,
+	TPS65218_REGULATOR("LDO1", "regulator-ldo1", TPS65218_LDO_1,
+			   REGULATOR_VOLTAGE, tps65218_ldo1_dcdc34_ops, 64,
 			   TPS65218_REG_CONTROL_LDO1,
 			   TPS65218_CONTROL_LDO1_MASK, TPS65218_REG_ENABLE2,
 			   TPS65218_ENABLE2_LDO1_EN, 0, 0, ldo1_dcdc3_ranges,
 			   2, 0, 0, TPS65218_REG_SEQ6,
 			   TPS65218_SEQ6_LDO1_SEQ_MASK),
-	TPS65218_REGULATOR("LS3", TPS65218_LS_3, REGULATOR_CURRENT,
-			   tps65218_ls3_ops, 0, 0, 0, TPS65218_REG_ENABLE2,
-			   TPS65218_ENABLE2_LS3_EN, TPS65218_REG_CONFIG2,
-			   TPS65218_CONFIG2_LS3ILIM_MASK, NULL, 0, 0, 0, 0, 0),
+	TPS65218_REGULATOR("LS3", "regulator-ls3", TPS65218_LS_3,
+			   REGULATOR_CURRENT, tps65218_ls3_ops, 0, 0, 0,
+			   TPS65218_REG_ENABLE2, TPS65218_ENABLE2_LS3_EN,
+			   TPS65218_REG_CONFIG2, TPS65218_CONFIG2_LS3ILIM_MASK,
+			   NULL, 0, 0, 0, 0, 0),
 };
 
 static int tps65218_regulator_probe(struct platform_device *pdev)
 {
 	struct tps65218 *tps = dev_get_drvdata(pdev->dev.parent);
-	struct regulator_init_data *init_data;
-	const struct tps_info	*template;
 	struct regulator_dev *rdev;
-	const struct of_device_id	*match;
 	struct regulator_config config = { };
-	int id, ret;
+	int i, ret;
 	unsigned int val;
 
-	match = of_match_device(tps65218_of_match, &pdev->dev);
-	if (!match)
-		return -ENODEV;
-
-	template = match->data;
-	id = template->id;
-	init_data = of_get_regulator_init_data(&pdev->dev, pdev->dev.of_node,
-					       &regulators[id]);
-
-	platform_set_drvdata(pdev, tps);
-
-	tps->info[id] = &tps65218_pmic_regs[id];
 	config.dev = &pdev->dev;
-	config.init_data = init_data;
+	config.dev->of_node = tps->dev->of_node;
 	config.driver_data = tps;
 	config.regmap = tps->regmap;
-	config.of_node = pdev->dev.of_node;
 
-	rdev = devm_regulator_register(&pdev->dev, &regulators[id], &config);
-	if (IS_ERR(rdev)) {
-		dev_err(tps->dev, "failed to register %s regulator\n",
-			pdev->name);
-		return PTR_ERR(rdev);
-	}
+	/* Allocate memory for strobes */
+	tps->strobes = devm_kzalloc(&pdev->dev, sizeof(u8) *
+				    TPS65218_NUM_REGULATOR, GFP_KERNEL);
 
-	ret = tps65218_reg_read(tps, regulators[id].bypass_reg, &val);
-	if (ret)
-		return ret;
+	for (i = 0; i < ARRAY_SIZE(regulators); i++) {
+		rdev = devm_regulator_register(&pdev->dev, &regulators[i],
+					       &config);
+		if (IS_ERR(rdev)) {
+			dev_err(tps->dev, "failed to register %s regulator\n",
+				pdev->name);
+			return PTR_ERR(rdev);
+		}
 
-	tps->info[id]->strobe = val & regulators[id].bypass_mask;
+		ret = regmap_read(tps->regmap, regulators[i].bypass_reg, &val);
+		if (ret)
+			return ret;
+
+		tps->strobes[i] = val & regulators[i].bypass_mask;
+	}
 
 	return 0;
 }
 
+static const struct platform_device_id tps65218_regulator_id_table[] = {
+	{ "tps65218-regulator", },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(platform, tps65218_regulator_id_table);
+
 static struct platform_driver tps65218_regulator_driver = {
 	.driver = {
 		.name = "tps65218-pmic",
-		.of_match_table = tps65218_of_match,
 	},
 	.probe = tps65218_regulator_probe,
+	.id_table = tps65218_regulator_id_table,
 };
 
 module_platform_driver(tps65218_regulator_driver);

include/linux/mfd/axp20x.h

@@ -115,6 +115,8 @@ enum {
 #define AXP806_CLDO2_V_CTRL		0x25
 #define AXP806_CLDO3_V_CTRL		0x26
 #define AXP806_VREF_TEMP_WARN_L		0xf3
+#define AXP806_BUS_ADDR_EXT		0xfe
+#define AXP806_REG_ADDR_EXT		0xff
 
 /* Interrupt */
 #define AXP152_IRQ1_EN			0x40
@@ -226,6 +228,10 @@ enum {
 #define AXP20X_OCV_MAX			0xf
 
 /* AXP22X specific registers */
+#define AXP22X_PMIC_ADC_H		0x56
+#define AXP22X_PMIC_ADC_L		0x57
+#define AXP22X_TS_ADC_H			0x58
+#define AXP22X_TS_ADC_L			0x59
 #define AXP22X_BATLOW_THRES1		0xe6
 
 /* AXP288 specific registers */

include/linux/mfd/davinci_voicecodec.h

@@ -28,8 +28,6 @@
 #include <linux/mfd/core.h>
 #include <linux/platform_data/edma.h>
 
-#include <mach/hardware.h>
-
 struct regmap;
 
 /*
@@ -99,8 +97,6 @@ struct davinci_vcif {
 	dma_addr_t dma_rx_addr;
 };
 
-struct davinci_vc;
-
 struct davinci_vc {
 	/* Device data */
 	struct device *dev;

include/linux/mfd/rk808.h

@@ -290,6 +290,7 @@ enum rk818_reg {
 #define SWITCH2_EN	BIT(6)
 #define SWITCH1_EN	BIT(5)
 #define DEV_OFF_RST	BIT(3)
+#define DEV_OFF		BIT(0)
 
 #define VB_LO_ACT		BIT(4)
 #define VB_LO_SEL_3500MV	(7 << 0)

include/linux/mfd/rn5t618.h

@@ -58,10 +58,13 @@
 #define RN5T618_DC3CTL2			0x31
 #define RN5T618_DC4CTL			0x32
 #define RN5T618_DC4CTL2			0x33
+#define RN5T618_DC5CTL			0x34
+#define RN5T618_DC5CTL2			0x35
 #define RN5T618_DC1DAC			0x36
 #define RN5T618_DC2DAC			0x37
 #define RN5T618_DC3DAC			0x38
 #define RN5T618_DC4DAC			0x39
+#define RN5T618_DC5DAC			0x3a
 #define RN5T618_DC1DAC_SLP		0x3b
 #define RN5T618_DC2DAC_SLP		0x3c
 #define RN5T618_DC3DAC_SLP		0x3d
@@ -77,6 +80,11 @@
 #define RN5T618_LDO3DAC			0x4e
 #define RN5T618_LDO4DAC			0x4f
 #define RN5T618_LDO5DAC			0x50
+#define RN5T618_LDO6DAC			0x51
+#define RN5T618_LDO7DAC			0x52
+#define RN5T618_LDO8DAC			0x53
+#define RN5T618_LDO9DAC			0x54
+#define RN5T618_LDO10DAC		0x55
 #define RN5T618_LDORTCDAC		0x56
 #define RN5T618_LDORTC2DAC		0x57
 #define RN5T618_LDO1DAC_SLP		0x58
@@ -231,6 +239,7 @@ enum {
 enum {
 	RN5T567 = 0,
 	RN5T618,
+	RC5T619,
 };
 
 struct rn5t618 {

include/linux/mfd/sun4i-gpadc.h

+/* Header of ADC MFD core driver for sunxi platforms
+ *
+ * Copyright (c) 2016 Quentin Schulz <quentin.schulz@free-electrons.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+
+#ifndef __SUN4I_GPADC__H__
+#define __SUN4I_GPADC__H__
+
+#define SUN4I_GPADC_CTRL0				0x00
+
+#define SUN4I_GPADC_CTRL0_ADC_FIRST_DLY(x)		((GENMASK(7, 0) & (x)) << 24)
+#define SUN4I_GPADC_CTRL0_ADC_FIRST_DLY_MODE		BIT(23)
+#define SUN4I_GPADC_CTRL0_ADC_CLK_SELECT		BIT(22)
+#define SUN4I_GPADC_CTRL0_ADC_CLK_DIVIDER(x)		((GENMASK(1, 0) & (x)) << 20)
+#define SUN4I_GPADC_CTRL0_FS_DIV(x)			((GENMASK(3, 0) & (x)) << 16)
+#define SUN4I_GPADC_CTRL0_T_ACQ(x)			(GENMASK(15, 0) & (x))
+
+#define SUN4I_GPADC_CTRL1				0x04
+
+#define SUN4I_GPADC_CTRL1_STYLUS_UP_DEBOUNCE(x)		((GENMASK(7, 0) & (x)) << 12)
+#define SUN4I_GPADC_CTRL1_STYLUS_UP_DEBOUNCE_EN		BIT(9)
+#define SUN4I_GPADC_CTRL1_TOUCH_PAN_CALI_EN		BIT(6)
+#define SUN4I_GPADC_CTRL1_TP_DUAL_EN			BIT(5)
+#define SUN4I_GPADC_CTRL1_TP_MODE_EN			BIT(4)
+#define SUN4I_GPADC_CTRL1_TP_ADC_SELECT			BIT(3)
+#define SUN4I_GPADC_CTRL1_ADC_CHAN_SELECT(x)		(GENMASK(2, 0) & (x))
+
+/* TP_CTRL1 bits for sun6i SOCs */
+#define SUN6I_GPADC_CTRL1_TOUCH_PAN_CALI_EN		BIT(7)
+#define SUN6I_GPADC_CTRL1_TP_DUAL_EN			BIT(6)
+#define SUN6I_GPADC_CTRL1_TP_MODE_EN			BIT(5)
+#define SUN6I_GPADC_CTRL1_TP_ADC_SELECT			BIT(4)
+#define SUN6I_GPADC_CTRL1_ADC_CHAN_SELECT(x)		(GENMASK(3, 0) & BIT(x))
+
+#define SUN4I_GPADC_CTRL2				0x08
+
+#define SUN4I_GPADC_CTRL2_TP_SENSITIVE_ADJUST(x)	((GENMASK(3, 0) & (x)) << 28)
+#define SUN4I_GPADC_CTRL2_TP_MODE_SELECT(x)		((GENMASK(1, 0) & (x)) << 26)
+#define SUN4I_GPADC_CTRL2_PRE_MEA_EN			BIT(24)
+#define SUN4I_GPADC_CTRL2_PRE_MEA_THRE_CNT(x)		(GENMASK(23, 0) & (x))
+
+#define SUN4I_GPADC_CTRL3				0x0c
+
+#define SUN4I_GPADC_CTRL3_FILTER_EN			BIT(2)
+#define SUN4I_GPADC_CTRL3_FILTER_TYPE(x)		(GENMASK(1, 0) & (x))
+
+#define SUN4I_GPADC_TPR					0x18
+
+#define SUN4I_GPADC_TPR_TEMP_ENABLE			BIT(16)
+#define SUN4I_GPADC_TPR_TEMP_PERIOD(x)			(GENMASK(15, 0) & (x))
+
+#define SUN4I_GPADC_INT_FIFOC				0x10
+
+#define SUN4I_GPADC_INT_FIFOC_TEMP_IRQ_EN		BIT(18)
+#define SUN4I_GPADC_INT_FIFOC_TP_OVERRUN_IRQ_EN		BIT(17)
+#define SUN4I_GPADC_INT_FIFOC_TP_DATA_IRQ_EN		BIT(16)
+#define SUN4I_GPADC_INT_FIFOC_TP_DATA_XY_CHANGE		BIT(13)
+#define SUN4I_GPADC_INT_FIFOC_TP_FIFO_TRIG_LEVEL(x)	((GENMASK(4, 0) & (x)) << 8)
+#define SUN4I_GPADC_INT_FIFOC_TP_DATA_DRQ_EN		BIT(7)
+#define SUN4I_GPADC_INT_FIFOC_TP_FIFO_FLUSH		BIT(4)
+#define SUN4I_GPADC_INT_FIFOC_TP_UP_IRQ_EN		BIT(1)
+#define SUN4I_GPADC_INT_FIFOC_TP_DOWN_IRQ_EN		BIT(0)
+
+#define SUN4I_GPADC_INT_FIFOS				0x14
+
+#define SUN4I_GPADC_INT_FIFOS_TEMP_DATA_PENDING		BIT(18)
+#define SUN4I_GPADC_INT_FIFOS_FIFO_OVERRUN_PENDING	BIT(17)
+#define SUN4I_GPADC_INT_FIFOS_FIFO_DATA_PENDING		BIT(16)
+#define SUN4I_GPADC_INT_FIFOS_TP_IDLE_FLG		BIT(2)
+#define SUN4I_GPADC_INT_FIFOS_TP_UP_PENDING		BIT(1)
+#define SUN4I_GPADC_INT_FIFOS_TP_DOWN_PENDING		BIT(0)
+
+#define SUN4I_GPADC_CDAT				0x1c
+#define SUN4I_GPADC_TEMP_DATA				0x20
+#define SUN4I_GPADC_DATA				0x24
+
+#define SUN4I_GPADC_IRQ_FIFO_DATA			0
+#define SUN4I_GPADC_IRQ_TEMP_DATA			1
+
+/* 10s delay before suspending the IP */
+#define SUN4I_GPADC_AUTOSUSPEND_DELAY			10000
+
+struct sun4i_gpadc_dev {
+	struct device			*dev;
+	struct regmap			*regmap;
+	struct regmap_irq_chip_data	*regmap_irqc;
+	void __iomem			*base;
+};
+
+#endif

include/linux/mfd/tps65217.h

@@ -73,13 +73,15 @@
 #define TPS65217_PPATH_AC_CURRENT_MASK	0x0C
 #define TPS65217_PPATH_USB_CURRENT_MASK	0x03
 
-#define TPS65217_INT_RESERVEDM		BIT(7)
 #define TPS65217_INT_PBM		BIT(6)
 #define TPS65217_INT_ACM		BIT(5)
 #define TPS65217_INT_USBM		BIT(4)
 #define TPS65217_INT_PBI		BIT(2)
 #define TPS65217_INT_ACI		BIT(1)
 #define TPS65217_INT_USBI		BIT(0)
+#define TPS65217_INT_SHIFT		4
+#define TPS65217_INT_MASK		(TPS65217_INT_PBM | TPS65217_INT_ACM | \
+					TPS65217_INT_USBM)
 
 #define TPS65217_CHGCONFIG0_TREG	BIT(7)
 #define TPS65217_CHGCONFIG0_DPPM	BIT(6)

include/linux/mfd/tps65218.h

@@ -282,10 +282,9 @@ struct tps65218 {
 	struct regulator_desc desc[TPS65218_NUM_REGULATOR];
 	struct tps_info *info[TPS65218_NUM_REGULATOR];
 	struct regmap *regmap;
+	u8 *strobes;
 };
 
-int tps65218_reg_read(struct tps65218 *tps, unsigned int reg,
-					unsigned int *val);
 int tps65218_reg_write(struct tps65218 *tps, unsigned int reg,
 			unsigned int val, unsigned int level);
 int tps65218_set_bits(struct tps65218 *tps, unsigned int reg,

include/linux/mfd/tps65912.h

@@ -319,21 +319,7 @@ struct tps65912 {
 	struct regmap_irq_chip_data *irq_data;
 };
 
-static const struct regmap_range tps65912_yes_ranges[] = {
-	regmap_reg_range(TPS65912_INT_STS, TPS65912_GPIO5),
-};
-
-static const struct regmap_access_table tps65912_volatile_table = {
-	.yes_ranges = tps65912_yes_ranges,
-	.n_yes_ranges = ARRAY_SIZE(tps65912_yes_ranges),
-};
-
-static const struct regmap_config tps65912_regmap_config = {
-	.reg_bits = 8,
-	.val_bits = 8,
-	.cache_type = REGCACHE_RBTREE,
-	.volatile_table = &tps65912_volatile_table,
-};
+extern const struct regmap_config tps65912_regmap_config;
 
 int tps65912_device_init(struct tps65912 *tps);
 int tps65912_device_exit(struct tps65912 *tps);