Commit af14e7c2 authored by Alex Deucher's avatar Alex Deucher

drm/amdgpu: add the IP discovery IP versions for HW INFO data

Use the former pad element to store the IP versions from the
IP discovery table.  This allows userspace to get the IP
version from the kernel to better align with hardware IP
versions.

Proposed mesa patch:
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17411/diffs?commit_id=c8a63590dfd0d64e6e6a634dcfed993f135dd075Reviewed-by: default avatarMarek Olšák <marek.olsak@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 041a1109
...@@ -461,6 +461,30 @@ static int amdgpu_hw_ip_info(struct amdgpu_device *adev, ...@@ -461,6 +461,30 @@ static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
result->hw_ip_version_major = adev->ip_blocks[i].version->major; result->hw_ip_version_major = adev->ip_blocks[i].version->major;
result->hw_ip_version_minor = adev->ip_blocks[i].version->minor; result->hw_ip_version_minor = adev->ip_blocks[i].version->minor;
if (adev->asic_type >= CHIP_VEGA10) {
switch (type) {
case AMD_IP_BLOCK_TYPE_GFX:
result->ip_discovery_version = adev->ip_versions[GC_HWIP][0];
break;
case AMD_IP_BLOCK_TYPE_SDMA:
result->ip_discovery_version = adev->ip_versions[SDMA0_HWIP][0];
break;
case AMD_IP_BLOCK_TYPE_UVD:
case AMD_IP_BLOCK_TYPE_VCN:
case AMD_IP_BLOCK_TYPE_JPEG:
result->ip_discovery_version = adev->ip_versions[UVD_HWIP][0];
break;
case AMD_IP_BLOCK_TYPE_VCE:
result->ip_discovery_version = adev->ip_versions[VCE_HWIP][0];
break;
default:
result->ip_discovery_version = 0;
break;
}
} else {
result->ip_discovery_version = 0;
}
result->capabilities_flags = 0; result->capabilities_flags = 0;
result->available_rings = (1 << num_rings) - 1; result->available_rings = (1 << num_rings) - 1;
result->ib_start_alignment = ib_start_alignment; result->ib_start_alignment = ib_start_alignment;
......
...@@ -1097,7 +1097,8 @@ struct drm_amdgpu_info_hw_ip { ...@@ -1097,7 +1097,8 @@ struct drm_amdgpu_info_hw_ip {
__u32 ib_size_alignment; __u32 ib_size_alignment;
/** Bitmask of available rings. Bit 0 means ring 0, etc. */ /** Bitmask of available rings. Bit 0 means ring 0, etc. */
__u32 available_rings; __u32 available_rings;
__u32 _pad; /** version info: bits 23:16 major, 15:8 minor, 7:0 revision */
__u32 ip_discovery_version;
}; };
struct drm_amdgpu_info_num_handles { struct drm_amdgpu_info_num_handles {
......
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