Skip to content

L
linux
Commit b25a51cb authored by Kevin Hilman's avatar Kevin Hilman
Browse files
Options

Merge tag 'tegra-for-3.13-cleanup' of... 

Merge tag 'tegra-for-3.13-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/cleanup

ARM: tegra: cleanup for 3.13

This branch mainly removes dead code and defines that were useful only
when booting using board files. A few other misc cleanups are also
included.

This branch is based on previous pull request
tegra-for-3.13-deps-for-arm-init-time-cleanup.

* tag 'tegra-for-3.13-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  ARM: tegra: fix ARCH_TEGRA_114_SOC select sort order
  ARM: tegra: make tegra_init_fuse() __init
  ARM: tegra: remove much of iomap.h
  ARM: tegra: move resume vector define to irammap.h
  ARM: tegra: delete gpio-names.h
  ARM: tegra: delete stale header content
  ARM: tegra: remove common.c
Signed-off-by: default avatarKevin Hilman <khilman@linaro.org>
parents 751bfe3e b6bda4e0
Show whitespace changes
Inline Side-by-side
Showing with 99 additions and 569 deletions
arch/arm/mach-tegra/Kconfig
View file @ b25a51cb
......@@ -51,9 +51,9 @@ config ARCH_TEGRA_3x_SOC
config ARCH_TEGRA_114_SOC
bool "Enable support for Tegra114 family"
select HAVE_ARM_ARCH_TIMER
select ARM_ERRATA_798181
select ARM_L1_CACHE_SHIFT_6
select HAVE_ARM_ARCH_TIMER
select PINCTRL_TEGRA114
help
Support for NVIDIA Tegra T114 processor family, based on the
......
arch/arm/mach-tegra/Makefile
View file @ b25a51cb
asflags-y += -march=armv7-a
obj-y += common.o
obj-y += io.o
obj-y += irq.o
obj-y += fuse.o
......
arch/arm/mach-tegra/board-paz00.c
View file @ b25a51cb
......@@ -20,12 +20,11 @@
#include <linux/platform_device.h>
#include <linux/rfkill-gpio.h>
#include "board.h"
#include "board-paz00.h"
static struct rfkill_gpio_platform_data wifi_rfkill_platform_data = {
.name = "wifi_rfkill",
.reset_gpio = TEGRA_WIFI_RST,
.shutdown_gpio = TEGRA_WIFI_PWRN,
.reset_gpio = 25, /* PD1 */
.shutdown_gpio = 85, /* PK5 */
.type = RFKILL_TYPE_WLAN,
};
......
arch/arm/mach-tegra/board-paz00.h deleted 100644 → 0
View file @ 751bfe3e
/*
* arch/arm/mach-tegra/board-paz00.h
*
* Copyright (C) 2010 Marc Dietrich <marvin24@gmx.de>
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef _MACH_TEGRA_BOARD_PAZ00_H
#define _MACH_TEGRA_BOARD_PAZ00_H
#include "gpio-names.h"
#define TEGRA_WIFI_PWRN TEGRA_GPIO_PK5
#define TEGRA_WIFI_RST TEGRA_GPIO_PD1
#endif
arch/arm/mach-tegra/board.h
View file @ b25a51cb
......@@ -25,20 +25,8 @@
#include <linux/types.h>
#include <linux/reboot.h>
void tegra_assert_system_reset(enum reboot_mode mode, const char *cmd);
void __init tegra_init_early(void);
void __init tegra_map_common_io(void);
void __init tegra_init_irq(void);
void __init tegra_dt_init_irq(void);
void tegra_init_late(void);
#ifdef CONFIG_DEBUG_FS
int tegra_clk_debugfs_init(void);
#else
static inline int tegra_clk_debugfs_init(void) { return 0; }
#endif
int __init tegra_powergate_init(void);
#if defined(CONFIG_ARCH_TEGRA_2x_SOC) && defined(CONFIG_DEBUG_FS)
......
arch/arm/mach-tegra/common.c deleted 100644 → 0
View file @ 751bfe3e
/*
* arch/arm/mach-tegra/common.c
*
* Copyright (c) 2013 NVIDIA Corporation. All rights reserved.
* Copyright (C) 2010 Google, Inc.
*
* Author:
* Colin Cross <ccross@android.com>
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <linux/init.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/reboot.h>
#include <linux/irqchip.h>
#include <asm/hardware/cache-l2x0.h>
#include "board.h"
#include "common.h"
#include "cpuidle.h"
#include "fuse.h"
#include "iomap.h"
#include "irq.h"
#include "pmc.h"
#include "apbio.h"
#include "sleep.h"
#include "pm.h"
#include "reset.h"
/*
* Storage for debug-macro.S's state.
*
* This must be in .data not .bss so that it gets initialized each time the
* kernel is loaded. The data is declared here rather than debug-macro.S so
* that multiple inclusions of debug-macro.S point at the same data.
*/
u32 tegra_uart_config[4] = {
/* Debug UART initialization required */
1,
/* Debug UART physical address */
0,
/* Debug UART virtual address */
0,
/* Scratch space for debug macro */
0,
};
#ifdef CONFIG_OF
void __init tegra_dt_init_irq(void)
{
tegra_pmc_init_irq();
tegra_init_irq();
irqchip_init();
tegra_legacy_irq_syscore_init();
}
#endif
void tegra_assert_system_reset(enum reboot_mode mode, const char *cmd)
{
void __iomem *reset = IO_ADDRESS(TEGRA_PMC_BASE + 0);
u32 reg;
reg = readl_relaxed(reset);
reg |= 0x10;
writel_relaxed(reg, reset);
}
static void __init tegra_init_cache(void)
{
#ifdef CONFIG_CACHE_L2X0
int ret;
void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
u32 aux_ctrl, cache_type;
cache_type = readl(p + L2X0_CACHE_TYPE);
aux_ctrl = (cache_type & 0x700) << (17-8);
aux_ctrl |= 0x7C400001;
ret = l2x0_of_init(aux_ctrl, 0x8200c3fe);
if (!ret)
l2x0_saved_regs_addr = virt_to_phys(&l2x0_saved_regs);
#endif
}
void __init tegra_init_early(void)
{
tegra_cpu_reset_handler_init();
tegra_apb_io_init();
tegra_init_fuse();
tegra_init_cache();
tegra_powergate_init();
tegra_hotplug_init();
}
void __init tegra_init_late(void)
{
tegra_init_suspend();
tegra_cpuidle_init();
tegra_powergate_debugfs_init();
}
arch/arm/mach-tegra/fuse.c
View file @ b25a51cb
......@@ -112,7 +112,7 @@ u32 tegra_read_chipid(void)
return readl_relaxed(IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804);
}
void tegra_init_fuse(void)
void __init tegra_init_fuse(void)
{
u32 id;
......
arch/arm/mach-tegra/gpio-names.h deleted 100644 → 0
View file @ 751bfe3e
/*
* arch/arm/mach-tegra/include/mach/gpio-names.h
*
* Copyright (c) 2010 Google, Inc
*
* Author:
* Erik Gilling <konkers@google.com>
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __MACH_TEGRA_GPIO_NAMES_H
#define __MACH_TEGRA_GPIO_NAMES_H
#define TEGRA_GPIO_PA0 0
#define TEGRA_GPIO_PA1 1
#define TEGRA_GPIO_PA2 2
#define TEGRA_GPIO_PA3 3
#define TEGRA_GPIO_PA4 4
#define TEGRA_GPIO_PA5 5
#define TEGRA_GPIO_PA6 6
#define TEGRA_GPIO_PA7 7
#define TEGRA_GPIO_PB0 8
#define TEGRA_GPIO_PB1 9
#define TEGRA_GPIO_PB2 10
#define TEGRA_GPIO_PB3 11
#define TEGRA_GPIO_PB4 12
#define TEGRA_GPIO_PB5 13
#define TEGRA_GPIO_PB6 14
#define TEGRA_GPIO_PB7 15
#define TEGRA_GPIO_PC0 16
#define TEGRA_GPIO_PC1 17
#define TEGRA_GPIO_PC2 18
#define TEGRA_GPIO_PC3 19
#define TEGRA_GPIO_PC4 20
#define TEGRA_GPIO_PC5 21
#define TEGRA_GPIO_PC6 22
#define TEGRA_GPIO_PC7 23
#define TEGRA_GPIO_PD0 24
#define TEGRA_GPIO_PD1 25
#define TEGRA_GPIO_PD2 26
#define TEGRA_GPIO_PD3 27
#define TEGRA_GPIO_PD4 28
#define TEGRA_GPIO_PD5 29
#define TEGRA_GPIO_PD6 30
#define TEGRA_GPIO_PD7 31
#define TEGRA_GPIO_PE0 32
#define TEGRA_GPIO_PE1 33
#define TEGRA_GPIO_PE2 34
#define TEGRA_GPIO_PE3 35
#define TEGRA_GPIO_PE4 36
#define TEGRA_GPIO_PE5 37
#define TEGRA_GPIO_PE6 38
#define TEGRA_GPIO_PE7 39
#define TEGRA_GPIO_PF0 40
#define TEGRA_GPIO_PF1 41
#define TEGRA_GPIO_PF2 42
#define TEGRA_GPIO_PF3 43
#define TEGRA_GPIO_PF4 44
#define TEGRA_GPIO_PF5 45
#define TEGRA_GPIO_PF6 46
#define TEGRA_GPIO_PF7 47
#define TEGRA_GPIO_PG0 48
#define TEGRA_GPIO_PG1 49
#define TEGRA_GPIO_PG2 50
#define TEGRA_GPIO_PG3 51
#define TEGRA_GPIO_PG4 52
#define TEGRA_GPIO_PG5 53
#define TEGRA_GPIO_PG6 54
#define TEGRA_GPIO_PG7 55
#define TEGRA_GPIO_PH0 56
#define TEGRA_GPIO_PH1 57
#define TEGRA_GPIO_PH2 58
#define TEGRA_GPIO_PH3 59
#define TEGRA_GPIO_PH4 60
#define TEGRA_GPIO_PH5 61
#define TEGRA_GPIO_PH6 62
#define TEGRA_GPIO_PH7 63
#define TEGRA_GPIO_PI0 64
#define TEGRA_GPIO_PI1 65
#define TEGRA_GPIO_PI2 66
#define TEGRA_GPIO_PI3 67
#define TEGRA_GPIO_PI4 68
#define TEGRA_GPIO_PI5 69
#define TEGRA_GPIO_PI6 70
#define TEGRA_GPIO_PI7 71
#define TEGRA_GPIO_PJ0 72
#define TEGRA_GPIO_PJ1 73
#define TEGRA_GPIO_PJ2 74
#define TEGRA_GPIO_PJ3 75
#define TEGRA_GPIO_PJ4 76
#define TEGRA_GPIO_PJ5 77
#define TEGRA_GPIO_PJ6 78
#define TEGRA_GPIO_PJ7 79
#define TEGRA_GPIO_PK0 80
#define TEGRA_GPIO_PK1 81
#define TEGRA_GPIO_PK2 82
#define TEGRA_GPIO_PK3 83
#define TEGRA_GPIO_PK4 84
#define TEGRA_GPIO_PK5 85
#define TEGRA_GPIO_PK6 86
#define TEGRA_GPIO_PK7 87
#define TEGRA_GPIO_PL0 88
#define TEGRA_GPIO_PL1 89
#define TEGRA_GPIO_PL2 90
#define TEGRA_GPIO_PL3 91
#define TEGRA_GPIO_PL4 92
#define TEGRA_GPIO_PL5 93
#define TEGRA_GPIO_PL6 94
#define TEGRA_GPIO_PL7 95
#define TEGRA_GPIO_PM0 96
#define TEGRA_GPIO_PM1 97
#define TEGRA_GPIO_PM2 98
#define TEGRA_GPIO_PM3 99
#define TEGRA_GPIO_PM4 100
#define TEGRA_GPIO_PM5 101
#define TEGRA_GPIO_PM6 102
#define TEGRA_GPIO_PM7 103
#define TEGRA_GPIO_PN0 104
#define TEGRA_GPIO_PN1 105
#define TEGRA_GPIO_PN2 106
#define TEGRA_GPIO_PN3 107
#define TEGRA_GPIO_PN4 108
#define TEGRA_GPIO_PN5 109
#define TEGRA_GPIO_PN6 110
#define TEGRA_GPIO_PN7 111
#define TEGRA_GPIO_PO0 112
#define TEGRA_GPIO_PO1 113
#define TEGRA_GPIO_PO2 114
#define TEGRA_GPIO_PO3 115
#define TEGRA_GPIO_PO4 116
#define TEGRA_GPIO_PO5 117
#define TEGRA_GPIO_PO6 118
#define TEGRA_GPIO_PO7 119
#define TEGRA_GPIO_PP0 120
#define TEGRA_GPIO_PP1 121
#define TEGRA_GPIO_PP2 122
#define TEGRA_GPIO_PP3 123
#define TEGRA_GPIO_PP4 124
#define TEGRA_GPIO_PP5 125
#define TEGRA_GPIO_PP6 126
#define TEGRA_GPIO_PP7 127
#define TEGRA_GPIO_PQ0 128
#define TEGRA_GPIO_PQ1 129
#define TEGRA_GPIO_PQ2 130
#define TEGRA_GPIO_PQ3 131
#define TEGRA_GPIO_PQ4 132
#define TEGRA_GPIO_PQ5 133
#define TEGRA_GPIO_PQ6 134
#define TEGRA_GPIO_PQ7 135
#define TEGRA_GPIO_PR0 136
#define TEGRA_GPIO_PR1 137
#define TEGRA_GPIO_PR2 138
#define TEGRA_GPIO_PR3 139
#define TEGRA_GPIO_PR4 140
#define TEGRA_GPIO_PR5 141
#define TEGRA_GPIO_PR6 142
#define TEGRA_GPIO_PR7 143
#define TEGRA_GPIO_PS0 144
#define TEGRA_GPIO_PS1 145
#define TEGRA_GPIO_PS2 146
#define TEGRA_GPIO_PS3 147
#define TEGRA_GPIO_PS4 148
#define TEGRA_GPIO_PS5 149
#define TEGRA_GPIO_PS6 150
#define TEGRA_GPIO_PS7 151
#define TEGRA_GPIO_PT0 152
#define TEGRA_GPIO_PT1 153
#define TEGRA_GPIO_PT2 154
#define TEGRA_GPIO_PT3 155
#define TEGRA_GPIO_PT4 156
#define TEGRA_GPIO_PT5 157
#define TEGRA_GPIO_PT6 158
#define TEGRA_GPIO_PT7 159
#define TEGRA_GPIO_PU0 160
#define TEGRA_GPIO_PU1 161
#define TEGRA_GPIO_PU2 162
#define TEGRA_GPIO_PU3 163
#define TEGRA_GPIO_PU4 164
#define TEGRA_GPIO_PU5 165
#define TEGRA_GPIO_PU6 166
#define TEGRA_GPIO_PU7 167
#define TEGRA_GPIO_PV0 168
#define TEGRA_GPIO_PV1 169
#define TEGRA_GPIO_PV2 170
#define TEGRA_GPIO_PV3 171
#define TEGRA_GPIO_PV4 172
#define TEGRA_GPIO_PV5 173
#define TEGRA_GPIO_PV6 174
#define TEGRA_GPIO_PV7 175
#define TEGRA_GPIO_PW0 176
#define TEGRA_GPIO_PW1 177
#define TEGRA_GPIO_PW2 178
#define TEGRA_GPIO_PW3 179
#define TEGRA_GPIO_PW4 180
#define TEGRA_GPIO_PW5 181
#define TEGRA_GPIO_PW6 182
#define TEGRA_GPIO_PW7 183
#define TEGRA_GPIO_PX0 184
#define TEGRA_GPIO_PX1 185
#define TEGRA_GPIO_PX2 186
#define TEGRA_GPIO_PX3 187
#define TEGRA_GPIO_PX4 188
#define TEGRA_GPIO_PX5 189
#define TEGRA_GPIO_PX6 190
#define TEGRA_GPIO_PX7 191
#define TEGRA_GPIO_PY0 192
#define TEGRA_GPIO_PY1 193
#define TEGRA_GPIO_PY2 194
#define TEGRA_GPIO_PY3 195
#define TEGRA_GPIO_PY4 196
#define TEGRA_GPIO_PY5 197
#define TEGRA_GPIO_PY6 198
#define TEGRA_GPIO_PY7 199
#define TEGRA_GPIO_PZ0 200
#define TEGRA_GPIO_PZ1 201
#define TEGRA_GPIO_PZ2 202
#define TEGRA_GPIO_PZ3 203
#define TEGRA_GPIO_PZ4 204
#define TEGRA_GPIO_PZ5 205
#define TEGRA_GPIO_PZ6 206
#define TEGRA_GPIO_PZ7 207
#define TEGRA_GPIO_PAA0 208
#define TEGRA_GPIO_PAA1 209
#define TEGRA_GPIO_PAA2 210
#define TEGRA_GPIO_PAA3 211
#define TEGRA_GPIO_PAA4 212
#define TEGRA_GPIO_PAA5 213
#define TEGRA_GPIO_PAA6 214
#define TEGRA_GPIO_PAA7 215
#define TEGRA_GPIO_PBB0 216
#define TEGRA_GPIO_PBB1 217
#define TEGRA_GPIO_PBB2 218
#define TEGRA_GPIO_PBB3 219
#define TEGRA_GPIO_PBB4 220
#define TEGRA_GPIO_PBB5 221
#define TEGRA_GPIO_PBB6 222
#define TEGRA_GPIO_PBB7 223
#endif
arch/arm/mach-tegra/iomap.h
View file @ b25a51cb
......@@ -24,44 +24,12 @@
#define TEGRA_IRAM_BASE 0x40000000
#define TEGRA_IRAM_SIZE SZ_256K
#define TEGRA_IRAM_CODE_AREA (TEGRA_IRAM_BASE + SZ_4K)
#define TEGRA_HOST1X_BASE 0x50000000
#define TEGRA_HOST1X_SIZE 0x24000
#define TEGRA_ARM_PERIF_BASE 0x50040000
#define TEGRA_ARM_PERIF_SIZE SZ_8K
#define TEGRA_ARM_PL310_BASE 0x50043000
#define TEGRA_ARM_PL310_SIZE SZ_4K
#define TEGRA_ARM_INT_DIST_BASE 0x50041000
#define TEGRA_ARM_INT_DIST_SIZE SZ_4K
#define TEGRA_MPE_BASE 0x54040000
#define TEGRA_MPE_SIZE SZ_256K
#define TEGRA_VI_BASE 0x54080000
#define TEGRA_VI_SIZE SZ_256K
#define TEGRA_ISP_BASE 0x54100000
#define TEGRA_ISP_SIZE SZ_256K
#define TEGRA_DISPLAY_BASE 0x54200000
#define TEGRA_DISPLAY_SIZE SZ_256K
#define TEGRA_DISPLAY2_BASE 0x54240000
#define TEGRA_DISPLAY2_SIZE SZ_256K
#define TEGRA_HDMI_BASE 0x54280000
#define TEGRA_HDMI_SIZE SZ_256K
#define TEGRA_GART_BASE 0x58000000
#define TEGRA_GART_SIZE SZ_32M
#define TEGRA_RES_SEMA_BASE 0x60001000
#define TEGRA_RES_SEMA_SIZE SZ_4K
#define TEGRA_PRIMARY_ICTLR_BASE 0x60004000
#define TEGRA_PRIMARY_ICTLR_SIZE SZ_64
......@@ -98,51 +66,15 @@
#define TEGRA_FLOW_CTRL_BASE 0x60007000
#define TEGRA_FLOW_CTRL_SIZE 20
#define TEGRA_AHB_DMA_BASE 0x60008000
#define TEGRA_AHB_DMA_SIZE SZ_4K
#define TEGRA_AHB_DMA_CH0_BASE 0x60009000
#define TEGRA_AHB_DMA_CH0_SIZE 32
#define TEGRA_APB_DMA_BASE 0x6000A000
#define TEGRA_APB_DMA_SIZE SZ_4K
#define TEGRA_APB_DMA_CH0_BASE 0x6000B000
#define TEGRA_APB_DMA_CH0_SIZE 32
#define TEGRA_AHB_GIZMO_BASE 0x6000C004
#define TEGRA_AHB_GIZMO_SIZE 0x10C
#define TEGRA_SB_BASE 0x6000C200
#define TEGRA_SB_SIZE 256
#define TEGRA_STATMON_BASE 0x6000C400
#define TEGRA_STATMON_SIZE SZ_1K
#define TEGRA_GPIO_BASE 0x6000D000
#define TEGRA_GPIO_SIZE SZ_4K
#define TEGRA_EXCEPTION_VECTORS_BASE 0x6000F000
#define TEGRA_EXCEPTION_VECTORS_SIZE SZ_4K
#define TEGRA_APB_MISC_BASE 0x70000000
#define TEGRA_APB_MISC_SIZE SZ_4K
#define TEGRA_APB_MISC_DAS_BASE 0x70000c00
#define TEGRA_APB_MISC_DAS_SIZE SZ_128
#define TEGRA_AC97_BASE 0x70002000
#define TEGRA_AC97_SIZE SZ_512
#define TEGRA_SPDIF_BASE 0x70002400
#define TEGRA_SPDIF_SIZE SZ_512
#define TEGRA_I2S1_BASE 0x70002800
#define TEGRA_I2S1_SIZE SZ_256
#define TEGRA_I2S2_BASE 0x70002A00
#define TEGRA_I2S2_SIZE SZ_256
#define TEGRA_UARTA_BASE 0x70006000
#define TEGRA_UARTA_SIZE SZ_64
......@@ -158,87 +90,15 @@
#define TEGRA_UARTE_BASE 0x70006400
#define TEGRA_UARTE_SIZE SZ_256
#define TEGRA_NAND_BASE 0x70008000
#define TEGRA_NAND_SIZE SZ_256
#define TEGRA_HSMMC_BASE 0x70008500
#define TEGRA_HSMMC_SIZE SZ_256
#define TEGRA_SNOR_BASE 0x70009000
#define TEGRA_SNOR_SIZE SZ_4K
#define TEGRA_PWFM_BASE 0x7000A000
#define TEGRA_PWFM_SIZE SZ_256
#define TEGRA_PWFM0_BASE 0x7000A000
#define TEGRA_PWFM0_SIZE 4
#define TEGRA_PWFM1_BASE 0x7000A010
#define TEGRA_PWFM1_SIZE 4
#define TEGRA_PWFM2_BASE 0x7000A020
#define TEGRA_PWFM2_SIZE 4
#define TEGRA_PWFM3_BASE 0x7000A030
#define TEGRA_PWFM3_SIZE 4
#define TEGRA_MIPI_BASE 0x7000B000
#define TEGRA_MIPI_SIZE SZ_256
#define TEGRA_I2C_BASE 0x7000C000
#define TEGRA_I2C_SIZE SZ_256
#define TEGRA_TWC_BASE 0x7000C100
#define TEGRA_TWC_SIZE SZ_256
#define TEGRA_SPI_BASE 0x7000C380
#define TEGRA_SPI_SIZE 48
#define TEGRA_I2C2_BASE 0x7000C400
#define TEGRA_I2C2_SIZE SZ_256
#define TEGRA_I2C3_BASE 0x7000C500
#define TEGRA_I2C3_SIZE SZ_256
#define TEGRA_OWR_BASE 0x7000C600
#define TEGRA_OWR_SIZE 80
#define TEGRA_DVC_BASE 0x7000D000
#define TEGRA_DVC_SIZE SZ_512
#define TEGRA_SPI1_BASE 0x7000D400
#define TEGRA_SPI1_SIZE SZ_512
#define TEGRA_SPI2_BASE 0x7000D600
#define TEGRA_SPI2_SIZE SZ_512
#define TEGRA_SPI3_BASE 0x7000D800
#define TEGRA_SPI3_SIZE SZ_512
#define TEGRA_SPI4_BASE 0x7000DA00
#define TEGRA_SPI4_SIZE SZ_512
#define TEGRA_RTC_BASE 0x7000E000
#define TEGRA_RTC_SIZE SZ_256
#define TEGRA_KBC_BASE 0x7000E200
#define TEGRA_KBC_SIZE SZ_256
#define TEGRA_PMC_BASE 0x7000E400
#define TEGRA_PMC_SIZE SZ_256
#define TEGRA_MC_BASE 0x7000F000
#define TEGRA_MC_SIZE SZ_1K
#define TEGRA_EMC_BASE 0x7000F400
#define TEGRA_EMC_SIZE SZ_1K
#define TEGRA_FUSE_BASE 0x7000F800
#define TEGRA_FUSE_SIZE SZ_1K
#define TEGRA_KFUSE_BASE 0x7000FC00
#define TEGRA_KFUSE_SIZE SZ_1K
#define TEGRA_EMC0_BASE 0x7001A000
#define TEGRA_EMC0_SIZE SZ_2K
......@@ -248,18 +108,6 @@
#define TEGRA_CSITE_BASE 0x70040000
#define TEGRA_CSITE_SIZE SZ_256K
#define TEGRA_SDMMC1_BASE 0xC8000000
#define TEGRA_SDMMC1_SIZE SZ_512
#define TEGRA_SDMMC2_BASE 0xC8000200
#define TEGRA_SDMMC2_SIZE SZ_512
#define TEGRA_SDMMC3_BASE 0xC8000400
#define TEGRA_SDMMC3_SIZE SZ_512
#define TEGRA_SDMMC4_BASE 0xC8000600
#define TEGRA_SDMMC4_SIZE SZ_512
/* On TEGRA, many peripherals are very closely packed in
* two 256MB io windows (that actually only use about 64KB
* at the start of each).
......
arch/arm/mach-tegra/irammap.h
View file @ b25a51cb
......@@ -23,4 +23,10 @@
#define TEGRA_IRAM_RESET_HANDLER_OFFSET 0
#define TEGRA_IRAM_RESET_HANDLER_SIZE SZ_1K
/*
* This area is used for LPx resume vector, only while LPx power state is
* active. At other times, the AVP may use this area for arbitrary purposes
*/
#define TEGRA_IRAM_LPx_RESUME_AREA (TEGRA_IRAM_BASE + SZ_4K)
#endif
arch/arm/mach-tegra/pm.c
View file @ b25a51cb
......@@ -263,10 +263,10 @@ static void tegra_suspend_enter_lp1(void)
tegra_pmc_suspend();
/* copy the reset vector & SDRAM shutdown code into IRAM */
memcpy(iram_save_addr, IO_ADDRESS(TEGRA_IRAM_CODE_AREA),
iram_save_size);
memcpy(IO_ADDRESS(TEGRA_IRAM_CODE_AREA), tegra_lp1_iram.start_addr,
memcpy(iram_save_addr, IO_ADDRESS(TEGRA_IRAM_LPx_RESUME_AREA),
iram_save_size);
memcpy(IO_ADDRESS(TEGRA_IRAM_LPx_RESUME_AREA),
tegra_lp1_iram.start_addr, iram_save_size);
*((u32 *)tegra_cpu_lp1_mask) = 1;
}
......@@ -276,7 +276,7 @@ static void tegra_suspend_exit_lp1(void)
tegra_pmc_resume();
/* restore IRAM */
memcpy(IO_ADDRESS(TEGRA_IRAM_CODE_AREA), iram_save_addr,
memcpy(IO_ADDRESS(TEGRA_IRAM_LPx_RESUME_AREA), iram_save_addr,
iram_save_size);
*(u32 *)tegra_cpu_lp1_mask = 0;
......
arch/arm/mach-tegra/pm.h
View file @ b25a51cb
......@@ -37,9 +37,6 @@ void tegra30_sleep_core_init(void);
extern unsigned long l2x0_saved_regs_addr;
void save_cpu_arch_register(void);
void restore_cpu_arch_register(void);
void tegra_clear_cpu_in_lp2(void);
bool tegra_set_cpu_in_lp2(void);
......
arch/arm/mach-tegra/pmc.c
View file @ b25a51cb
......@@ -166,6 +166,15 @@ int tegra_pmc_cpu_remove_clamping(int cpuid)
return tegra_pmc_powergate_remove_clamping(id);
}
void tegra_pmc_restart(enum reboot_mode mode, const char *cmd)
{
u32 val;
val = tegra_pmc_readl(0);
val |= 0x10;
tegra_pmc_writel(val, 0);
}
#ifdef CONFIG_PM_SLEEP
static void set_power_timers(u32 us_on, u32 us_off, unsigned long rate)
{
......
arch/arm/mach-tegra/pmc.h
View file @ b25a51cb
......@@ -18,6 +18,8 @@
#ifndef __MACH_TEGRA_PMC_H
#define __MACH_TEGRA_PMC_H
#include <linux/reboot.h>
enum tegra_suspend_mode {
TEGRA_SUSPEND_NONE = 0,
TEGRA_SUSPEND_LP2, /* CPU voltage off */
......@@ -39,6 +41,8 @@ bool tegra_pmc_cpu_is_powered(int cpuid);
int tegra_pmc_cpu_power_on(int cpuid);
int tegra_pmc_cpu_remove_clamping(int cpuid);
void tegra_pmc_restart(enum reboot_mode mode, const char *cmd);
void tegra_pmc_init_irq(void);
void tegra_pmc_init(void);
......
arch/arm/mach-tegra/reset.c
View file @ b25a51cb
......@@ -82,7 +82,7 @@ void __init tegra_cpu_reset_handler_init(void)
#ifdef CONFIG_PM_SLEEP
__tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_LP1] =
TEGRA_IRAM_CODE_AREA;
TEGRA_IRAM_LPx_RESUME_AREA;
__tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_LP2] =
virt_to_phys((void *)tegra_resume);
#endif
......
arch/arm/mach-tegra/sleep-tegra20.S
View file @ b25a51cb
......@@ -25,6 +25,7 @@
#include <asm/cp15.h>
#include <asm/cache.h>
#include "irammap.h"
#include "sleep.h"
#include "flowctrl.h"
......@@ -235,7 +236,7 @@ ENTRY(tegra20_sleep_core_finish)
mov32 r0, tegra20_tear_down_core
mov32 r1, tegra20_iram_start
sub r0, r0, r1
mov32 r1, TEGRA_IRAM_CODE_AREA
mov32 r1, TEGRA_IRAM_LPx_RESUME_AREA
add r0, r0, r1
mov pc, r3
......@@ -328,7 +329,7 @@ tegra20_iram_start:
* The physical address of tegra_resume expected to be stored in
* PMC_SCRATCH41.
*
* NOTE: THIS *MUST* BE RELOCATED TO TEGRA_IRAM_CODE_AREA.
* NOTE: THIS *MUST* BE RELOCATED TO TEGRA_IRAM_LPx_RESUME_AREA.
*/
ENTRY(tegra20_lp1_reset)
/*
......
arch/arm/mach-tegra/sleep-tegra30.S
View file @ b25a51cb
......@@ -20,6 +20,7 @@
#include <asm/asm-offsets.h>
#include <asm/cache.h>
#include "irammap.h"
#include "fuse.h"
#include "sleep.h"
#include "flowctrl.h"
......@@ -262,7 +263,7 @@ ENTRY(tegra30_sleep_core_finish)
mov32 r0, tegra30_tear_down_core
mov32 r1, tegra30_iram_start
sub r0, r0, r1
mov32 r1, TEGRA_IRAM_CODE_AREA
mov32 r1, TEGRA_IRAM_LPx_RESUME_AREA
add r0, r0, r1
mov pc, r3
......@@ -314,7 +315,7 @@ tegra30_iram_start:
* The physical address of tegra_resume expected to be stored in
* PMC_SCRATCH41.
*
* NOTE: THIS *MUST* BE RELOCATED TO TEGRA_IRAM_CODE_AREA.
* NOTE: THIS *MUST* BE RELOCATED TO TEGRA_IRAM_LPx_RESUME_AREA.
*/
ENTRY(tegra30_lp1_reset)
/*
......
arch/arm/mach-tegra/tegra.c
View file @ b25a51cb
......@@ -33,17 +33,78 @@
#include <linux/sys_soc.h>
#include <linux/usb/tegra_usb_phy.h>
#include <linux/clk/tegra.h>
#include <linux/irqchip.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <asm/setup.h>
#include "apbio.h"
#include "board.h"
#include "common.h"
#include "cpuidle.h"
#include "fuse.h"
#include "iomap.h"
#include "irq.h"
#include "pmc.h"
#include "pm.h"
#include "reset.h"
#include "sleep.h"
/*
* Storage for debug-macro.S's state.
*
* This must be in .data not .bss so that it gets initialized each time the
* kernel is loaded. The data is declared here rather than debug-macro.S so
* that multiple inclusions of debug-macro.S point at the same data.
*/
u32 tegra_uart_config[4] = {
/* Debug UART initialization required */
1,
/* Debug UART physical address */
0,
/* Debug UART virtual address */
0,
/* Scratch space for debug macro */
0,
};
static void __init tegra_init_cache(void)
{
#ifdef CONFIG_CACHE_L2X0
int ret;
void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
u32 aux_ctrl, cache_type;
cache_type = readl(p + L2X0_CACHE_TYPE);
aux_ctrl = (cache_type & 0x700) << (17-8);
aux_ctrl |= 0x7C400001;
ret = l2x0_of_init(aux_ctrl, 0x8200c3fe);
if (!ret)
l2x0_saved_regs_addr = virt_to_phys(&l2x0_saved_regs);
#endif
}
static void __init tegra_init_early(void)
{
tegra_cpu_reset_handler_init();
tegra_apb_io_init();
tegra_init_fuse();
tegra_init_cache();
tegra_powergate_init();
tegra_hotplug_init();
}
static void __init tegra_dt_init_irq(void)
{
tegra_pmc_init_irq();
tegra_init_irq();
irqchip_init();
tegra_legacy_irq_syscore_init();
}
static void __init tegra_dt_init(void)
{
......@@ -99,7 +160,9 @@ static void __init tegra_dt_init_late(void)
{
int i;
tegra_init_late();
tegra_init_suspend();
tegra_cpuidle_init();
tegra_powergate_debugfs_init();
for (i = 0; i < ARRAY_SIZE(board_init_funcs); i++) {
if (of_machine_is_compatible(board_init_funcs[i].machine)) {
......@@ -123,6 +186,6 @@ DT_MACHINE_START(TEGRA_DT, "NVIDIA Tegra SoC (Flattened Device Tree)")
.init_irq = tegra_dt_init_irq,
.init_machine = tegra_dt_init,
.init_late = tegra_dt_init_late,
.restart = tegra_assert_system_reset,
.restart = tegra_pmc_restart,
.dt_compat = tegra_dt_board_compat,
MACHINE_END
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7