habanalabs: load linux image to device

Implementing dynamic linux image load to the device.
This patch also implements the FW communication steps during the
boot-fit.
This patch also enables the dynamic protocol based on the compatibility
flag.
Signed-off-by: Ohad Sharabi <osharabi@habana.ai>
Reviewed-by: Oded Gabbay <ogabbay@kernel.org>
Signed-off-by: Oded Gabbay <ogabbay@kernel.org>

drivers/misc/habanalabs/common/habanalabs.h

@@ -180,10 +180,12 @@ enum hl_pci_match_mode {
  * enum hl_fw_component - F/W components to read version through registers.
  * @FW_COMP_BOOT_FIT: boot fit.
  * @FW_COMP_PREBOOT: preboot.
+ * @FW_COMP_LINUX: linux.
  */
 enum hl_fw_component {
 	FW_COMP_BOOT_FIT,
-	FW_COMP_PREBOOT
+	FW_COMP_PREBOOT,
+	FW_COMP_LINUX,
 };
 
 /**
@@ -830,6 +832,7 @@ enum pci_region {
  * struct pci_mem_region - describe memory region in a PCI bar
  * @region_base: region base address
  * @region_size: region size
+ * @bar_size: size of the BAR
  * @offset_in_bar: region offset into the bar
  * @bar_id: bar ID of the region
  * @used: if used 1, otherwise 0
@@ -837,6 +840,7 @@ enum pci_region {
 struct pci_mem_region {
 	u64 region_base;
 	u64 region_size;
+	u64 bar_size;
 	u32 offset_in_bar;
 	u8 bar_id;
 	u8 used;
@@ -885,13 +889,15 @@ struct fw_response {
  * @response: FW to LKD response
  * @comm_desc: the communication descriptor with FW
  * @image_region: region to copy the FW image to
- * @fw_image_size: FW image size
+ * @fw_image_size: size of FW image to load
+ * @wait_for_bl_timeout: timeout for waiting for boot loader to respond
  */
 struct dynamic_fw_load_mgr {
 	struct fw_response response;
 	struct lkd_fw_comms_desc comm_desc;
 	struct pci_mem_region *image_region;
 	size_t fw_image_size;
+	u32 wait_for_bl_timeout;
 };
 
 /**

drivers/misc/habanalabs/gaudi/gaudi.c

@@ -78,6 +78,7 @@
 #define GAUDI_PLDM_TPC_KERNEL_WAIT_USEC	(HL_DEVICE_TIMEOUT_USEC * 30)
 #define GAUDI_BOOT_FIT_REQ_TIMEOUT_USEC	1000000		/* 1s */
 #define GAUDI_MSG_TO_CPU_TIMEOUT_USEC	4000000		/* 4s */
+#define GAUDI_WAIT_FOR_BL_TIMEOUT_USEC	15000000	/* 15s */
 
 #define GAUDI_QMAN0_FENCE_VAL		0x72E91AB9
 
@@ -1592,6 +1593,7 @@ static int gaudi_alloc_internal_qmans_pq_mem(struct hl_device *hdev)
 
 static void gaudi_set_pci_memory_regions(struct hl_device *hdev)
 {
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
 	struct pci_mem_region *region;
 
 	/* CFG */
@@ -1599,6 +1601,7 @@ static void gaudi_set_pci_memory_regions(struct hl_device *hdev)
 	region->region_base = CFG_BASE;
 	region->region_size = CFG_SIZE;
 	region->offset_in_bar = CFG_BASE - SPI_FLASH_BASE_ADDR;
+	region->bar_size = CFG_BAR_SIZE;
 	region->bar_id = CFG_BAR_ID;
 	region->used = 1;
 
@@ -1607,6 +1610,7 @@ static void gaudi_set_pci_memory_regions(struct hl_device *hdev)
 	region->region_base = SRAM_BASE_ADDR;
 	region->region_size = SRAM_SIZE;
 	region->offset_in_bar = 0;
+	region->bar_size = SRAM_BAR_SIZE;
 	region->bar_id = SRAM_BAR_ID;
 	region->used = 1;
 
@@ -1615,6 +1619,7 @@ static void gaudi_set_pci_memory_regions(struct hl_device *hdev)
 	region->region_base = DRAM_PHYS_BASE;
 	region->region_size = hdev->asic_prop.dram_size;
 	region->offset_in_bar = 0;
+	region->bar_size = prop->dram_pci_bar_size;
 	region->bar_id = HBM_BAR_ID;
 	region->used = 1;
 
@@ -1623,6 +1628,7 @@ static void gaudi_set_pci_memory_regions(struct hl_device *hdev)
 	region->region_base = PSOC_SCRATCHPAD_ADDR;
 	region->region_size = PSOC_SCRATCHPAD_SIZE;
 	region->offset_in_bar = PSOC_SCRATCHPAD_ADDR - SPI_FLASH_BASE_ADDR;
+	region->bar_size = CFG_BAR_SIZE;
 	region->bar_id = CFG_BAR_ID;
 	region->used = 1;
 }
@@ -3749,6 +3755,8 @@ static void gaudi_init_dynamic_firmware_loader(struct hl_device *hdev)
 				cpu_to_le32(mmPSOC_GLOBAL_CONF_KMD_MSG_TO_CPU);
 	dyn_regs->cpu_cmd_status_to_host =
 				cpu_to_le32(mmCPU_CMD_STATUS_TO_HOST);
+
+	dynamic_loader->wait_for_bl_timeout = GAUDI_WAIT_FOR_BL_TIMEOUT_USEC;
 }
 
 static void gaudi_init_static_firmware_loader(struct hl_device *hdev)

drivers/misc/habanalabs/goya/goya.c

@@ -87,6 +87,7 @@
 #define GOYA_PLDM_QMAN0_TIMEOUT_USEC	(HL_DEVICE_TIMEOUT_USEC * 30)
 #define GOYA_BOOT_FIT_REQ_TIMEOUT_USEC	1000000		/* 1s */
 #define GOYA_MSG_TO_CPU_TIMEOUT_USEC	4000000		/* 4s */
+#define GOYA_WAIT_FOR_BL_TIMEOUT_USEC	15000000	/* 15s */
 
 #define GOYA_QMAN0_FENCE_VAL		0xD169B243
 
@@ -851,6 +852,7 @@ void goya_late_fini(struct hl_device *hdev)
 
 static void goya_set_pci_memory_regions(struct hl_device *hdev)
 {
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
 	struct pci_mem_region *region;
 
 	/* CFG */
@@ -858,6 +860,7 @@ static void goya_set_pci_memory_regions(struct hl_device *hdev)
 	region->region_base = CFG_BASE;
 	region->region_size = CFG_SIZE;
 	region->offset_in_bar = CFG_BASE - SRAM_BASE_ADDR;
+	region->bar_size = CFG_BAR_SIZE;
 	region->bar_id = SRAM_CFG_BAR_ID;
 	region->used = 1;
 
@@ -866,6 +869,7 @@ static void goya_set_pci_memory_regions(struct hl_device *hdev)
 	region->region_base = SRAM_BASE_ADDR;
 	region->region_size = SRAM_SIZE;
 	region->offset_in_bar = 0;
+	region->bar_size = CFG_BAR_SIZE;
 	region->bar_id = SRAM_CFG_BAR_ID;
 	region->used = 1;
 
@@ -874,6 +878,7 @@ static void goya_set_pci_memory_regions(struct hl_device *hdev)
 	region->region_base = DRAM_PHYS_BASE;
 	region->region_size = hdev->asic_prop.dram_size;
 	region->offset_in_bar = 0;
+	region->bar_size = prop->dram_pci_bar_size;
 	region->bar_id = DDR_BAR_ID;
 	region->used = 1;
 }
@@ -2452,6 +2457,8 @@ static void goya_init_dynamic_firmware_loader(struct hl_device *hdev)
 				cpu_to_le32(mmPSOC_GLOBAL_CONF_KMD_MSG_TO_CPU);
 	dyn_regs->cpu_cmd_status_to_host =
 				cpu_to_le32(mmCPU_CMD_STATUS_TO_HOST);
+
+	dynamic_loader->wait_for_bl_timeout = GOYA_WAIT_FOR_BL_TIMEOUT_USEC;
 }
 
 static void goya_init_static_firmware_loader(struct hl_device *hdev)