Merge bk://bk.arm.linux.org.uk

into penguin.transmeta.com:/home/penguin/torvalds/repositories/kernel/linux

Documentation/arm/Interrupts

+2.5.2-rmk5
+----------
+
+This is the first kernel that contains a major shake up of some of the
+major architecture-specific subsystems.
+
+Firstly, it contains some pretty major changes to the way we handle the
+MMU TLB.  Each MMU TLB variant is now handled completely separately -
+we have TLB v3, TLB v4 (without write buffer), TLB v4 (with write buffer),
+and finally TLB v4 (with write buffer, with I TLB invalidate entry).
+There is more assembly code inside each of these functions, mainly to
+allow more flexible TLB handling for the future.
+
+Secondly, the IRQ subsystem.
+
+The 2.5 kernels will be having major changes to the way IRQs are handled.
+Unfortunately, this means that machine types that touch the irq_desc[]
+array (basically all machine types) will break, and this means every
+machine type that we currently have.
+
+Lets take an example.  On the Assabet with Neponset, we have:
+
+                  GPIO25                 IRR:2
+        SA1100 ------------> Neponset -----------> SA1111
+                                         IIR:1
+                                      -----------> USAR
+                                         IIR:0
+                                      -----------> SMC9196
+
+The way stuff currently works, all SA1111 interrupts are mutually
+exclusive of each other - if you're processing one interrupt from the
+SA1111 and another comes in, you have to wait for that interrupt to
+finish processing before you can service the new interrupt.  Eg, an
+IDE PIO-based interrupt on the SA1111 excludes all other SA1111 and
+SMC9196 interrupts until it has finished transferring its multi-sector
+data, which can be a long time.  Note also that since we loop in the
+SA1111 IRQ handler, SA1111 IRQs can hold off SMC9196 IRQs indefinitely.
+
+
+The new approach brings several new ideas...
+
+We introduce the concept of a "parent" and a "child".  For example,
+to the Neponset handler, the "parent" is GPIO25, and the "children"d
+are SA1111, SMC9196 and USAR.
+
+We also bring the idea of an IRQ "chip" (mainly to reduce the size of
+the irqdesc array).  This doesn't have to be a real "IC"; indeed the
+SA11x0 IRQs are handled by two separate "chip" structures, one for
+GPIO0-10, and another for all the rest.  It is just a container for
+the various operations (maybe this'll change to a better name).
+This structure has the following operations:
+
+struct irqchip {
+        /*
+         * Acknowledge the IRQ.
+         * If this is a level-based IRQ, then it is expected to mask the IRQ
+         * as well.
+         */
+        void (*ack)(unsigned int irq);
+        /*
+         * Mask the IRQ in hardware.
+         */
+        void (*mask)(unsigned int irq);
+        /*
+         * Unmask the IRQ in hardware.
+         */
+        void (*unmask)(unsigned int irq);
+        /*
+         * Re-run the IRQ
+         */
+        void (*rerun)(unsigned int irq);
+        /*
+         * Set the type of the IRQ.
+         */
+        int (*type)(unsigned int irq, unsigned int, type);
+};
+
+ack    - required.  May be the same function as mask for IRQs
+         handled by do_level_IRQ.
+mask   - required.
+unmask - required.
+rerun  - optional.  Not required if you're using do_level_IRQ for all
+         IRQs that use this 'irqchip'.  Generally expected to re-trigger
+         the hardware IRQ if possible.  If not, may call the handler
+	 directly.
+type   - optional.  If you don't support changing the type of an IRQ,
+         it should be null so people can detect if they are unable to
+         set the IRQ type.
+
+For each IRQ, we keep the following information:
+
+        - "disable" depth (number of disable_irq()s without enable_irq()s)
+        - flags indicating what we can do with this IRQ (valid, probe,
+          noautounmask) as before
+        - status of the IRQ (probing, enable, etc)
+        - chip
+        - per-IRQ handler
+        - irqaction structure list
+
+The handler can be one of the 3 standard handlers - "level", "edge" and
+"simple", or your own specific handler if you need to do something special.
+
+The "level" handler is what we currently have - its pretty simple.
+"edge" knows about the brokenness of such IRQ implementations - that you
+need to leave the hardware IRQ enabled while processing it, and queueing
+further IRQ events should the IRQ happen again while processing.  The
+"simple" handler is very basic, and does not perform any hardware
+manipulation, nor state tracking.  This is useful for things like the
+SMC9196 and USAR above.
+
+So, what's changed?
+
+1. Machine implementations must not write to the irqdesc array.
+
+2. New functions to manipulate the irqdesc array.  The first 4 are expected
+   to be useful only to machine specific code.  The last is recommended to
+   only be used by machine specific code, but may be used in drivers if
+   absolutely necessary.
+
+        set_irq_chip(irq,chip)
+
+                Set the mask/unmask methods for handling this IRQ
+
+        set_irq_handler(irq,handler)
+
+                Set the handler for this IRQ (level, edge, simple)
+
+        set_irq_chained_handler(irq,handler)
+
+                Set a "chained" handler for this IRQ - automatically
+                enables this IRQ (eg, Neponset and SA1111 handlers).
+
+        set_irq_flags(irq,flags)
+
+                Set the valid/probe/noautoenable flags.
+
+        set_irq_type(irq,type)
+
+                Set active the IRQ edge(s)/level.  This replaces the
+                SA1111 INTPOL manipulation, and the set_GPIO_IRQ_edge()
+                function.  Type should be one of the following:
+
+                #define IRQT_NOEDGE     (0)
+                #define IRQT_RISING     (__IRQT_RISEDGE)
+                #define IRQT_FALLING    (__IRQT_FALEDGE)
+                #define IRQT_BOTHEDGE   (__IRQT_RISEDGE|__IRQT_FALEDGE)
+                #define IRQT_LOW        (__IRQT_LOWLVL)
+                #define IRQT_HIGH       (__IRQT_HIGHLVL)
+
+3. set_GPIO_IRQ_edge() is obsolete, and should be replaced by set_irq_type.
+
+4. Direct access to SA1111 INTPOL is depreciated.  Use set_irq_type instead.
+
+5. A handler is expected to perform any necessary acknowledgement of the
+   parent IRQ via the correct chip specific function.  For instance, if
+   the SA1111 is directly connected to a SA1110 GPIO, then you should
+   acknowledge the SA1110 IRQ each time you re-read the SA1111 IRQ status.
+
+6. For any child which doesn't have its own IRQ enable/disable controls
+   (eg, SMC9196), the handler must mask or acknowledge the parent IRQ
+   while the child handler is called, and the child handler should be the
+   "simple" handler (not "edge" nor "level").  After the handler completes,
+   the parent IRQ should be unmasked, and the status of all children must
+   be re-checked for pending events.  (see the Neponset IRQ handler for
+   details).
+
+7. fixup_irq() is gone, as is include/asm-arm/arch-*/irq.h
+
+Please note that this will not solve all problems - some of them are
+hardware based.  Mixing level-based and edge-based IRQs on the same
+parent signal (eg neponset) is one such area where a software based
+solution can't provide the full answer to low IRQ latency.
+

arch/arm/Config.help

@@ -657,6 +657,10 @@ CONFIG_SA1100_SHANNON
   platform with a 640x480 LCD, touchscreen, CIR keyboard, PCMCIA slots,
   and a telco interface.
 
+CONFIG_SA1100_STORK
+  Say Y here if you intend to run this kernel on the Stork
+  handheld computer.
+
 CONFIG_SA1100_VICTOR
   Say Y here if you are using a Visu Aide Intel(R) StrongARM(R)
   SA-1100 based Victor Digital Talking Book Reader.  See

arch/arm/Makefile

@@ -134,6 +134,10 @@ TEXTADDR	 = 0xc0028000
 MACHINE		 = clps711x
 endif
 
+ifeq ($(CONFIG_ARCH_FORTUNET),y)
+TEXTADDR	 = 0xc0008000
+endif
+
 ifeq ($(CONFIG_ARCH_ANAKIN),y)
 MACHINE		 = anakin
 endif
@@ -215,6 +219,7 @@ CLEAN_FILES	+= \
 	arch/arm/vmlinux.lds
 
 MRPROPER_FILES	+= \
+	arch/arm/tools/constants.h* \
 	include/asm-arm/arch \
 	include/asm-arm/proc \
 	include/asm-arm/constants.h* \

arch/arm/boot/Makefile

@@ -54,6 +54,10 @@ INITRD_PHYS	 = 0x00800000
 INITRD_VIRT	 = 0xc0800000
 endif
 
+ifeq ($(CONFIG_ARCH_CAMELOT),y)
+ZTEXTADDR	 = 0x00008000
+endif
+
 ifeq ($(CONFIG_ARCH_NEXUSPCI),y)
 ZTEXTADDR	 = 0x40008000
 endif

arch/arm/boot/compressed/Makefile

@@ -33,6 +33,10 @@ ifeq ($(CONFIG_ARCH_INTEGRATOR),y)
 OBJS		+= head-integrator.o
 endif
 
+ifeq ($(CONFIG_ARCH_CAMELOT),y)
+OBJS		+= head-epxa10db.o
+endif
+
 ifeq ($(CONFIG_ARCH_FTVPCI),y)
 OBJS		+= head-ftvpci.o
 endif

arch/arm/boot/compressed/head-epxa10db.S

+#include <asm/mach-types.h>
+#include <asm/arch/excalibur.h>
+
+		.section	".start", #alloc, #execinstr
+		mov	r7, #MACH_TYPE_CAMELOT

arch/arm/boot/compressed/misc.c

@@ -18,6 +18,8 @@
 
 unsigned int __machine_arch_type;
 
+#include <linux/kernel.h>
+
 #include <asm/uaccess.h>
 #include <asm/arch/uncompress.h>
 #include <asm/proc/uncompress.h>

arch/arm/config.in

@@ -91,6 +91,7 @@ dep_bool '  FlexaNet' CONFIG_SA1100_FLEXANET $CONFIG_ARCH_SA1100
 dep_bool '  FreeBird-v1.1' CONFIG_SA1100_FREEBIRD $CONFIG_ARCH_SA1100
 dep_bool '  GraphicsClient Plus' CONFIG_SA1100_GRAPHICSCLIENT $CONFIG_ARCH_SA1100
 dep_bool '  GraphicsMaster' CONFIG_SA1100_GRAPHICSMASTER $CONFIG_ARCH_SA1100
+dep_bool '  HP Labs BadgePAD 4' CONFIG_SA1100_BADGE4 $CONFIG_ARCH_SA1100
 dep_bool '  HP Jornada 720' CONFIG_SA1100_JORNADA720 $CONFIG_ARCH_SA1100
 dep_bool '  HuW WebPanel' CONFIG_SA1100_HUW_WEBPANEL $CONFIG_ARCH_SA1100
 dep_bool '  Itsy' CONFIG_SA1100_ITSY $CONFIG_ARCH_SA1100
@@ -107,6 +108,7 @@ dep_bool '  Tulsa' CONFIG_SA1100_PFS168 $CONFIG_ARCH_SA1100
 dep_bool '  Victor' CONFIG_SA1100_VICTOR $CONFIG_ARCH_SA1100
 dep_bool '  XP860' CONFIG_SA1100_XP860 $CONFIG_ARCH_SA1100
 dep_bool '  Yopy' CONFIG_SA1100_YOPY $CONFIG_ARCH_SA1100
+dep_bool '  Stork' CONFIG_SA1100_STORK $CONFIG_ARCH_SA1100
 
 # Determine if SA1111 support is required
 if [ "$CONFIG_ASSABET_NEPONSET" = "y" -o \
@@ -115,7 +117,8 @@ if [ "$CONFIG_ASSABET_NEPONSET" = "y" -o \
      "$CONFIG_SA1100_XP860" = "y" -o \
      "$CONFIG_SA1100_GRAPHICSMASTER" = "y" -o \
      "$CONFIG_SA1100_PT_SYSTEM3" = "y" -o \
-     "$CONFIG_SA1100_ADSBITSY" = "y" ]; then
+     "$CONFIG_SA1100_ADSBITSY" = "y" -o \
+     "$CONFIG_SA1100_BADGE4" = "y" ]; then
    define_bool CONFIG_SA1111 y
    define_int CONFIG_FORCE_MAX_ZONEORDER 9
 fi
@@ -134,6 +137,7 @@ dep_bool '  CDB89712' CONFIG_ARCH_CDB89712 $CONFIG_ARCH_CLPS711X
 dep_bool '  CLEP7312' CONFIG_ARCH_CLEP7312 $CONFIG_ARCH_CLPS711X
 dep_bool '  EDB7211' CONFIG_ARCH_EDB7211 $CONFIG_ARCH_CLPS711X
 dep_bool '  P720T' CONFIG_ARCH_P720T $CONFIG_ARCH_CLPS711X
+dep_bool '  FORTUNET' CONFIG_ARCH_FORTUNET $CONFIG_ARCH_CLPS711X
 
 # XXX Maybe these should indicate register compatibility
 # instead of being mutually exclusive.

arch/arm/kernel/armksyms.c

@@ -124,6 +124,7 @@ EXPORT_SYMBOL(__bad_xchg);
 EXPORT_SYMBOL(__readwrite_bug);
 EXPORT_SYMBOL(enable_irq);
 EXPORT_SYMBOL(disable_irq);
+EXPORT_SYMBOL(set_irq_type);
 EXPORT_SYMBOL(pm_idle);
 EXPORT_SYMBOL(pm_power_off);
 

arch/arm/kernel/debug.S

@@ -164,28 +164,49 @@
 		.endm
 
 #elif defined(CONFIG_ARCH_SA1100)
+
 		.macro	addruart,rx
 		mrc	p15, 0, \rx, c1, c0
 		tst	\rx, #1			@ MMU enabled?
 		moveq	\rx, #0x80000000	@ physical base address
 		movne	\rx, #0xf8000000	@ virtual address
-		@add	\rx, \rx, #0x00050000	@ Ser3
-		add	\rx, \rx, #0x00010000	@ Ser1
+
+		@ We probe for the active serial port here, coherently with
+		@ the comment in include/asm-arm/arch-sa1100/uncompress.h.
+		@ We assume r1 can be clobbered.
+
+		@ see if Ser3 is active
+		add	\rx, \rx, #0x00050000
+		ldr	r1, [\rx, #UTCR3]
+		tst	r1, #UTCR3_TXE
+
+		@ if Ser3 is inactive, then try Ser1
+		addeq	\rx, \rx, #(0x00010000 - 0x00050000)
+		ldreq	r1, [\rx, #UTCR3]
+		tsteq	r1, #UTCR3_TXE
+
+		@ if Ser1 is inactive, then try Ser2
+		addeq	\rx, \rx, #(0x00030000 - 0x00010000)
+		ldreq	r1, [\rx, #UTCR3]
+		tsteq	r1, #UTCR3_TXE
+
+		@ if all ports are inactive, then there is nothing we can do
+		moveq	pc, lr
 		.endm
 
 		.macro	senduart,rd,rx
-		str	\rd, [\rx, #0x14]	@ UTDR
+		str	\rd, [\rx, #UTDR]
 		.endm
 
 		.macro	waituart,rd,rx
-1001:		ldr	\rd, [\rx, #0x20]	@ UTSR1
-		tst	\rd, #1 << 2		@ UTSR1_TNF
+1001:		ldr	\rd, [\rx, #UTSR1]
+		tst	\rd, #UTSR1_TNF
 		beq	1001b
 		.endm
 
 		.macro	busyuart,rd,rx
-1001:		ldr	\rd, [\rx, #0x20]	@ UTSR1
-		tst	\rd, #1 << 0		@ UTSR1_TBY
+1001:		ldr	\rd, [\rx, #UTSR1]
+		tst	\rd, #UTSR1_TBY
 		bne	1001b
 		.endm
 

arch/arm/kernel/ecard.c

@@ -91,17 +91,8 @@ asmlinkage extern int
 ecard_loader_reset(volatile unsigned char *pa, loader_t loader);
 asmlinkage extern int
 ecard_loader_read(int off, volatile unsigned char *pa, loader_t loader);
-extern int setup_arm_irq(int, struct irqaction *);
-extern void do_ecard_IRQ(int, struct pt_regs *);
 
 
-static void
-ecard_irq_noexpmask(int intr_no, void *dev_id, struct pt_regs *regs);
-
-static struct irqaction irqexpansioncard = {
-	ecard_irq_noexpmask, SA_INTERRUPT, 0, "expansion cards", NULL, NULL
-};
-
 static inline unsigned short
 ecard_getu16(unsigned char *v)
 {
@@ -558,7 +549,7 @@ static expansioncard_ops_t ecard_default_ops = {
  *
  * They are not meant to be called directly, but via enable/disable_irq.
  */
-static void ecard_enableirq(unsigned int irqnr)
+static void ecard_irq_mask(unsigned int irqnr)
 {
 	ecard_t *ec = slot_to_ecard(irqnr - 32);
 
@@ -574,7 +565,7 @@ static void ecard_enableirq(unsigned int irqnr)
 	}
 }
 
-static void ecard_disableirq(unsigned int irqnr)
+static void ecard_irq_unmask(unsigned int irqnr)
 {
 	ecard_t *ec = slot_to_ecard(irqnr - 32);
 
@@ -587,6 +578,12 @@ static void ecard_disableirq(unsigned int irqnr)
 	}
 }
 
+static struct irqchip ecard_chip = {
+	ack:	ecard_irq_mask,
+	mask:	ecard_irq_mask,
+	unmask:	ecard_irq_unmask,
+};
+
 void ecard_enablefiq(unsigned int fiqnr)
 {
 	ecard_t *ec = slot_to_ecard(fiqnr);
@@ -632,8 +629,7 @@ ecard_dump_irq_state(ecard_t *ec)
 		       ec->irqaddr, ec->irqmask, *ec->irqaddr);
 }
 
-static void
-ecard_check_lockup(void)
+static void ecard_check_lockup(struct irqdesc *desc)
 {
 	static int last, lockup;
 	ecard_t *ec;
@@ -653,7 +649,7 @@ ecard_check_lockup(void)
 			printk(KERN_ERR "\nInterrupt lockup detected - "
 			       "disabling all expansion card interrupts\n");
 
-			disable_irq(IRQ_EXPANSIONCARD);
+			desc->chip->mask(IRQ_EXPANSIONCARD);
 
 			printk("Expansion card IRQ state:\n");
 
@@ -674,11 +670,12 @@ ecard_check_lockup(void)
 }
 
 static void
-ecard_irq_noexpmask(int intr_no, void *dev_id, struct pt_regs *regs)
+ecard_irq_handler(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
 {
 	ecard_t *ec;
 	int called = 0;
 
+	desc->chip->mask(irq);
 	for (ec = cards; ec; ec = ec->next) {
 		int pending;
 
@@ -691,14 +688,15 @@ ecard_irq_noexpmask(int intr_no, void *dev_id, struct pt_regs *regs)
 			pending = ecard_default_ops.irqpending(ec);
 
 		if (pending) {
-			do_ecard_IRQ(ec->irq, regs);
+			struct irqdesc *d = irq_desc + ec->irq;
+			d->handle(ec->irq, d, regs);
 			called ++;
 		}
 	}
-	cli();
+	desc->chip->unmask(irq);
 
 	if (called == 0)
-		ecard_check_lockup();
+		ecard_check_lockup(desc);
 }
 
 #ifdef HAS_EXPMASK
@@ -714,20 +712,18 @@ static unsigned char first_set[] =
 };
 
 static void
-ecard_irq_expmask(int intr_no, void *dev_id, struct pt_regs *regs)
+ecard_irqexp_handler(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
 {
 	const unsigned int statusmask = 15;
 	unsigned int status;
 
 	status = __raw_readb(EXPMASK_STATUS) & statusmask;
 	if (status) {
-		unsigned int slot;
-		ecard_t *ec;
-again:
-		slot = first_set[status];
-		ec = slot_to_ecard(slot);
+		unsigned int slot = first_set[status];
+		ecard_t *ec = slot_to_ecard(slot);
+
 		if (ec->claimed) {
-			unsigned int oldexpmask;
+			struct irqdesc *d = irqdesc + ec->irq;
 			/*
 			 * this ugly code is so that we can operate a
 			 * prioritorising system:
@@ -740,17 +736,7 @@ ecard_irq_expmask(int intr_no, void *dev_id, struct pt_regs *regs)
 			 * Serial cards should go in 0/1, ethernet/scsi in 2/3
 			 * otherwise you will lose serial data at high speeds!
 			 */
-			oldexpmask = have_expmask;
-			have_expmask &= priority_masks[slot];
-			__raw_writeb(have_expmask, EXPMASK_ENABLE);
-			sti();
-			do_ecard_IRQ(ec->irq, regs);
-			cli();
-			have_expmask = oldexpmask;
-			__raw_writeb(have_expmask, EXPMASK_ENABLE);
-			status = __raw_readb(EXPMASK_STATUS) & statusmask;
-			if (status)
-				goto again;
+			d->handle(ec->irq, d, regs);
 		} else {
 			printk(KERN_WARNING "card%d: interrupt from unclaimed "
 			       "card???\n", slot);
@@ -761,8 +747,7 @@ ecard_irq_expmask(int intr_no, void *dev_id, struct pt_regs *regs)
 		printk(KERN_WARNING "Wild interrupt from backplane (masks)\n");
 }
 
-static void __init
-ecard_probeirqhw(void)
+static int __init ecard_probeirqhw(void)
 {
 	ecard_t *ec;
 	int found;
@@ -772,14 +757,10 @@ ecard_probeirqhw(void)
 	found = (__raw_readb(EXPMASK_STATUS) & 15) == 0;
 	__raw_writeb(0xff, EXPMASK_ENABLE);
 
-	if (!found)
-		return;
-
+	if (found) {
 		printk(KERN_DEBUG "Expansion card interrupt "
 		       "management hardware found\n");
 
-	irqexpansioncard.handler = ecard_irq_expmask;
-
 		/* for each card present, set a bit to '1' */
 		have_expmask = 0x80000000;
 
@@ -787,9 +768,13 @@ ecard_probeirqhw(void)
 			have_expmask |= 1 << ec->slot_no;
 
 		__raw_writeb(have_expmask, EXPMASK_ENABLE);
+	}
+
+	return found;
 }
 #else
-#define ecard_probeirqhw()
+#define ecard_irqexp_handler NULL
+#define ecard_probeirqhw() (0)
 #endif
 
 #ifndef IO_EC_MEMC8_BASE
@@ -977,10 +962,9 @@ ecard_probe(int slot, card_type_t type)
 	 * hook the interrupt handlers
 	 */
 	if (ec->irq != 0 && ec->irq >= 32) {
-		irq_desc[ec->irq].mask_ack = ecard_disableirq;
-		irq_desc[ec->irq].mask     = ecard_disableirq;
-		irq_desc[ec->irq].unmask   = ecard_enableirq;
-		irq_desc[ec->irq].valid    = 1;
+		set_irq_chip(ec->irq, &ecard_chip);
+		set_irq_handler(ec->irq, do_level_IRQ);
+		set_irq_flags(ec->irq, IRQF_VALID);
 	}
 
 #ifdef CONFIG_ARCH_RPC
@@ -1042,21 +1026,6 @@ ecard_t *ecard_find(int cid, const card_ids *cids)
 	return finding_pos;
 }
 
-static void __init ecard_free_all(void)
-{
-	ecard_t *ec, *ecn;
-
-	for (ec = cards; ec; ec = ecn) {
-		ecn = ec->next;
-
-		kfree(ec);
-	}
-
-	cards = NULL;
-
-	memset(slot_to_expcard, 0, sizeof(slot_to_expcard));
-}
-
 /*
  * Initialise the expansion card system.
  * Locate all hardware - interrupt management and
@@ -1064,7 +1033,7 @@ static void __init ecard_free_all(void)
  */
 void __init ecard_init(void)
 {
-	int slot;
+	int slot, irqhw;
 
 	/*
 	 * Register our reboot notifier
@@ -1086,13 +1055,10 @@ void __init ecard_init(void)
 	ecard_probe(8, ECARD_IOC);
 #endif
 
-	ecard_probeirqhw();
+	irqhw = ecard_probeirqhw();
 
-	if (setup_arm_irq(IRQ_EXPANSIONCARD, &irqexpansioncard)) {
-		printk(KERN_ERR "Unable to claim IRQ%d for expansion cards\n",
-		       IRQ_EXPANSIONCARD);
-		ecard_free_all();
-	}
+	set_irq_chained_handler(IRQ_EXPANSIONCARD,
+				irqhw ? ecard_irqexp_handler : ecard_irq_handler);
 
 	ecard_proc_init();
 }

arch/arm/kernel/entry-armo.S

@@ -354,7 +354,7 @@ vector_IRQ:	ldr	r13, .LCirq			@ I will leave this one in just in case...
 		@
 		adr	lr, 1b
 		orr	lr, lr, #0x08000003		@ Force SVC
-		bne	do_IRQ
+		bne	asm_do_IRQ
 
 		mov	why, #0
 		get_current_task r5
@@ -377,7 +377,7 @@ __irq_svc:	teqp	pc, #0x08000003
 		@
 		adr	lr, 1b
 		orr	lr, lr, #0x08000003		@ Force SVC
-		bne	do_IRQ				@ Returns to 1b
+		bne	asm_do_IRQ			@ Returns to 1b
 		SVC_RESTORE_ALL
 
 __irq_invalid:	mov	r0, sp

arch/arm/kernel/entry-armv.S

@@ -734,19 +734,22 @@ preempt_return:
 		ldmia	sp, {r0 - pc}^			@ load r0 - pc, cpsr
 
 #ifdef CONFIG_PREEMPT
-svc_preempt:	teq	r9, #0
-		movne	pc, lr
+svc_preempt:	teq	r9, #0				@ was preempt count = 0
+		movne	pc, lr				@ no
 		ldr	r0, [r6, #4]			@ local_irq_count
-		ldr	r1, [r6, #8]			@ local_b_count
+		ldr	r1, [r6, #8]			@ local_bh_count
 		adds	r0, r0, r1
 		movne	pc, lr
-1:		set_cpsr_c r0, #MODE_SVC		@ enable IRQs
-		bl	SYMBOL_NAME(preempt_schedule)
+		ldr	r1, [r8, #TI_TASK]
+		set_cpsr_c r2, #MODE_SVC		@ enable IRQs
+		str	r0, [r1, #0]			@ current->state = TASK_RUNNING
+1:		bl	SYMBOL_NAME(schedule)
 		set_cpsr_c r0, #PSR_I_BIT | MODE_SVC	@ disable IRQs
 		ldr	r0, [r8, #TI_FLAGS]
 		tst	r0, #_TIF_NEED_RESCHED
-		bne	1b
-		b	preempt_return
+		beq	preempt_return
+		set_cpsr_c r0, #MODE_SVC		@ enable IRQs
+		b	1b
 #endif
 
 		.align	5

arch/arm/kernel/entry-common.S

@@ -55,7 +55,7 @@ work_resched:
  */
 ENTRY(ret_to_user)
 ret_slow_syscall:
-	set_cpsr_c r1, #PSR_I_BIT | MODE_SVC
+	set_cpsr_c r1, #PSR_I_BIT | MODE_SVC	@ disable interrupts
 	ldr	r1, [tsk, #TI_FLAGS]
 	tst	r1, #_TIF_WORK_MASK
 	beq	no_work_pending
@@ -73,12 +73,9 @@ __do_notify_resume:
 	b	SYMBOL_NAME(do_notify_resume)	@ note the bl above sets lr
 
 /*
- * This is how we return from a fork.  __switch_to will be calling us
- * with r0 pointing at the previous task that was running (ready for
- * calling schedule_tail).
+ * This is how we return from a fork.
  */
 ENTRY(ret_from_fork)
-	bl	SYMBOL_NAME(schedule_tail)
 	get_thread_info tsk
 	ldr	ip, [tsk, #TI_FLAGS]		@ check for syscall tracing
 	mov	why, #1

arch/arm/kernel/head.S

@@ -14,6 +14,7 @@
 
 #include <asm/assembler.h>
 #include <asm/mach-types.h>
+#include <asm/procinfo.h>
 #include <asm/mach/arch.h>
 
 #define K(a,b,c)	((a) << 24 | (b) << 12 | (c))
@@ -126,7 +127,7 @@ __entry:
 		mov	r1, #MACH_TYPE_L7200
 #endif
 
-		mov	r0, #F_BIT | I_BIT | MODE_SVC	@ make sure svc mode
+		mov	r0, #PSR_F_BIT | PSR_I_BIT | MODE_SVC	@ make sure svc mode
 		msr	cpsr_c, r0			@ and all irqs disabled
 		bl	__lookup_processor_type
 		teq	r10, #0				@ invalid processor?
@@ -374,7 +375,7 @@ __lookup_processor_type:
 		and	r6, r6, r9			@ mask wanted bits
 		teq	r5, r6
 		moveq	pc, lr
-		add	r10, r10, #36			@ sizeof(proc_info_list)
+		add	r10, r10, #PROC_INFO_SZ		@ sizeof(proc_info_list)
 		cmp	r10, r7
 		blt	1b
 		mov	r10, #0				@ unknown processor

arch/arm/kernel/ptrace.c

@@ -34,7 +34,7 @@
 /*
  * Breakpoint SWI instruction: SWI &9F0001
  */
-#define BREAKINST	0xef9f0001
+#define BREAKINST_ARM	0xef9f0001
 
 /*
  * Get the address of the live pt_regs for the specified task.
@@ -183,6 +183,20 @@ ptrace_getldrop2(struct task_struct *child, unsigned long insn)
 	return val;
 }
 
+#define OP_MASK	0x01e00000
+#define OP_AND	0x00000000
+#define OP_EOR	0x00200000
+#define OP_SUB	0x00400000
+#define OP_RSB	0x00600000
+#define OP_ADD	0x00800000
+#define OP_ADC	0x00a00000
+#define OP_SBC	0x00c00000
+#define OP_RSC	0x00e00000
+#define OP_ORR	0x01800000
+#define OP_MOV	0x01a00000
+#define OP_BIC	0x01c00000
+#define OP_MVN	0x01e00000
+
 static unsigned long
 get_branch_address(struct task_struct *child, unsigned long pc, unsigned long insn)
 {
@@ -201,21 +215,21 @@ get_branch_address(struct task_struct *child, unsigned long pc, unsigned long in
 
 		aluop1 = ptrace_getrn(child, insn);
 		aluop2 = ptrace_getaluop2(child, insn);
-		ccbit  = get_stack_long(child, REG_PSR) & CC_C_BIT ? 1 : 0;
-
-		switch (insn & 0x01e00000) {
-		case 0x00000000: alt = aluop1 & aluop2;		break;
-		case 0x00200000: alt = aluop1 ^ aluop2;		break;
-		case 0x00400000: alt = aluop1 - aluop2;		break;
-		case 0x00600000: alt = aluop2 - aluop1;		break;
-		case 0x00800000: alt = aluop1 + aluop2;		break;
-		case 0x00a00000: alt = aluop1 + aluop2 + ccbit;	break;
-		case 0x00c00000: alt = aluop1 - aluop2 + ccbit;	break;
-		case 0x00e00000: alt = aluop2 - aluop1 + ccbit;	break;
-		case 0x01800000: alt = aluop1 | aluop2;		break;
-		case 0x01a00000: alt = aluop2;			break;
-		case 0x01c00000: alt = aluop1 & ~aluop2;	break;
-		case 0x01e00000: alt = ~aluop2;			break;
+		ccbit  = get_stack_long(child, REG_PSR) & PSR_C_BIT ? 1 : 0;
+
+		switch (insn & OP_MASK) {
+		case OP_AND: alt = aluop1 & aluop2;		break;
+		case OP_EOR: alt = aluop1 ^ aluop2;		break;
+		case OP_SUB: alt = aluop1 - aluop2;		break;
+		case OP_RSB: alt = aluop2 - aluop1;		break;
+		case OP_ADD: alt = aluop1 + aluop2;		break;
+		case OP_ADC: alt = aluop1 + aluop2 + ccbit;	break;
+		case OP_SBC: alt = aluop1 - aluop2 + ccbit;	break;
+		case OP_RSC: alt = aluop2 - aluop1 + ccbit;	break;
+		case OP_ORR: alt = aluop1 | aluop2;		break;
+		case OP_MOV: alt = aluop2;			break;
+		case OP_BIC: alt = aluop1 & ~aluop2;		break;
+		case OP_MVN: alt = ~aluop2;			break;
 		}
 		break;
 	}
@@ -276,7 +290,7 @@ get_branch_address(struct task_struct *child, unsigned long pc, unsigned long in
 			base = ptrace_getrn(child, insn);
 
 			if (read_tsk_long(child, base + nr_regs, &alt) == 0)
-				alt = pc_pointer (alt);
+				alt = pc_pointer(alt);
 			break;
 		}
 		break;
@@ -313,7 +327,7 @@ add_breakpoint(struct task_struct *child, struct debug_info *dbg, unsigned long
 	if (nr < 2) {
 		res = read_tsk_long(child, addr, &dbg->bp[nr].insn);
 		if (res == 0)
-			res = write_tsk_long(child, addr, BREAKINST);
+			res = write_tsk_long(child, addr, BREAKINST_ARM);
 
 		if (res == 0) {
 			dbg->bp[nr].address = addr;
@@ -382,7 +396,7 @@ void __ptrace_cancel_bpt(struct task_struct *child)
 
 		read_tsk_long(child, dbg->bp[i].address, &tmp);
 		write_tsk_long(child, dbg->bp[i].address, dbg->bp[i].insn);
-		if (tmp != BREAKINST)
+		if (tmp != BREAKINST_ARM)
 			printk(KERN_ERR "ptrace_cancel_bpt: weirdness\n");
 	}
 }

arch/arm/kernel/setup.c

@@ -73,6 +73,9 @@ unsigned int elf_hwcap;
 #ifdef MULTI_CPU
 struct processor processor;
 #endif
+#ifdef MULTI_TLB
+struct cpu_tlb_fns cpu_tlb;
+#endif
 
 unsigned char aux_device_present;
 char elf_platform[ELF_PLATFORM_SIZE];
@@ -180,7 +183,7 @@ static const char *cache_lockdown[16] = {
 
 static inline void dump_cache(const char *prefix, unsigned int cache)
 {
-	unsigned int mult = 2 + CACHE_M(cache) ? 1 : 0;
+	unsigned int mult = 2 + (CACHE_M(cache) ? 1 : 0);
 
 	printk("%s size %dK associativity %d line length %d sets %d\n",
 		prefix,
@@ -242,6 +245,9 @@ static void __init setup_processor(void)
 #ifdef MULTI_CPU
 	processor = *list->proc;
 #endif
+#ifdef MULTI_TLB
+	cpu_tlb = *list->tlb;
+#endif
 
 	printk("Processor: %s %s revision %d\n",
 	       proc_info.manufacturer, proc_info.cpu_name,
@@ -665,7 +671,7 @@ static const char *proc_arch[16] = {
 static void
 c_show_cache(struct seq_file *m, const char *type, unsigned int cache)
 {
-	unsigned int mult = 2 + CACHE_M(cache) ? 1 : 0;
+	unsigned int mult = 2 + (CACHE_M(cache) ? 1 : 0);
 
 	seq_printf(m, "%s size\t\t: %d\n"
 		      "%s assoc\t\t: %d\n"
@@ -738,7 +744,7 @@ static int c_show(struct seq_file *m, void *v)
 				   cache_types[CACHE_TYPE(cache_info)],
 				   cache_clean[CACHE_TYPE(cache_info)],
 				   cache_lockdown[CACHE_TYPE(cache_info)],
-				   CACHE_S(cache_info) ? "separate I,D" : "unified");
+				   CACHE_S(cache_info) ? "Harvard" : "Unified");
 
 			if (CACHE_S(cache_info)) {
 				c_show_cache(m, "I", CACHE_ISIZE(cache_info));

arch/arm/kernel/signal.c

@@ -396,7 +396,11 @@ setup_return(struct pt_regs *regs, struct k_sigaction *ka,
 		if (__put_user(retcodes[idx], rc))
 			return 1;
 
-		flush_icache_range((unsigned long)rc,
+		/*
+		 * Ensure that the instruction cache sees
+		 * the return code written onto the stack.
+		 */
+		cpu_icache_invalidate_range((unsigned long)rc,
 					    (unsigned long)(rc + 1));
 
 		retcode = ((unsigned long)rc) + thumb;

arch/arm/kernel/time.c

@@ -31,10 +31,16 @@
 #include <asm/irq.h>
 #include <asm/leds.h>
 
-extern int setup_arm_irq(int, struct irqaction *);
 extern rwlock_t xtime_lock;
 extern unsigned long wall_jiffies;
 
+/* this needs a better home */
+spinlock_t rtc_lock = SPIN_LOCK_UNLOCKED;
+
+#ifdef CONFIG_SA1100_RTC_MODULE
+EXPORT_SYMBOL(rtc_lock);
+#endif
+
 /* change this if you have some constant time drift */
 #define USECS_PER_JIFFY	(1000000/HZ)
 

arch/arm/kernel/traps.c

@@ -95,7 +95,7 @@ static void dump_instr(struct pt_regs *regs)
 	int i;
 
 	printk("Code: ");
-	for (i = -2; i < 3; i++) {
+	for (i = -4; i < 1; i++) {
 		unsigned int val, bad;
 
 		if (thumb)

arch/arm/kernel/via82c505.c

@@ -74,85 +74,7 @@ static struct pci_ops via82c505_ops = {
 	via82c505_write_config_dword,
 };
 
-#ifdef CONFIG_ARCH_SHARK
-
-static char size_wanted;
-
-static int
-dummy_read_config_byte(struct pci_dev *dev, int where, u8 *value)
-{
-	*value=0;
-	return PCIBIOS_SUCCESSFUL;
-}
-
-static int
-dummy_read_config_word(struct pci_dev *dev, int where, u16 *value)
-{
-	*value=0;
-	return PCIBIOS_SUCCESSFUL;
-}
-
-static int
-dummy_read_config_dword(struct pci_dev *dev, int where, u32 *value)
-{
-	if (dev->devfn != 0) *value = 0;
-	else
-	  switch(where) {
-	  case PCI_VENDOR_ID:
-	    *value = PCI_VENDOR_ID_INTERG | PCI_DEVICE_ID_INTERG_2010 << 16;
-	    break;
-	  case PCI_CLASS_REVISION:
-	    *value = PCI_CLASS_DISPLAY_VGA << 16;
-	    break;
-	  case PCI_BASE_ADDRESS_0:
-	    if (size_wanted) {
-	      /* 0x00900000 bytes long (0xff700000) */
-	      *value = 0xff000000;
-	      size_wanted = 0;
-	    } else {
-	      *value = FB_START;
-	    }
-	    break;
-	  case PCI_INTERRUPT_LINE:
-	    *value = 6;
-	    break;
-	  default:
-	    *value = 0;
-	  }
-	return PCIBIOS_SUCCESSFUL;
-}
-
-static int
-dummy_write_config_byte(struct pci_dev *dev, int where, u8 value)
-{
-	return PCIBIOS_SUCCESSFUL;
-}
-
-static int
-dummy_write_config_word(struct pci_dev *dev, int where, u16 value)
-{
-	return PCIBIOS_SUCCESSFUL;
-}
-
-static int
-dummy_write_config_dword(struct pci_dev *dev, int where, u32 value)
-{
-	if ((dev->devfn == 0) && (where == PCI_BASE_ADDRESS_0) && (value == 0xffffffff))
-	  size_wanted = 1;
-	return PCIBIOS_SUCCESSFUL;
-}
-
-static struct pci_ops dummy_ops = {
-	dummy_read_config_byte,
-	dummy_read_config_word,
-	dummy_read_config_dword,
-	dummy_write_config_byte,
-	dummy_write_config_word,
-	dummy_write_config_dword,
-};
-#endif
-
-void __init via82c505_init(void *sysdata)
+void __init via82c505_preinit(void *sysdata)
 {
 	struct pci_bus *bus;
 
@@ -166,13 +88,17 @@ void __init via82c505_init(void *sysdata)
 	outb(0x93,0xA8);
 	outb(0xd0,0xA9);
 
-	pci_scan_bus(0, &via82c505_ops, sysdata);
+}
+
+int __init via82c505_setup(int nr, struct pci_sys_data *sys)
+{
+	return (nr == 0);
+}
+
+struct pci_bus * __init via82c505_scan_bus(int nr, struct pci_sys_data *sysdata)
+{
+	if (nr == 0)
+		return pci_scan_bus(0, &via82c505_ops, sysdata);
 
-#ifdef CONFIG_ARCH_SHARK
-	/* 
-	 * Initialize a fake pci-bus number 1 for the CyberPro
-         * on the vlbus
-	 */
-	bus = pci_scan_bus(1, &dummy_ops, sysdata);
-#endif
+	return NULL;
 }

arch/arm/lib/Makefile

@@ -44,8 +44,6 @@ obj-$(v4)	+= io-readsw-armv4.o io-writesw-armv4.o io-readsl-armv4.o
 obj-y		+= io-writesl.o
 
 obj-$(CONFIG_CPU_26) += uaccess-armo.o
-obj-$(CONFIG_CPU_32) += copy_page-armv3.o copy_page-armv4.o copy_page-armv4mc.o
-obj-$(CONFIG_CPU_32v5) += copy_page-armv5te.o
 
 include $(TOPDIR)/Rules.make
 

arch/arm/lib/ecard.S

@@ -12,7 +12,7 @@
 #include <asm/assembler.h>
 #include <asm/hardware.h>
 
-#if defined(CONFIG_CPU_26)
+#ifdef CONFIG_CPU_26
 #define CPSR2SPSR(rt)
 #else
 #define CPSR2SPSR(rt) \

arch/arm/lib/io-acorn.S

@@ -58,7 +58,7 @@ ENTRY(outsl)
 @ Proto  : void memc_write(int register, int value);
 @ Returns: nothing
 
-#if defined(CONFIG_CPU_26)
+#ifdef CONFIG_CPU_26
 ENTRY(memc_write)
 		cmp	r0, #7
 		RETINSTR(movgt,pc,lr)

arch/arm/mach-arc/dma.c

@@ -28,6 +28,10 @@
 static void arc_floppy_data_enable_dma(dmach_t channel, dma_t *dma)
 {
 	DPRINTK("arc_floppy_data_enable_dma\n");
+
+	if (dma->using_sg)
+		BUG();
+
 	switch (dma->dma_mode) {
 	case DMA_MODE_READ: { /* read */
 		extern unsigned char fdc1772_dma_read, fdc1772_dma_read_end;
@@ -39,7 +43,7 @@ static void arc_floppy_data_enable_dma(dmach_t channel, dma_t *dma)
 			
 		memcpy ((void *)0x1c, (void *)&fdc1772_dma_read,
 			&fdc1772_dma_read_end - &fdc1772_dma_read);
-		fdc1772_setupdma(dma->buf.length, dma->buf.address); /* Sets data pointer up */
+		fdc1772_setupdma(dma->buf.length, dma->buf.__address); /* Sets data pointer up */
 		enable_fiq(FIQ_FLOPPYDATA);
 		restore_flags(flags);
 	   }
@@ -54,7 +58,7 @@ static void arc_floppy_data_enable_dma(dmach_t channel, dma_t *dma)
 		clf();
 		memcpy ((void *)0x1c, (void *)&fdc1772_dma_write,
 			&fdc1772_dma_write_end - &fdc1772_dma_write);
-		fdc1772_setupdma(dma->buf.length, dma->buf.address); /* Sets data pointer up */
+		fdc1772_setupdma(dma->buf.length, dma->buf.__address); /* Sets data pointer up */
 		enable_fiq(FIQ_FLOPPYDATA;
 
 		restore_flags(flags);
@@ -140,6 +144,9 @@ static void a5k_floppy_enable_dma(dmach_t channel, dma_t *dma)
 	extern void floppy_fiqsetup(unsigned long len, unsigned long addr,
 				     unsigned long port);
 
+	if (dma->using_sg)
+		BUG();
+
 	if (dma->dma_mode == DMA_MODE_READ) {
 		extern unsigned char floppy_fiqin_start, floppy_fiqin_end;
 		fiqhandler_start = &floppy_fiqin_start;
@@ -155,7 +162,7 @@ static void a5k_floppy_enable_dma(dmach_t channel, dma_t *dma)
 	}
 	memcpy((void *)0x1c, fiqhandler_start, fiqhandler_length);
 	regs.ARM_r9 = dma->buf.length;
-	regs.ARM_r10 = (unsigned long)dma->buf.address;
+	regs.ARM_r10 = (unsigned long)dma->buf.__address;
 	regs.ARM_fp = FLOPPYDMA_BASE;
 	set_fiq_regs(&regs);
 	enable_fiq(dma->dma_irq);

arch/arm/mach-clps711x/Makefile

@@ -22,6 +22,7 @@ obj-$(CONFIG_ARCH_AUTCPU12) += autcpu12.o
 obj-$(CONFIG_ARCH_CDB89712) += cdb89712.o
 obj-$(CONFIG_ARCH_CLEP7312) += clep7312.o
 obj-$(CONFIG_ARCH_EDB7211)  += edb7211-arch.o edb7211-mm.o
+obj-$(CONFIG_ARCH_FORTUNET) += fortunet.o
 obj-$(CONFIG_ARCH_P720T)    += p720t.o
 leds-$(CONFIG_ARCH_P720T)   += p720t-leds.o
 obj-$(CONFIG_LEDS)          += $(leds-y)

include/asm-arm/arch-integrator/irq.h → arch/arm/mach-clps711x/fortunet.c

 /*
- *  linux/include/asm-arm/arch-integrator/irq.h
+ *  linux/arch/arm/mach-clps711x/fortunet.c
  *
- *  Copyright (C) 1999 ARM Limited
+ *  Derived from linux/arch/arm/mach-integrator/arch.c
+ *
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -17,4 +19,63 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
-#define fixup_irq(i)	(i)
+#include <linux/config.h>
+#include <linux/types.h>
+#include <linux/sched.h>
+#include <linux/interrupt.h>
+#include <linux/init.h>
+#include <linux/blk.h>
+
+#include <asm/hardware.h>
+#include <asm/irq.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/amba_kmi.h>
+
+extern void clps711x_map_io(void);
+extern void clps711x_init_irq(void);
+
+struct meminfo memmap = { 1, 0xC1000000, {{0xC0000000,0x01000000,0}}};
+
+typedef struct tag_IMAGE_PARAMS
+{
+	int	ramdisk_ok;
+	int	ramdisk_address;
+	int	ramdisk_size;
+	int	ram_size;
+	int	extra_param_type;
+	int	extra_param_ptr;
+	int	command_line;
+} IMAGE_PARAMS;
+
+#define IMAGE_PARAMS_PHYS	0xC01F0000
+
+static void __init
+fortunet_fixup(struct machine_desc *desc, struct param_struct *params,
+		 char **cmdline, struct meminfo *mi)
+{
+	IMAGE_PARAMS *ip;
+	ip = (IMAGE_PARAMS *)__phys_to_virt(IMAGE_PARAMS_PHYS);
+	*cmdline = (char *)__phys_to_virt(ip->command_line);
+#ifdef CONFIG_BLK_DEV_INITRD
+	if(ip->ramdisk_ok)
+	{
+		initrd_start = __phys_to_virt(ip->ramdisk_address);
+		initrd_end = initrd_start + ip->ramdisk_size;
+	}
+#endif
+	memmap.bank[0].size = ip->ram_size;
+	memmap.end = ip->ram_size+0xC0000000;
+	*mi = memmap;
+}
+
+MACHINE_START(FORTUNET, "ARM-FortuNet")
+	MAINTAINER("FortuNet Inc.")
+        BOOT_MEM(0xc0000000, 0x80000000, 0xf0000000)
+	BOOT_PARAMS(0x00000000)
+	FIXUP(fortunet_fixup)
+	MAPIO(clps711x_map_io)
+	INITIRQ(clps711x_init_irq)
+MACHINE_END

arch/arm/mach-clps711x/irq.c

@@ -26,7 +26,7 @@
 
 #include <asm/hardware/clps7111.h>
 
-static void mask_irq_int1(unsigned int irq)
+static void int1_mask(unsigned int irq)
 {
 	u32 intmr1;
 
@@ -35,7 +35,7 @@ static void mask_irq_int1(unsigned int irq)
 	clps_writel(intmr1, INTMR1);
 }
 
-static void mask_ack_irq_int1(unsigned int irq)
+static void int1_ack(unsigned int irq)
 {
 	u32 intmr1;
 
@@ -53,7 +53,7 @@ static void mask_ack_irq_int1(unsigned int irq)
 	}
 }
 
-static void unmask_irq_int1(unsigned int irq)
+static void int1_unmask(unsigned int irq)
 {
 	u32 intmr1;
 
@@ -62,7 +62,13 @@ static void unmask_irq_int1(unsigned int irq)
 	clps_writel(intmr1, INTMR1);
 }
 
-static void mask_irq_int2(unsigned int irq)
+static struct irqchip int1_chip = {
+	ack:	int1_ack,
+	mask:	int1_mask,
+	unmask:	int1_unmask,
+};
+
+static void int2_mask(unsigned int irq)
 {
 	u32 intmr2;
 
@@ -71,7 +77,7 @@ static void mask_irq_int2(unsigned int irq)
 	clps_writel(intmr2, INTMR2);
 }
 
-static void mask_ack_irq_int2(unsigned int irq)
+static void int2_ack(unsigned int irq)
 {
 	u32 intmr2;
 
@@ -84,7 +90,7 @@ static void mask_ack_irq_int2(unsigned int irq)
 	}
 }
 
-static void unmask_irq_int2(unsigned int irq)
+static void int2_unmask(unsigned int irq)
 {
 	u32 intmr2;
 
@@ -93,28 +99,26 @@ static void unmask_irq_int2(unsigned int irq)
 	clps_writel(intmr2, INTMR2);
 }
 
+static struct irqchip int2_chip = {
+	ack:	int2_ack,
+	mask:	int2_mask,
+	unmask:	int2_unmask,
+};
+
 void __init clps711x_init_irq(void)
 {
 	unsigned int i;
 
 	for (i = 0; i < NR_IRQS; i++) {
 	        if (INT1_IRQS & (1 << i)) {
-		        irq_desc[i].valid	= 1;
-			irq_desc[i].probe_ok	= 1;
-			irq_desc[i].mask_ack	= (INT1_ACK_IRQS & (1 << i)) ?
-						   mask_ack_irq_int1 :
-						   mask_irq_int1;
-			irq_desc[i].mask	= mask_irq_int1;
-			irq_desc[i].unmask	= unmask_irq_int1;
+	        	set_irq_handler(i, do_level_IRQ);
+	        	set_irq_chip(i, &int1_chip);
+	        	set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
 		}
 		if (INT2_IRQS & (1 << i)) {
-		        irq_desc[i].valid	= 1;
-			irq_desc[i].probe_ok	= 1;
-			irq_desc[i].mask_ack	= (INT2_ACK_IRQS & (1 << i)) ?
-						   mask_ack_irq_int2 :
-						   mask_irq_int2;
-			irq_desc[i].mask	= mask_irq_int2;
-			irq_desc[i].unmask	= unmask_irq_int2;
+			set_irq_handler(i, do_level_IRQ);
+			set_irq_chip(i, &int2_chip);
+			set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
 		}			
 	}
 

arch/arm/mach-ebsa110/core.c

@@ -40,26 +40,30 @@ static void ebsa110_unmask_irq(unsigned int irq)
 	__raw_writeb(1 << irq, IRQ_MSET);
 }
 
+static struct irqchip ebsa110_irq_chip = {
+	ack:	ebsa110_mask_irq,
+	mask:	ebsa110_mask_irq,
+	unmask:	ebsa110_unmask_irq,
+};
+ 
 static void __init ebsa110_init_irq(void)
 {
 	unsigned long flags;
-	int irq;
+	unsigned int irq;
 
-	save_flags_cli (flags);
+	local_irq_save(flags);
 	__raw_writeb(0xff, IRQ_MCLR);
 	__raw_writeb(0x55, IRQ_MSET);
 	__raw_writeb(0x00, IRQ_MSET);
 	if (__raw_readb(IRQ_MASK) != 0x55)
 		while (1);
 	__raw_writeb(0xff, IRQ_MCLR);	/* clear all interrupt enables */
-	restore_flags (flags);
+	local_irq_restore(flags);
 
 	for (irq = 0; irq < NR_IRQS; irq++) {
-		irq_desc[irq].valid	= 1;
-		irq_desc[irq].probe_ok	= 1;
-		irq_desc[irq].mask_ack	= ebsa110_mask_irq;
-		irq_desc[irq].mask	= ebsa110_mask_irq;
-		irq_desc[irq].unmask	= ebsa110_unmask_irq;
+		set_irq_chip(irq, &ebsa110_irq_chip);
+		set_irq_handler(irq, do_level_IRQ);
+		set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
 	}
 }
 

arch/arm/mach-epxa10db/irq.c

@@ -18,28 +18,44 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 #include <linux/init.h>
+#include <linux/ioport.h>
+#include <asm/io.h>
 #include <asm/hardware.h>
 #include <asm/irq.h>
-#include <asm/io.h>
 #include <asm/mach/irq.h>
 #include <asm/arch/platform.h>
 #include <asm/arch/int_ctrl00.h>
 
 
-static void mask_irq(unsigned int irq)
+static void epxa_mask_irq(unsigned int irq)
 {
-        __raw_writel(1 << irq, INT_MC(IO_ADDRESS(EXC_INT_CTRL00_BASE)));
+        writel(1 << irq, INT_MC(IO_ADDRESS(EXC_INT_CTRL00_BASE)));
 }
 
-static void unmask_irq(unsigned int irq)
+static void epxa_unmask_irq(unsigned int irq)
 {
-        __raw_writel(1 << irq, INT_MS(IO_ADDRESS(EXC_INT_CTRL00_BASE)));
+        writel(1 << irq, INT_MS(IO_ADDRESS(EXC_INT_CTRL00_BASE)));
 }
  
+
+static struct irqchip epxa_irq_chip = {
+	ack:		epxa_mask_irq,
+	mask:		epxa_mask_irq,
+	unmask:		epxa_unmask_irq,
+};
+
+static struct resource irq_resource = {
+	name:	"irq_handler",
+	start:	IO_ADDRESS(EXC_INT_CTRL00_BASE),
+	end:	IO_ADDRESS(INT_PRIORITY_FC(EXC_INT_CTRL00_BASE))+4,
+};
+
 void __init epxa10db_init_irq(void)
 {
 	unsigned int i;
 	
+	request_resource(&iomem_resource, &irq_resource);
+
 	/*
 	 * This bit sets up the interrupt controller using 
 	 * the 6 PLD interrupts mode (the default) each 
@@ -49,22 +65,15 @@ void __init epxa10db_init_irq(void)
 	 * on the contents of your PLD
 	 */
 
-	__raw_writel(3,INT_MODE(IO_ADDRESS(EXC_INT_CTRL00_BASE)));
+	writel(3,INT_MODE(IO_ADDRESS(EXC_INT_CTRL00_BASE)));
 	for (i = 0; i < NR_IRQS; i++){
-		__raw_writel(i+1, INT_PRIORITY_P0(IO_ADDRESS(EXC_INT_CTRL00_BASE)) + (4*i));
-	}
-
-
-	for (i = 0; i < NR_IRQS; i++) {
-	       
-		irq_desc[i].valid	= 1;
-		irq_desc[i].probe_ok	= 1;
-		irq_desc[i].mask_ack	= mask_irq;
-		irq_desc[i].mask	= mask_irq;
-		irq_desc[i].unmask	= unmask_irq;
+		writel(i+1, INT_PRIORITY_P0(IO_ADDRESS(EXC_INT_CTRL00_BASE)) + (4*i));
+		set_irq_chip(i,&epxa_irq_chip);
+		set_irq_handler(i,do_level_IRQ);
+		set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
 	}
 
-	/* Disable all interrupt */
-	__raw_writel(-1,INT_MC(IO_ADDRESS(EXC_INT_CTRL00_BASE)));
+	/* Disable all interrupts */
+	writel(-1,INT_MC(IO_ADDRESS(EXC_INT_CTRL00_BASE)));
 
 }

arch/arm/mach-footbridge/Makefile

@@ -11,7 +11,7 @@ O_TARGET		:= footbridge.o
 
 # Object file lists.
 
-obj-y			:= arch.o dc21285.o dma.o irq.o mm.o
+obj-y			:= arch.o dc21285.o dma.o irq.o isa-irq.o mm.o
 obj-m			:=
 obj-n			:=
 obj-			:=