Commit b430081b authored by David S. Miller's avatar David S. Miller

Merge branch 'net-phy-mscc-PHC-and-timestamping-support'

Antoine Tenart says:

====================
net: phy: mscc: PHC and timestamping support

This series aims at adding support for PHC and timestamping operations
in the MSCC PHY driver, for the VSC858x and VSC8575. Those PHYs are
capable of timestamping in 1-step and 2-step for both L2 and L4 traffic.

As of this series, only IPv4 support was implemented when using L4 mode.
This is because of an hardware limitation which prevents us for
supporting both IPv4 and IPv6 at the same time. Implementing support for
IPv6 should be quite easy (I do have the modifications needed for the
hardware configuration) but I did not see a way to retrieve this
information in hwtstamp(). What would you suggest?

Those PHYs are distributed in hardware packages containing multiple
times the PHY. The VSC8584 for example is composed of 4 PHYs. With
hardware packages, parts of the logic is usually common and one of the
PHY has to be used for some parts of the initialization. Following this
logic, the 1588 blocks of those PHYs are shared between two PHYs and
accessing the registers has to be done using the "base" PHY of the
group. This is handled thanks to helpers in the PTP code (and locks).
We also need the MDIO bus lock while performing a single read or write
to the 1588 registers as the read/write are composed of multiple MDIO
transactions (and we don't want other threads updating the page).

To get and set the PHC time, a GPIO has to be used and changes are only
retrieved or committed when on a rising edge. The same GPIO is shared by
all PHYs, so the granularity of the lock protecting it has to be
different from the ones protecting the 1588 registers (the VSC8584 PHY
has 2 1588 blocks, and a single load/save pin).

Patch 1 extends the recently added helpers to share information between
PHYs of the same hardware package; to allow having part of the probe to
be shared (in addition to the already supported init part). This will be
used when adding support for PHC/TS to initialize locks.

Patches 2 and 3 are mostly cosmetic.

Patch 4 takes into account the 1588 block in the MACsec initialization,
to allow having both the MACsec and 1588 blocks initialized on a running
system.

Patches 5 and 6 add support for PHC and timestamping operations in the
MSCC driver. An initialization of the 1588 block (plus all the registers
definition; and helpers) is added first; and then comes a patch to
implement the PHC and timestamping API.

Patches 7 and 8 add the required hardware description for device trees,
to be able to use the load/save GPIO pin on the PCB120 board.

To use this on a PCB120 board, two other series are needed and have
already been sent upstream (one is merged). There are no dependency
between all those series.

Since v3:
  - Fixed a SKB leak.
  - Removed ts_lock from the init, as TS and PHC operations aren't
    registered at this time.
  - Refectored the ts_base_addr/phy intialization.
  - Cleaned up the ingr/egr latencies definitons.
  - Fixed a comment about locking and the shared GPIO.
  - A few cosmetic fixes.

Since v2:
  - Removed explicit inlines from .c files.
  - Fixed three warnings.

Since v1:
  - Removed checks in rxtstamp/txtstamp as skb cannot be NULL here.
  - Reworked get_ptp_header_rx/get_ptp_header.
  - Reworked the locking logic between the PHC and timestamping
    operations.
  - Fixed a compilation issue on x86 reported by Jakub.
====================
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 7b0cc34a 15324652
......@@ -31,6 +31,8 @@ Optional properties:
VSC8531_LINK_100_ACTIVITY (2),
VSC8531_LINK_ACTIVITY (0) and
VSC8531_DUPLEX_COLLISION (8).
- load-save-gpios : GPIO used for the load/save operation of the PTP
hardware clock (PHC).
Table: 1 - Edge rate change
......@@ -67,4 +69,5 @@ Example:
vsc8531,edge-slowdown = <7>;
vsc8531,led-0-mode = <LINK_1000_ACTIVITY>;
vsc8531,led-1-mode = <LINK_100_ACTIVITY>;
load-save-gpios = <&gpio 10 GPIO_ACTIVE_HIGH>;
};
......@@ -3,6 +3,7 @@
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/phy/phy-ocelot-serdes.h>
#include "ocelot.dtsi"
......@@ -25,6 +26,11 @@ phy_int_pins: phy_int_pins {
pins = "GPIO_4";
function = "gpio";
};
phy_load_save_pins: phy_load_save_pins {
pins = "GPIO_10";
function = "ptp2";
};
};
&mdio0 {
......@@ -34,27 +40,31 @@ &mdio0 {
&mdio1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&miim1>, <&phy_int_pins>;
pinctrl-0 = <&miim1>, <&phy_int_pins>, <&phy_load_save_pins>;
phy7: ethernet-phy@0 {
reg = <0>;
interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gpio>;
load-save-gpios = <&gpio 10 GPIO_ACTIVE_HIGH>;
};
phy6: ethernet-phy@1 {
reg = <1>;
interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gpio>;
load-save-gpios = <&gpio 10 GPIO_ACTIVE_HIGH>;
};
phy5: ethernet-phy@2 {
reg = <2>;
interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gpio>;
load-save-gpios = <&gpio 10 GPIO_ACTIVE_HIGH>;
};
phy4: ethernet-phy@3 {
reg = <3>;
interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gpio>;
load-save-gpios = <&gpio 10 GPIO_ACTIVE_HIGH>;
};
};
......
......@@ -8,3 +8,7 @@ mscc-objs := mscc_main.o
ifdef CONFIG_MACSEC
mscc-objs += mscc_macsec.o
endif
ifdef CONFIG_NETWORK_PHY_TIMESTAMPING
mscc-objs += mscc_ptp.o
endif
......@@ -133,6 +133,7 @@ enum rgmii_clock_delay {
* in the same package.
*/
#define MSCC_PHY_PAGE_EXTENDED_GPIO 0x0010 /* Extended reg - GPIO */
#define MSCC_PHY_PAGE_1588 0x1588 /* PTP (1588) */
#define MSCC_PHY_PAGE_TEST 0x2a30 /* Test reg */
#define MSCC_PHY_PAGE_TR 0x52b5 /* Token ring registers */
......@@ -252,6 +253,7 @@ enum rgmii_clock_delay {
/* Test page Registers */
#define MSCC_PHY_TEST_PAGE_5 5
#define MSCC_PHY_TEST_PAGE_8 8
#define TR_CLK_DISABLE 0x8000
#define MSCC_PHY_TEST_PAGE_9 9
#define MSCC_PHY_TEST_PAGE_20 20
#define MSCC_PHY_TEST_PAGE_24 24
......@@ -372,6 +374,35 @@ struct vsc8531_private {
unsigned long ingr_flows;
unsigned long egr_flows;
#endif
struct mii_timestamper mii_ts;
bool input_clk_init;
struct vsc85xx_ptp *ptp;
/* LOAD/SAVE GPIO pin, used for retrieving or setting time to the PHC. */
struct gpio_desc *load_save;
/* For multiple port PHYs; the MDIO address of the base PHY in the
* pair of two PHYs that share a 1588 engine. PHY0 and PHY2 are coupled.
* PHY1 and PHY3 as well. PHY0 and PHY1 are base PHYs for their
* respective pair.
*/
unsigned int ts_base_addr;
u8 ts_base_phy;
/* ts_lock: used for per-PHY timestamping operations.
* phc_lock: used for per-PHY PHC opertations.
*/
struct mutex ts_lock;
struct mutex phc_lock;
};
/* Shared structure between the PHYs of the same package.
* gpio_lock: used for PHC operations. Common for all PHYs as the load/save GPIO
* is shared.
*/
struct vsc85xx_shared_private {
struct mutex gpio_lock;
};
#if IS_ENABLED(CONFIG_OF_MDIO)
......@@ -398,4 +429,36 @@ static inline void vsc8584_config_macsec_intr(struct phy_device *phydev)
}
#endif
#if IS_ENABLED(CONFIG_NETWORK_PHY_TIMESTAMPING)
void vsc85xx_link_change_notify(struct phy_device *phydev);
void vsc8584_config_ts_intr(struct phy_device *phydev);
int vsc8584_ptp_init(struct phy_device *phydev);
int vsc8584_ptp_probe_once(struct phy_device *phydev);
int vsc8584_ptp_probe(struct phy_device *phydev);
irqreturn_t vsc8584_handle_ts_interrupt(struct phy_device *phydev);
#else
static inline void vsc85xx_link_change_notify(struct phy_device *phydev)
{
}
static inline void vsc8584_config_ts_intr(struct phy_device *phydev)
{
}
static inline int vsc8584_ptp_init(struct phy_device *phydev)
{
return 0;
}
static inline int vsc8584_ptp_probe_once(struct phy_device *phydev)
{
return 0;
}
static inline int vsc8584_ptp_probe(struct phy_device *phydev)
{
return 0;
}
static inline irqreturn_t vsc8584_handle_ts_interrupt(struct phy_device *phydev)
{
return IRQ_NONE;
}
#endif
#endif /* _MSCC_PHY_H_ */
......@@ -2,7 +2,7 @@
/*
* Driver for Microsemi VSC85xx PHYs
*
* Copyright (C) 2019 Microsemi Corporation
* Copyright (C) 2020 Microsemi Corporation
*/
#ifndef _MSCC_PHY_FC_BUFFER_H_
......
......@@ -2,7 +2,7 @@
/*
* Driver for Microsemi VSC85xx PHYs
*
* Copyright (c) 2017 Microsemi Corporation
* Copyright (c) 2020 Microsemi Corporation
*/
#ifndef _MSCC_PHY_LINE_MAC_H_
......
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Driver for Microsemi VSC85xx PHYs
* Driver for Microsemi VSC85xx PHYs - MACsec support
*
* Author: Nagaraju Lakkaraju
* Author: Antoine Tenart
* License: Dual MIT/GPL
* Copyright (c) 2016 Microsemi Corporation
* Copyright (c) 2020 Microsemi Corporation
*/
#include <linux/phy.h>
......@@ -285,7 +285,9 @@ static void vsc8584_macsec_mac_init(struct phy_device *phydev,
MSCC_MAC_CFG_PKTINF_CFG_STRIP_PREAMBLE_ENA |
MSCC_MAC_CFG_PKTINF_CFG_INSERT_PREAMBLE_ENA |
(bank == HOST_MAC ?
MSCC_MAC_CFG_PKTINF_CFG_ENABLE_TX_PADDING : 0));
MSCC_MAC_CFG_PKTINF_CFG_ENABLE_TX_PADDING : 0) |
(IS_ENABLED(CONFIG_NETWORK_PHY_TIMESTAMPING) ?
MSCC_MAC_CFG_PKTINF_CFG_MACSEC_BYPASS_NUM_PTP_STALL_CLKS(0x8) : 0));
val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MAC_CFG_MODE_CFG);
val &= ~MSCC_MAC_CFG_MODE_CFG_DISABLE_DIC;
......
......@@ -2,7 +2,7 @@
/*
* Driver for Microsemi VSC85xx PHYs
*
* Copyright (c) 2018 Microsemi Corporation
* Copyright (c) 2020 Microsemi Corporation
*/
#ifndef _MSCC_PHY_MACSEC_H_
......
......@@ -629,7 +629,7 @@ static int vsc8531_pre_init_seq_set(struct phy_device *phydev)
if (rc < 0)
return rc;
rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_TEST,
MSCC_PHY_TEST_PAGE_8, 0x8000, 0x8000);
MSCC_PHY_TEST_PAGE_8, TR_CLK_DISABLE, TR_CLK_DISABLE);
if (rc < 0)
return rc;
......@@ -1026,7 +1026,7 @@ static int vsc8574_config_pre_init(struct phy_device *phydev)
phy_base_write(phydev, MSCC_PHY_TEST_PAGE_5, 0x1b20);
reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
reg |= 0x8000;
reg |= TR_CLK_DISABLE;
phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);
......@@ -1046,7 +1046,7 @@ static int vsc8574_config_pre_init(struct phy_device *phydev)
phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);
reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
reg &= ~0x8000;
reg &= ~TR_CLK_DISABLE;
phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
......@@ -1196,7 +1196,7 @@ static int vsc8584_config_pre_init(struct phy_device *phydev)
phy_base_write(phydev, MSCC_PHY_TEST_PAGE_5, 0x1f20);
reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
reg |= 0x8000;
reg |= TR_CLK_DISABLE;
phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);
......@@ -1225,7 +1225,7 @@ static int vsc8584_config_pre_init(struct phy_device *phydev)
phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);
reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
reg &= ~0x8000;
reg &= ~TR_CLK_DISABLE;
phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
......@@ -1299,10 +1299,26 @@ static void vsc8584_get_base_addr(struct phy_device *phydev)
__phy_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
mutex_unlock(&phydev->mdio.bus->mdio_lock);
if (val & PHY_ADDR_REVERSED)
/* In the package, there are two pairs of PHYs (PHY0 + PHY2 and
* PHY1 + PHY3). The first PHY of each pair (PHY0 and PHY1) is
* the base PHY for timestamping operations.
*/
vsc8531->ts_base_addr = phydev->mdio.addr;
vsc8531->ts_base_phy = addr;
if (val & PHY_ADDR_REVERSED) {
vsc8531->base_addr = phydev->mdio.addr + addr;
else
if (addr > 1) {
vsc8531->ts_base_addr += 2;
vsc8531->ts_base_phy += 2;
}
} else {
vsc8531->base_addr = phydev->mdio.addr - addr;
if (addr > 1) {
vsc8531->ts_base_addr -= 2;
vsc8531->ts_base_phy -= 2;
}
}
vsc8531->addr = addr;
}
......@@ -1418,6 +1434,10 @@ static int vsc8584_config_init(struct phy_device *phydev)
if (ret)
return ret;
ret = vsc8584_ptp_init(phydev);
if (ret)
goto err;
phy_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
val = phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_1);
......@@ -1455,12 +1475,20 @@ static int vsc8584_config_init(struct phy_device *phydev)
static irqreturn_t vsc8584_handle_interrupt(struct phy_device *phydev)
{
irqreturn_t ret;
int irq_status;
irq_status = phy_read(phydev, MII_VSC85XX_INT_STATUS);
if (irq_status < 0 || !(irq_status & MII_VSC85XX_INT_MASK_MASK))
if (irq_status < 0)
return IRQ_NONE;
/* Timestamping IRQ does not set a bit in the global INT_STATUS, so
* irq_status would be 0.
*/
ret = vsc8584_handle_ts_interrupt(phydev);
if (!(irq_status & MII_VSC85XX_INT_MASK_MASK))
return ret;
if (irq_status & MII_VSC85XX_INT_MASK_EXT)
vsc8584_handle_macsec_interrupt(phydev);
......@@ -1900,6 +1928,7 @@ static int vsc85xx_config_intr(struct phy_device *phydev)
if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
vsc8584_config_macsec_intr(phydev);
vsc8584_config_ts_intr(phydev);
rc = phy_write(phydev, MII_VSC85XX_INT_MASK,
MII_VSC85XX_INT_MASK_MASK);
......@@ -1999,6 +2028,7 @@ static int vsc8584_probe(struct phy_device *phydev)
u32 default_mode[4] = {VSC8531_LINK_1000_ACTIVITY,
VSC8531_LINK_100_ACTIVITY, VSC8531_LINK_ACTIVITY,
VSC8531_DUPLEX_COLLISION};
int ret;
if ((phydev->phy_id & MSCC_DEV_REV_MASK) != VSC8584_REVB) {
dev_err(&phydev->mdio.dev, "Only VSC8584 revB is supported.\n");
......@@ -2012,8 +2042,8 @@ static int vsc8584_probe(struct phy_device *phydev)
phydev->priv = vsc8531;
vsc8584_get_base_addr(phydev);
devm_phy_package_join(&phydev->mdio.dev, phydev,
vsc8531->base_addr, 0);
devm_phy_package_join(&phydev->mdio.dev, phydev, vsc8531->base_addr,
sizeof(struct vsc85xx_shared_private));
vsc8531->nleds = 4;
vsc8531->supp_led_modes = VSC8584_SUPP_LED_MODES;
......@@ -2024,6 +2054,16 @@ static int vsc8584_probe(struct phy_device *phydev)
if (!vsc8531->stats)
return -ENOMEM;
if (phy_package_probe_once(phydev)) {
ret = vsc8584_ptp_probe_once(phydev);
if (ret)
return ret;
}
ret = vsc8584_ptp_probe(phydev);
if (ret)
return ret;
return vsc85xx_dt_led_modes_get(phydev, default_mode);
}
......@@ -2403,6 +2443,7 @@ static struct phy_driver vsc85xx_driver[] = {
.get_sset_count = &vsc85xx_get_sset_count,
.get_strings = &vsc85xx_get_strings,
.get_stats = &vsc85xx_get_stats,
.link_change_notify = &vsc85xx_link_change_notify,
}
};
......
This diff is collapsed.
This diff is collapsed.
......@@ -245,6 +245,7 @@ struct phy_package_shared {
/* used as bit number in atomic bitops */
#define PHY_SHARED_F_INIT_DONE 0
#define PHY_SHARED_F_PROBE_DONE 1
/*
* The Bus class for PHYs. Devices which provide access to
......@@ -1566,14 +1567,25 @@ static inline int __phy_package_write(struct phy_device *phydev,
return __mdiobus_write(phydev->mdio.bus, shared->addr, regnum, val);
}
static inline bool phy_package_init_once(struct phy_device *phydev)
static inline bool __phy_package_set_once(struct phy_device *phydev,
unsigned int b)
{
struct phy_package_shared *shared = phydev->shared;
if (!shared)
return false;
return !test_and_set_bit(PHY_SHARED_F_INIT_DONE, &shared->flags);
return !test_and_set_bit(b, &shared->flags);
}
static inline bool phy_package_init_once(struct phy_device *phydev)
{
return __phy_package_set_once(phydev, PHY_SHARED_F_INIT_DONE);
}
static inline bool phy_package_probe_once(struct phy_device *phydev)
{
return __phy_package_set_once(phydev, PHY_SHARED_F_PROBE_DONE);
}
extern struct bus_type mdio_bus_type;
......
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