Commit b5568894 authored by Marc Zyngier's avatar Marc Zyngier

KVM: arm64: Move SVCR into the sysreg array

SVCR is just a system register, and has no purpose being outside
of the sysreg array. If anything, it only makes it more difficult
to eventually support SME one day. If ever.

Move it into the array with its little friends, and associate it
with a visibility predicate.

Although this is dead code, it at least paves the way for the
next set of FP-related extensions.
Reviewed-by: default avatarMark Brown <broonie@kernel.org>
Tested-by: default avatarMark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20240820131802.3547589-2-maz@kernel.orgSigned-off-by: default avatarMarc Zyngier <maz@kernel.org>
parent 8400291e
...@@ -446,6 +446,9 @@ enum vcpu_sysreg { ...@@ -446,6 +446,9 @@ enum vcpu_sysreg {
GCR_EL1, /* Tag Control Register */ GCR_EL1, /* Tag Control Register */
TFSRE0_EL1, /* Tag Fault Status Register (EL0) */ TFSRE0_EL1, /* Tag Fault Status Register (EL0) */
/* FP/SIMD/SVE */
SVCR,
/* 32bit specific registers. */ /* 32bit specific registers. */
DACR32_EL2, /* Domain Access Control Register */ DACR32_EL2, /* Domain Access Control Register */
IFSR32_EL2, /* Instruction Fault Status Register */ IFSR32_EL2, /* Instruction Fault Status Register */
...@@ -664,7 +667,6 @@ struct kvm_vcpu_arch { ...@@ -664,7 +667,6 @@ struct kvm_vcpu_arch {
void *sve_state; void *sve_state;
enum fp_type fp_type; enum fp_type fp_type;
unsigned int sve_max_vl; unsigned int sve_max_vl;
u64 svcr;
u64 fpmr; u64 fpmr;
/* Stage 2 paging state used by the hardware on next switch */ /* Stage 2 paging state used by the hardware on next switch */
......
...@@ -134,7 +134,7 @@ void kvm_arch_vcpu_ctxsync_fp(struct kvm_vcpu *vcpu) ...@@ -134,7 +134,7 @@ void kvm_arch_vcpu_ctxsync_fp(struct kvm_vcpu *vcpu)
fp_state.sve_state = vcpu->arch.sve_state; fp_state.sve_state = vcpu->arch.sve_state;
fp_state.sve_vl = vcpu->arch.sve_max_vl; fp_state.sve_vl = vcpu->arch.sve_max_vl;
fp_state.sme_state = NULL; fp_state.sme_state = NULL;
fp_state.svcr = &vcpu->arch.svcr; fp_state.svcr = &__vcpu_sys_reg(vcpu, SVCR);
fp_state.fpmr = &vcpu->arch.fpmr; fp_state.fpmr = &vcpu->arch.fpmr;
fp_state.fp_type = &vcpu->arch.fp_type; fp_state.fp_type = &vcpu->arch.fp_type;
......
...@@ -1669,6 +1669,15 @@ static unsigned int sve_visibility(const struct kvm_vcpu *vcpu, ...@@ -1669,6 +1669,15 @@ static unsigned int sve_visibility(const struct kvm_vcpu *vcpu,
return REG_HIDDEN; return REG_HIDDEN;
} }
static unsigned int sme_visibility(const struct kvm_vcpu *vcpu,
const struct sys_reg_desc *rd)
{
if (kvm_has_feat(vcpu->kvm, ID_AA64PFR1_EL1, SME, IMP))
return 0;
return REG_HIDDEN;
}
static u64 read_sanitised_id_aa64pfr0_el1(struct kvm_vcpu *vcpu, static u64 read_sanitised_id_aa64pfr0_el1(struct kvm_vcpu *vcpu,
const struct sys_reg_desc *rd) const struct sys_reg_desc *rd)
{ {
...@@ -2535,7 +2544,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { ...@@ -2535,7 +2544,7 @@ static const struct sys_reg_desc sys_reg_descs[] = {
CTR_EL0_IDC_MASK | CTR_EL0_IDC_MASK |
CTR_EL0_DminLine_MASK | CTR_EL0_DminLine_MASK |
CTR_EL0_IminLine_MASK), CTR_EL0_IminLine_MASK),
{ SYS_DESC(SYS_SVCR), undef_access }, { SYS_DESC(SYS_SVCR), undef_access, reset_val, SVCR, 0, .visibility = sme_visibility },
{ PMU_SYS_REG(PMCR_EL0), .access = access_pmcr, .reset = reset_pmcr, { PMU_SYS_REG(PMCR_EL0), .access = access_pmcr, .reset = reset_pmcr,
.reg = PMCR_EL0, .get_user = get_pmcr, .set_user = set_pmcr }, .reg = PMCR_EL0, .get_user = get_pmcr, .set_user = set_pmcr },
......
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