Commit b61adeed authored by Ping-Ke Shih's avatar Ping-Ke Shih Committed by Kalle Valo

rtw89: 8852c: update security engine setting

The security setting of 8852A and 8852C are different, so change the
settings accordingly.
Signed-off-by: default avatarPing-Ke Shih <pkshih@realtek.com>
Signed-off-by: default avatarKalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20220325060055.58482-13-pkshih@realtek.com
parent 5cb5562d
...@@ -1620,6 +1620,7 @@ static int mpdu_proc_init(struct rtw89_dev *rtwdev) ...@@ -1620,6 +1620,7 @@ static int mpdu_proc_init(struct rtw89_dev *rtwdev)
static int sec_eng_init(struct rtw89_dev *rtwdev) static int sec_eng_init(struct rtw89_dev *rtwdev)
{ {
const struct rtw89_chip_info *chip = rtwdev->chip;
u32 val = 0; u32 val = 0;
int ret; int ret;
...@@ -1633,6 +1634,7 @@ static int sec_eng_init(struct rtw89_dev *rtwdev) ...@@ -1633,6 +1634,7 @@ static int sec_eng_init(struct rtw89_dev *rtwdev)
/* init TX encryption */ /* init TX encryption */
val |= (B_AX_SEC_TX_ENC | B_AX_SEC_RX_DEC); val |= (B_AX_SEC_TX_ENC | B_AX_SEC_RX_DEC);
val |= (B_AX_MC_DEC | B_AX_BC_DEC); val |= (B_AX_MC_DEC | B_AX_BC_DEC);
if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B)
val &= ~B_AX_TX_PARTIAL_MODE; val &= ~B_AX_TX_PARTIAL_MODE;
rtw89_write32(rtwdev, R_AX_SEC_ENG_CTRL, val); rtw89_write32(rtwdev, R_AX_SEC_ENG_CTRL, val);
...@@ -1643,6 +1645,10 @@ static int sec_eng_init(struct rtw89_dev *rtwdev) ...@@ -1643,6 +1645,10 @@ static int sec_eng_init(struct rtw89_dev *rtwdev)
/* option init */ /* option init */
rtw89_write32(rtwdev, R_AX_SEC_MPDU_PROC, val); rtw89_write32(rtwdev, R_AX_SEC_MPDU_PROC, val);
if (chip->chip_id == RTL8852C)
rtw89_write32_mask(rtwdev, R_AX_SEC_DEBUG1,
B_AX_TX_TIMEOUT_SEL_MASK, AX_TX_TO_VAL);
return 0; return 0;
} }
......
...@@ -799,6 +799,9 @@ ...@@ -799,6 +799,9 @@
#define R_AX_SEC_CAM_RDATA 0x9D14 #define R_AX_SEC_CAM_RDATA 0x9D14
#define R_AX_SEC_CAM_WDATA 0x9D18 #define R_AX_SEC_CAM_WDATA 0x9D18
#define R_AX_SEC_DEBUG 0x9D1C #define R_AX_SEC_DEBUG 0x9D1C
#define R_AX_SEC_DEBUG1 0x9D1C
#define B_AX_TX_TIMEOUT_SEL_MASK GENMASK(31, 30)
#define AX_TX_TO_VAL 0x2
#define R_AX_SEC_TX_DEBUG 0x9D20 #define R_AX_SEC_TX_DEBUG 0x9D20
#define R_AX_SEC_RX_DEBUG 0x9D24 #define R_AX_SEC_RX_DEBUG 0x9D24
#define R_AX_SEC_TRX_PKT_CNT 0x9D28 #define R_AX_SEC_TRX_PKT_CNT 0x9D28
......
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