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Commit b8889c4f authored by Linus Torvalds's avatar Linus Torvalds
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Merge tag 'tty-4.3-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty 

Pull tty driver reverts from Greg KH:
 "Here are some reverts for some tty patches (specifically the pl011
  driver) that ended up breaking a bunch of machines (i.e. almost all
  of the ones with this chip).

  People are working on a fix for this, but in the meantime, it's best
  to just revert all 5 patches to restore people's serial consoles.

  These reverts have been in linux-next for many days now"

* tag 'tty-4.3-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty:
  Revert "uart: pl011: Rename regs with enumeration"
  Revert "uart: pl011: Introduce register accessor"
  Revert "uart: pl011: Introduce register look up table"
  Revert "uart: pl011: Improve LCRH register access decision"
  Revert "uart: pl011: Add support to ZTE ZX296702 uart"
parents fac33bfd 0de6cfb9
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drivers/tty/serial/Kconfig
View file @ b8889c4f
......@@ -47,12 +47,12 @@ config SERIAL_AMBA_PL010_CONSOLE
config SERIAL_AMBA_PL011
tristate "ARM AMBA PL011 serial port support"
depends on ARM_AMBA || SOC_ZX296702
depends on ARM_AMBA
select SERIAL_CORE
help
This selects the ARM(R) AMBA(R) PrimeCell PL011 UART. If you have
an Integrator/PP2, Integrator/CP or Versatile platform, say Y or M
here. Say Y or M if you have SOC_ZX296702.
here.
If unsure, say N.
......
drivers/tty/serial/amba-pl011.c
View file @ b8889c4f
......@@ -74,13 +74,8 @@
/* There is by now at least one vendor with differing details, so handle it */
struct vendor_data {
unsigned int ifls;
unsigned int fr_busy;
unsigned int fr_dsr;
unsigned int fr_cts;
unsigned int fr_ri;
unsigned int lcrh_tx;
unsigned int lcrh_rx;
u16 *reg_lut;
bool oversampling;
bool dma_threshold;
bool cts_event_workaround;
......@@ -90,48 +85,6 @@ struct vendor_data {
unsigned int (*get_fifosize)(struct amba_device *dev);
};
/* Max address offset of register in use is 0x48 */
#define REG_NR (0x48 >> 2)
#define IDX(x) (x >> 2)
enum reg_idx {
REG_DR = IDX(UART01x_DR),
REG_RSR = IDX(UART01x_RSR),
REG_ST_DMAWM = IDX(ST_UART011_DMAWM),
REG_FR = IDX(UART01x_FR),
REG_ST_LCRH_RX = IDX(ST_UART011_LCRH_RX),
REG_ILPR = IDX(UART01x_ILPR),
REG_IBRD = IDX(UART011_IBRD),
REG_FBRD = IDX(UART011_FBRD),
REG_LCRH = IDX(UART011_LCRH),
REG_CR = IDX(UART011_CR),
REG_IFLS = IDX(UART011_IFLS),
REG_IMSC = IDX(UART011_IMSC),
REG_RIS = IDX(UART011_RIS),
REG_MIS = IDX(UART011_MIS),
REG_ICR = IDX(UART011_ICR),
REG_DMACR = IDX(UART011_DMACR),
};
static u16 arm_reg[] = {
[REG_DR] = UART01x_DR,
[REG_RSR] = UART01x_RSR,
[REG_ST_DMAWM] = ~0,
[REG_FR] = UART01x_FR,
[REG_ST_LCRH_RX] = ~0,
[REG_ILPR] = UART01x_ILPR,
[REG_IBRD] = UART011_IBRD,
[REG_FBRD] = UART011_FBRD,
[REG_LCRH] = UART011_LCRH,
[REG_CR] = UART011_CR,
[REG_IFLS] = UART011_IFLS,
[REG_IMSC] = UART011_IMSC,
[REG_RIS] = UART011_RIS,
[REG_MIS] = UART011_MIS,
[REG_ICR] = UART011_ICR,
[REG_DMACR] = UART011_DMACR,
};
#ifdef CONFIG_ARM_AMBA
static unsigned int get_fifosize_arm(struct amba_device *dev)
{
return amba_rev(dev) < 3 ? 16 : 32;
......@@ -139,13 +92,8 @@ static unsigned int get_fifosize_arm(struct amba_device *dev)
static struct vendor_data vendor_arm = {
.ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
.fr_busy = UART01x_FR_BUSY,
.fr_dsr = UART01x_FR_DSR,
.fr_cts = UART01x_FR_CTS,
.fr_ri = UART011_FR_RI,
.lcrh_tx = REG_LCRH,
.lcrh_rx = REG_LCRH,
.reg_lut = arm_reg,
.lcrh_tx = UART011_LCRH,
.lcrh_rx = UART011_LCRH,
.oversampling = false,
.dma_threshold = false,
.cts_event_workaround = false,
......@@ -153,14 +101,8 @@ static struct vendor_data vendor_arm = {
.fixed_options = false,
.get_fifosize = get_fifosize_arm,
};
#endif
static struct vendor_data vendor_sbsa = {
.fr_busy = UART01x_FR_BUSY,
.fr_dsr = UART01x_FR_DSR,
.fr_cts = UART01x_FR_CTS,
.fr_ri = UART011_FR_RI,
.reg_lut = arm_reg,
.oversampling = false,
.dma_threshold = false,
.cts_event_workaround = false,
......@@ -168,26 +110,6 @@ static struct vendor_data vendor_sbsa = {
.fixed_options = true,
};
#ifdef CONFIG_ARM_AMBA
static u16 st_reg[] = {
[REG_DR] = UART01x_DR,
[REG_RSR] = UART01x_RSR,
[REG_ST_DMAWM] = ST_UART011_DMAWM,
[REG_FR] = UART01x_FR,
[REG_ST_LCRH_RX] = ST_UART011_LCRH_RX,
[REG_ILPR] = UART01x_ILPR,
[REG_IBRD] = UART011_IBRD,
[REG_FBRD] = UART011_FBRD,
[REG_LCRH] = UART011_LCRH,
[REG_CR] = UART011_CR,
[REG_IFLS] = UART011_IFLS,
[REG_IMSC] = UART011_IMSC,
[REG_RIS] = UART011_RIS,
[REG_MIS] = UART011_MIS,
[REG_ICR] = UART011_ICR,
[REG_DMACR] = UART011_DMACR,
};
static unsigned int get_fifosize_st(struct amba_device *dev)
{
return 64;
......@@ -195,13 +117,8 @@ static unsigned int get_fifosize_st(struct amba_device *dev)
static struct vendor_data vendor_st = {
.ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF,
.fr_busy = UART01x_FR_BUSY,
.fr_dsr = UART01x_FR_DSR,
.fr_cts = UART01x_FR_CTS,
.fr_ri = UART011_FR_RI,
.lcrh_tx = REG_LCRH,
.lcrh_rx = REG_ST_LCRH_RX,
.reg_lut = st_reg,
.lcrh_tx = ST_UART011_LCRH_TX,
.lcrh_rx = ST_UART011_LCRH_RX,
.oversampling = true,
.dma_threshold = true,
.cts_event_workaround = true,
......@@ -209,43 +126,6 @@ static struct vendor_data vendor_st = {
.fixed_options = false,
.get_fifosize = get_fifosize_st,
};
#endif
#ifdef CONFIG_SOC_ZX296702
static u16 zte_reg[] = {
[REG_DR] = ZX_UART01x_DR,
[REG_RSR] = UART01x_RSR,
[REG_ST_DMAWM] = ST_UART011_DMAWM,
[REG_FR] = ZX_UART01x_FR,
[REG_ST_LCRH_RX] = ST_UART011_LCRH_RX,
[REG_ILPR] = UART01x_ILPR,
[REG_IBRD] = UART011_IBRD,
[REG_FBRD] = UART011_FBRD,
[REG_LCRH] = ZX_UART011_LCRH_TX,
[REG_CR] = ZX_UART011_CR,
[REG_IFLS] = ZX_UART011_IFLS,
[REG_IMSC] = ZX_UART011_IMSC,
[REG_RIS] = ZX_UART011_RIS,
[REG_MIS] = ZX_UART011_MIS,
[REG_ICR] = ZX_UART011_ICR,
[REG_DMACR] = ZX_UART011_DMACR,
};
static struct vendor_data vendor_zte = {
.ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
.fr_busy = ZX_UART01x_FR_BUSY,
.fr_dsr = ZX_UART01x_FR_DSR,
.fr_cts = ZX_UART01x_FR_CTS,
.fr_ri = ZX_UART011_FR_RI,
.lcrh_tx = REG_LCRH,
.lcrh_rx = REG_ST_LCRH_RX,
.reg_lut = zte_reg,
.oversampling = false,
.dma_threshold = false,
.cts_event_workaround = false,
.fixed_options = false,
};
#endif
/* Deals with DMA transactions */
......@@ -284,15 +164,10 @@ struct uart_amba_port {
struct uart_port port;
struct clk *clk;
const struct vendor_data *vendor;
u16 *reg_lut;
unsigned int dmacr; /* dma control reg */
unsigned int im; /* interrupt mask */
unsigned int old_status;
unsigned int fifosize; /* vendor-specific */
unsigned int fr_busy; /* vendor-specific */
unsigned int fr_dsr; /* vendor-specific */
unsigned int fr_cts; /* vendor-specific */
unsigned int fr_ri; /* vendor-specific */
unsigned int lcrh_tx; /* vendor-specific */
unsigned int lcrh_rx; /* vendor-specific */
unsigned int old_cr; /* state during shutdown */
......@@ -309,29 +184,6 @@ struct uart_amba_port {
#endif
};
static bool is_implemented(struct uart_amba_port *uap, unsigned int reg)
{
return uap->reg_lut[reg] != (u16)~0;
}
static unsigned int pl011_readw(struct uart_amba_port *uap, int index)
{
WARN_ON(index > REG_NR);
return readw_relaxed(uap->port.membase + uap->reg_lut[index]);
}
static void pl011_writew(struct uart_amba_port *uap, int val, int index)
{
WARN_ON(index > REG_NR);
writew_relaxed(val, uap->port.membase + uap->reg_lut[index]);
}
static void pl011_writeb(struct uart_amba_port *uap, u8 val, int index)
{
WARN_ON(index > REG_NR);
writeb_relaxed(val, uap->port.membase + uap->reg_lut[index]);
}
/*
* Reads up to 256 characters from the FIFO or until it's empty and
* inserts them into the TTY layer. Returns the number of characters
......@@ -344,12 +196,12 @@ static int pl011_fifo_to_tty(struct uart_amba_port *uap)
int fifotaken = 0;
while (max_count--) {
status = pl011_readw(uap, REG_FR);
status = readw(uap->port.membase + UART01x_FR);
if (status & UART01x_FR_RXFE)
break;
/* Take chars from the FIFO and update status */
ch = pl011_readw(uap, REG_DR) |
ch = readw(uap->port.membase + UART01x_DR) |
UART_DUMMY_DR_RX;
flag = TTY_NORMAL;
uap->port.icount.rx++;
......@@ -432,7 +284,7 @@ static void pl011_dma_probe(struct uart_amba_port *uap)
struct amba_pl011_data *plat = dev_get_platdata(uap->port.dev);
struct device *dev = uap->port.dev;
struct dma_slave_config tx_conf = {
.dst_addr = uap->port.mapbase + uap->reg_lut[REG_DR],
.dst_addr = uap->port.mapbase + UART01x_DR,
.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
.direction = DMA_MEM_TO_DEV,
.dst_maxburst = uap->fifosize >> 1,
......@@ -487,7 +339,7 @@ static void pl011_dma_probe(struct uart_amba_port *uap)
if (chan) {
struct dma_slave_config rx_conf = {
.src_addr = uap->port.mapbase + uap->reg_lut[REG_DR],
.src_addr = uap->port.mapbase + UART01x_DR,
.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
.direction = DMA_DEV_TO_MEM,
.src_maxburst = uap->fifosize >> 2,
......@@ -586,7 +438,7 @@ static void pl011_dma_tx_callback(void *data)
dmacr = uap->dmacr;
uap->dmacr = dmacr & ~UART011_TXDMAE;
pl011_writew(uap, uap->dmacr, REG_DMACR);
writew(uap->dmacr, uap->port.membase + UART011_DMACR);
/*
* If TX DMA was disabled, it means that we've stopped the DMA for
......@@ -700,7 +552,7 @@ static int pl011_dma_tx_refill(struct uart_amba_port *uap)
dma_dev->device_issue_pending(chan);
uap->dmacr |= UART011_TXDMAE;
pl011_writew(uap, uap->dmacr, REG_DMACR);
writew(uap->dmacr, uap->port.membase + UART011_DMACR);
uap->dmatx.queued = true;
/*
......@@ -736,9 +588,9 @@ static bool pl011_dma_tx_irq(struct uart_amba_port *uap)
*/
if (uap->dmatx.queued) {
uap->dmacr |= UART011_TXDMAE;
pl011_writew(uap, uap->dmacr, REG_DMACR);
writew(uap->dmacr, uap->port.membase + UART011_DMACR);
uap->im &= ~UART011_TXIM;
pl011_writew(uap, uap->im, REG_IMSC);
writew(uap->im, uap->port.membase + UART011_IMSC);
return true;
}
......@@ -748,7 +600,7 @@ static bool pl011_dma_tx_irq(struct uart_amba_port *uap)
*/
if (pl011_dma_tx_refill(uap) > 0) {
uap->im &= ~UART011_TXIM;
pl011_writew(uap, uap->im, REG_IMSC);
writew(uap->im, uap->port.membase + UART011_IMSC);
return true;
}
return false;
......@@ -762,7 +614,7 @@ static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
{
if (uap->dmatx.queued) {
uap->dmacr &= ~UART011_TXDMAE;
pl011_writew(uap, uap->dmacr, REG_DMACR);
writew(uap->dmacr, uap->port.membase + UART011_DMACR);
}
}
......@@ -788,12 +640,14 @@ static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
if (!uap->dmatx.queued) {
if (pl011_dma_tx_refill(uap) > 0) {
uap->im &= ~UART011_TXIM;
pl011_writew(uap, uap->im, REG_IMSC);
writew(uap->im, uap->port.membase +
UART011_IMSC);
} else
ret = false;
} else if (!(uap->dmacr & UART011_TXDMAE)) {
uap->dmacr |= UART011_TXDMAE;
pl011_writew(uap, uap->dmacr, REG_DMACR);
writew(uap->dmacr,
uap->port.membase + UART011_DMACR);
}
return ret;
}
......@@ -804,9 +658,9 @@ static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
*/
dmacr = uap->dmacr;
uap->dmacr &= ~UART011_TXDMAE;
pl011_writew(uap, uap->dmacr, REG_DMACR);
writew(uap->dmacr, uap->port.membase + UART011_DMACR);
if (pl011_readw(uap, REG_FR) & UART01x_FR_TXFF) {
if (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF) {
/*
* No space in the FIFO, so enable the transmit interrupt
* so we know when there is space. Note that once we've
......@@ -815,13 +669,13 @@ static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
return false;
}
pl011_writew(uap, uap->port.x_char, REG_DR);
writew(uap->port.x_char, uap->port.membase + UART01x_DR);
uap->port.icount.tx++;
uap->port.x_char = 0;
/* Success - restore the DMA state */
uap->dmacr = dmacr;
pl011_writew(uap, dmacr, REG_DMACR);
writew(dmacr, uap->port.membase + UART011_DMACR);
return true;
}
......@@ -849,7 +703,7 @@ __acquires(&uap->port.lock)
DMA_TO_DEVICE);
uap->dmatx.queued = false;
uap->dmacr &= ~UART011_TXDMAE;
pl011_writew(uap, uap->dmacr, REG_DMACR);
writew(uap->dmacr, uap->port.membase + UART011_DMACR);
}
}
......@@ -889,11 +743,11 @@ static int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
dma_async_issue_pending(rxchan);
uap->dmacr |= UART011_RXDMAE;
pl011_writew(uap, uap->dmacr, REG_DMACR);
writew(uap->dmacr, uap->port.membase + UART011_DMACR);
uap->dmarx.running = true;
uap->im &= ~UART011_RXIM;
pl011_writew(uap, uap->im, REG_IMSC);
writew(uap->im, uap->port.membase + UART011_IMSC);
return 0;
}
......@@ -951,9 +805,8 @@ static void pl011_dma_rx_chars(struct uart_amba_port *uap,
*/
if (dma_count == pending && readfifo) {
/* Clear any error flags */
pl011_writew(uap,
UART011_OEIS | UART011_BEIS | UART011_PEIS
| UART011_FEIS, REG_ICR);
writew(UART011_OEIS | UART011_BEIS | UART011_PEIS | UART011_FEIS,
uap->port.membase + UART011_ICR);
/*
* If we read all the DMA'd characters, and we had an
......@@ -1001,7 +854,7 @@ static void pl011_dma_rx_irq(struct uart_amba_port *uap)
/* Disable RX DMA - incoming data will wait in the FIFO */
uap->dmacr &= ~UART011_RXDMAE;
pl011_writew(uap, uap->dmacr, REG_DMACR);
writew(uap->dmacr, uap->port.membase + UART011_DMACR);
uap->dmarx.running = false;
pending = sgbuf->sg.length - state.residue;
......@@ -1021,7 +874,7 @@ static void pl011_dma_rx_irq(struct uart_amba_port *uap)
dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
"fall back to interrupt mode\n");
uap->im |= UART011_RXIM;
pl011_writew(uap, uap->im, REG_IMSC);
writew(uap->im, uap->port.membase + UART011_IMSC);
}
}
......@@ -1069,7 +922,7 @@ static void pl011_dma_rx_callback(void *data)
dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
"fall back to interrupt mode\n");
uap->im |= UART011_RXIM;
pl011_writew(uap, uap->im, REG_IMSC);
writew(uap->im, uap->port.membase + UART011_IMSC);
}
}
......@@ -1082,7 +935,7 @@ static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
{
/* FIXME. Just disable the DMA enable */
uap->dmacr &= ~UART011_RXDMAE;
pl011_writew(uap, uap->dmacr, REG_DMACR);
writew(uap->dmacr, uap->port.membase + UART011_DMACR);
}
/*
......@@ -1126,7 +979,7 @@ static void pl011_dma_rx_poll(unsigned long args)
spin_lock_irqsave(&uap->port.lock, flags);
pl011_dma_rx_stop(uap);
uap->im |= UART011_RXIM;
pl011_writew(uap, uap->im, REG_IMSC);
writew(uap->im, uap->port.membase + UART011_IMSC);
spin_unlock_irqrestore(&uap->port.lock, flags);
uap->dmarx.running = false;
......@@ -1188,7 +1041,7 @@ static void pl011_dma_startup(struct uart_amba_port *uap)
skip_rx:
/* Turn on DMA error (RX/TX will be enabled on demand) */
uap->dmacr |= UART011_DMAONERR;
pl011_writew(uap, uap->dmacr, REG_DMACR);
writew(uap->dmacr, uap->port.membase + UART011_DMACR);
/*
* ST Micro variants has some specific dma burst threshold
......@@ -1196,9 +1049,8 @@ static void pl011_dma_startup(struct uart_amba_port *uap)
* be issued above/below 16 bytes.
*/
if (uap->vendor->dma_threshold)
pl011_writew(uap,
ST_UART011_DMAWM_RX_16 | ST_UART011_DMAWM_TX_16,
REG_ST_DMAWM);
writew(ST_UART011_DMAWM_RX_16 | ST_UART011_DMAWM_TX_16,
uap->port.membase + ST_UART011_DMAWM);
if (uap->using_rx_dma) {
if (pl011_dma_rx_trigger_dma(uap))
......@@ -1223,12 +1075,12 @@ static void pl011_dma_shutdown(struct uart_amba_port *uap)
return;
/* Disable RX and TX DMA */
while (pl011_readw(uap, REG_FR) & uap->fr_busy)
while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY)
barrier();
spin_lock_irq(&uap->port.lock);
uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE);
pl011_writew(uap, uap->dmacr, REG_DMACR);
writew(uap->dmacr, uap->port.membase + UART011_DMACR);
spin_unlock_irq(&uap->port.lock);
if (uap->using_tx_dma) {
......@@ -1329,7 +1181,7 @@ static void pl011_stop_tx(struct uart_port *port)
container_of(port, struct uart_amba_port, port);
uap->im &= ~UART011_TXIM;
pl011_writew(uap, uap->im, REG_IMSC);
writew(uap->im, uap->port.membase + UART011_IMSC);
pl011_dma_tx_stop(uap);
}
......@@ -1339,7 +1191,7 @@ static void pl011_tx_chars(struct uart_amba_port *uap, bool from_irq);
static void pl011_start_tx_pio(struct uart_amba_port *uap)
{
uap->im |= UART011_TXIM;
pl011_writew(uap, uap->im, REG_IMSC);
writew(uap->im, uap->port.membase + UART011_IMSC);
pl011_tx_chars(uap, false);
}
......@@ -1359,7 +1211,7 @@ static void pl011_stop_rx(struct uart_port *port)
uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM|
UART011_PEIM|UART011_BEIM|UART011_OEIM);
pl011_writew(uap, uap->im, REG_IMSC);
writew(uap->im, uap->port.membase + UART011_IMSC);
pl011_dma_rx_stop(uap);
}
......@@ -1370,7 +1222,7 @@ static void pl011_enable_ms(struct uart_port *port)
container_of(port, struct uart_amba_port, port);
uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM;
pl011_writew(uap, uap->im, REG_IMSC);
writew(uap->im, uap->port.membase + UART011_IMSC);
}
static void pl011_rx_chars(struct uart_amba_port *uap)
......@@ -1390,7 +1242,7 @@ __acquires(&uap->port.lock)
dev_dbg(uap->port.dev, "could not trigger RX DMA job "
"fall back to interrupt mode again\n");
uap->im |= UART011_RXIM;
pl011_writew(uap, uap->im, REG_IMSC);
writew(uap->im, uap->port.membase + UART011_IMSC);
} else {
#ifdef CONFIG_DMA_ENGINE
/* Start Rx DMA poll */
......@@ -1411,10 +1263,10 @@ static bool pl011_tx_char(struct uart_amba_port *uap, unsigned char c,
bool from_irq)
{
if (unlikely(!from_irq) &&
pl011_readw(uap, REG_FR) & UART01x_FR_TXFF)
readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF)
return false; /* unable to transmit character */
pl011_writew(uap, c, REG_DR);
writew(c, uap->port.membase + UART01x_DR);
uap->port.icount.tx++;
return true;
......@@ -1461,7 +1313,7 @@ static void pl011_modem_status(struct uart_amba_port *uap)
{
unsigned int status, delta;
status = pl011_readw(uap, REG_FR) & UART01x_FR_MODEM_ANY;
status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
delta = status ^ uap->old_status;
uap->old_status = status;
......@@ -1472,11 +1324,11 @@ static void pl011_modem_status(struct uart_amba_port *uap)
if (delta & UART01x_FR_DCD)
uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD);
if (delta & uap->fr_dsr)
if (delta & UART01x_FR_DSR)
uap->port.icount.dsr++;
if (delta & uap->fr_cts)
uart_handle_cts_change(&uap->port, status & uap->fr_cts);
if (delta & UART01x_FR_CTS)
uart_handle_cts_change(&uap->port, status & UART01x_FR_CTS);
wake_up_interruptible(&uap->port.state->port.delta_msr_wait);
}
......@@ -1489,15 +1341,15 @@ static void check_apply_cts_event_workaround(struct uart_amba_port *uap)
return;
/* workaround to make sure that all bits are unlocked.. */
pl011_writew(uap, 0x00, REG_ICR);
writew(0x00, uap->port.membase + UART011_ICR);
/*
* WA: introduce 26ns(1 uart clk) delay before W1C;
* single apb access will incur 2 pclk(133.12Mhz) delay,
* so add 2 dummy reads
*/
dummy_read = pl011_readw(uap, REG_ICR);
dummy_read = pl011_readw(uap, REG_ICR);
dummy_read = readw(uap->port.membase + UART011_ICR);
dummy_read = readw(uap->port.membase + UART011_ICR);
}
static irqreturn_t pl011_int(int irq, void *dev_id)
......@@ -1509,13 +1361,15 @@ static irqreturn_t pl011_int(int irq, void *dev_id)
int handled = 0;
spin_lock_irqsave(&uap->port.lock, flags);
imsc = pl011_readw(uap, REG_IMSC);
status = pl011_readw(uap, REG_RIS) & imsc;
imsc = readw(uap->port.membase + UART011_IMSC);
status = readw(uap->port.membase + UART011_RIS) & imsc;
if (status) {
do {
check_apply_cts_event_workaround(uap);
pl011_writew(uap, status & ~(UART011_TXIS|UART011_RTIS|
UART011_RXIS), REG_ICR);
writew(status & ~(UART011_TXIS|UART011_RTIS|
UART011_RXIS),
uap->port.membase + UART011_ICR);
if (status & (UART011_RTIS|UART011_RXIS)) {
if (pl011_dma_rx_running(uap))
......@@ -1532,7 +1386,7 @@ static irqreturn_t pl011_int(int irq, void *dev_id)
if (pass_counter-- == 0)
break;
status = pl011_readw(uap, REG_RIS) & imsc;
status = readw(uap->port.membase + UART011_RIS) & imsc;
} while (status != 0);
handled = 1;
}
......@@ -1546,8 +1400,8 @@ static unsigned int pl011_tx_empty(struct uart_port *port)
{
struct uart_amba_port *uap =
container_of(port, struct uart_amba_port, port);
unsigned int status = pl011_readw(uap, REG_FR);
return status & (uap->fr_busy|UART01x_FR_TXFF) ? 0 : TIOCSER_TEMT;
unsigned int status = readw(uap->port.membase + UART01x_FR);
return status & (UART01x_FR_BUSY|UART01x_FR_TXFF) ? 0 : TIOCSER_TEMT;
}
static unsigned int pl011_get_mctrl(struct uart_port *port)
......@@ -1555,16 +1409,16 @@ static unsigned int pl011_get_mctrl(struct uart_port *port)
struct uart_amba_port *uap =
container_of(port, struct uart_amba_port, port);
unsigned int result = 0;
unsigned int status = pl011_readw(uap, REG_FR);
unsigned int status = readw(uap->port.membase + UART01x_FR);
#define TIOCMBIT(uartbit, tiocmbit) \
if (status & uartbit) \
result |= tiocmbit
TIOCMBIT(UART01x_FR_DCD, TIOCM_CAR);
TIOCMBIT(uap->fr_dsr, TIOCM_DSR);
TIOCMBIT(uap->fr_cts, TIOCM_CTS);
TIOCMBIT(uap->fr_ri, TIOCM_RNG);
TIOCMBIT(UART01x_FR_DSR, TIOCM_DSR);
TIOCMBIT(UART01x_FR_CTS, TIOCM_CTS);
TIOCMBIT(UART011_FR_RI, TIOCM_RNG);
#undef TIOCMBIT
return result;
}
......@@ -1575,7 +1429,7 @@ static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl)
container_of(port, struct uart_amba_port, port);
unsigned int cr;
cr = pl011_readw(uap, REG_CR);
cr = readw(uap->port.membase + UART011_CR);
#define TIOCMBIT(tiocmbit, uartbit) \
if (mctrl & tiocmbit) \
......@@ -1595,7 +1449,7 @@ static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl)
}
#undef TIOCMBIT
pl011_writew(uap, cr, REG_CR);
writew(cr, uap->port.membase + UART011_CR);
}
static void pl011_break_ctl(struct uart_port *port, int break_state)
......@@ -1606,12 +1460,12 @@ static void pl011_break_ctl(struct uart_port *port, int break_state)
unsigned int lcr_h;
spin_lock_irqsave(&uap->port.lock, flags);
lcr_h = pl011_readw(uap, uap->lcrh_tx);
lcr_h = readw(uap->port.membase + uap->lcrh_tx);
if (break_state == -1)
lcr_h |= UART01x_LCRH_BRK;
else
lcr_h &= ~UART01x_LCRH_BRK;
pl011_writew(uap, lcr_h, uap->lcrh_tx);
writew(lcr_h, uap->port.membase + uap->lcrh_tx);
spin_unlock_irqrestore(&uap->port.lock, flags);
}
......@@ -1621,8 +1475,9 @@ static void pl011_quiesce_irqs(struct uart_port *port)
{
struct uart_amba_port *uap =
container_of(port, struct uart_amba_port, port);
unsigned char __iomem *regs = uap->port.membase;
pl011_writew(uap, pl011_readw(uap, REG_MIS), REG_ICR);
writew(readw(regs + UART011_MIS), regs + UART011_ICR);
/*
* There is no way to clear TXIM as this is "ready to transmit IRQ", so
* we simply mask it. start_tx() will unmask it.
......@@ -1636,7 +1491,7 @@ static void pl011_quiesce_irqs(struct uart_port *port)
* (including tx queue), so we're also fine with start_tx()'s caller
* side.
*/
pl011_writew(uap, pl011_readw(uap, REG_IMSC) & ~UART011_TXIM, REG_IMSC);
writew(readw(regs + UART011_IMSC) & ~UART011_TXIM, regs + UART011_IMSC);
}
static int pl011_get_poll_char(struct uart_port *port)
......@@ -1651,11 +1506,11 @@ static int pl011_get_poll_char(struct uart_port *port)
*/
pl011_quiesce_irqs(port);
status = pl011_readw(uap, REG_FR);
status = readw(uap->port.membase + UART01x_FR);
if (status & UART01x_FR_RXFE)
return NO_POLL_CHAR;
return pl011_readw(uap, REG_DR);
return readw(uap->port.membase + UART01x_DR);
}
static void pl011_put_poll_char(struct uart_port *port,
......@@ -1664,10 +1519,10 @@ static void pl011_put_poll_char(struct uart_port *port,
struct uart_amba_port *uap =
container_of(port, struct uart_amba_port, port);
while (pl011_readw(uap, REG_FR) & UART01x_FR_TXFF)
while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF)
barrier();
pl011_writew(uap, ch, REG_DR);
writew(ch, uap->port.membase + UART01x_DR);
}
#endif /* CONFIG_CONSOLE_POLL */
......@@ -1691,15 +1546,15 @@ static int pl011_hwinit(struct uart_port *port)
uap->port.uartclk = clk_get_rate(uap->clk);
/* Clear pending error and receive interrupts */
pl011_writew(uap, UART011_OEIS | UART011_BEIS | UART011_PEIS |
UART011_FEIS | UART011_RTIS | UART011_RXIS, REG_ICR);
writew(UART011_OEIS | UART011_BEIS | UART011_PEIS | UART011_FEIS |
UART011_RTIS | UART011_RXIS, uap->port.membase + UART011_ICR);
/*
* Save interrupts enable mask, and enable RX interrupts in case if
* the interrupt is used for NMI entry.
*/
uap->im = pl011_readw(uap, REG_IMSC);
pl011_writew(uap, UART011_RTIM | UART011_RXIM, REG_IMSC);
uap->im = readw(uap->port.membase + UART011_IMSC);
writew(UART011_RTIM | UART011_RXIM, uap->port.membase + UART011_IMSC);
if (dev_get_platdata(uap->port.dev)) {
struct amba_pl011_data *plat;
......@@ -1713,22 +1568,22 @@ static int pl011_hwinit(struct uart_port *port)
static void pl011_write_lcr_h(struct uart_amba_port *uap, unsigned int lcr_h)
{
pl011_writew(uap, lcr_h, uap->lcrh_rx);
if (is_implemented(uap, REG_ST_LCRH_RX)) {
writew(lcr_h, uap->port.membase + uap->lcrh_rx);
if (uap->lcrh_rx != uap->lcrh_tx) {
int i;
/*
* Wait 10 PCLKs before writing LCRH_TX register,
* to get this delay write read only register 10 times
*/
for (i = 0; i < 10; ++i)
pl011_writew(uap, 0xff, REG_MIS);
pl011_writew(uap, lcr_h, uap->lcrh_tx);
writew(0xff, uap->port.membase + UART011_MIS);
writew(lcr_h, uap->port.membase + uap->lcrh_tx);
}
}
static int pl011_allocate_irq(struct uart_amba_port *uap)
{
pl011_writew(uap, uap->im, REG_IMSC);
writew(uap->im, uap->port.membase + UART011_IMSC);
return request_irq(uap->port.irq, pl011_int, 0, "uart-pl011", uap);
}
......@@ -1743,11 +1598,12 @@ static void pl011_enable_interrupts(struct uart_amba_port *uap)
spin_lock_irq(&uap->port.lock);
/* Clear out any spuriously appearing RX interrupts */
pl011_writew(uap, UART011_RTIS | UART011_RXIS, REG_ICR);
writew(UART011_RTIS | UART011_RXIS,
uap->port.membase + UART011_ICR);
uap->im = UART011_RTIM;
if (!pl011_dma_rx_running(uap))
uap->im |= UART011_RXIM;
pl011_writew(uap, uap->im, REG_IMSC);
writew(uap->im, uap->port.membase + UART011_IMSC);
spin_unlock_irq(&uap->port.lock);
}
......@@ -1766,21 +1622,21 @@ static int pl011_startup(struct uart_port *port)
if (retval)
goto clk_dis;
pl011_writew(uap, uap->vendor->ifls, REG_IFLS);
writew(uap->vendor->ifls, uap->port.membase + UART011_IFLS);
spin_lock_irq(&uap->port.lock);
/* restore RTS and DTR */
cr = uap->old_cr & (UART011_CR_RTS | UART011_CR_DTR);
cr |= UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE;
pl011_writew(uap, cr, REG_CR);
writew(cr, uap->port.membase + UART011_CR);
spin_unlock_irq(&uap->port.lock);
/*
* initialise the old status of the modem signals
*/
uap->old_status = pl011_readw(uap, REG_FR) & UART01x_FR_MODEM_ANY;
uap->old_status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
/* Startup DMA */
pl011_dma_startup(uap);
......@@ -1821,9 +1677,9 @@ static void pl011_shutdown_channel(struct uart_amba_port *uap,
{
unsigned long val;
val = pl011_readw(uap, lcrh);
val = readw(uap->port.membase + lcrh);
val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN);
pl011_writew(uap, val, lcrh);
writew(val, uap->port.membase + lcrh);
}
/*
......@@ -1837,18 +1693,18 @@ static void pl011_disable_uart(struct uart_amba_port *uap)
uap->autorts = false;
spin_lock_irq(&uap->port.lock);
cr = pl011_readw(uap, REG_CR);
cr = readw(uap->port.membase + UART011_CR);
uap->old_cr = cr;
cr &= UART011_CR_RTS | UART011_CR_DTR;
cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
pl011_writew(uap, cr, REG_CR);
writew(cr, uap->port.membase + UART011_CR);
spin_unlock_irq(&uap->port.lock);
/*
* disable break condition and fifos
*/
pl011_shutdown_channel(uap, uap->lcrh_rx);
if (is_implemented(uap, REG_ST_LCRH_RX))
if (uap->lcrh_rx != uap->lcrh_tx)
pl011_shutdown_channel(uap, uap->lcrh_tx);
}
......@@ -1858,8 +1714,8 @@ static void pl011_disable_interrupts(struct uart_amba_port *uap)
/* mask all interrupts and clear all pending ones */
uap->im = 0;
pl011_writew(uap, uap->im, REG_IMSC);
pl011_writew(uap, 0xffff, REG_ICR);
writew(uap->im, uap->port.membase + UART011_IMSC);
writew(0xffff, uap->port.membase + UART011_ICR);
spin_unlock_irq(&uap->port.lock);
}
......@@ -2011,8 +1867,8 @@ pl011_set_termios(struct uart_port *port, struct ktermios *termios,
pl011_enable_ms(port);
/* first, disable everything */
old_cr = pl011_readw(uap, REG_CR);
pl011_writew(uap, 0, REG_CR);
old_cr = readw(port->membase + UART011_CR);
writew(0, port->membase + UART011_CR);
if (termios->c_cflag & CRTSCTS) {
if (old_cr & UART011_CR_RTS)
......@@ -2045,17 +1901,17 @@ pl011_set_termios(struct uart_port *port, struct ktermios *termios,
quot -= 2;
}
/* Set baud rate */
pl011_writew(uap, quot & 0x3f, REG_FBRD);
pl011_writew(uap, quot >> 6, REG_IBRD);
writew(quot & 0x3f, port->membase + UART011_FBRD);
writew(quot >> 6, port->membase + UART011_IBRD);
/*
* ----------v----------v----------v----------v-----
* NOTE: lcrh_tx and lcrh_rx MUST BE WRITTEN AFTER
* REG_FBRD & REG_IBRD.
* UART011_FBRD & UART011_IBRD.
* ----------^----------^----------^----------^-----
*/
pl011_write_lcr_h(uap, lcr_h);
pl011_writew(uap, old_cr, REG_CR);
writew(old_cr, port->membase + UART011_CR);
spin_unlock_irqrestore(&port->lock, flags);
}
......@@ -2196,9 +2052,9 @@ static void pl011_console_putchar(struct uart_port *port, int ch)
struct uart_amba_port *uap =
container_of(port, struct uart_amba_port, port);
while (pl011_readw(uap, REG_FR) & UART01x_FR_TXFF)
while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF)
barrier();
pl011_writew(uap, ch, REG_DR);
writew(ch, uap->port.membase + UART01x_DR);
}
static void
......@@ -2223,10 +2079,10 @@ pl011_console_write(struct console *co, const char *s, unsigned int count)
* First save the CR then disable the interrupts
*/
if (!uap->vendor->always_enabled) {
old_cr = pl011_readw(uap, REG_CR);
old_cr = readw(uap->port.membase + UART011_CR);
new_cr = old_cr & ~UART011_CR_CTSEN;
new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
pl011_writew(uap, new_cr, REG_CR);
writew(new_cr, uap->port.membase + UART011_CR);
}
uart_console_write(&uap->port, s, count, pl011_console_putchar);
......@@ -2236,10 +2092,10 @@ pl011_console_write(struct console *co, const char *s, unsigned int count)
* and restore the TCR
*/
do {
status = pl011_readw(uap, REG_FR);
} while (status & uap->fr_busy);
status = readw(uap->port.membase + UART01x_FR);
} while (status & UART01x_FR_BUSY);
if (!uap->vendor->always_enabled)
pl011_writew(uap, old_cr, REG_CR);
writew(old_cr, uap->port.membase + UART011_CR);
if (locked)
spin_unlock(&uap->port.lock);
......@@ -2252,10 +2108,10 @@ static void __init
pl011_console_get_options(struct uart_amba_port *uap, int *baud,
int *parity, int *bits)
{
if (pl011_readw(uap, REG_CR) & UART01x_CR_UARTEN) {
if (readw(uap->port.membase + UART011_CR) & UART01x_CR_UARTEN) {
unsigned int lcr_h, ibrd, fbrd;
lcr_h = pl011_readw(uap, uap->lcrh_tx);
lcr_h = readw(uap->port.membase + uap->lcrh_tx);
*parity = 'n';
if (lcr_h & UART01x_LCRH_PEN) {
......@@ -2270,13 +2126,13 @@ pl011_console_get_options(struct uart_amba_port *uap, int *baud,
else
*bits = 8;
ibrd = pl011_readw(uap, REG_IBRD);
fbrd = pl011_readw(uap, REG_FBRD);
ibrd = readw(uap->port.membase + UART011_IBRD);
fbrd = readw(uap->port.membase + UART011_FBRD);
*baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd);
if (uap->vendor->oversampling) {
if (pl011_readw(uap, REG_CR)
if (readw(uap->port.membase + UART011_CR)
& ST_UART011_CR_OVSFACT)
*baud *= 2;
}
......@@ -2348,13 +2204,10 @@ static struct console amba_console = {
static void pl011_putc(struct uart_port *port, int c)
{
struct uart_amba_port *uap =
container_of(port, struct uart_amba_port, port);
while (pl011_readw(uap, REG_FR) & UART01x_FR_TXFF)
while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF)
;
pl011_writeb(uap, c, REG_DR);
while (pl011_readw(uap, REG_FR) & uap->fr_busy)
writeb(c, port->membase + UART01x_DR);
while (readl(port->membase + UART01x_FR) & UART01x_FR_BUSY)
;
}
......@@ -2481,8 +2334,8 @@ static int pl011_register_port(struct uart_amba_port *uap)
int ret;
/* Ensure interrupts from this UART are masked and cleared */
pl011_writew(uap, 0, REG_IMSC);
pl011_writew(uap, 0xffff, REG_ICR);
writew(0, uap->port.membase + UART011_IMSC);
writew(0xffff, uap->port.membase + UART011_ICR);
if (!amba_reg.state) {
ret = uart_register_driver(&amba_reg);
......@@ -2500,7 +2353,6 @@ static int pl011_register_port(struct uart_amba_port *uap)
return ret;
}
#ifdef CONFIG_ARM_AMBA
static int pl011_probe(struct amba_device *dev, const struct amba_id *id)
{
struct uart_amba_port *uap;
......@@ -2521,13 +2373,8 @@ static int pl011_probe(struct amba_device *dev, const struct amba_id *id)
return PTR_ERR(uap->clk);
uap->vendor = vendor;
uap->reg_lut = vendor->reg_lut;
uap->lcrh_rx = vendor->lcrh_rx;
uap->lcrh_tx = vendor->lcrh_tx;
uap->fr_busy = vendor->fr_busy;
uap->fr_dsr = vendor->fr_dsr;
uap->fr_cts = vendor->fr_cts;
uap->fr_ri = vendor->fr_ri;
uap->fifosize = vendor->get_fifosize(dev);
uap->port.irq = dev->irq[0];
uap->port.ops = &amba_pl011_pops;
......@@ -2551,67 +2398,6 @@ static int pl011_remove(struct amba_device *dev)
pl011_unregister_port(uap);
return 0;
}
#endif
#ifdef CONFIG_SOC_ZX296702
static int zx_uart_probe(struct platform_device *pdev)
{
struct uart_amba_port *uap;
struct vendor_data *vendor = &vendor_zte;
struct resource *res;
int portnr, ret;
portnr = pl011_find_free_port();
if (portnr < 0)
return portnr;
uap = devm_kzalloc(&pdev->dev, sizeof(struct uart_amba_port),
GFP_KERNEL);
if (!uap) {
ret = -ENOMEM;
goto out;
}
uap->clk = devm_clk_get(&pdev->dev, NULL);
if (IS_ERR(uap->clk)) {
ret = PTR_ERR(uap->clk);
goto out;
}
uap->vendor = vendor;
uap->reg_lut = vendor->reg_lut;
uap->lcrh_rx = vendor->lcrh_rx;
uap->lcrh_tx = vendor->lcrh_tx;
uap->fr_busy = vendor->fr_busy;
uap->fr_dsr = vendor->fr_dsr;
uap->fr_cts = vendor->fr_cts;
uap->fr_ri = vendor->fr_ri;
uap->fifosize = 16;
uap->port.irq = platform_get_irq(pdev, 0);
uap->port.ops = &amba_pl011_pops;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
ret = pl011_setup_port(&pdev->dev, uap, res, portnr);
if (ret)
return ret;
platform_set_drvdata(pdev, uap);
return pl011_register_port(uap);
out:
return ret;
}
static int zx_uart_remove(struct platform_device *pdev)
{
struct uart_amba_port *uap = platform_get_drvdata(pdev);
uart_remove_one_port(&amba_reg, &uap->port);
pl011_unregister_port(uap);
return 0;
}
#endif
#ifdef CONFIG_PM_SLEEP
static int pl011_suspend(struct device *dev)
......@@ -2668,11 +2454,6 @@ static int sbsa_uart_probe(struct platform_device *pdev)
return -ENOMEM;
uap->vendor = &vendor_sbsa;
uap->reg_lut = vendor_sbsa.reg_lut;
uap->fr_busy = vendor_sbsa.fr_busy;
uap->fr_dsr = vendor_sbsa.fr_dsr;
uap->fr_cts = vendor_sbsa.fr_cts;
uap->fr_ri = vendor_sbsa.fr_ri;
uap->fifosize = 32;
uap->port.irq = platform_get_irq(pdev, 0);
uap->port.ops = &sbsa_uart_pops;
......@@ -2722,7 +2503,6 @@ static struct platform_driver arm_sbsa_uart_platform_driver = {
},
};
#ifdef CONFIG_ARM_AMBA
static struct amba_id pl011_ids[] = {
{
.id = 0x00041011,
......@@ -2748,57 +2528,20 @@ static struct amba_driver pl011_driver = {
.probe = pl011_probe,
.remove = pl011_remove,
};
#endif
#ifdef CONFIG_SOC_ZX296702
static const struct of_device_id zx_uart_dt_ids[] = {
{ .compatible = "zte,zx296702-uart", },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, zx_uart_dt_ids);
static struct platform_driver zx_uart_driver = {
.driver = {
.name = "zx-uart",
.owner = THIS_MODULE,
.pm = &pl011_dev_pm_ops,
.of_match_table = zx_uart_dt_ids,
},
.probe = zx_uart_probe,
.remove = zx_uart_remove,
};
#endif
static int __init pl011_init(void)
{
int ret;
printk(KERN_INFO "Serial: AMBA PL011 UART driver\n");
if (platform_driver_register(&arm_sbsa_uart_platform_driver))
pr_warn("could not register SBSA UART platform driver\n");
#ifdef CONFIG_SOC_ZX296702
ret = platform_driver_register(&zx_uart_driver);
if (ret)
pr_warn("could not register ZX UART platform driver\n");
#endif
#ifdef CONFIG_ARM_AMBA
ret = amba_driver_register(&pl011_driver);
#endif
return ret;
return amba_driver_register(&pl011_driver);
}
static void __exit pl011_exit(void)
{
platform_driver_unregister(&arm_sbsa_uart_platform_driver);
#ifdef CONFIG_SOC_ZX296702
platform_driver_unregister(&zx_uart_driver);
#endif
#ifdef CONFIG_ARM_AMBA
amba_driver_unregister(&pl011_driver);
#endif
}
/*
......
include/linux/amba/serial.h
View file @ b8889c4f
......@@ -33,14 +33,12 @@
#define UART01x_DR 0x00 /* Data read or written from the interface. */
#define UART01x_RSR 0x04 /* Receive status register (Read). */
#define UART01x_ECR 0x04 /* Error clear register (Write). */
#define ZX_UART01x_DR 0x04 /* Data read or written from the interface. */
#define UART010_LCRH 0x08 /* Line control register, high byte. */
#define ST_UART011_DMAWM 0x08 /* DMA watermark configure register. */
#define UART010_LCRM 0x0C /* Line control register, middle byte. */
#define ST_UART011_TIMEOUT 0x0C /* Timeout period register. */
#define UART010_LCRL 0x10 /* Line control register, low byte. */
#define UART010_CR 0x14 /* Control register. */
#define ZX_UART01x_FR 0x14 /* Flag register (Read only). */
#define UART01x_FR 0x18 /* Flag register (Read only). */
#define UART010_IIR 0x1C /* Interrupt identification register (Read). */
#define UART010_ICR 0x1C /* Interrupt clear register (Write). */
......@@ -51,21 +49,13 @@
#define UART011_LCRH 0x2c /* Line control register. */
#define ST_UART011_LCRH_TX 0x2c /* Tx Line control register. */
#define UART011_CR 0x30 /* Control register. */
#define ZX_UART011_LCRH_TX 0x30 /* Tx Line control register. */
#define UART011_IFLS 0x34 /* Interrupt fifo level select. */
#define ZX_UART011_CR 0x34 /* Control register. */
#define ZX_UART011_IFLS 0x38 /* Interrupt fifo level select. */
#define UART011_IMSC 0x38 /* Interrupt mask. */
#define UART011_RIS 0x3c /* Raw interrupt status. */
#define UART011_MIS 0x40 /* Masked interrupt status. */
#define ZX_UART011_IMSC 0x40 /* Interrupt mask. */
#define UART011_ICR 0x44 /* Interrupt clear register. */
#define ZX_UART011_RIS 0x44 /* Raw interrupt status. */
#define UART011_DMACR 0x48 /* DMA control register. */
#define ZX_UART011_MIS 0x48 /* Masked interrupt status. */
#define ZX_UART011_ICR 0x4c /* Interrupt clear register. */
#define ST_UART011_XFCR 0x50 /* XON/XOFF control register. */
#define ZX_UART011_DMACR 0x50 /* DMA control register. */
#define ST_UART011_XON1 0x54 /* XON1 register. */
#define ST_UART011_XON2 0x58 /* XON2 register. */
#define ST_UART011_XOFF1 0x5C /* XON1 register. */
......@@ -85,19 +75,15 @@
#define UART01x_RSR_PE 0x02
#define UART01x_RSR_FE 0x01
#define ZX_UART01x_FR_BUSY 0x300
#define UART011_FR_RI 0x100
#define UART011_FR_TXFE 0x080
#define UART011_FR_RXFF 0x040
#define UART01x_FR_TXFF 0x020
#define UART01x_FR_RXFE 0x010
#define UART01x_FR_BUSY 0x008
#define ZX_UART01x_FR_DSR 0x008
#define UART01x_FR_DCD 0x004
#define UART01x_FR_DSR 0x002
#define ZX_UART01x_FR_CTS 0x002
#define UART01x_FR_CTS 0x001
#define ZX_UART011_FR_RI 0x001
#define UART01x_FR_TMSK (UART01x_FR_TXFF + UART01x_FR_BUSY)
#define UART011_CR_CTSEN 0x8000 /* CTS hardware flow control */
......
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