Commit b9a1077a authored by Dave Airlie's avatar Dave Airlie

Merge branch 'msm-next' of git://people.freedesktop.org/~robclark/linux into drm-next

Main pull req for 4.2.. I think there will be a secondary pull-req..
I'd like to land the hdcp support patches, since all the review
comments have been long since addressed, and they have been ready to
merge for a couple release cycles now other than the scm dependency
(which should be coming in through arm-soc tree for 4.2). So I am not
including them in this initial pull req to avoid merge ordering
issues.

Main highlights:

1) adreno a306 support (for apq8x16 and upcoming dragonboard 410c)
2) various dsi bits
3) various 64bit fixes (mostly warnings)
4) NV12MT support, pulled in via msm-next rather than drm-misc since
dependency on on regenerated envytools headers (but lgtm'd-by danvet)
5) random fixes and cleanups

* 'msm-next' of git://people.freedesktop.org/~robclark/linux: (36 commits)
  drm/msm: restart queued submits after hang
  drm/msm: fix timeout calculation
  drm/msm/hdmi: Use pinctrl in HDMI driver
  drm/msm/hdmi: Point to the right struct device
  drm/msm/mdp: Add support for more 32-bit RGB formats
  drm/msm: use __s32, __s64, __u32 and __u64 from linux/types.h for uabi
  drm/msm/atomic: Clean up planes in the error paths of .atomic_commit()
  drm/msm/mdp5: Always generate active-high sync signals for DSI
  drm/msm: dsi: fix compile errors when CONFIG_GPIOLIB=n
  drm/msm: use devm_gpiod_get_optional for optional reset gpio
  drm/msm/dsi: Separate PHY to another platform device
  drm/msm/dsi: Enable PLL driver in MSM DSI
  drm/msm/dsi: Add DSI PLL clock driver support
  drm/msm: use IS_ERR() to check regulator_get() return
  drm/msm: use IS_ERR() to check msm_ioremap() return
  drm/msm/mdp5: Wait for PP_DONE irq for command mode CRTC atomic commit
  drm/msm: Use customized function to wait for atomic commit done
  dt-bindings: Add MSM eDP controller documentation
  dt-bindings: Add MSM DSI controller documentation
  drm/msm: drop redundant debug output
  ...
parents 5c70c464 1a370be9
Qualcomm Technologies Inc. adreno/snapdragon DSI output
DSI Controller:
Required properties:
- compatible:
* "qcom,mdss-dsi-ctrl"
- reg: Physical base address and length of the registers of controller
- reg-names: The names of register regions. The following regions are required:
* "dsi_ctrl"
- qcom,dsi-host-index: The ID of DSI controller hardware instance. This should
be 0 or 1, since we have 2 DSI controllers at most for now.
- interrupts: The interrupt signal from the DSI block.
- power-domains: Should be <&mmcc MDSS_GDSC>.
- clocks: device clocks
See Documentation/devicetree/bindings/clocks/clock-bindings.txt for details.
- clock-names: the following clocks are required:
* "bus_clk"
* "byte_clk"
* "core_clk"
* "core_mmss_clk"
* "iface_clk"
* "mdp_core_clk"
* "pixel_clk"
- vdd-supply: phandle to vdd regulator device node
- vddio-supply: phandle to vdd-io regulator device node
- vdda-supply: phandle to vdda regulator device node
- qcom,dsi-phy: phandle to DSI PHY device node
Optional properties:
- panel@0: Node of panel connected to this DSI controller.
See files in Documentation/devicetree/bindings/panel/ for each supported
panel.
- qcom,dual-panel-mode: Boolean value indicating if the DSI controller is
driving a panel which needs 2 DSI links.
- qcom,master-panel: Boolean value indicating if the DSI controller is driving
the master link of the 2-DSI panel.
- qcom,sync-dual-panel: Boolean value indicating if the DSI controller is
driving a 2-DSI panel whose 2 links need receive command simultaneously.
- interrupt-parent: phandle to the MDP block if the interrupt signal is routed
through MDP block
DSI PHY:
Required properties:
- compatible: Could be the following
* "qcom,dsi-phy-28nm-hpm"
* "qcom,dsi-phy-28nm-lp"
- reg: Physical base address and length of the registers of PLL, PHY and PHY
regulator
- reg-names: The names of register regions. The following regions are required:
* "dsi_pll"
* "dsi_phy"
* "dsi_phy_regulator"
- qcom,dsi-phy-index: The ID of DSI PHY hardware instance. This should
be 0 or 1, since we have 2 DSI PHYs at most for now.
- power-domains: Should be <&mmcc MDSS_GDSC>.
- clocks: device clocks
See Documentation/devicetree/bindings/clocks/clock-bindings.txt for details.
- clock-names: the following clocks are required:
* "iface_clk"
- vddio-supply: phandle to vdd-io regulator device node
Example:
mdss_dsi0: qcom,mdss_dsi@fd922800 {
compatible = "qcom,mdss-dsi-ctrl";
qcom,dsi-host-index = <0>;
interrupt-parent = <&mdss_mdp>;
interrupts = <4 0>;
reg-names = "dsi_ctrl";
reg = <0xfd922800 0x200>;
power-domains = <&mmcc MDSS_GDSC>;
clock-names =
"bus_clk",
"byte_clk",
"core_clk",
"core_mmss_clk",
"iface_clk",
"mdp_core_clk",
"pixel_clk";
clocks =
<&mmcc MDSS_AXI_CLK>,
<&mmcc MDSS_BYTE0_CLK>,
<&mmcc MDSS_ESC0_CLK>,
<&mmcc MMSS_MISC_AHB_CLK>,
<&mmcc MDSS_AHB_CLK>,
<&mmcc MDSS_MDP_CLK>,
<&mmcc MDSS_PCLK0_CLK>;
vdda-supply = <&pma8084_l2>;
vdd-supply = <&pma8084_l22>;
vddio-supply = <&pma8084_l12>;
qcom,dsi-phy = <&mdss_dsi_phy0>;
qcom,dual-panel-mode;
qcom,master-panel;
qcom,sync-dual-panel;
panel: panel@0 {
compatible = "sharp,lq101r1sx01";
reg = <0>;
link2 = <&secondary>;
power-supply = <...>;
backlight = <...>;
};
};
mdss_dsi_phy0: qcom,mdss_dsi_phy@fd922a00 {
compatible = "qcom,dsi-phy-28nm-hpm";
qcom,dsi-phy-index = <0>;
reg-names =
"dsi_pll",
"dsi_phy",
"dsi_phy_regulator";
reg = <0xfd922a00 0xd4>,
<0xfd922b00 0x2b0>,
<0xfd922d80 0x7b>;
clock-names = "iface_clk";
clocks = <&mmcc MDSS_AHB_CLK>;
vddio-supply = <&pma8084_l12>;
};
Qualcomm Technologies Inc. adreno/snapdragon eDP output
Required properties:
- compatible:
* "qcom,mdss-edp"
- reg: Physical base address and length of the registers of controller and PLL
- reg-names: The names of register regions. The following regions are required:
* "edp"
* "pll_base"
- interrupts: The interrupt signal from the eDP block.
- power-domains: Should be <&mmcc MDSS_GDSC>.
- clocks: device clocks
See Documentation/devicetree/bindings/clocks/clock-bindings.txt for details.
- clock-names: the following clocks are required:
* "core_clk"
* "iface_clk"
* "mdp_core_clk"
* "pixel_clk"
* "link_clk"
- #clock-cells: The value should be 1.
- vdda-supply: phandle to vdda regulator device node
- lvl-vdd-supply: phandle to regulator device node which is used to supply power
to HPD receiving chip
- panel-en-gpios: GPIO pin to supply power to panel.
- panel-hpd-gpios: GPIO pin used for eDP hpd.
Optional properties:
- interrupt-parent: phandle to the MDP block if the interrupt signal is routed
through MDP block
Example:
mdss_edp: qcom,mdss_edp@fd923400 {
compatible = "qcom,mdss-edp";
reg-names =
"edp",
"pll_base";
reg = <0xfd923400 0x700>,
<0xfd923a00 0xd4>;
interrupt-parent = <&mdss_mdp>;
interrupts = <12 0>;
power-domains = <&mmcc MDSS_GDSC>;
clock-names =
"core_clk",
"pixel_clk",
"iface_clk",
"link_clk",
"mdp_core_clk";
clocks =
<&mmcc MDSS_EDPAUX_CLK>,
<&mmcc MDSS_EDPPIXEL_CLK>,
<&mmcc MDSS_AHB_CLK>,
<&mmcc MDSS_EDPLINK_CLK>,
<&mmcc MDSS_MDP_CLK>;
#clock-cells = <1>;
vdda-supply = <&pma8084_l12>;
lvl-vdd-supply = <&lvl_vreg>;
panel-en-gpios = <&tlmm 137 0>;
panel-hpd-gpios = <&tlmm 103 0>;
};
...@@ -20,6 +20,9 @@ Required properties: ...@@ -20,6 +20,9 @@ Required properties:
Optional properties: Optional properties:
- qcom,hdmi-tx-mux-en-gpio: hdmi mux enable pin - qcom,hdmi-tx-mux-en-gpio: hdmi mux enable pin
- qcom,hdmi-tx-mux-sel-gpio: hdmi mux select pin - qcom,hdmi-tx-mux-sel-gpio: hdmi mux select pin
- pinctrl-names: the pin control state names; should contain "default"
- pinctrl-0: the default pinctrl state (active)
- pinctrl-1: the "sleep" pinctrl state
Example: Example:
...@@ -44,5 +47,8 @@ Example: ...@@ -44,5 +47,8 @@ Example:
qcom,hdmi-tx-hpd = <&msmgpio 72 GPIO_ACTIVE_HIGH>; qcom,hdmi-tx-hpd = <&msmgpio 72 GPIO_ACTIVE_HIGH>;
core-vdda-supply = <&pm8921_hdmi_mvs>; core-vdda-supply = <&pm8921_hdmi_mvs>;
hdmi-mux-supply = <&ext_3p3v>; hdmi-mux-supply = <&ext_3p3v>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&hpd_active &ddc_active &cec_active>;
pinctrl-1 = <&hpd_suspend &ddc_suspend &cec_suspend>;
}; };
}; };
...@@ -3255,6 +3255,24 @@ static int framebuffer_check(const struct drm_mode_fb_cmd2 *r) ...@@ -3255,6 +3255,24 @@ static int framebuffer_check(const struct drm_mode_fb_cmd2 *r)
r->modifier[i], i); r->modifier[i], i);
return -EINVAL; return -EINVAL;
} }
/* modifier specific checks: */
switch (r->modifier[i]) {
case DRM_FORMAT_MOD_SAMSUNG_64_32_TILE:
/* NOTE: the pitch restriction may be lifted later if it turns
* out that no hw has this restriction:
*/
if (r->pixel_format != DRM_FORMAT_NV12 ||
width % 128 || height % 32 ||
r->pitches[i] % 128) {
DRM_DEBUG_KMS("bad modifier data for plane %d\n", i);
return -EINVAL;
}
break;
default:
break;
}
} }
for (i = num_planes; i < 4; i++) { for (i = num_planes; i < 4; i++) {
......
...@@ -46,3 +46,10 @@ config DRM_MSM_DSI ...@@ -46,3 +46,10 @@ config DRM_MSM_DSI
Choose this option if you have a need for MIPI DSI connector Choose this option if you have a need for MIPI DSI connector
support. support.
config DRM_MSM_DSI_PLL
bool "Enable DSI PLL driver in MSM DRM"
depends on DRM_MSM_DSI && COMMON_CLK
default y
help
Choose this option to enable DSI PLL driver which provides DSI
source clocks under common clock framework.
ccflags-y := -Iinclude/drm -Idrivers/gpu/drm/msm ccflags-y := -Iinclude/drm -Idrivers/gpu/drm/msm
ccflags-$(CONFIG_DRM_MSM_DSI_PLL) += -Idrivers/gpu/drm/msm/dsi
msm-y := \ msm-y := \
adreno/adreno_device.o \ adreno/adreno_device.o \
...@@ -50,10 +51,14 @@ msm-y := \ ...@@ -50,10 +51,14 @@ msm-y := \
msm-$(CONFIG_DRM_MSM_FBDEV) += msm_fbdev.o msm-$(CONFIG_DRM_MSM_FBDEV) += msm_fbdev.o
msm-$(CONFIG_COMMON_CLK) += mdp/mdp4/mdp4_lvds_pll.o msm-$(CONFIG_COMMON_CLK) += mdp/mdp4/mdp4_lvds_pll.o
msm-$(CONFIG_DRM_MSM_DSI) += dsi/dsi.o \ msm-$(CONFIG_DRM_MSM_DSI) += dsi/dsi.o \
dsi/dsi_host.o \ dsi/dsi_host.o \
dsi/dsi_manager.o \ dsi/dsi_manager.o \
dsi/dsi_phy.o \ dsi/dsi_phy.o \
mdp/mdp5/mdp5_cmd_encoder.o mdp/mdp5/mdp5_cmd_encoder.o
msm-$(CONFIG_DRM_MSM_DSI_PLL) += dsi/pll/dsi_pll.o \
dsi/pll/dsi_pll_28nm.o
obj-$(CONFIG_DRM_MSM) += msm.o obj-$(CONFIG_DRM_MSM) += msm.o
...@@ -12,9 +12,9 @@ The rules-ng-ng source files this header was generated from are: ...@@ -12,9 +12,9 @@ The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2014-06-02 15:21:30) - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2014-06-02 15:21:30)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10551 bytes, from 2014-11-13 22:44:30) - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10551 bytes, from 2014-11-13 22:44:30)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 15085 bytes, from 2014-12-20 21:49:41) - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14895 bytes, from 2015-04-19 15:23:28)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 64344 bytes, from 2014-12-12 20:22:26) - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 66709 bytes, from 2015-04-12 18:16:35)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 51069 bytes, from 2014-12-21 15:51:54) - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 60633 bytes, from 2015-05-20 14:48:19)
Copyright (C) 2013-2014 by the following authors: Copyright (C) 2013-2014 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark) - Rob Clark <robdclark@gmail.com> (robclark)
......
This diff is collapsed.
...@@ -93,7 +93,10 @@ static int a3xx_hw_init(struct msm_gpu *gpu) ...@@ -93,7 +93,10 @@ static int a3xx_hw_init(struct msm_gpu *gpu)
/* Set up AOOO: */ /* Set up AOOO: */
gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO_EN, 0x0000003c); gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO_EN, 0x0000003c);
gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO, 0x003c003c); gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO, 0x003c003c);
} else if (adreno_is_a306(adreno_gpu)) {
gpu_write(gpu, REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x0003);
gpu_write(gpu, REG_A3XX_VBIF_OUT_RD_LIM_CONF0, 0x0000000a);
gpu_write(gpu, REG_A3XX_VBIF_OUT_WR_LIM_CONF0, 0x0000000a);
} else if (adreno_is_a320(adreno_gpu)) { } else if (adreno_is_a320(adreno_gpu)) {
/* Set up 16 deep read/write request queues: */ /* Set up 16 deep read/write request queues: */
gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF0, 0x10101010); gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF0, 0x10101010);
...@@ -186,7 +189,9 @@ static int a3xx_hw_init(struct msm_gpu *gpu) ...@@ -186,7 +189,9 @@ static int a3xx_hw_init(struct msm_gpu *gpu)
gpu_write(gpu, REG_A3XX_UCHE_CACHE_MODE_CONTROL_REG, 0x00000001); gpu_write(gpu, REG_A3XX_UCHE_CACHE_MODE_CONTROL_REG, 0x00000001);
/* Enable Clock gating: */ /* Enable Clock gating: */
if (adreno_is_a320(adreno_gpu)) if (adreno_is_a306(adreno_gpu))
gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0xaaaaaaaa);
else if (adreno_is_a320(adreno_gpu))
gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0xbfffffff); gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0xbfffffff);
else if (adreno_is_a330v2(adreno_gpu)) else if (adreno_is_a330v2(adreno_gpu))
gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0xaaaaaaaa); gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0xaaaaaaaa);
...@@ -271,7 +276,8 @@ static int a3xx_hw_init(struct msm_gpu *gpu) ...@@ -271,7 +276,8 @@ static int a3xx_hw_init(struct msm_gpu *gpu)
gpu_write(gpu, REG_A3XX_CP_PFP_UCODE_DATA, ptr[i]); gpu_write(gpu, REG_A3XX_CP_PFP_UCODE_DATA, ptr[i]);
/* CP ROQ queue sizes (bytes) - RB:16, ST:16, IB1:32, IB2:64 */ /* CP ROQ queue sizes (bytes) - RB:16, ST:16, IB1:32, IB2:64 */
if (adreno_is_a305(adreno_gpu) || adreno_is_a320(adreno_gpu)) { if (adreno_is_a305(adreno_gpu) || adreno_is_a306(adreno_gpu) ||
adreno_is_a320(adreno_gpu)) {
gpu_write(gpu, REG_AXXX_CP_QUEUE_THRESHOLDS, gpu_write(gpu, REG_AXXX_CP_QUEUE_THRESHOLDS,
AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START(2) | AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START(2) |
AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START(6) | AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START(6) |
...@@ -295,9 +301,12 @@ static int a3xx_hw_init(struct msm_gpu *gpu) ...@@ -295,9 +301,12 @@ static int a3xx_hw_init(struct msm_gpu *gpu)
static void a3xx_recover(struct msm_gpu *gpu) static void a3xx_recover(struct msm_gpu *gpu)
{ {
adreno_dump_info(gpu);
/* dump registers before resetting gpu, if enabled: */ /* dump registers before resetting gpu, if enabled: */
if (hang_debug) if (hang_debug)
a3xx_dump(gpu); a3xx_dump(gpu);
gpu_write(gpu, REG_A3XX_RBBM_SW_RESET_CMD, 1); gpu_write(gpu, REG_A3XX_RBBM_SW_RESET_CMD, 1);
gpu_read(gpu, REG_A3XX_RBBM_SW_RESET_CMD); gpu_read(gpu, REG_A3XX_RBBM_SW_RESET_CMD);
gpu_write(gpu, REG_A3XX_RBBM_SW_RESET_CMD, 0); gpu_write(gpu, REG_A3XX_RBBM_SW_RESET_CMD, 0);
......
This diff is collapsed.
...@@ -268,6 +268,8 @@ static int a4xx_hw_init(struct msm_gpu *gpu) ...@@ -268,6 +268,8 @@ static int a4xx_hw_init(struct msm_gpu *gpu)
static void a4xx_recover(struct msm_gpu *gpu) static void a4xx_recover(struct msm_gpu *gpu)
{ {
adreno_dump_info(gpu);
/* dump registers before resetting gpu, if enabled: */ /* dump registers before resetting gpu, if enabled: */
if (hang_debug) if (hang_debug)
a4xx_dump(gpu); a4xx_dump(gpu);
...@@ -505,7 +507,6 @@ static const unsigned int a4xx_register_offsets[REG_ADRENO_REGISTER_MAX] = { ...@@ -505,7 +507,6 @@ static const unsigned int a4xx_register_offsets[REG_ADRENO_REGISTER_MAX] = {
static void a4xx_dump(struct msm_gpu *gpu) static void a4xx_dump(struct msm_gpu *gpu)
{ {
adreno_dump(gpu);
printk("status: %08x\n", printk("status: %08x\n",
gpu_read(gpu, REG_A4XX_RBBM_STATUS)); gpu_read(gpu, REG_A4XX_RBBM_STATUS));
adreno_dump(gpu); adreno_dump(gpu);
......
...@@ -12,9 +12,9 @@ The rules-ng-ng source files this header was generated from are: ...@@ -12,9 +12,9 @@ The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2014-06-02 15:21:30) - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2014-06-02 15:21:30)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10551 bytes, from 2014-11-13 22:44:30) - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10551 bytes, from 2014-11-13 22:44:30)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 15085 bytes, from 2014-12-20 21:49:41) - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14895 bytes, from 2015-04-19 15:23:28)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 64344 bytes, from 2014-12-12 20:22:26) - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 66709 bytes, from 2015-04-12 18:16:35)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 51069 bytes, from 2014-12-21 15:51:54) - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 60633 bytes, from 2015-05-20 14:48:19)
Copyright (C) 2013-2014 by the following authors: Copyright (C) 2013-2014 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark) - Rob Clark <robdclark@gmail.com> (robclark)
......
...@@ -19,7 +19,7 @@ ...@@ -19,7 +19,7 @@
#include "adreno_gpu.h" #include "adreno_gpu.h"
#if defined(CONFIG_MSM_BUS_SCALING) && !defined(CONFIG_OF) #if defined(DOWNSTREAM_CONFIG_MSM_BUS_SCALING) && !defined(CONFIG_OF)
# include <mach/kgsl.h> # include <mach/kgsl.h>
#endif #endif
...@@ -41,6 +41,14 @@ static const struct adreno_info gpulist[] = { ...@@ -41,6 +41,14 @@ static const struct adreno_info gpulist[] = {
.pfpfw = "a300_pfp.fw", .pfpfw = "a300_pfp.fw",
.gmem = SZ_256K, .gmem = SZ_256K,
.init = a3xx_gpu_init, .init = a3xx_gpu_init,
}, {
.rev = ADRENO_REV(3, 0, 6, 0),
.revn = 307, /* because a305c is revn==306 */
.name = "A306",
.pm4fw = "a300_pm4.fw",
.pfpfw = "a300_pfp.fw",
.gmem = SZ_128K,
.init = a3xx_gpu_init,
}, { }, {
.rev = ADRENO_REV(3, 2, ANY_ID, ANY_ID), .rev = ADRENO_REV(3, 2, ANY_ID, ANY_ID),
.revn = 320, .revn = 320,
...@@ -240,7 +248,7 @@ static int adreno_bind(struct device *dev, struct device *master, void *data) ...@@ -240,7 +248,7 @@ static int adreno_bind(struct device *dev, struct device *master, void *data)
config.rev = ADRENO_REV(3, 0, 5, 0); config.rev = ADRENO_REV(3, 0, 5, 0);
} }
# ifdef CONFIG_MSM_BUS_SCALING # ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING
config.bus_scale_table = pdata->bus_scale_table; config.bus_scale_table = pdata->bus_scale_table;
# endif # endif
#endif #endif
......
...@@ -176,6 +176,17 @@ int adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit, ...@@ -176,6 +176,17 @@ int adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
OUT_PKT3(ring, CP_INTERRUPT, 1); OUT_PKT3(ring, CP_INTERRUPT, 1);
OUT_RING(ring, 0x80000000); OUT_RING(ring, 0x80000000);
/* Workaround for missing irq issue on 8x16/a306. Unsure if the
* root cause is a platform issue or some a306 quirk, but this
* keeps things humming along:
*/
if (adreno_is_a306(adreno_gpu)) {
OUT_PKT3(ring, CP_WAIT_FOR_IDLE, 1);
OUT_RING(ring, 0x00000000);
OUT_PKT3(ring, CP_INTERRUPT, 1);
OUT_RING(ring, 0x80000000);
}
#if 0 #if 0
if (adreno_is_a3xx(adreno_gpu)) { if (adreno_is_a3xx(adreno_gpu)) {
/* Dummy set-constant to trigger context rollover */ /* Dummy set-constant to trigger context rollover */
...@@ -249,8 +260,13 @@ void adreno_show(struct msm_gpu *gpu, struct seq_file *m) ...@@ -249,8 +260,13 @@ void adreno_show(struct msm_gpu *gpu, struct seq_file *m)
} }
#endif #endif
/* would be nice to not have to duplicate the _show() stuff with printk(): */ /* Dump common gpu status and scratch registers on any hang, to make
void adreno_dump(struct msm_gpu *gpu) * the hangcheck logs more useful. The scratch registers seem always
* safe to read when GPU has hung (unlike some other regs, depending
* on how the GPU hung), and they are useful to match up to cmdstream
* dumps when debugging hangs:
*/
void adreno_dump_info(struct msm_gpu *gpu)
{ {
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
int i; int i;
...@@ -266,6 +282,18 @@ void adreno_dump(struct msm_gpu *gpu) ...@@ -266,6 +282,18 @@ void adreno_dump(struct msm_gpu *gpu)
printk("wptr: %d\n", adreno_gpu->memptrs->wptr); printk("wptr: %d\n", adreno_gpu->memptrs->wptr);
printk("rb wptr: %d\n", get_wptr(gpu->rb)); printk("rb wptr: %d\n", get_wptr(gpu->rb));
for (i = 0; i < 8; i++) {
printk("CP_SCRATCH_REG%d: %u\n", i,
gpu_read(gpu, REG_AXXX_CP_SCRATCH_REG0 + i));
}
}
/* would be nice to not have to duplicate the _show() stuff with printk(): */
void adreno_dump(struct msm_gpu *gpu)
{
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
int i;
/* dump these out in a form that can be parsed by demsm: */ /* dump these out in a form that can be parsed by demsm: */
printk("IO:region %s 00000000 00020000\n", gpu->name); printk("IO:region %s 00000000 00020000\n", gpu->name);
for (i = 0; adreno_gpu->registers[i] != ~0; i += 2) { for (i = 0; adreno_gpu->registers[i] != ~0; i += 2) {
...@@ -317,7 +345,7 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, ...@@ -317,7 +345,7 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
gpu->fast_rate = config->fast_rate; gpu->fast_rate = config->fast_rate;
gpu->slow_rate = config->slow_rate; gpu->slow_rate = config->slow_rate;
gpu->bus_freq = config->bus_freq; gpu->bus_freq = config->bus_freq;
#ifdef CONFIG_MSM_BUS_SCALING #ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING
gpu->bus_scale_table = config->bus_scale_table; gpu->bus_scale_table = config->bus_scale_table;
#endif #endif
......
...@@ -167,7 +167,7 @@ struct adreno_gpu { ...@@ -167,7 +167,7 @@ struct adreno_gpu {
struct adreno_platform_config { struct adreno_platform_config {
struct adreno_rev rev; struct adreno_rev rev;
uint32_t fast_rate, slow_rate, bus_freq; uint32_t fast_rate, slow_rate, bus_freq;
#ifdef CONFIG_MSM_BUS_SCALING #ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING
struct msm_bus_scale_pdata *bus_scale_table; struct msm_bus_scale_pdata *bus_scale_table;
#endif #endif
}; };
...@@ -197,6 +197,12 @@ static inline bool adreno_is_a305(struct adreno_gpu *gpu) ...@@ -197,6 +197,12 @@ static inline bool adreno_is_a305(struct adreno_gpu *gpu)
return gpu->revn == 305; return gpu->revn == 305;
} }
static inline bool adreno_is_a306(struct adreno_gpu *gpu)
{
/* yes, 307, because a305c is 306 */
return gpu->revn == 307;
}
static inline bool adreno_is_a320(struct adreno_gpu *gpu) static inline bool adreno_is_a320(struct adreno_gpu *gpu)
{ {
return gpu->revn == 320; return gpu->revn == 320;
...@@ -233,6 +239,7 @@ void adreno_idle(struct msm_gpu *gpu); ...@@ -233,6 +239,7 @@ void adreno_idle(struct msm_gpu *gpu);
#ifdef CONFIG_DEBUG_FS #ifdef CONFIG_DEBUG_FS
void adreno_show(struct msm_gpu *gpu, struct seq_file *m); void adreno_show(struct msm_gpu *gpu, struct seq_file *m);
#endif #endif
void adreno_dump_info(struct msm_gpu *gpu);
void adreno_dump(struct msm_gpu *gpu); void adreno_dump(struct msm_gpu *gpu);
void adreno_wait_ring(struct msm_gpu *gpu, uint32_t ndwords); void adreno_wait_ring(struct msm_gpu *gpu, uint32_t ndwords);
......
...@@ -12,11 +12,11 @@ The rules-ng-ng source files this header was generated from are: ...@@ -12,11 +12,11 @@ The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2014-06-02 15:21:30) - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2014-06-02 15:21:30)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10551 bytes, from 2014-11-13 22:44:30) - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10551 bytes, from 2014-11-13 22:44:30)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 15085 bytes, from 2014-12-20 21:49:41) - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14895 bytes, from 2015-04-19 15:23:28)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 64344 bytes, from 2014-12-12 20:22:26) - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 66709 bytes, from 2015-04-12 18:16:35)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 51069 bytes, from 2014-12-21 15:51:54) - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 60633 bytes, from 2015-05-20 14:48:19)
Copyright (C) 2013-2014 by the following authors: Copyright (C) 2013-2015 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark) - Rob Clark <robdclark@gmail.com> (robclark)
Permission is hereby granted, free of charge, to any person obtaining Permission is hereby granted, free of charge, to any person obtaining
...@@ -76,16 +76,11 @@ enum pc_di_primtype { ...@@ -76,16 +76,11 @@ enum pc_di_primtype {
DI_PT_LINELOOP = 7, DI_PT_LINELOOP = 7,
DI_PT_RECTLIST = 8, DI_PT_RECTLIST = 8,
DI_PT_POINTLIST_A3XX = 9, DI_PT_POINTLIST_A3XX = 9,
DI_PT_QUADLIST = 13, DI_PT_LINE_ADJ = 10,
DI_PT_QUADSTRIP = 14, DI_PT_LINESTRIP_ADJ = 11,
DI_PT_POLYGON = 15, DI_PT_TRI_ADJ = 12,
DI_PT_2D_COPY_RECT_LIST_V0 = 16, DI_PT_TRISTRIP_ADJ = 13,
DI_PT_2D_COPY_RECT_LIST_V1 = 17, DI_PT_PATCHES = 34,
DI_PT_2D_COPY_RECT_LIST_V2 = 18,
DI_PT_2D_COPY_RECT_LIST_V3 = 19,
DI_PT_2D_FILL_RECT_LIST = 20,
DI_PT_2D_LINE_STRIP = 21,
DI_PT_2D_TRI_STRIP = 22,
}; };
enum pc_di_src_sel { enum pc_di_src_sel {
...@@ -192,6 +187,7 @@ enum adreno_state_block { ...@@ -192,6 +187,7 @@ enum adreno_state_block {
SB_FRAG_TEX = 2, SB_FRAG_TEX = 2,
SB_FRAG_MIPADDR = 3, SB_FRAG_MIPADDR = 3,
SB_VERT_SHADER = 4, SB_VERT_SHADER = 4,
SB_GEOM_SHADER = 5,
SB_FRAG_SHADER = 6, SB_FRAG_SHADER = 6,
}; };
...@@ -382,12 +378,19 @@ static inline uint32_t CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(enum pc_di_src_sel va ...@@ -382,12 +378,19 @@ static inline uint32_t CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(enum pc_di_src_sel va
{ {
return ((val) << CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK; return ((val) << CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK;
} }
#define CP_DRAW_INDX_OFFSET_0_TESSELLATE 0x00000100
#define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK 0x00000c00 #define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK 0x00000c00
#define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT 10 #define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT 10
static inline uint32_t CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(enum a4xx_index_size val) static inline uint32_t CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(enum a4xx_index_size val)
{ {
return ((val) << CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK; return ((val) << CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK;
} }
#define CP_DRAW_INDX_OFFSET_0_TESS_MODE__MASK 0x01f00000
#define CP_DRAW_INDX_OFFSET_0_TESS_MODE__SHIFT 20
static inline uint32_t CP_DRAW_INDX_OFFSET_0_TESS_MODE(uint32_t val)
{
return ((val) << CP_DRAW_INDX_OFFSET_0_TESS_MODE__SHIFT) & CP_DRAW_INDX_OFFSET_0_TESS_MODE__MASK;
}
#define REG_CP_DRAW_INDX_OFFSET_1 0x00000001 #define REG_CP_DRAW_INDX_OFFSET_1 0x00000001
#define CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK 0xffffffff #define CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK 0xffffffff
......
...@@ -23,12 +23,47 @@ struct drm_encoder *msm_dsi_get_encoder(struct msm_dsi *msm_dsi) ...@@ -23,12 +23,47 @@ struct drm_encoder *msm_dsi_get_encoder(struct msm_dsi *msm_dsi)
msm_dsi->encoders[MSM_DSI_CMD_ENCODER_ID]; msm_dsi->encoders[MSM_DSI_CMD_ENCODER_ID];
} }
static int dsi_get_phy(struct msm_dsi *msm_dsi)
{
struct platform_device *pdev = msm_dsi->pdev;
struct platform_device *phy_pdev;
struct device_node *phy_node;
phy_node = of_parse_phandle(pdev->dev.of_node, "qcom,dsi-phy", 0);
if (!phy_node) {
dev_err(&pdev->dev, "cannot find phy device\n");
return -ENXIO;
}
phy_pdev = of_find_device_by_node(phy_node);
if (phy_pdev)
msm_dsi->phy = platform_get_drvdata(phy_pdev);
of_node_put(phy_node);
if (!phy_pdev || !msm_dsi->phy) {
dev_err(&pdev->dev, "%s: phy driver is not ready\n", __func__);
return -EPROBE_DEFER;
}
msm_dsi->phy_dev = get_device(&phy_pdev->dev);
return 0;
}
static void dsi_destroy(struct msm_dsi *msm_dsi) static void dsi_destroy(struct msm_dsi *msm_dsi)
{ {
if (!msm_dsi) if (!msm_dsi)
return; return;
msm_dsi_manager_unregister(msm_dsi); msm_dsi_manager_unregister(msm_dsi);
if (msm_dsi->phy_dev) {
put_device(msm_dsi->phy_dev);
msm_dsi->phy = NULL;
msm_dsi->phy_dev = NULL;
}
if (msm_dsi->host) { if (msm_dsi->host) {
msm_dsi_host_destroy(msm_dsi->host); msm_dsi_host_destroy(msm_dsi->host);
msm_dsi->host = NULL; msm_dsi->host = NULL;
...@@ -43,7 +78,6 @@ static struct msm_dsi *dsi_init(struct platform_device *pdev) ...@@ -43,7 +78,6 @@ static struct msm_dsi *dsi_init(struct platform_device *pdev)
int ret; int ret;
if (!pdev) { if (!pdev) {
dev_err(&pdev->dev, "no dsi device\n");
ret = -ENXIO; ret = -ENXIO;
goto fail; goto fail;
} }
...@@ -63,6 +97,11 @@ static struct msm_dsi *dsi_init(struct platform_device *pdev) ...@@ -63,6 +97,11 @@ static struct msm_dsi *dsi_init(struct platform_device *pdev)
if (ret) if (ret)
goto fail; goto fail;
/* GET dsi PHY */
ret = dsi_get_phy(msm_dsi);
if (ret)
goto fail;
/* Register to dsi manager */ /* Register to dsi manager */
ret = msm_dsi_manager_register(msm_dsi); ret = msm_dsi_manager_register(msm_dsi);
if (ret) if (ret)
...@@ -142,12 +181,14 @@ static struct platform_driver dsi_driver = { ...@@ -142,12 +181,14 @@ static struct platform_driver dsi_driver = {
void __init msm_dsi_register(void) void __init msm_dsi_register(void)
{ {
DBG(""); DBG("");
msm_dsi_phy_driver_register();
platform_driver_register(&dsi_driver); platform_driver_register(&dsi_driver);
} }
void __exit msm_dsi_unregister(void) void __exit msm_dsi_unregister(void)
{ {
DBG(""); DBG("");
msm_dsi_phy_driver_unregister();
platform_driver_unregister(&dsi_driver); platform_driver_unregister(&dsi_driver);
} }
......
...@@ -14,6 +14,7 @@ ...@@ -14,6 +14,7 @@
#ifndef __DSI_CONNECTOR_H__ #ifndef __DSI_CONNECTOR_H__
#define __DSI_CONNECTOR_H__ #define __DSI_CONNECTOR_H__
#include <linux/of_platform.h>
#include <linux/platform_device.h> #include <linux/platform_device.h>
#include "drm_crtc.h" #include "drm_crtc.h"
...@@ -38,6 +39,28 @@ ...@@ -38,6 +39,28 @@
#define DSI_ENCODER_MASTER DSI_1 #define DSI_ENCODER_MASTER DSI_1
#define DSI_ENCODER_SLAVE DSI_0 #define DSI_ENCODER_SLAVE DSI_0
enum msm_dsi_phy_type {
MSM_DSI_PHY_28NM_HPM,
MSM_DSI_PHY_28NM_LP,
MSM_DSI_PHY_MAX
};
#define DSI_DEV_REGULATOR_MAX 8
/* Regulators for DSI devices */
struct dsi_reg_entry {
char name[32];
int min_voltage;
int max_voltage;
int enable_load;
int disable_load;
};
struct dsi_reg_config {
int num;
struct dsi_reg_entry regs[DSI_DEV_REGULATOR_MAX];
};
struct msm_dsi { struct msm_dsi {
struct drm_device *dev; struct drm_device *dev;
struct platform_device *pdev; struct platform_device *pdev;
...@@ -49,6 +72,8 @@ struct msm_dsi { ...@@ -49,6 +72,8 @@ struct msm_dsi {
struct msm_dsi_phy *phy; struct msm_dsi_phy *phy;
struct drm_panel *panel; struct drm_panel *panel;
unsigned long panel_flags; unsigned long panel_flags;
struct device *phy_dev;
bool phy_enabled; bool phy_enabled;
/* the encoders we are hooked to (outside of dsi block) */ /* the encoders we are hooked to (outside of dsi block) */
...@@ -73,6 +98,29 @@ void msm_dsi_manager_unregister(struct msm_dsi *msm_dsi); ...@@ -73,6 +98,29 @@ void msm_dsi_manager_unregister(struct msm_dsi *msm_dsi);
/* msm dsi */ /* msm dsi */
struct drm_encoder *msm_dsi_get_encoder(struct msm_dsi *msm_dsi); struct drm_encoder *msm_dsi_get_encoder(struct msm_dsi *msm_dsi);
/* dsi pll */
struct msm_dsi_pll;
#ifdef CONFIG_DRM_MSM_DSI_PLL
struct msm_dsi_pll *msm_dsi_pll_init(struct platform_device *pdev,
enum msm_dsi_phy_type type, int dsi_id);
void msm_dsi_pll_destroy(struct msm_dsi_pll *pll);
int msm_dsi_pll_get_clk_provider(struct msm_dsi_pll *pll,
struct clk **byte_clk_provider, struct clk **pixel_clk_provider);
#else
static inline struct msm_dsi_pll *msm_dsi_pll_init(struct platform_device *pdev,
enum msm_dsi_phy_type type, int id) {
return ERR_PTR(-ENODEV);
}
static inline void msm_dsi_pll_destroy(struct msm_dsi_pll *pll)
{
}
static inline int msm_dsi_pll_get_clk_provider(struct msm_dsi_pll *pll,
struct clk **byte_clk_provider, struct clk **pixel_clk_provider)
{
return -ENODEV;
}
#endif
/* dsi host */ /* dsi host */
int msm_dsi_host_xfer_prepare(struct mipi_dsi_host *host, int msm_dsi_host_xfer_prepare(struct mipi_dsi_host *host,
const struct mipi_dsi_msg *msg); const struct mipi_dsi_msg *msg);
...@@ -94,6 +142,8 @@ struct drm_panel *msm_dsi_host_get_panel(struct mipi_dsi_host *host, ...@@ -94,6 +142,8 @@ struct drm_panel *msm_dsi_host_get_panel(struct mipi_dsi_host *host,
unsigned long *panel_flags); unsigned long *panel_flags);
int msm_dsi_host_register(struct mipi_dsi_host *host, bool check_defer); int msm_dsi_host_register(struct mipi_dsi_host *host, bool check_defer);
void msm_dsi_host_unregister(struct mipi_dsi_host *host); void msm_dsi_host_unregister(struct mipi_dsi_host *host);
int msm_dsi_host_set_src_pll(struct mipi_dsi_host *host,
struct msm_dsi_pll *src_pll);
void msm_dsi_host_destroy(struct mipi_dsi_host *host); void msm_dsi_host_destroy(struct mipi_dsi_host *host);
int msm_dsi_host_modeset_init(struct mipi_dsi_host *host, int msm_dsi_host_modeset_init(struct mipi_dsi_host *host,
struct drm_device *dev); struct drm_device *dev);
...@@ -101,17 +151,14 @@ int msm_dsi_host_init(struct msm_dsi *msm_dsi); ...@@ -101,17 +151,14 @@ int msm_dsi_host_init(struct msm_dsi *msm_dsi);
/* dsi phy */ /* dsi phy */
struct msm_dsi_phy; struct msm_dsi_phy;
enum msm_dsi_phy_type { void msm_dsi_phy_driver_register(void);
MSM_DSI_PHY_UNKNOWN, void msm_dsi_phy_driver_unregister(void);
MSM_DSI_PHY_28NM,
MSM_DSI_PHY_MAX
};
struct msm_dsi_phy *msm_dsi_phy_init(struct platform_device *pdev,
enum msm_dsi_phy_type type, int id);
int msm_dsi_phy_enable(struct msm_dsi_phy *phy, bool is_dual_panel, int msm_dsi_phy_enable(struct msm_dsi_phy *phy, bool is_dual_panel,
const unsigned long bit_rate, const unsigned long esc_rate); const unsigned long bit_rate, const unsigned long esc_rate);
int msm_dsi_phy_disable(struct msm_dsi_phy *phy); int msm_dsi_phy_disable(struct msm_dsi_phy *phy);
void msm_dsi_phy_get_clk_pre_post(struct msm_dsi_phy *phy, void msm_dsi_phy_get_clk_pre_post(struct msm_dsi_phy *phy,
u32 *clk_pre, u32 *clk_post); u32 *clk_pre, u32 *clk_post);
struct msm_dsi_pll *msm_dsi_phy_get_pll(struct msm_dsi_phy *phy);
#endif /* __DSI_CONNECTOR_H__ */ #endif /* __DSI_CONNECTOR_H__ */
...@@ -8,8 +8,17 @@ This file was generated by the rules-ng-ng headergen tool in this git repository ...@@ -8,8 +8,17 @@ This file was generated by the rules-ng-ng headergen tool in this git repository
git clone https://github.com/freedreno/envytools.git git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are: The rules-ng-ng source files this header was generated from are:
- /usr2/hali/local/envytools/envytools/rnndb/dsi/dsi.xml ( 18681 bytes, from 2015-03-04 23:08:31) - /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2014-12-05 15:34:49)
- /usr2/hali/local/envytools/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-01-28 21:43:22) - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-03-24 22:05:22)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2352 bytes, from 2015-04-12 15:02:42)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 35083 bytes, from 2015-04-12 15:04:03)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 22094 bytes, from 2015-05-12 12:45:23)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2014-10-31 16:48:57)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29012 bytes, from 2015-05-12 12:45:23)
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-12 12:45:23)
Copyright (C) 2013-2015 by the following authors: Copyright (C) 2013-2015 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark) - Rob Clark <robdclark@gmail.com> (robclark)
...@@ -394,6 +403,9 @@ static inline uint32_t DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(uint32_t val) ...@@ -394,6 +403,9 @@ static inline uint32_t DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(uint32_t val)
#define DSI_EOT_PACKET_CTRL_TX_EOT_APPEND 0x00000001 #define DSI_EOT_PACKET_CTRL_TX_EOT_APPEND 0x00000001
#define DSI_EOT_PACKET_CTRL_RX_EOT_IGNORE 0x00000010 #define DSI_EOT_PACKET_CTRL_RX_EOT_IGNORE 0x00000010
#define REG_DSI_LANE_CTRL 0x000000a8
#define DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST 0x10000000
#define REG_DSI_LANE_SWAP_CTRL 0x000000ac #define REG_DSI_LANE_SWAP_CTRL 0x000000ac
#define DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__MASK 0x00000007 #define DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__MASK 0x00000007
#define DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__SHIFT 0 #define DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__SHIFT 0
...@@ -835,5 +847,152 @@ static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val) ...@@ -835,5 +847,152 @@ static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)
#define REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG 0x00000018 #define REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG 0x00000018
#define REG_DSI_28nm_PHY_PLL_REFCLK_CFG 0x00000000
#define DSI_28nm_PHY_PLL_REFCLK_CFG_DBLR 0x00000001
#define REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG 0x00000004
#define REG_DSI_28nm_PHY_PLL_CHGPUMP_CFG 0x00000008
#define REG_DSI_28nm_PHY_PLL_VCOLPF_CFG 0x0000000c
#define REG_DSI_28nm_PHY_PLL_VREG_CFG 0x00000010
#define DSI_28nm_PHY_PLL_VREG_CFG_POSTDIV1_BYPASS_B 0x00000002
#define REG_DSI_28nm_PHY_PLL_PWRGEN_CFG 0x00000014
#define REG_DSI_28nm_PHY_PLL_DMUX_CFG 0x00000018
#define REG_DSI_28nm_PHY_PLL_AMUX_CFG 0x0000001c
#define REG_DSI_28nm_PHY_PLL_GLB_CFG 0x00000020
#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B 0x00000001
#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B 0x00000002
#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B 0x00000004
#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE 0x00000008
#define REG_DSI_28nm_PHY_PLL_POSTDIV2_CFG 0x00000024
#define REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG 0x00000028
#define REG_DSI_28nm_PHY_PLL_LPFR_CFG 0x0000002c
#define REG_DSI_28nm_PHY_PLL_LPFC1_CFG 0x00000030
#define REG_DSI_28nm_PHY_PLL_LPFC2_CFG 0x00000034
#define REG_DSI_28nm_PHY_PLL_SDM_CFG0 0x00000038
#define DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__MASK 0x0000003f
#define DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__SHIFT 0
static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV(uint32_t val)
{
return ((val) << DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__MASK;
}
#define DSI_28nm_PHY_PLL_SDM_CFG0_BYP 0x00000040
#define REG_DSI_28nm_PHY_PLL_SDM_CFG1 0x0000003c
#define DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__MASK 0x0000003f
#define DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__SHIFT 0
static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET(uint32_t val)
{
return ((val) << DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__MASK;
}
#define DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__MASK 0x00000040
#define DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__SHIFT 6
static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN(uint32_t val)
{
return ((val) << DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__MASK;
}
#define REG_DSI_28nm_PHY_PLL_SDM_CFG2 0x00000040
#define DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__MASK 0x000000ff
#define DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__SHIFT 0
static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0(uint32_t val)
{
return ((val) << DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__MASK;
}
#define REG_DSI_28nm_PHY_PLL_SDM_CFG3 0x00000044
#define DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__MASK 0x000000ff
#define DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__SHIFT 0
static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8(uint32_t val)
{
return ((val) << DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__MASK;
}
#define REG_DSI_28nm_PHY_PLL_SDM_CFG4 0x00000048
#define REG_DSI_28nm_PHY_PLL_SSC_CFG0 0x0000004c
#define REG_DSI_28nm_PHY_PLL_SSC_CFG1 0x00000050
#define REG_DSI_28nm_PHY_PLL_SSC_CFG2 0x00000054
#define REG_DSI_28nm_PHY_PLL_SSC_CFG3 0x00000058
#define REG_DSI_28nm_PHY_PLL_LKDET_CFG0 0x0000005c
#define REG_DSI_28nm_PHY_PLL_LKDET_CFG1 0x00000060
#define REG_DSI_28nm_PHY_PLL_LKDET_CFG2 0x00000064
#define REG_DSI_28nm_PHY_PLL_TEST_CFG 0x00000068
#define DSI_28nm_PHY_PLL_TEST_CFG_PLL_SW_RESET 0x00000001
#define REG_DSI_28nm_PHY_PLL_CAL_CFG0 0x0000006c
#define REG_DSI_28nm_PHY_PLL_CAL_CFG1 0x00000070
#define REG_DSI_28nm_PHY_PLL_CAL_CFG2 0x00000074
#define REG_DSI_28nm_PHY_PLL_CAL_CFG3 0x00000078
#define REG_DSI_28nm_PHY_PLL_CAL_CFG4 0x0000007c
#define REG_DSI_28nm_PHY_PLL_CAL_CFG5 0x00000080
#define REG_DSI_28nm_PHY_PLL_CAL_CFG6 0x00000084
#define REG_DSI_28nm_PHY_PLL_CAL_CFG7 0x00000088
#define REG_DSI_28nm_PHY_PLL_CAL_CFG8 0x0000008c
#define REG_DSI_28nm_PHY_PLL_CAL_CFG9 0x00000090
#define REG_DSI_28nm_PHY_PLL_CAL_CFG10 0x00000094
#define REG_DSI_28nm_PHY_PLL_CAL_CFG11 0x00000098
#define REG_DSI_28nm_PHY_PLL_EFUSE_CFG 0x0000009c
#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS_SEL 0x000000a0
#define REG_DSI_28nm_PHY_PLL_CTRL_42 0x000000a4
#define REG_DSI_28nm_PHY_PLL_CTRL_43 0x000000a8
#define REG_DSI_28nm_PHY_PLL_CTRL_44 0x000000ac
#define REG_DSI_28nm_PHY_PLL_CTRL_45 0x000000b0
#define REG_DSI_28nm_PHY_PLL_CTRL_46 0x000000b4
#define REG_DSI_28nm_PHY_PLL_CTRL_47 0x000000b8
#define REG_DSI_28nm_PHY_PLL_CTRL_48 0x000000bc
#define REG_DSI_28nm_PHY_PLL_STATUS 0x000000c0
#define DSI_28nm_PHY_PLL_STATUS_PLL_RDY 0x00000001
#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS0 0x000000c4
#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS1 0x000000c8
#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS2 0x000000cc
#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS3 0x000000d0
#define REG_DSI_28nm_PHY_PLL_CTRL_54 0x000000d4
#endif /* DSI_XML */ #endif /* DSI_XML */
...@@ -15,6 +15,7 @@ ...@@ -15,6 +15,7 @@
#include <linux/delay.h> #include <linux/delay.h>
#include <linux/err.h> #include <linux/err.h>
#include <linux/gpio.h> #include <linux/gpio.h>
#include <linux/gpio/consumer.h>
#include <linux/interrupt.h> #include <linux/interrupt.h>
#include <linux/of_device.h> #include <linux/of_device.h>
#include <linux/of_gpio.h> #include <linux/of_gpio.h>
...@@ -36,35 +37,19 @@ ...@@ -36,35 +37,19 @@
#define DSI_6G_REG_SHIFT 4 #define DSI_6G_REG_SHIFT 4
#define DSI_REGULATOR_MAX 8
struct dsi_reg_entry {
char name[32];
int min_voltage;
int max_voltage;
int enable_load;
int disable_load;
};
struct dsi_reg_config {
int num;
struct dsi_reg_entry regs[DSI_REGULATOR_MAX];
};
struct dsi_config { struct dsi_config {
u32 major; u32 major;
u32 minor; u32 minor;
u32 io_offset; u32 io_offset;
enum msm_dsi_phy_type phy_type;
struct dsi_reg_config reg_cfg; struct dsi_reg_config reg_cfg;
}; };
static const struct dsi_config dsi_cfgs[] = { static const struct dsi_config dsi_cfgs[] = {
{MSM_DSI_VER_MAJOR_V2, 0, 0, MSM_DSI_PHY_UNKNOWN}, {MSM_DSI_VER_MAJOR_V2, 0, 0, {0,} },
{ /* 8974 v1 */ { /* 8974 v1 */
.major = MSM_DSI_VER_MAJOR_6G, .major = MSM_DSI_VER_MAJOR_6G,
.minor = MSM_DSI_6G_VER_MINOR_V1_0, .minor = MSM_DSI_6G_VER_MINOR_V1_0,
.io_offset = DSI_6G_REG_SHIFT, .io_offset = DSI_6G_REG_SHIFT,
.phy_type = MSM_DSI_PHY_28NM,
.reg_cfg = { .reg_cfg = {
.num = 4, .num = 4,
.regs = { .regs = {
...@@ -79,7 +64,6 @@ static const struct dsi_config dsi_cfgs[] = { ...@@ -79,7 +64,6 @@ static const struct dsi_config dsi_cfgs[] = {
.major = MSM_DSI_VER_MAJOR_6G, .major = MSM_DSI_VER_MAJOR_6G,
.minor = MSM_DSI_6G_VER_MINOR_V1_1, .minor = MSM_DSI_6G_VER_MINOR_V1_1,
.io_offset = DSI_6G_REG_SHIFT, .io_offset = DSI_6G_REG_SHIFT,
.phy_type = MSM_DSI_PHY_28NM,
.reg_cfg = { .reg_cfg = {
.num = 4, .num = 4,
.regs = { .regs = {
...@@ -94,7 +78,6 @@ static const struct dsi_config dsi_cfgs[] = { ...@@ -94,7 +78,6 @@ static const struct dsi_config dsi_cfgs[] = {
.major = MSM_DSI_VER_MAJOR_6G, .major = MSM_DSI_VER_MAJOR_6G,
.minor = MSM_DSI_6G_VER_MINOR_V1_1_1, .minor = MSM_DSI_6G_VER_MINOR_V1_1_1,
.io_offset = DSI_6G_REG_SHIFT, .io_offset = DSI_6G_REG_SHIFT,
.phy_type = MSM_DSI_PHY_28NM,
.reg_cfg = { .reg_cfg = {
.num = 4, .num = 4,
.regs = { .regs = {
...@@ -109,7 +92,6 @@ static const struct dsi_config dsi_cfgs[] = { ...@@ -109,7 +92,6 @@ static const struct dsi_config dsi_cfgs[] = {
.major = MSM_DSI_VER_MAJOR_6G, .major = MSM_DSI_VER_MAJOR_6G,
.minor = MSM_DSI_6G_VER_MINOR_V1_2, .minor = MSM_DSI_6G_VER_MINOR_V1_2,
.io_offset = DSI_6G_REG_SHIFT, .io_offset = DSI_6G_REG_SHIFT,
.phy_type = MSM_DSI_PHY_28NM,
.reg_cfg = { .reg_cfg = {
.num = 4, .num = 4,
.regs = { .regs = {
...@@ -124,7 +106,6 @@ static const struct dsi_config dsi_cfgs[] = { ...@@ -124,7 +106,6 @@ static const struct dsi_config dsi_cfgs[] = {
.major = MSM_DSI_VER_MAJOR_6G, .major = MSM_DSI_VER_MAJOR_6G,
.minor = MSM_DSI_6G_VER_MINOR_V1_3_1, .minor = MSM_DSI_6G_VER_MINOR_V1_3_1,
.io_offset = DSI_6G_REG_SHIFT, .io_offset = DSI_6G_REG_SHIFT,
.phy_type = MSM_DSI_PHY_28NM,
.reg_cfg = { .reg_cfg = {
.num = 4, .num = 4,
.regs = { .regs = {
...@@ -197,7 +178,7 @@ struct msm_dsi_host { ...@@ -197,7 +178,7 @@ struct msm_dsi_host {
int id; int id;
void __iomem *ctrl_base; void __iomem *ctrl_base;
struct regulator_bulk_data supplies[DSI_REGULATOR_MAX]; struct regulator_bulk_data supplies[DSI_DEV_REGULATOR_MAX];
struct clk *mdp_core_clk; struct clk *mdp_core_clk;
struct clk *ahb_clk; struct clk *ahb_clk;
struct clk *axi_clk; struct clk *axi_clk;
...@@ -205,6 +186,9 @@ struct msm_dsi_host { ...@@ -205,6 +186,9 @@ struct msm_dsi_host {
struct clk *byte_clk; struct clk *byte_clk;
struct clk *esc_clk; struct clk *esc_clk;
struct clk *pixel_clk; struct clk *pixel_clk;
struct clk *byte_clk_src;
struct clk *pixel_clk_src;
u32 byte_clk_rate; u32 byte_clk_rate;
struct gpio_desc *disp_en_gpio; struct gpio_desc *disp_en_gpio;
...@@ -273,7 +257,7 @@ static const struct dsi_config *dsi_get_config(struct msm_dsi_host *msm_host) ...@@ -273,7 +257,7 @@ static const struct dsi_config *dsi_get_config(struct msm_dsi_host *msm_host)
u32 major = 0, minor = 0; u32 major = 0, minor = 0;
gdsc_reg = regulator_get(&msm_host->pdev->dev, "gdsc"); gdsc_reg = regulator_get(&msm_host->pdev->dev, "gdsc");
if (IS_ERR_OR_NULL(gdsc_reg)) { if (IS_ERR(gdsc_reg)) {
pr_err("%s: cannot get gdsc\n", __func__); pr_err("%s: cannot get gdsc\n", __func__);
goto fail; goto fail;
} }
...@@ -463,6 +447,22 @@ static int dsi_clk_init(struct msm_dsi_host *msm_host) ...@@ -463,6 +447,22 @@ static int dsi_clk_init(struct msm_dsi_host *msm_host)
goto exit; goto exit;
} }
msm_host->byte_clk_src = devm_clk_get(dev, "byte_clk_src");
if (IS_ERR(msm_host->byte_clk_src)) {
ret = PTR_ERR(msm_host->byte_clk_src);
pr_err("%s: can't find byte_clk_src. ret=%d\n", __func__, ret);
msm_host->byte_clk_src = NULL;
goto exit;
}
msm_host->pixel_clk_src = devm_clk_get(dev, "pixel_clk_src");
if (IS_ERR(msm_host->pixel_clk_src)) {
ret = PTR_ERR(msm_host->pixel_clk_src);
pr_err("%s: can't find pixel_clk_src. ret=%d\n", __func__, ret);
msm_host->pixel_clk_src = NULL;
goto exit;
}
exit: exit:
return ret; return ret;
} }
...@@ -787,6 +787,11 @@ static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable, ...@@ -787,6 +787,11 @@ static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable,
dsi_write(msm_host, REG_DSI_LANE_SWAP_CTRL, dsi_write(msm_host, REG_DSI_LANE_SWAP_CTRL,
DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(LANE_SWAP_0123)); DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(LANE_SWAP_0123));
} }
if (!(flags & MIPI_DSI_CLOCK_NON_CONTINUOUS))
dsi_write(msm_host, REG_DSI_LANE_CTRL,
DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST);
data |= DSI_CTRL_ENABLE; data |= DSI_CTRL_ENABLE;
dsi_write(msm_host, REG_DSI_CTRL, data); dsi_write(msm_host, REG_DSI_CTRL, data);
...@@ -1345,36 +1350,19 @@ static irqreturn_t dsi_host_irq(int irq, void *ptr) ...@@ -1345,36 +1350,19 @@ static irqreturn_t dsi_host_irq(int irq, void *ptr)
static int dsi_host_init_panel_gpios(struct msm_dsi_host *msm_host, static int dsi_host_init_panel_gpios(struct msm_dsi_host *msm_host,
struct device *panel_device) struct device *panel_device)
{ {
int ret; msm_host->disp_en_gpio = devm_gpiod_get_optional(panel_device,
"disp-enable",
msm_host->disp_en_gpio = devm_gpiod_get(panel_device, GPIOD_OUT_LOW);
"disp-enable");
if (IS_ERR(msm_host->disp_en_gpio)) { if (IS_ERR(msm_host->disp_en_gpio)) {
DBG("cannot get disp-enable-gpios %ld", DBG("cannot get disp-enable-gpios %ld",
PTR_ERR(msm_host->disp_en_gpio)); PTR_ERR(msm_host->disp_en_gpio));
msm_host->disp_en_gpio = NULL; return PTR_ERR(msm_host->disp_en_gpio);
}
if (msm_host->disp_en_gpio) {
ret = gpiod_direction_output(msm_host->disp_en_gpio, 0);
if (ret) {
pr_err("cannot set dir to disp-en-gpios %d\n", ret);
return ret;
}
} }
msm_host->te_gpio = devm_gpiod_get(panel_device, "disp-te"); msm_host->te_gpio = devm_gpiod_get(panel_device, "disp-te", GPIOD_IN);
if (IS_ERR(msm_host->te_gpio)) { if (IS_ERR(msm_host->te_gpio)) {
DBG("cannot get disp-te-gpios %ld", PTR_ERR(msm_host->te_gpio)); DBG("cannot get disp-te-gpios %ld", PTR_ERR(msm_host->te_gpio));
msm_host->te_gpio = NULL; return PTR_ERR(msm_host->te_gpio);
}
if (msm_host->te_gpio) {
ret = gpiod_direction_input(msm_host->te_gpio);
if (ret) {
pr_err("%s: cannot set dir to disp-te-gpios, %d\n",
__func__, ret);
return ret;
}
} }
return 0; return 0;
...@@ -1508,13 +1496,6 @@ int msm_dsi_host_init(struct msm_dsi *msm_dsi) ...@@ -1508,13 +1496,6 @@ int msm_dsi_host_init(struct msm_dsi *msm_dsi)
msm_host->workqueue = alloc_ordered_workqueue("dsi_drm_work", 0); msm_host->workqueue = alloc_ordered_workqueue("dsi_drm_work", 0);
INIT_WORK(&msm_host->err_work, dsi_err_worker); INIT_WORK(&msm_host->err_work, dsi_err_worker);
msm_dsi->phy = msm_dsi_phy_init(pdev, msm_host->cfg->phy_type,
msm_host->id);
if (!msm_dsi->phy) {
ret = -EINVAL;
pr_err("%s: phy init failed\n", __func__);
goto fail;
}
msm_dsi->host = &msm_host->base; msm_dsi->host = &msm_host->base;
msm_dsi->id = msm_host->id; msm_dsi->id = msm_host->id;
...@@ -1824,6 +1805,39 @@ void msm_dsi_host_cmd_xfer_commit(struct mipi_dsi_host *host, u32 iova, u32 len) ...@@ -1824,6 +1805,39 @@ void msm_dsi_host_cmd_xfer_commit(struct mipi_dsi_host *host, u32 iova, u32 len)
wmb(); wmb();
} }
int msm_dsi_host_set_src_pll(struct mipi_dsi_host *host,
struct msm_dsi_pll *src_pll)
{
struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
struct clk *byte_clk_provider, *pixel_clk_provider;
int ret;
ret = msm_dsi_pll_get_clk_provider(src_pll,
&byte_clk_provider, &pixel_clk_provider);
if (ret) {
pr_info("%s: can't get provider from pll, don't set parent\n",
__func__);
return 0;
}
ret = clk_set_parent(msm_host->byte_clk_src, byte_clk_provider);
if (ret) {
pr_err("%s: can't set parent to byte_clk_src. ret=%d\n",
__func__, ret);
goto exit;
}
ret = clk_set_parent(msm_host->pixel_clk_src, pixel_clk_provider);
if (ret) {
pr_err("%s: can't set parent to pixel_clk_src. ret=%d\n",
__func__, ret);
goto exit;
}
exit:
return ret;
}
int msm_dsi_host_enable(struct mipi_dsi_host *host) int msm_dsi_host_enable(struct mipi_dsi_host *host)
{ {
struct msm_dsi_host *msm_host = to_msm_dsi_host(host); struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
......
...@@ -60,6 +60,53 @@ static int dsi_mgr_parse_dual_panel(struct device_node *np, int id) ...@@ -60,6 +60,53 @@ static int dsi_mgr_parse_dual_panel(struct device_node *np, int id)
return 0; return 0;
} }
static int dsi_mgr_host_register(int id)
{
struct msm_dsi *msm_dsi = dsi_mgr_get_dsi(id);
struct msm_dsi *other_dsi = dsi_mgr_get_other_dsi(id);
struct msm_dsi *clk_master_dsi = dsi_mgr_get_dsi(DSI_CLOCK_MASTER);
struct msm_dsi_pll *src_pll;
int ret;
if (!IS_DUAL_PANEL()) {
ret = msm_dsi_host_register(msm_dsi->host, true);
if (ret)
return ret;
src_pll = msm_dsi_phy_get_pll(msm_dsi->phy);
ret = msm_dsi_host_set_src_pll(msm_dsi->host, src_pll);
} else if (!other_dsi) {
ret = 0;
} else {
struct msm_dsi *mdsi = IS_MASTER_PANEL(id) ?
msm_dsi : other_dsi;
struct msm_dsi *sdsi = IS_MASTER_PANEL(id) ?
other_dsi : msm_dsi;
/* Register slave host first, so that slave DSI device
* has a chance to probe, and do not block the master
* DSI device's probe.
* Also, do not check defer for the slave host,
* because only master DSI device adds the panel to global
* panel list. The panel's device is the master DSI device.
*/
ret = msm_dsi_host_register(sdsi->host, false);
if (ret)
return ret;
ret = msm_dsi_host_register(mdsi->host, true);
if (ret)
return ret;
/* PLL0 is to drive both 2 DSI link clocks in Dual DSI mode. */
src_pll = msm_dsi_phy_get_pll(clk_master_dsi->phy);
ret = msm_dsi_host_set_src_pll(msm_dsi->host, src_pll);
if (ret)
return ret;
ret = msm_dsi_host_set_src_pll(other_dsi->host, src_pll);
}
return ret;
}
struct dsi_connector { struct dsi_connector {
struct drm_connector base; struct drm_connector base;
int id; int id;
...@@ -652,7 +699,6 @@ int msm_dsi_manager_register(struct msm_dsi *msm_dsi) ...@@ -652,7 +699,6 @@ int msm_dsi_manager_register(struct msm_dsi *msm_dsi)
{ {
struct msm_dsi_manager *msm_dsim = &msm_dsim_glb; struct msm_dsi_manager *msm_dsim = &msm_dsim_glb;
int id = msm_dsi->id; int id = msm_dsi->id;
struct msm_dsi *other_dsi = dsi_mgr_get_other_dsi(id);
int ret; int ret;
if (id > DSI_MAX) { if (id > DSI_MAX) {
...@@ -670,31 +716,20 @@ int msm_dsi_manager_register(struct msm_dsi *msm_dsi) ...@@ -670,31 +716,20 @@ int msm_dsi_manager_register(struct msm_dsi *msm_dsi)
ret = dsi_mgr_parse_dual_panel(msm_dsi->pdev->dev.of_node, id); ret = dsi_mgr_parse_dual_panel(msm_dsi->pdev->dev.of_node, id);
if (ret) { if (ret) {
pr_err("%s: failed to parse dual panel info\n", __func__); pr_err("%s: failed to parse dual panel info\n", __func__);
return ret; goto fail;
} }
if (!IS_DUAL_PANEL()) { ret = dsi_mgr_host_register(id);
ret = msm_dsi_host_register(msm_dsi->host, true); if (ret) {
} else if (!other_dsi) { pr_err("%s: failed to register mipi dsi host for DSI %d\n",
return 0; __func__, id);
} else { goto fail;
struct msm_dsi *mdsi = IS_MASTER_PANEL(id) ?
msm_dsi : other_dsi;
struct msm_dsi *sdsi = IS_MASTER_PANEL(id) ?
other_dsi : msm_dsi;
/* Register slave host first, so that slave DSI device
* has a chance to probe, and do not block the master
* DSI device's probe.
* Also, do not check defer for the slave host,
* because only master DSI device adds the panel to global
* panel list. The panel's device is the master DSI device.
*/
ret = msm_dsi_host_register(sdsi->host, false);
if (ret)
return ret;
ret = msm_dsi_host_register(mdsi->host, true);
} }
return 0;
fail:
msm_dsim->dsi[id] = NULL;
return ret; return ret;
} }
......
...@@ -11,12 +11,27 @@ ...@@ -11,12 +11,27 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>
#include "dsi.h" #include "dsi.h"
#include "dsi.xml.h" #include "dsi.xml.h"
#define dsi_phy_read(offset) msm_readl((offset)) #define dsi_phy_read(offset) msm_readl((offset))
#define dsi_phy_write(offset, data) msm_writel((data), (offset)) #define dsi_phy_write(offset, data) msm_writel((data), (offset))
struct dsi_phy_ops {
int (*enable)(struct msm_dsi_phy *phy, bool is_dual_panel,
const unsigned long bit_rate, const unsigned long esc_rate);
int (*disable)(struct msm_dsi_phy *phy);
};
struct dsi_phy_cfg {
enum msm_dsi_phy_type type;
struct dsi_reg_config reg_cfg;
struct dsi_phy_ops ops;
};
struct dsi_dphy_timing { struct dsi_dphy_timing {
u32 clk_pre; u32 clk_pre;
u32 clk_post; u32 clk_post;
...@@ -34,15 +49,106 @@ struct dsi_dphy_timing { ...@@ -34,15 +49,106 @@ struct dsi_dphy_timing {
}; };
struct msm_dsi_phy { struct msm_dsi_phy {
struct platform_device *pdev;
void __iomem *base; void __iomem *base;
void __iomem *reg_base; void __iomem *reg_base;
int id; int id;
struct clk *ahb_clk;
struct regulator_bulk_data supplies[DSI_DEV_REGULATOR_MAX];
struct dsi_dphy_timing timing; struct dsi_dphy_timing timing;
int (*enable)(struct msm_dsi_phy *phy, bool is_dual_panel, const struct dsi_phy_cfg *cfg;
const unsigned long bit_rate, const unsigned long esc_rate);
int (*disable)(struct msm_dsi_phy *phy); struct msm_dsi_pll *pll;
}; };
static int dsi_phy_regulator_init(struct msm_dsi_phy *phy)
{
struct regulator_bulk_data *s = phy->supplies;
const struct dsi_reg_entry *regs = phy->cfg->reg_cfg.regs;
struct device *dev = &phy->pdev->dev;
int num = phy->cfg->reg_cfg.num;
int i, ret;
for (i = 0; i < num; i++)
s[i].supply = regs[i].name;
ret = devm_regulator_bulk_get(&phy->pdev->dev, num, s);
if (ret < 0) {
dev_err(dev, "%s: failed to init regulator, ret=%d\n",
__func__, ret);
return ret;
}
for (i = 0; i < num; i++) {
if ((regs[i].min_voltage >= 0) && (regs[i].max_voltage >= 0)) {
ret = regulator_set_voltage(s[i].consumer,
regs[i].min_voltage, regs[i].max_voltage);
if (ret < 0) {
dev_err(dev,
"regulator %d set voltage failed, %d\n",
i, ret);
return ret;
}
}
}
return 0;
}
static void dsi_phy_regulator_disable(struct msm_dsi_phy *phy)
{
struct regulator_bulk_data *s = phy->supplies;
const struct dsi_reg_entry *regs = phy->cfg->reg_cfg.regs;
int num = phy->cfg->reg_cfg.num;
int i;
DBG("");
for (i = num - 1; i >= 0; i--)
if (regs[i].disable_load >= 0)
regulator_set_load(s[i].consumer,
regs[i].disable_load);
regulator_bulk_disable(num, s);
}
static int dsi_phy_regulator_enable(struct msm_dsi_phy *phy)
{
struct regulator_bulk_data *s = phy->supplies;
const struct dsi_reg_entry *regs = phy->cfg->reg_cfg.regs;
struct device *dev = &phy->pdev->dev;
int num = phy->cfg->reg_cfg.num;
int ret, i;
DBG("");
for (i = 0; i < num; i++) {
if (regs[i].enable_load >= 0) {
ret = regulator_set_load(s[i].consumer,
regs[i].enable_load);
if (ret < 0) {
dev_err(dev,
"regulator %d set op mode failed, %d\n",
i, ret);
goto fail;
}
}
}
ret = regulator_bulk_enable(num, s);
if (ret < 0) {
dev_err(dev, "regulator enable failed, %d\n", ret);
goto fail;
}
return 0;
fail:
for (i--; i >= 0; i--)
regulator_set_load(s[i].consumer, regs[i].disable_load);
return ret;
}
#define S_DIV_ROUND_UP(n, d) \ #define S_DIV_ROUND_UP(n, d) \
(((n) >= 0) ? (((n) + (d) - 1) / (d)) : (((n) - (d) + 1) / (d))) (((n) >= 0) ? (((n) + (d) - 1) / (d)) : (((n) - (d) + 1) / (d)))
...@@ -284,59 +390,200 @@ static int dsi_28nm_phy_disable(struct msm_dsi_phy *phy) ...@@ -284,59 +390,200 @@ static int dsi_28nm_phy_disable(struct msm_dsi_phy *phy)
return 0; return 0;
} }
#define dsi_phy_func_init(name) \ static int dsi_phy_enable_resource(struct msm_dsi_phy *phy)
do { \ {
phy->enable = dsi_##name##_phy_enable; \ int ret;
phy->disable = dsi_##name##_phy_disable; \
} while (0) pm_runtime_get_sync(&phy->pdev->dev);
ret = clk_prepare_enable(phy->ahb_clk);
if (ret) {
pr_err("%s: can't enable ahb clk, %d\n", __func__, ret);
pm_runtime_put_sync(&phy->pdev->dev);
}
return ret;
}
struct msm_dsi_phy *msm_dsi_phy_init(struct platform_device *pdev, static void dsi_phy_disable_resource(struct msm_dsi_phy *phy)
enum msm_dsi_phy_type type, int id) {
clk_disable_unprepare(phy->ahb_clk);
pm_runtime_put_sync(&phy->pdev->dev);
}
static const struct dsi_phy_cfg dsi_phy_cfgs[MSM_DSI_PHY_MAX] = {
[MSM_DSI_PHY_28NM_HPM] = {
.type = MSM_DSI_PHY_28NM_HPM,
.reg_cfg = {
.num = 1,
.regs = {
{"vddio", 1800000, 1800000, 100000, 100},
},
},
.ops = {
.enable = dsi_28nm_phy_enable,
.disable = dsi_28nm_phy_disable,
}
},
[MSM_DSI_PHY_28NM_LP] = {
.type = MSM_DSI_PHY_28NM_LP,
.reg_cfg = {
.num = 1,
.regs = {
{"vddio", 1800000, 1800000, 100000, 100},
},
},
.ops = {
.enable = dsi_28nm_phy_enable,
.disable = dsi_28nm_phy_disable,
}
},
};
static const struct of_device_id dsi_phy_dt_match[] = {
{ .compatible = "qcom,dsi-phy-28nm-hpm",
.data = &dsi_phy_cfgs[MSM_DSI_PHY_28NM_HPM],},
{ .compatible = "qcom,dsi-phy-28nm-lp",
.data = &dsi_phy_cfgs[MSM_DSI_PHY_28NM_LP],},
{}
};
static int dsi_phy_driver_probe(struct platform_device *pdev)
{ {
struct msm_dsi_phy *phy; struct msm_dsi_phy *phy;
const struct of_device_id *match;
int ret;
phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL); phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL);
if (!phy) if (!phy)
return NULL; return -ENOMEM;
match = of_match_node(dsi_phy_dt_match, pdev->dev.of_node);
if (!match)
return -ENODEV;
phy->cfg = match->data;
phy->pdev = pdev;
ret = of_property_read_u32(pdev->dev.of_node,
"qcom,dsi-phy-index", &phy->id);
if (ret) {
dev_err(&pdev->dev,
"%s: PHY index not specified, ret=%d\n",
__func__, ret);
goto fail;
}
phy->base = msm_ioremap(pdev, "dsi_phy", "DSI_PHY"); phy->base = msm_ioremap(pdev, "dsi_phy", "DSI_PHY");
if (IS_ERR_OR_NULL(phy->base)) { if (IS_ERR(phy->base)) {
pr_err("%s: failed to map phy base\n", __func__); dev_err(&pdev->dev, "%s: failed to map phy base\n", __func__);
return NULL; ret = -ENOMEM;
goto fail;
} }
phy->reg_base = msm_ioremap(pdev, "dsi_phy_regulator", "DSI_PHY_REG"); phy->reg_base = msm_ioremap(pdev, "dsi_phy_regulator", "DSI_PHY_REG");
if (IS_ERR_OR_NULL(phy->reg_base)) { if (IS_ERR(phy->reg_base)) {
pr_err("%s: failed to map phy regulator base\n", __func__); dev_err(&pdev->dev,
return NULL; "%s: failed to map phy regulator base\n", __func__);
ret = -ENOMEM;
goto fail;
} }
switch (type) { ret = dsi_phy_regulator_init(phy);
case MSM_DSI_PHY_28NM: if (ret) {
dsi_phy_func_init(28nm); dev_err(&pdev->dev, "%s: failed to init regulator\n", __func__);
break; goto fail;
default: }
pr_err("%s: unsupported type, %d\n", __func__, type);
return NULL; phy->ahb_clk = devm_clk_get(&pdev->dev, "iface_clk");
if (IS_ERR(phy->ahb_clk)) {
pr_err("%s: Unable to get ahb clk\n", __func__);
ret = PTR_ERR(phy->ahb_clk);
goto fail;
}
/* PLL init will call into clk_register which requires
* register access, so we need to enable power and ahb clock.
*/
ret = dsi_phy_enable_resource(phy);
if (ret)
goto fail;
phy->pll = msm_dsi_pll_init(pdev, phy->cfg->type, phy->id);
if (!phy->pll)
dev_info(&pdev->dev,
"%s: pll init failed, need separate pll clk driver\n",
__func__);
dsi_phy_disable_resource(phy);
platform_set_drvdata(pdev, phy);
return 0;
fail:
return ret;
}
static int dsi_phy_driver_remove(struct platform_device *pdev)
{
struct msm_dsi_phy *phy = platform_get_drvdata(pdev);
if (phy && phy->pll) {
msm_dsi_pll_destroy(phy->pll);
phy->pll = NULL;
} }
phy->id = id; platform_set_drvdata(pdev, NULL);
return phy; return 0;
}
static struct platform_driver dsi_phy_platform_driver = {
.probe = dsi_phy_driver_probe,
.remove = dsi_phy_driver_remove,
.driver = {
.name = "msm_dsi_phy",
.of_match_table = dsi_phy_dt_match,
},
};
void __init msm_dsi_phy_driver_register(void)
{
platform_driver_register(&dsi_phy_platform_driver);
}
void __exit msm_dsi_phy_driver_unregister(void)
{
platform_driver_unregister(&dsi_phy_platform_driver);
} }
int msm_dsi_phy_enable(struct msm_dsi_phy *phy, bool is_dual_panel, int msm_dsi_phy_enable(struct msm_dsi_phy *phy, bool is_dual_panel,
const unsigned long bit_rate, const unsigned long esc_rate) const unsigned long bit_rate, const unsigned long esc_rate)
{ {
if (!phy || !phy->enable) int ret;
if (!phy || !phy->cfg->ops.enable)
return -EINVAL; return -EINVAL;
return phy->enable(phy, is_dual_panel, bit_rate, esc_rate);
ret = dsi_phy_regulator_enable(phy);
if (ret) {
dev_err(&phy->pdev->dev, "%s: regulator enable failed, %d\n",
__func__, ret);
return ret;
}
return phy->cfg->ops.enable(phy, is_dual_panel, bit_rate, esc_rate);
} }
int msm_dsi_phy_disable(struct msm_dsi_phy *phy) int msm_dsi_phy_disable(struct msm_dsi_phy *phy)
{ {
if (!phy || !phy->disable) if (!phy || !phy->cfg->ops.disable)
return -EINVAL; return -EINVAL;
return phy->disable(phy);
phy->cfg->ops.disable(phy);
dsi_phy_regulator_disable(phy);
return 0;
} }
void msm_dsi_phy_get_clk_pre_post(struct msm_dsi_phy *phy, void msm_dsi_phy_get_clk_pre_post(struct msm_dsi_phy *phy,
...@@ -350,3 +597,11 @@ void msm_dsi_phy_get_clk_pre_post(struct msm_dsi_phy *phy, ...@@ -350,3 +597,11 @@ void msm_dsi_phy_get_clk_pre_post(struct msm_dsi_phy *phy,
*clk_post = phy->timing.clk_post; *clk_post = phy->timing.clk_post;
} }
struct msm_dsi_pll *msm_dsi_phy_get_pll(struct msm_dsi_phy *phy)
{
if (!phy)
return NULL;
return phy->pll;
}
...@@ -10,15 +10,15 @@ git clone https://github.com/freedreno/envytools.git ...@@ -10,15 +10,15 @@ git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are: The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2014-12-05 15:34:49) - /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2014-12-05 15:34:49)
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20908 bytes, from 2014-12-08 16:13:00) - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-03-24 22:05:22)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2357 bytes, from 2014-12-08 16:13:00) - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2352 bytes, from 2015-04-12 15:02:42)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 27208 bytes, from 2015-01-13 23:56:11) - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 35083 bytes, from 2015-04-12 15:04:03)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43) - /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 22094 bytes, from 2015-05-12 12:45:23)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32) - /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2014-10-31 16:48:57) - /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2014-10-31 16:48:57)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12) - /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 26848 bytes, from 2015-01-13 23:55:57) - /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29012 bytes, from 2015-05-12 12:45:23)
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 8253 bytes, from 2014-12-08 16:13:00) - /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-12 12:45:23)
Copyright (C) 2013-2014 by the following authors: Copyright (C) 2013-2014 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark) - Rob Clark <robdclark@gmail.com> (robclark)
......
/*
* Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include "dsi_pll.h"
static int dsi_pll_enable(struct msm_dsi_pll *pll)
{
int i, ret = 0;
/*
* Certain PLLs do not allow VCO rate update when it is on.
* Keep track of their status to turn on/off after set rate success.
*/
if (unlikely(pll->pll_on))
return 0;
/* Try all enable sequences until one succeeds */
for (i = 0; i < pll->en_seq_cnt; i++) {
ret = pll->enable_seqs[i](pll);
DBG("DSI PLL %s after sequence #%d",
ret ? "unlocked" : "locked", i + 1);
if (!ret)
break;
}
if (ret) {
DRM_ERROR("DSI PLL failed to lock\n");
return ret;
}
pll->pll_on = true;
return 0;
}
static void dsi_pll_disable(struct msm_dsi_pll *pll)
{
if (unlikely(!pll->pll_on))
return;
pll->disable_seq(pll);
pll->pll_on = false;
}
/*
* DSI PLL Helper functions
*/
long msm_dsi_pll_helper_clk_round_rate(struct clk_hw *hw,
unsigned long rate, unsigned long *parent_rate)
{
struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
if (rate < pll->min_rate)
return pll->min_rate;
else if (rate > pll->max_rate)
return pll->max_rate;
else
return rate;
}
int msm_dsi_pll_helper_clk_prepare(struct clk_hw *hw)
{
struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
int ret;
/*
* Certain PLLs need to update the same VCO rate and registers
* after resume in suspend/resume scenario.
*/
if (pll->restore_state) {
ret = pll->restore_state(pll);
if (ret)
goto error;
}
ret = dsi_pll_enable(pll);
error:
return ret;
}
void msm_dsi_pll_helper_clk_unprepare(struct clk_hw *hw)
{
struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
if (pll->save_state)
pll->save_state(pll);
dsi_pll_disable(pll);
}
void msm_dsi_pll_helper_unregister_clks(struct platform_device *pdev,
struct clk **clks, u32 num_clks)
{
of_clk_del_provider(pdev->dev.of_node);
if (!num_clks || !clks)
return;
do {
clk_unregister(clks[--num_clks]);
clks[num_clks] = NULL;
} while (num_clks);
}
/*
* DSI PLL API
*/
int msm_dsi_pll_get_clk_provider(struct msm_dsi_pll *pll,
struct clk **byte_clk_provider, struct clk **pixel_clk_provider)
{
if (pll->get_provider)
return pll->get_provider(pll,
byte_clk_provider,
pixel_clk_provider);
return -EINVAL;
}
void msm_dsi_pll_destroy(struct msm_dsi_pll *pll)
{
if (pll->destroy)
pll->destroy(pll);
}
struct msm_dsi_pll *msm_dsi_pll_init(struct platform_device *pdev,
enum msm_dsi_phy_type type, int id)
{
struct device *dev = &pdev->dev;
struct msm_dsi_pll *pll;
switch (type) {
case MSM_DSI_PHY_28NM_HPM:
case MSM_DSI_PHY_28NM_LP:
pll = msm_dsi_pll_28nm_init(pdev, type, id);
break;
default:
pll = ERR_PTR(-ENXIO);
break;
}
if (IS_ERR(pll)) {
dev_err(dev, "%s: failed to init DSI PLL\n", __func__);
return NULL;
}
pll->type = type;
DBG("DSI:%d PLL registered", id);
return pll;
}
/*
* Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __DSI_PLL_H__
#define __DSI_PLL_H__
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include "dsi.h"
#define NUM_DSI_CLOCKS_MAX 6
#define MAX_DSI_PLL_EN_SEQS 10
struct msm_dsi_pll {
enum msm_dsi_phy_type type;
struct clk_hw clk_hw;
bool pll_on;
unsigned long min_rate;
unsigned long max_rate;
u32 en_seq_cnt;
int (*enable_seqs[MAX_DSI_PLL_EN_SEQS])(struct msm_dsi_pll *pll);
void (*disable_seq)(struct msm_dsi_pll *pll);
int (*get_provider)(struct msm_dsi_pll *pll,
struct clk **byte_clk_provider,
struct clk **pixel_clk_provider);
void (*destroy)(struct msm_dsi_pll *pll);
void (*save_state)(struct msm_dsi_pll *pll);
int (*restore_state)(struct msm_dsi_pll *pll);
};
#define hw_clk_to_pll(x) container_of(x, struct msm_dsi_pll, clk_hw)
static inline void pll_write(void __iomem *reg, u32 data)
{
msm_writel(data, reg);
}
static inline u32 pll_read(const void __iomem *reg)
{
return msm_readl(reg);
}
static inline void pll_write_udelay(void __iomem *reg, u32 data, u32 delay_us)
{
pll_write(reg, data);
udelay(delay_us);
}
static inline void pll_write_ndelay(void __iomem *reg, u32 data, u32 delay_ns)
{
pll_write((reg), data);
ndelay(delay_ns);
}
/*
* DSI PLL Helper functions
*/
/* clock callbacks */
long msm_dsi_pll_helper_clk_round_rate(struct clk_hw *hw,
unsigned long rate, unsigned long *parent_rate);
int msm_dsi_pll_helper_clk_prepare(struct clk_hw *hw);
void msm_dsi_pll_helper_clk_unprepare(struct clk_hw *hw);
/* misc */
void msm_dsi_pll_helper_unregister_clks(struct platform_device *pdev,
struct clk **clks, u32 num_clks);
/*
* Initialization for Each PLL Type
*/
struct msm_dsi_pll *msm_dsi_pll_28nm_init(struct platform_device *pdev,
enum msm_dsi_phy_type type, int id);
#endif /* __DSI_PLL_H__ */
This diff is collapsed.
...@@ -10,15 +10,15 @@ git clone https://github.com/freedreno/envytools.git ...@@ -10,15 +10,15 @@ git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are: The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2014-12-05 15:34:49) - /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2014-12-05 15:34:49)
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20908 bytes, from 2014-12-08 16:13:00) - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-03-24 22:05:22)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2357 bytes, from 2014-12-08 16:13:00) - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2352 bytes, from 2015-04-12 15:02:42)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 27208 bytes, from 2015-01-13 23:56:11) - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 35083 bytes, from 2015-04-12 15:04:03)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43) - /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 22094 bytes, from 2015-05-12 12:45:23)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32) - /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2014-10-31 16:48:57) - /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2014-10-31 16:48:57)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12) - /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 26848 bytes, from 2015-01-13 23:55:57) - /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29012 bytes, from 2015-05-12 12:45:23)
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 8253 bytes, from 2014-12-08 16:13:00) - /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-12 12:45:23)
Copyright (C) 2013 by the following authors: Copyright (C) 2013 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark) - Rob Clark <robdclark@gmail.com> (robclark)
......
...@@ -10,17 +10,17 @@ git clone https://github.com/freedreno/envytools.git ...@@ -10,17 +10,17 @@ git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are: The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2014-12-05 15:34:49) - /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2014-12-05 15:34:49)
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20908 bytes, from 2014-12-08 16:13:00) - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-03-24 22:05:22)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2357 bytes, from 2014-12-08 16:13:00) - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2352 bytes, from 2015-04-12 15:02:42)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 27208 bytes, from 2015-01-13 23:56:11) - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 35083 bytes, from 2015-04-12 15:04:03)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43) - /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 22094 bytes, from 2015-05-12 12:45:23)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32) - /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2014-10-31 16:48:57) - /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2014-10-31 16:48:57)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12) - /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 26848 bytes, from 2015-01-13 23:55:57) - /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29012 bytes, from 2015-05-12 12:45:23)
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 8253 bytes, from 2014-12-08 16:13:00) - /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-12 12:45:23)
Copyright (C) 2013-2014 by the following authors: Copyright (C) 2013-2015 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark) - Rob Clark <robdclark@gmail.com> (robclark)
Permission is hereby granted, free of charge, to any person obtaining Permission is hereby granted, free of charge, to any person obtaining
...@@ -288,5 +288,92 @@ static inline uint32_t REG_EDP_PHY_LN_PD_CTL(uint32_t i0) { return 0x00000404 + ...@@ -288,5 +288,92 @@ static inline uint32_t REG_EDP_PHY_LN_PD_CTL(uint32_t i0) { return 0x00000404 +
#define REG_EDP_PHY_GLB_PHY_STATUS 0x00000598 #define REG_EDP_PHY_GLB_PHY_STATUS 0x00000598
#define REG_EDP_28nm_PHY_PLL_REFCLK_CFG 0x00000000
#define REG_EDP_28nm_PHY_PLL_POSTDIV1_CFG 0x00000004
#define REG_EDP_28nm_PHY_PLL_CHGPUMP_CFG 0x00000008
#define REG_EDP_28nm_PHY_PLL_VCOLPF_CFG 0x0000000c
#define REG_EDP_28nm_PHY_PLL_VREG_CFG 0x00000010
#define REG_EDP_28nm_PHY_PLL_PWRGEN_CFG 0x00000014
#define REG_EDP_28nm_PHY_PLL_DMUX_CFG 0x00000018
#define REG_EDP_28nm_PHY_PLL_AMUX_CFG 0x0000001c
#define REG_EDP_28nm_PHY_PLL_GLB_CFG 0x00000020
#define EDP_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B 0x00000001
#define EDP_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B 0x00000002
#define EDP_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B 0x00000004
#define EDP_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE 0x00000008
#define REG_EDP_28nm_PHY_PLL_POSTDIV2_CFG 0x00000024
#define REG_EDP_28nm_PHY_PLL_POSTDIV3_CFG 0x00000028
#define REG_EDP_28nm_PHY_PLL_LPFR_CFG 0x0000002c
#define REG_EDP_28nm_PHY_PLL_LPFC1_CFG 0x00000030
#define REG_EDP_28nm_PHY_PLL_LPFC2_CFG 0x00000034
#define REG_EDP_28nm_PHY_PLL_SDM_CFG0 0x00000038
#define REG_EDP_28nm_PHY_PLL_SDM_CFG1 0x0000003c
#define REG_EDP_28nm_PHY_PLL_SDM_CFG2 0x00000040
#define REG_EDP_28nm_PHY_PLL_SDM_CFG3 0x00000044
#define REG_EDP_28nm_PHY_PLL_SDM_CFG4 0x00000048
#define REG_EDP_28nm_PHY_PLL_SSC_CFG0 0x0000004c
#define REG_EDP_28nm_PHY_PLL_SSC_CFG1 0x00000050
#define REG_EDP_28nm_PHY_PLL_SSC_CFG2 0x00000054
#define REG_EDP_28nm_PHY_PLL_SSC_CFG3 0x00000058
#define REG_EDP_28nm_PHY_PLL_LKDET_CFG0 0x0000005c
#define REG_EDP_28nm_PHY_PLL_LKDET_CFG1 0x00000060
#define REG_EDP_28nm_PHY_PLL_LKDET_CFG2 0x00000064
#define REG_EDP_28nm_PHY_PLL_TEST_CFG 0x00000068
#define EDP_28nm_PHY_PLL_TEST_CFG_PLL_SW_RESET 0x00000001
#define REG_EDP_28nm_PHY_PLL_CAL_CFG0 0x0000006c
#define REG_EDP_28nm_PHY_PLL_CAL_CFG1 0x00000070
#define REG_EDP_28nm_PHY_PLL_CAL_CFG2 0x00000074
#define REG_EDP_28nm_PHY_PLL_CAL_CFG3 0x00000078
#define REG_EDP_28nm_PHY_PLL_CAL_CFG4 0x0000007c
#define REG_EDP_28nm_PHY_PLL_CAL_CFG5 0x00000080
#define REG_EDP_28nm_PHY_PLL_CAL_CFG6 0x00000084
#define REG_EDP_28nm_PHY_PLL_CAL_CFG7 0x00000088
#define REG_EDP_28nm_PHY_PLL_CAL_CFG8 0x0000008c
#define REG_EDP_28nm_PHY_PLL_CAL_CFG9 0x00000090
#define REG_EDP_28nm_PHY_PLL_CAL_CFG10 0x00000094
#define REG_EDP_28nm_PHY_PLL_CAL_CFG11 0x00000098
#define REG_EDP_28nm_PHY_PLL_EFUSE_CFG 0x0000009c
#define REG_EDP_28nm_PHY_PLL_DEBUG_BUS_SEL 0x000000a0
#endif /* EDP_XML */ #endif /* EDP_XML */
...@@ -115,10 +115,12 @@ static int edp_msg_fifo_rx(struct edp_aux *aux, struct drm_dp_aux_msg *msg) ...@@ -115,10 +115,12 @@ static int edp_msg_fifo_rx(struct edp_aux *aux, struct drm_dp_aux_msg *msg)
* msm_edp_aux_ctrl() running concurrently in other threads, i.e. * msm_edp_aux_ctrl() running concurrently in other threads, i.e.
* start transaction only when AUX channel is fully enabled. * start transaction only when AUX channel is fully enabled.
*/ */
ssize_t edp_aux_transfer(struct drm_dp_aux *drm_aux, struct drm_dp_aux_msg *msg) static ssize_t edp_aux_transfer(struct drm_dp_aux *drm_aux,
struct drm_dp_aux_msg *msg)
{ {
struct edp_aux *aux = to_edp_aux(drm_aux); struct edp_aux *aux = to_edp_aux(drm_aux);
ssize_t ret; ssize_t ret;
unsigned long time_left;
bool native = msg->request & (DP_AUX_NATIVE_WRITE & DP_AUX_NATIVE_READ); bool native = msg->request & (DP_AUX_NATIVE_WRITE & DP_AUX_NATIVE_READ);
bool read = msg->request & (DP_AUX_I2C_READ & DP_AUX_NATIVE_READ); bool read = msg->request & (DP_AUX_I2C_READ & DP_AUX_NATIVE_READ);
...@@ -147,15 +149,17 @@ ssize_t edp_aux_transfer(struct drm_dp_aux *drm_aux, struct drm_dp_aux_msg *msg) ...@@ -147,15 +149,17 @@ ssize_t edp_aux_transfer(struct drm_dp_aux *drm_aux, struct drm_dp_aux_msg *msg)
goto unlock_exit; goto unlock_exit;
DBG("wait_for_completion"); DBG("wait_for_completion");
ret = wait_for_completion_timeout(&aux->msg_comp, 300); time_left = wait_for_completion_timeout(&aux->msg_comp,
if (ret <= 0) { msecs_to_jiffies(300));
if (!time_left) {
/* /*
* Clear GO and reset AUX channel * Clear GO and reset AUX channel
* to cancel the current transaction. * to cancel the current transaction.
*/ */
edp_write(aux->base + REG_EDP_AUX_TRANS_CTRL, 0); edp_write(aux->base + REG_EDP_AUX_TRANS_CTRL, 0);
msm_edp_aux_ctrl(aux, 1); msm_edp_aux_ctrl(aux, 1);
pr_err("%s: aux timeout, %zd\n", __func__, ret); pr_err("%s: aux timeout,\n", __func__);
ret = -ETIMEDOUT;
goto unlock_exit; goto unlock_exit;
} }
DBG("completion"); DBG("completion");
......
...@@ -1018,7 +1018,7 @@ static void edp_ctrl_off_worker(struct work_struct *work) ...@@ -1018,7 +1018,7 @@ static void edp_ctrl_off_worker(struct work_struct *work)
{ {
struct edp_ctrl *ctrl = container_of( struct edp_ctrl *ctrl = container_of(
work, struct edp_ctrl, off_work); work, struct edp_ctrl, off_work);
int ret; unsigned long time_left;
mutex_lock(&ctrl->dev_mutex); mutex_lock(&ctrl->dev_mutex);
...@@ -1030,11 +1030,10 @@ static void edp_ctrl_off_worker(struct work_struct *work) ...@@ -1030,11 +1030,10 @@ static void edp_ctrl_off_worker(struct work_struct *work)
reinit_completion(&ctrl->idle_comp); reinit_completion(&ctrl->idle_comp);
edp_state_ctrl(ctrl, EDP_STATE_CTRL_PUSH_IDLE); edp_state_ctrl(ctrl, EDP_STATE_CTRL_PUSH_IDLE);
ret = wait_for_completion_timeout(&ctrl->idle_comp, time_left = wait_for_completion_timeout(&ctrl->idle_comp,
msecs_to_jiffies(500)); msecs_to_jiffies(500));
if (ret <= 0) if (!time_left)
DBG("%s: idle pattern timedout, %d\n", DBG("%s: idle pattern timedout\n", __func__);
__func__, ret);
edp_state_ctrl(ctrl, 0); edp_state_ctrl(ctrl, 0);
......
...@@ -10,15 +10,15 @@ git clone https://github.com/freedreno/envytools.git ...@@ -10,15 +10,15 @@ git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are: The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2014-12-05 15:34:49) - /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2014-12-05 15:34:49)
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20908 bytes, from 2014-12-08 16:13:00) - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-03-24 22:05:22)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2357 bytes, from 2014-12-08 16:13:00) - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2352 bytes, from 2015-04-12 15:02:42)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 27208 bytes, from 2015-01-13 23:56:11) - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 35083 bytes, from 2015-04-12 15:04:03)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43) - /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 22094 bytes, from 2015-05-12 12:45:23)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32) - /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2014-10-31 16:48:57) - /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2014-10-31 16:48:57)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12) - /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 26848 bytes, from 2015-01-13 23:55:57) - /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29012 bytes, from 2015-05-12 12:45:23)
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 8253 bytes, from 2014-12-08 16:13:00) - /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-12 12:45:23)
Copyright (C) 2013-2015 by the following authors: Copyright (C) 2013-2015 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark) - Rob Clark <robdclark@gmail.com> (robclark)
...@@ -750,5 +750,92 @@ static inline uint32_t HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL(uint32_t val) ...@@ -750,5 +750,92 @@ static inline uint32_t HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL(uint32_t val)
#define REG_HDMI_8x74_BIST_PATN3 0x00000048 #define REG_HDMI_8x74_BIST_PATN3 0x00000048
#define REG_HDMI_28nm_PHY_PLL_REFCLK_CFG 0x00000000
#define REG_HDMI_28nm_PHY_PLL_POSTDIV1_CFG 0x00000004
#define REG_HDMI_28nm_PHY_PLL_CHGPUMP_CFG 0x00000008
#define REG_HDMI_28nm_PHY_PLL_VCOLPF_CFG 0x0000000c
#define REG_HDMI_28nm_PHY_PLL_VREG_CFG 0x00000010
#define REG_HDMI_28nm_PHY_PLL_PWRGEN_CFG 0x00000014
#define REG_HDMI_28nm_PHY_PLL_DMUX_CFG 0x00000018
#define REG_HDMI_28nm_PHY_PLL_AMUX_CFG 0x0000001c
#define REG_HDMI_28nm_PHY_PLL_GLB_CFG 0x00000020
#define HDMI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B 0x00000001
#define HDMI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B 0x00000002
#define HDMI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B 0x00000004
#define HDMI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE 0x00000008
#define REG_HDMI_28nm_PHY_PLL_POSTDIV2_CFG 0x00000024
#define REG_HDMI_28nm_PHY_PLL_POSTDIV3_CFG 0x00000028
#define REG_HDMI_28nm_PHY_PLL_LPFR_CFG 0x0000002c
#define REG_HDMI_28nm_PHY_PLL_LPFC1_CFG 0x00000030
#define REG_HDMI_28nm_PHY_PLL_LPFC2_CFG 0x00000034
#define REG_HDMI_28nm_PHY_PLL_SDM_CFG0 0x00000038
#define REG_HDMI_28nm_PHY_PLL_SDM_CFG1 0x0000003c
#define REG_HDMI_28nm_PHY_PLL_SDM_CFG2 0x00000040
#define REG_HDMI_28nm_PHY_PLL_SDM_CFG3 0x00000044
#define REG_HDMI_28nm_PHY_PLL_SDM_CFG4 0x00000048
#define REG_HDMI_28nm_PHY_PLL_SSC_CFG0 0x0000004c
#define REG_HDMI_28nm_PHY_PLL_SSC_CFG1 0x00000050
#define REG_HDMI_28nm_PHY_PLL_SSC_CFG2 0x00000054
#define REG_HDMI_28nm_PHY_PLL_SSC_CFG3 0x00000058
#define REG_HDMI_28nm_PHY_PLL_LKDET_CFG0 0x0000005c
#define REG_HDMI_28nm_PHY_PLL_LKDET_CFG1 0x00000060
#define REG_HDMI_28nm_PHY_PLL_LKDET_CFG2 0x00000064
#define REG_HDMI_28nm_PHY_PLL_TEST_CFG 0x00000068
#define HDMI_28nm_PHY_PLL_TEST_CFG_PLL_SW_RESET 0x00000001
#define REG_HDMI_28nm_PHY_PLL_CAL_CFG0 0x0000006c
#define REG_HDMI_28nm_PHY_PLL_CAL_CFG1 0x00000070
#define REG_HDMI_28nm_PHY_PLL_CAL_CFG2 0x00000074
#define REG_HDMI_28nm_PHY_PLL_CAL_CFG3 0x00000078
#define REG_HDMI_28nm_PHY_PLL_CAL_CFG4 0x0000007c
#define REG_HDMI_28nm_PHY_PLL_CAL_CFG5 0x00000080
#define REG_HDMI_28nm_PHY_PLL_CAL_CFG6 0x00000084
#define REG_HDMI_28nm_PHY_PLL_CAL_CFG7 0x00000088
#define REG_HDMI_28nm_PHY_PLL_CAL_CFG8 0x0000008c
#define REG_HDMI_28nm_PHY_PLL_CAL_CFG9 0x00000090
#define REG_HDMI_28nm_PHY_PLL_CAL_CFG10 0x00000094
#define REG_HDMI_28nm_PHY_PLL_CAL_CFG11 0x00000098
#define REG_HDMI_28nm_PHY_PLL_EFUSE_CFG 0x0000009c
#define REG_HDMI_28nm_PHY_PLL_DEBUG_BUS_SEL 0x000000a0
#endif /* HDMI_XML */ #endif /* HDMI_XML */
...@@ -16,6 +16,7 @@ ...@@ -16,6 +16,7 @@
*/ */
#include <linux/gpio.h> #include <linux/gpio.h>
#include <linux/pinctrl/consumer.h>
#include "msm_kms.h" #include "msm_kms.h"
#include "hdmi.h" #include "hdmi.h"
...@@ -29,14 +30,14 @@ struct hdmi_connector { ...@@ -29,14 +30,14 @@ struct hdmi_connector {
static int gpio_config(struct hdmi *hdmi, bool on) static int gpio_config(struct hdmi *hdmi, bool on)
{ {
struct drm_device *dev = hdmi->dev; struct device *dev = &hdmi->pdev->dev;
const struct hdmi_platform_config *config = hdmi->config; const struct hdmi_platform_config *config = hdmi->config;
int ret; int ret;
if (on) { if (on) {
ret = gpio_request(config->ddc_clk_gpio, "HDMI_DDC_CLK"); ret = gpio_request(config->ddc_clk_gpio, "HDMI_DDC_CLK");
if (ret) { if (ret) {
dev_err(dev->dev, "'%s'(%d) gpio_request failed: %d\n", dev_err(dev, "'%s'(%d) gpio_request failed: %d\n",
"HDMI_DDC_CLK", config->ddc_clk_gpio, ret); "HDMI_DDC_CLK", config->ddc_clk_gpio, ret);
goto error1; goto error1;
} }
...@@ -44,7 +45,7 @@ static int gpio_config(struct hdmi *hdmi, bool on) ...@@ -44,7 +45,7 @@ static int gpio_config(struct hdmi *hdmi, bool on)
ret = gpio_request(config->ddc_data_gpio, "HDMI_DDC_DATA"); ret = gpio_request(config->ddc_data_gpio, "HDMI_DDC_DATA");
if (ret) { if (ret) {
dev_err(dev->dev, "'%s'(%d) gpio_request failed: %d\n", dev_err(dev, "'%s'(%d) gpio_request failed: %d\n",
"HDMI_DDC_DATA", config->ddc_data_gpio, ret); "HDMI_DDC_DATA", config->ddc_data_gpio, ret);
goto error2; goto error2;
} }
...@@ -52,7 +53,7 @@ static int gpio_config(struct hdmi *hdmi, bool on) ...@@ -52,7 +53,7 @@ static int gpio_config(struct hdmi *hdmi, bool on)
ret = gpio_request(config->hpd_gpio, "HDMI_HPD"); ret = gpio_request(config->hpd_gpio, "HDMI_HPD");
if (ret) { if (ret) {
dev_err(dev->dev, "'%s'(%d) gpio_request failed: %d\n", dev_err(dev, "'%s'(%d) gpio_request failed: %d\n",
"HDMI_HPD", config->hpd_gpio, ret); "HDMI_HPD", config->hpd_gpio, ret);
goto error3; goto error3;
} }
...@@ -62,7 +63,7 @@ static int gpio_config(struct hdmi *hdmi, bool on) ...@@ -62,7 +63,7 @@ static int gpio_config(struct hdmi *hdmi, bool on)
if (config->mux_en_gpio != -1) { if (config->mux_en_gpio != -1) {
ret = gpio_request(config->mux_en_gpio, "HDMI_MUX_EN"); ret = gpio_request(config->mux_en_gpio, "HDMI_MUX_EN");
if (ret) { if (ret) {
dev_err(dev->dev, "'%s'(%d) gpio_request failed: %d\n", dev_err(dev, "'%s'(%d) gpio_request failed: %d\n",
"HDMI_MUX_EN", config->mux_en_gpio, ret); "HDMI_MUX_EN", config->mux_en_gpio, ret);
goto error4; goto error4;
} }
...@@ -72,7 +73,7 @@ static int gpio_config(struct hdmi *hdmi, bool on) ...@@ -72,7 +73,7 @@ static int gpio_config(struct hdmi *hdmi, bool on)
if (config->mux_sel_gpio != -1) { if (config->mux_sel_gpio != -1) {
ret = gpio_request(config->mux_sel_gpio, "HDMI_MUX_SEL"); ret = gpio_request(config->mux_sel_gpio, "HDMI_MUX_SEL");
if (ret) { if (ret) {
dev_err(dev->dev, "'%s'(%d) gpio_request failed: %d\n", dev_err(dev, "'%s'(%d) gpio_request failed: %d\n",
"HDMI_MUX_SEL", config->mux_sel_gpio, ret); "HDMI_MUX_SEL", config->mux_sel_gpio, ret);
goto error5; goto error5;
} }
...@@ -83,7 +84,7 @@ static int gpio_config(struct hdmi *hdmi, bool on) ...@@ -83,7 +84,7 @@ static int gpio_config(struct hdmi *hdmi, bool on)
ret = gpio_request(config->mux_lpm_gpio, ret = gpio_request(config->mux_lpm_gpio,
"HDMI_MUX_LPM"); "HDMI_MUX_LPM");
if (ret) { if (ret) {
dev_err(dev->dev, dev_err(dev,
"'%s'(%d) gpio_request failed: %d\n", "'%s'(%d) gpio_request failed: %d\n",
"HDMI_MUX_LPM", "HDMI_MUX_LPM",
config->mux_lpm_gpio, ret); config->mux_lpm_gpio, ret);
...@@ -136,7 +137,7 @@ static int hpd_enable(struct hdmi_connector *hdmi_connector) ...@@ -136,7 +137,7 @@ static int hpd_enable(struct hdmi_connector *hdmi_connector)
{ {
struct hdmi *hdmi = hdmi_connector->hdmi; struct hdmi *hdmi = hdmi_connector->hdmi;
const struct hdmi_platform_config *config = hdmi->config; const struct hdmi_platform_config *config = hdmi->config;
struct drm_device *dev = hdmi_connector->base.dev; struct device *dev = &hdmi->pdev->dev;
struct hdmi_phy *phy = hdmi->phy; struct hdmi_phy *phy = hdmi->phy;
uint32_t hpd_ctrl; uint32_t hpd_ctrl;
int i, ret; int i, ret;
...@@ -144,15 +145,21 @@ static int hpd_enable(struct hdmi_connector *hdmi_connector) ...@@ -144,15 +145,21 @@ static int hpd_enable(struct hdmi_connector *hdmi_connector)
for (i = 0; i < config->hpd_reg_cnt; i++) { for (i = 0; i < config->hpd_reg_cnt; i++) {
ret = regulator_enable(hdmi->hpd_regs[i]); ret = regulator_enable(hdmi->hpd_regs[i]);
if (ret) { if (ret) {
dev_err(dev->dev, "failed to enable hpd regulator: %s (%d)\n", dev_err(dev, "failed to enable hpd regulator: %s (%d)\n",
config->hpd_reg_names[i], ret); config->hpd_reg_names[i], ret);
goto fail; goto fail;
} }
} }
ret = pinctrl_pm_select_default_state(dev);
if (ret) {
dev_err(dev, "pinctrl state chg failed: %d\n", ret);
goto fail;
}
ret = gpio_config(hdmi, true); ret = gpio_config(hdmi, true);
if (ret) { if (ret) {
dev_err(dev->dev, "failed to configure GPIOs: %d\n", ret); dev_err(dev, "failed to configure GPIOs: %d\n", ret);
goto fail; goto fail;
} }
...@@ -161,13 +168,13 @@ static int hpd_enable(struct hdmi_connector *hdmi_connector) ...@@ -161,13 +168,13 @@ static int hpd_enable(struct hdmi_connector *hdmi_connector)
ret = clk_set_rate(hdmi->hpd_clks[i], ret = clk_set_rate(hdmi->hpd_clks[i],
config->hpd_freq[i]); config->hpd_freq[i]);
if (ret) if (ret)
dev_warn(dev->dev, "failed to set clk %s (%d)\n", dev_warn(dev, "failed to set clk %s (%d)\n",
config->hpd_clk_names[i], ret); config->hpd_clk_names[i], ret);
} }
ret = clk_prepare_enable(hdmi->hpd_clks[i]); ret = clk_prepare_enable(hdmi->hpd_clks[i]);
if (ret) { if (ret) {
dev_err(dev->dev, "failed to enable hpd clk: %s (%d)\n", dev_err(dev, "failed to enable hpd clk: %s (%d)\n",
config->hpd_clk_names[i], ret); config->hpd_clk_names[i], ret);
goto fail; goto fail;
} }
...@@ -204,7 +211,7 @@ static void hdp_disable(struct hdmi_connector *hdmi_connector) ...@@ -204,7 +211,7 @@ static void hdp_disable(struct hdmi_connector *hdmi_connector)
{ {
struct hdmi *hdmi = hdmi_connector->hdmi; struct hdmi *hdmi = hdmi_connector->hdmi;
const struct hdmi_platform_config *config = hdmi->config; const struct hdmi_platform_config *config = hdmi->config;
struct drm_device *dev = hdmi_connector->base.dev; struct device *dev = &hdmi->pdev->dev;
int i, ret = 0; int i, ret = 0;
/* Disable HPD interrupt */ /* Disable HPD interrupt */
...@@ -217,12 +224,16 @@ static void hdp_disable(struct hdmi_connector *hdmi_connector) ...@@ -217,12 +224,16 @@ static void hdp_disable(struct hdmi_connector *hdmi_connector)
ret = gpio_config(hdmi, false); ret = gpio_config(hdmi, false);
if (ret) if (ret)
dev_warn(dev->dev, "failed to unconfigure GPIOs: %d\n", ret); dev_warn(dev, "failed to unconfigure GPIOs: %d\n", ret);
ret = pinctrl_pm_select_sleep_state(dev);
if (ret)
dev_warn(dev, "pinctrl state chg failed: %d\n", ret);
for (i = 0; i < config->hpd_reg_cnt; i++) { for (i = 0; i < config->hpd_reg_cnt; i++) {
ret = regulator_disable(hdmi->hpd_regs[i]); ret = regulator_disable(hdmi->hpd_regs[i]);
if (ret) if (ret)
dev_warn(dev->dev, "failed to disable hpd regulator: %s (%d)\n", dev_warn(dev, "failed to disable hpd regulator: %s (%d)\n",
config->hpd_reg_names[i], ret); config->hpd_reg_names[i], ret);
} }
} }
...@@ -433,7 +444,7 @@ struct drm_connector *hdmi_connector_init(struct hdmi *hdmi) ...@@ -433,7 +444,7 @@ struct drm_connector *hdmi_connector_init(struct hdmi *hdmi)
ret = hpd_enable(hdmi_connector); ret = hpd_enable(hdmi_connector);
if (ret) { if (ret) {
dev_err(hdmi->dev->dev, "failed to enable HPD: %d\n", ret); dev_err(&hdmi->pdev->dev, "failed to enable HPD: %d\n", ret);
goto fail; goto fail;
} }
......
...@@ -10,15 +10,15 @@ git clone https://github.com/freedreno/envytools.git ...@@ -10,15 +10,15 @@ git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are: The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2014-12-05 15:34:49) - /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2014-12-05 15:34:49)
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20908 bytes, from 2014-12-08 16:13:00) - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-03-24 22:05:22)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2357 bytes, from 2014-12-08 16:13:00) - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2352 bytes, from 2015-04-12 15:02:42)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 27208 bytes, from 2015-01-13 23:56:11) - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 35083 bytes, from 2015-04-12 15:04:03)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43) - /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 22094 bytes, from 2015-05-12 12:45:23)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32) - /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2014-10-31 16:48:57) - /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2014-10-31 16:48:57)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12) - /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 26848 bytes, from 2015-01-13 23:55:57) - /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29012 bytes, from 2015-05-12 12:45:23)
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 8253 bytes, from 2014-12-08 16:13:00) - /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-12 12:45:23)
Copyright (C) 2013 by the following authors: Copyright (C) 2013 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark) - Rob Clark <robdclark@gmail.com> (robclark)
......
...@@ -10,17 +10,17 @@ git clone https://github.com/freedreno/envytools.git ...@@ -10,17 +10,17 @@ git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are: The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2014-12-05 15:34:49) - /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2014-12-05 15:34:49)
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20908 bytes, from 2014-12-08 16:13:00) - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-03-24 22:05:22)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2357 bytes, from 2014-12-08 16:13:00) - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2352 bytes, from 2015-04-12 15:02:42)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 27208 bytes, from 2015-01-13 23:56:11) - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 35083 bytes, from 2015-04-12 15:04:03)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43) - /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 22094 bytes, from 2015-05-12 12:45:23)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32) - /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2014-10-31 16:48:57) - /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2014-10-31 16:48:57)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12) - /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 26848 bytes, from 2015-01-13 23:55:57) - /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29012 bytes, from 2015-05-12 12:45:23)
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 8253 bytes, from 2014-12-08 16:13:00) - /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-12 12:45:23)
Copyright (C) 2013-2014 by the following authors: Copyright (C) 2013-2015 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark) - Rob Clark <robdclark@gmail.com> (robclark)
Permission is hereby granted, free of charge, to any person obtaining Permission is hereby granted, free of charge, to any person obtaining
...@@ -680,18 +680,18 @@ static inline uint32_t MDP4_PIPE_SRC_STRIDE_B_P3(uint32_t val) ...@@ -680,18 +680,18 @@ static inline uint32_t MDP4_PIPE_SRC_STRIDE_B_P3(uint32_t val)
return ((val) << MDP4_PIPE_SRC_STRIDE_B_P3__SHIFT) & MDP4_PIPE_SRC_STRIDE_B_P3__MASK; return ((val) << MDP4_PIPE_SRC_STRIDE_B_P3__SHIFT) & MDP4_PIPE_SRC_STRIDE_B_P3__MASK;
} }
static inline uint32_t REG_MDP4_PIPE_FRAME_SIZE(enum mdp4_pipe i0) { return 0x00020048 + 0x10000*i0; } static inline uint32_t REG_MDP4_PIPE_SSTILE_FRAME_SIZE(enum mdp4_pipe i0) { return 0x00020048 + 0x10000*i0; }
#define MDP4_PIPE_FRAME_SIZE_HEIGHT__MASK 0xffff0000 #define MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT__MASK 0xffff0000
#define MDP4_PIPE_FRAME_SIZE_HEIGHT__SHIFT 16 #define MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT__SHIFT 16
static inline uint32_t MDP4_PIPE_FRAME_SIZE_HEIGHT(uint32_t val) static inline uint32_t MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT(uint32_t val)
{ {
return ((val) << MDP4_PIPE_FRAME_SIZE_HEIGHT__SHIFT) & MDP4_PIPE_FRAME_SIZE_HEIGHT__MASK; return ((val) << MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT__SHIFT) & MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT__MASK;
} }
#define MDP4_PIPE_FRAME_SIZE_WIDTH__MASK 0x0000ffff #define MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH__MASK 0x0000ffff
#define MDP4_PIPE_FRAME_SIZE_WIDTH__SHIFT 0 #define MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH__SHIFT 0
static inline uint32_t MDP4_PIPE_FRAME_SIZE_WIDTH(uint32_t val) static inline uint32_t MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH(uint32_t val)
{ {
return ((val) << MDP4_PIPE_FRAME_SIZE_WIDTH__SHIFT) & MDP4_PIPE_FRAME_SIZE_WIDTH__MASK; return ((val) << MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH__SHIFT) & MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH__MASK;
} }
static inline uint32_t REG_MDP4_PIPE_SRC_FORMAT(enum mdp4_pipe i0) { return 0x00020050 + 0x10000*i0; } static inline uint32_t REG_MDP4_PIPE_SRC_FORMAT(enum mdp4_pipe i0) { return 0x00020050 + 0x10000*i0; }
......
...@@ -51,6 +51,11 @@ struct mdp4_crtc { ...@@ -51,6 +51,11 @@ struct mdp4_crtc {
/* if there is a pending flip, these will be non-null: */ /* if there is a pending flip, these will be non-null: */
struct drm_pending_vblank_event *event; struct drm_pending_vblank_event *event;
/* Bits have been flushed at the last commit,
* used to decide if a vsync has happened since last commit.
*/
u32 flushed_mask;
#define PENDING_CURSOR 0x1 #define PENDING_CURSOR 0x1
#define PENDING_FLIP 0x2 #define PENDING_FLIP 0x2
atomic_t pending; atomic_t pending;
...@@ -93,6 +98,8 @@ static void crtc_flush(struct drm_crtc *crtc) ...@@ -93,6 +98,8 @@ static void crtc_flush(struct drm_crtc *crtc)
DBG("%s: flush=%08x", mdp4_crtc->name, flush); DBG("%s: flush=%08x", mdp4_crtc->name, flush);
mdp4_crtc->flushed_mask = flush;
mdp4_write(mdp4_kms, REG_MDP4_OVERLAY_FLUSH, flush); mdp4_write(mdp4_kms, REG_MDP4_OVERLAY_FLUSH, flush);
} }
...@@ -537,6 +544,29 @@ static void mdp4_crtc_err_irq(struct mdp_irq *irq, uint32_t irqstatus) ...@@ -537,6 +544,29 @@ static void mdp4_crtc_err_irq(struct mdp_irq *irq, uint32_t irqstatus)
crtc_flush(crtc); crtc_flush(crtc);
} }
static void mdp4_crtc_wait_for_flush_done(struct drm_crtc *crtc)
{
struct drm_device *dev = crtc->dev;
struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
struct mdp4_kms *mdp4_kms = get_kms(crtc);
int ret;
ret = drm_crtc_vblank_get(crtc);
if (ret)
return;
ret = wait_event_timeout(dev->vblank[drm_crtc_index(crtc)].queue,
!(mdp4_read(mdp4_kms, REG_MDP4_OVERLAY_FLUSH) &
mdp4_crtc->flushed_mask),
msecs_to_jiffies(50));
if (ret <= 0)
dev_warn(dev->dev, "vblank time out, crtc=%d\n", mdp4_crtc->id);
mdp4_crtc->flushed_mask = 0;
drm_crtc_vblank_put(crtc);
}
uint32_t mdp4_crtc_vblank(struct drm_crtc *crtc) uint32_t mdp4_crtc_vblank(struct drm_crtc *crtc)
{ {
struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc); struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
...@@ -600,6 +630,15 @@ void mdp4_crtc_set_intf(struct drm_crtc *crtc, enum mdp4_intf intf, int mixer) ...@@ -600,6 +630,15 @@ void mdp4_crtc_set_intf(struct drm_crtc *crtc, enum mdp4_intf intf, int mixer)
mdp4_write(mdp4_kms, REG_MDP4_DISP_INTF_SEL, intf_sel); mdp4_write(mdp4_kms, REG_MDP4_DISP_INTF_SEL, intf_sel);
} }
void mdp4_crtc_wait_for_commit_done(struct drm_crtc *crtc)
{
/* wait_for_flush_done is the only case for now.
* Later we will have command mode CRTC to wait for
* other event.
*/
mdp4_crtc_wait_for_flush_done(crtc);
}
static const char *dma_names[] = { static const char *dma_names[] = {
"DMA_P", "DMA_S", "DMA_E", "DMA_P", "DMA_S", "DMA_E",
}; };
......
...@@ -38,7 +38,7 @@ static struct mdp4_kms *get_kms(struct drm_encoder *encoder) ...@@ -38,7 +38,7 @@ static struct mdp4_kms *get_kms(struct drm_encoder *encoder)
return to_mdp4_kms(to_mdp_kms(priv->kms)); return to_mdp4_kms(to_mdp_kms(priv->kms));
} }
#ifdef CONFIG_MSM_BUS_SCALING #ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING
#include <mach/board.h> #include <mach/board.h>
/* not ironically named at all.. no, really.. */ /* not ironically named at all.. no, really.. */
static void bs_init(struct mdp4_dtv_encoder *mdp4_dtv_encoder) static void bs_init(struct mdp4_dtv_encoder *mdp4_dtv_encoder)
......
...@@ -119,6 +119,8 @@ static int mdp4_hw_init(struct msm_kms *kms) ...@@ -119,6 +119,8 @@ static int mdp4_hw_init(struct msm_kms *kms)
if (mdp4_kms->rev > 1) if (mdp4_kms->rev > 1)
mdp4_write(mdp4_kms, REG_MDP4_RESET_STATUS, 1); mdp4_write(mdp4_kms, REG_MDP4_RESET_STATUS, 1);
dev->mode_config.allow_fb_modifiers = true;
out: out:
pm_runtime_put_sync(dev->dev); pm_runtime_put_sync(dev->dev);
...@@ -157,6 +159,12 @@ static void mdp4_complete_commit(struct msm_kms *kms, struct drm_atomic_state *s ...@@ -157,6 +159,12 @@ static void mdp4_complete_commit(struct msm_kms *kms, struct drm_atomic_state *s
mdp4_disable(mdp4_kms); mdp4_disable(mdp4_kms);
} }
static void mdp4_wait_for_crtc_commit_done(struct msm_kms *kms,
struct drm_crtc *crtc)
{
mdp4_crtc_wait_for_commit_done(crtc);
}
static long mdp4_round_pixclk(struct msm_kms *kms, unsigned long rate, static long mdp4_round_pixclk(struct msm_kms *kms, unsigned long rate,
struct drm_encoder *encoder) struct drm_encoder *encoder)
{ {
...@@ -195,6 +203,7 @@ static const struct mdp_kms_funcs kms_funcs = { ...@@ -195,6 +203,7 @@ static const struct mdp_kms_funcs kms_funcs = {
.disable_vblank = mdp4_disable_vblank, .disable_vblank = mdp4_disable_vblank,
.prepare_commit = mdp4_prepare_commit, .prepare_commit = mdp4_prepare_commit,
.complete_commit = mdp4_complete_commit, .complete_commit = mdp4_complete_commit,
.wait_for_crtc_commit_done = mdp4_wait_for_crtc_commit_done,
.get_format = mdp_get_format, .get_format = mdp_get_format,
.round_pixclk = mdp4_round_pixclk, .round_pixclk = mdp4_round_pixclk,
.preclose = mdp4_preclose, .preclose = mdp4_preclose,
......
...@@ -206,6 +206,7 @@ uint32_t mdp4_crtc_vblank(struct drm_crtc *crtc); ...@@ -206,6 +206,7 @@ uint32_t mdp4_crtc_vblank(struct drm_crtc *crtc);
void mdp4_crtc_cancel_pending_flip(struct drm_crtc *crtc, struct drm_file *file); void mdp4_crtc_cancel_pending_flip(struct drm_crtc *crtc, struct drm_file *file);
void mdp4_crtc_set_config(struct drm_crtc *crtc, uint32_t config); void mdp4_crtc_set_config(struct drm_crtc *crtc, uint32_t config);
void mdp4_crtc_set_intf(struct drm_crtc *crtc, enum mdp4_intf intf, int mixer); void mdp4_crtc_set_intf(struct drm_crtc *crtc, enum mdp4_intf intf, int mixer);
void mdp4_crtc_wait_for_commit_done(struct drm_crtc *crtc);
struct drm_crtc *mdp4_crtc_init(struct drm_device *dev, struct drm_crtc *mdp4_crtc_init(struct drm_device *dev,
struct drm_plane *plane, int id, int ovlp_id, struct drm_plane *plane, int id, int ovlp_id,
enum mdp4_dma dma_id); enum mdp4_dma dma_id);
...@@ -229,7 +230,7 @@ static inline struct clk *mpd4_lvds_pll_init(struct drm_device *dev) ...@@ -229,7 +230,7 @@ static inline struct clk *mpd4_lvds_pll_init(struct drm_device *dev)
} }
#endif #endif
#ifdef CONFIG_MSM_BUS_SCALING #ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING
static inline int match_dev_name(struct device *dev, void *data) static inline int match_dev_name(struct device *dev, void *data)
{ {
return !strcmp(dev_name(dev), data); return !strcmp(dev_name(dev), data);
......
...@@ -38,7 +38,7 @@ static struct mdp4_kms *get_kms(struct drm_encoder *encoder) ...@@ -38,7 +38,7 @@ static struct mdp4_kms *get_kms(struct drm_encoder *encoder)
return to_mdp4_kms(to_mdp_kms(priv->kms)); return to_mdp4_kms(to_mdp_kms(priv->kms));
} }
#ifdef CONFIG_MSM_BUS_SCALING #ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING
#include <mach/board.h> #include <mach/board.h>
static void bs_init(struct mdp4_lcdc_encoder *mdp4_lcdc_encoder) static void bs_init(struct mdp4_lcdc_encoder *mdp4_lcdc_encoder)
{ {
......
...@@ -33,6 +33,21 @@ struct mdp4_plane { ...@@ -33,6 +33,21 @@ struct mdp4_plane {
}; };
#define to_mdp4_plane(x) container_of(x, struct mdp4_plane, base) #define to_mdp4_plane(x) container_of(x, struct mdp4_plane, base)
/* MDP format helper functions */
static inline
enum mdp4_frame_format mdp4_get_frame_format(struct drm_framebuffer *fb)
{
bool is_tile = false;
if (fb->modifier[1] == DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
is_tile = true;
if (fb->pixel_format == DRM_FORMAT_NV12 && is_tile)
return FRAME_TILE_YCBCR_420;
return FRAME_LINEAR;
}
static void mdp4_plane_set_scanout(struct drm_plane *plane, static void mdp4_plane_set_scanout(struct drm_plane *plane,
struct drm_framebuffer *fb); struct drm_framebuffer *fb);
static int mdp4_plane_mode_set(struct drm_plane *plane, static int mdp4_plane_mode_set(struct drm_plane *plane,
...@@ -205,6 +220,7 @@ static int mdp4_plane_mode_set(struct drm_plane *plane, ...@@ -205,6 +220,7 @@ static int mdp4_plane_mode_set(struct drm_plane *plane,
uint32_t op_mode = 0; uint32_t op_mode = 0;
uint32_t phasex_step = MDP4_VG_PHASE_STEP_DEFAULT; uint32_t phasex_step = MDP4_VG_PHASE_STEP_DEFAULT;
uint32_t phasey_step = MDP4_VG_PHASE_STEP_DEFAULT; uint32_t phasey_step = MDP4_VG_PHASE_STEP_DEFAULT;
enum mdp4_frame_format frame_type = mdp4_get_frame_format(fb);
if (!(crtc && fb)) { if (!(crtc && fb)) {
DBG("%s: disabled!", mdp4_plane->name); DBG("%s: disabled!", mdp4_plane->name);
...@@ -304,6 +320,7 @@ static int mdp4_plane_mode_set(struct drm_plane *plane, ...@@ -304,6 +320,7 @@ static int mdp4_plane_mode_set(struct drm_plane *plane,
MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT(format->unpack_count - 1) | MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT(format->unpack_count - 1) |
MDP4_PIPE_SRC_FORMAT_FETCH_PLANES(format->fetch_type) | MDP4_PIPE_SRC_FORMAT_FETCH_PLANES(format->fetch_type) |
MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP(format->chroma_sample) | MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP(format->chroma_sample) |
MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT(frame_type) |
COND(format->unpack_tight, MDP4_PIPE_SRC_FORMAT_UNPACK_TIGHT)); COND(format->unpack_tight, MDP4_PIPE_SRC_FORMAT_UNPACK_TIGHT));
mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRC_UNPACK(pipe), mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRC_UNPACK(pipe),
...@@ -324,6 +341,11 @@ static int mdp4_plane_mode_set(struct drm_plane *plane, ...@@ -324,6 +341,11 @@ static int mdp4_plane_mode_set(struct drm_plane *plane,
mdp4_write(mdp4_kms, REG_MDP4_PIPE_PHASEX_STEP(pipe), phasex_step); mdp4_write(mdp4_kms, REG_MDP4_PIPE_PHASEX_STEP(pipe), phasex_step);
mdp4_write(mdp4_kms, REG_MDP4_PIPE_PHASEY_STEP(pipe), phasey_step); mdp4_write(mdp4_kms, REG_MDP4_PIPE_PHASEY_STEP(pipe), phasey_step);
if (frame_type != FRAME_LINEAR)
mdp4_write(mdp4_kms, REG_MDP4_PIPE_SSTILE_FRAME_SIZE(pipe),
MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH(src_w) |
MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT(src_h));
return 0; return 0;
} }
......
This diff is collapsed.
...@@ -30,7 +30,7 @@ static struct mdp5_kms *get_kms(struct drm_encoder *encoder) ...@@ -30,7 +30,7 @@ static struct mdp5_kms *get_kms(struct drm_encoder *encoder)
return to_mdp5_kms(to_mdp_kms(priv->kms)); return to_mdp5_kms(to_mdp_kms(priv->kms));
} }
#ifdef CONFIG_MSM_BUS_SCALING #ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING
#include <mach/board.h> #include <mach/board.h>
#include <linux/msm-bus.h> #include <linux/msm-bus.h>
#include <linux/msm-bus-board.h> #include <linux/msm-bus-board.h>
...@@ -216,16 +216,12 @@ static void mdp5_cmd_encoder_mode_set(struct drm_encoder *encoder, ...@@ -216,16 +216,12 @@ static void mdp5_cmd_encoder_mode_set(struct drm_encoder *encoder,
static void mdp5_cmd_encoder_disable(struct drm_encoder *encoder) static void mdp5_cmd_encoder_disable(struct drm_encoder *encoder)
{ {
struct mdp5_cmd_encoder *mdp5_cmd_enc = to_mdp5_cmd_encoder(encoder); struct mdp5_cmd_encoder *mdp5_cmd_enc = to_mdp5_cmd_encoder(encoder);
struct mdp5_kms *mdp5_kms = get_kms(encoder);
struct mdp5_ctl *ctl = mdp5_crtc_get_ctl(encoder->crtc); struct mdp5_ctl *ctl = mdp5_crtc_get_ctl(encoder->crtc);
struct mdp5_interface *intf = &mdp5_cmd_enc->intf; struct mdp5_interface *intf = &mdp5_cmd_enc->intf;
int lm = mdp5_crtc_get_lm(encoder->crtc);
if (WARN_ON(!mdp5_cmd_enc->enabled)) if (WARN_ON(!mdp5_cmd_enc->enabled))
return; return;
/* Wait for the last frame done */
mdp_irq_wait(&mdp5_kms->base, lm2ppdone(lm));
pingpong_tearcheck_disable(encoder); pingpong_tearcheck_disable(encoder);
mdp5_ctl_set_encoder_state(ctl, false); mdp5_ctl_set_encoder_state(ctl, false);
...@@ -281,22 +277,22 @@ int mdp5_cmd_encoder_set_split_display(struct drm_encoder *encoder, ...@@ -281,22 +277,22 @@ int mdp5_cmd_encoder_set_split_display(struct drm_encoder *encoder,
* start signal for the slave encoder * start signal for the slave encoder
*/ */
if (intf_num == 1) if (intf_num == 1)
data |= MDP5_SPLIT_DPL_UPPER_INTF2_SW_TRG_MUX; data |= MDP5_MDP_SPLIT_DPL_UPPER_INTF2_SW_TRG_MUX;
else if (intf_num == 2) else if (intf_num == 2)
data |= MDP5_SPLIT_DPL_UPPER_INTF1_SW_TRG_MUX; data |= MDP5_MDP_SPLIT_DPL_UPPER_INTF1_SW_TRG_MUX;
else else
return -EINVAL; return -EINVAL;
/* Smart Panel, Sync mode */ /* Smart Panel, Sync mode */
data |= MDP5_SPLIT_DPL_UPPER_SMART_PANEL; data |= MDP5_MDP_SPLIT_DPL_UPPER_SMART_PANEL;
/* Make sure clocks are on when connectors calling this function. */ /* Make sure clocks are on when connectors calling this function. */
mdp5_enable(mdp5_kms); mdp5_enable(mdp5_kms);
mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_UPPER, data); mdp5_write(mdp5_kms, REG_MDP5_MDP_SPLIT_DPL_UPPER(0), data);
mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_LOWER, mdp5_write(mdp5_kms, REG_MDP5_MDP_SPLIT_DPL_LOWER(0),
MDP5_SPLIT_DPL_LOWER_SMART_PANEL); MDP5_MDP_SPLIT_DPL_LOWER_SMART_PANEL);
mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_EN, 1); mdp5_write(mdp5_kms, REG_MDP5_MDP_SPLIT_DPL_EN(0), 1);
mdp5_disable(mdp5_kms); mdp5_disable(mdp5_kms);
return 0; return 0;
......
/* /*
* Copyright (c) 2014 The Linux Foundation. All rights reserved. * Copyright (c) 2014-2015 The Linux Foundation. All rights reserved.
* Copyright (C) 2013 Red Hat * Copyright (C) 2013 Red Hat
* Author: Rob Clark <robdclark@gmail.com> * Author: Rob Clark <robdclark@gmail.com>
* *
...@@ -46,6 +46,11 @@ struct mdp5_crtc { ...@@ -46,6 +46,11 @@ struct mdp5_crtc {
/* if there is a pending flip, these will be non-null: */ /* if there is a pending flip, these will be non-null: */
struct drm_pending_vblank_event *event; struct drm_pending_vblank_event *event;
/* Bits have been flushed at the last commit,
* used to decide if a vsync has happened since last commit.
*/
u32 flushed_mask;
#define PENDING_CURSOR 0x1 #define PENDING_CURSOR 0x1
#define PENDING_FLIP 0x2 #define PENDING_FLIP 0x2
atomic_t pending; atomic_t pending;
...@@ -55,6 +60,11 @@ struct mdp5_crtc { ...@@ -55,6 +60,11 @@ struct mdp5_crtc {
struct mdp_irq vblank; struct mdp_irq vblank;
struct mdp_irq err; struct mdp_irq err;
struct mdp_irq pp_done;
struct completion pp_completion;
bool cmd_mode;
struct { struct {
/* protect REG_MDP5_LM_CURSOR* registers and cursor scanout_bo*/ /* protect REG_MDP5_LM_CURSOR* registers and cursor scanout_bo*/
...@@ -82,12 +92,18 @@ static void request_pending(struct drm_crtc *crtc, uint32_t pending) ...@@ -82,12 +92,18 @@ static void request_pending(struct drm_crtc *crtc, uint32_t pending)
mdp_irq_register(&get_kms(crtc)->base, &mdp5_crtc->vblank); mdp_irq_register(&get_kms(crtc)->base, &mdp5_crtc->vblank);
} }
static void crtc_flush(struct drm_crtc *crtc, u32 flush_mask) static void request_pp_done_pending(struct drm_crtc *crtc)
{
struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
reinit_completion(&mdp5_crtc->pp_completion);
}
static u32 crtc_flush(struct drm_crtc *crtc, u32 flush_mask)
{ {
struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
DBG("%s: flush=%08x", mdp5_crtc->name, flush_mask); DBG("%s: flush=%08x", mdp5_crtc->name, flush_mask);
mdp5_ctl_commit(mdp5_crtc->ctl, flush_mask); return mdp5_ctl_commit(mdp5_crtc->ctl, flush_mask);
} }
/* /*
...@@ -95,7 +111,7 @@ static void crtc_flush(struct drm_crtc *crtc, u32 flush_mask) ...@@ -95,7 +111,7 @@ static void crtc_flush(struct drm_crtc *crtc, u32 flush_mask)
* so that we can safely queue unref to current fb (ie. next * so that we can safely queue unref to current fb (ie. next
* vblank we know hw is done w/ previous scanout_fb). * vblank we know hw is done w/ previous scanout_fb).
*/ */
static void crtc_flush_all(struct drm_crtc *crtc) static u32 crtc_flush_all(struct drm_crtc *crtc)
{ {
struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
struct drm_plane *plane; struct drm_plane *plane;
...@@ -103,7 +119,7 @@ static void crtc_flush_all(struct drm_crtc *crtc) ...@@ -103,7 +119,7 @@ static void crtc_flush_all(struct drm_crtc *crtc)
/* this should not happen: */ /* this should not happen: */
if (WARN_ON(!mdp5_crtc->ctl)) if (WARN_ON(!mdp5_crtc->ctl))
return; return 0;
drm_atomic_crtc_for_each_plane(plane, crtc) { drm_atomic_crtc_for_each_plane(plane, crtc) {
flush_mask |= mdp5_plane_get_flush(plane); flush_mask |= mdp5_plane_get_flush(plane);
...@@ -111,7 +127,7 @@ static void crtc_flush_all(struct drm_crtc *crtc) ...@@ -111,7 +127,7 @@ static void crtc_flush_all(struct drm_crtc *crtc)
flush_mask |= mdp_ctl_flush_mask_lm(mdp5_crtc->lm); flush_mask |= mdp_ctl_flush_mask_lm(mdp5_crtc->lm);
crtc_flush(crtc, flush_mask); return crtc_flush(crtc, flush_mask);
} }
/* if file!=NULL, this is preclose potential cancel-flip path */ /* if file!=NULL, this is preclose potential cancel-flip path */
...@@ -143,6 +159,8 @@ static void complete_flip(struct drm_crtc *crtc, struct drm_file *file) ...@@ -143,6 +159,8 @@ static void complete_flip(struct drm_crtc *crtc, struct drm_file *file)
} }
if (mdp5_crtc->ctl && !crtc->state->enable) { if (mdp5_crtc->ctl && !crtc->state->enable) {
/* set STAGE_UNUSED for all layers */
mdp5_ctl_blend(mdp5_crtc->ctl, mdp5_crtc->lm, 0x00000000);
mdp5_ctl_release(mdp5_crtc->ctl); mdp5_ctl_release(mdp5_crtc->ctl);
mdp5_crtc->ctl = NULL; mdp5_crtc->ctl = NULL;
} }
...@@ -274,8 +292,8 @@ static void mdp5_crtc_disable(struct drm_crtc *crtc) ...@@ -274,8 +292,8 @@ static void mdp5_crtc_disable(struct drm_crtc *crtc)
if (WARN_ON(!mdp5_crtc->enabled)) if (WARN_ON(!mdp5_crtc->enabled))
return; return;
/* set STAGE_UNUSED for all layers */ if (mdp5_crtc->cmd_mode)
mdp5_ctl_blend(mdp5_crtc->ctl, mdp5_crtc->lm, 0x00000000); mdp_irq_unregister(&mdp5_kms->base, &mdp5_crtc->pp_done);
mdp_irq_unregister(&mdp5_kms->base, &mdp5_crtc->err); mdp_irq_unregister(&mdp5_kms->base, &mdp5_crtc->err);
mdp5_disable(mdp5_kms); mdp5_disable(mdp5_kms);
...@@ -296,6 +314,9 @@ static void mdp5_crtc_enable(struct drm_crtc *crtc) ...@@ -296,6 +314,9 @@ static void mdp5_crtc_enable(struct drm_crtc *crtc)
mdp5_enable(mdp5_kms); mdp5_enable(mdp5_kms);
mdp_irq_register(&mdp5_kms->base, &mdp5_crtc->err); mdp_irq_register(&mdp5_kms->base, &mdp5_crtc->err);
if (mdp5_crtc->cmd_mode)
mdp_irq_register(&mdp5_kms->base, &mdp5_crtc->pp_done);
mdp5_crtc->enabled = true; mdp5_crtc->enabled = true;
} }
...@@ -396,7 +417,18 @@ static void mdp5_crtc_atomic_flush(struct drm_crtc *crtc) ...@@ -396,7 +417,18 @@ static void mdp5_crtc_atomic_flush(struct drm_crtc *crtc)
return; return;
blend_setup(crtc); blend_setup(crtc);
crtc_flush_all(crtc);
/* PP_DONE irq is only used by command mode for now.
* It is better to request pending before FLUSH and START trigger
* to make sure no pp_done irq missed.
* This is safe because no pp_done will happen before SW trigger
* in command mode.
*/
if (mdp5_crtc->cmd_mode)
request_pp_done_pending(crtc);
mdp5_crtc->flushed_mask = crtc_flush_all(crtc);
request_pending(crtc, PENDING_FLIP); request_pending(crtc, PENDING_FLIP);
} }
...@@ -601,6 +633,52 @@ static void mdp5_crtc_err_irq(struct mdp_irq *irq, uint32_t irqstatus) ...@@ -601,6 +633,52 @@ static void mdp5_crtc_err_irq(struct mdp_irq *irq, uint32_t irqstatus)
DBG("%s: error: %08x", mdp5_crtc->name, irqstatus); DBG("%s: error: %08x", mdp5_crtc->name, irqstatus);
} }
static void mdp5_crtc_pp_done_irq(struct mdp_irq *irq, uint32_t irqstatus)
{
struct mdp5_crtc *mdp5_crtc = container_of(irq, struct mdp5_crtc,
pp_done);
complete(&mdp5_crtc->pp_completion);
}
static void mdp5_crtc_wait_for_pp_done(struct drm_crtc *crtc)
{
struct drm_device *dev = crtc->dev;
struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
int ret;
ret = wait_for_completion_timeout(&mdp5_crtc->pp_completion,
msecs_to_jiffies(50));
if (ret == 0)
dev_warn(dev->dev, "pp done time out, lm=%d\n", mdp5_crtc->lm);
}
static void mdp5_crtc_wait_for_flush_done(struct drm_crtc *crtc)
{
struct drm_device *dev = crtc->dev;
struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
int ret;
/* Should not call this function if crtc is disabled. */
if (!mdp5_crtc->ctl)
return;
ret = drm_crtc_vblank_get(crtc);
if (ret)
return;
ret = wait_event_timeout(dev->vblank[drm_crtc_index(crtc)].queue,
((mdp5_ctl_get_commit_status(mdp5_crtc->ctl) &
mdp5_crtc->flushed_mask) == 0),
msecs_to_jiffies(50));
if (ret <= 0)
dev_warn(dev->dev, "vblank time out, crtc=%d\n", mdp5_crtc->id);
mdp5_crtc->flushed_mask = 0;
drm_crtc_vblank_put(crtc);
}
uint32_t mdp5_crtc_vblank(struct drm_crtc *crtc) uint32_t mdp5_crtc_vblank(struct drm_crtc *crtc)
{ {
struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
...@@ -622,16 +700,19 @@ void mdp5_crtc_set_intf(struct drm_crtc *crtc, struct mdp5_interface *intf) ...@@ -622,16 +700,19 @@ void mdp5_crtc_set_intf(struct drm_crtc *crtc, struct mdp5_interface *intf)
/* now that we know what irq's we want: */ /* now that we know what irq's we want: */
mdp5_crtc->err.irqmask = intf2err(intf->num); mdp5_crtc->err.irqmask = intf2err(intf->num);
/* Register command mode Pingpong done as vblank for now,
* so that atomic commit should wait for it to finish.
* Ideally, in the future, we should take rd_ptr done as vblank,
* and let atomic commit wait for pingpong done for commond mode.
*/
if (intf->mode == MDP5_INTF_DSI_MODE_COMMAND)
mdp5_crtc->vblank.irqmask = lm2ppdone(lm);
else
mdp5_crtc->vblank.irqmask = intf2vblank(lm, intf); mdp5_crtc->vblank.irqmask = intf2vblank(lm, intf);
if ((intf->type == INTF_DSI) &&
(intf->mode == MDP5_INTF_DSI_MODE_COMMAND)) {
mdp5_crtc->pp_done.irqmask = lm2ppdone(lm);
mdp5_crtc->pp_done.irq = mdp5_crtc_pp_done_irq;
mdp5_crtc->cmd_mode = true;
} else {
mdp5_crtc->pp_done.irqmask = 0;
mdp5_crtc->pp_done.irq = NULL;
mdp5_crtc->cmd_mode = false;
}
mdp_irq_update(&mdp5_kms->base); mdp_irq_update(&mdp5_kms->base);
mdp5_ctl_set_intf(mdp5_crtc->ctl, intf); mdp5_ctl_set_intf(mdp5_crtc->ctl, intf);
...@@ -649,6 +730,16 @@ struct mdp5_ctl *mdp5_crtc_get_ctl(struct drm_crtc *crtc) ...@@ -649,6 +730,16 @@ struct mdp5_ctl *mdp5_crtc_get_ctl(struct drm_crtc *crtc)
return WARN_ON(!crtc) ? NULL : mdp5_crtc->ctl; return WARN_ON(!crtc) ? NULL : mdp5_crtc->ctl;
} }
void mdp5_crtc_wait_for_commit_done(struct drm_crtc *crtc)
{
struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
if (mdp5_crtc->cmd_mode)
mdp5_crtc_wait_for_pp_done(crtc);
else
mdp5_crtc_wait_for_flush_done(crtc);
}
/* initialize crtc */ /* initialize crtc */
struct drm_crtc *mdp5_crtc_init(struct drm_device *dev, struct drm_crtc *mdp5_crtc_init(struct drm_device *dev,
struct drm_plane *plane, int id) struct drm_plane *plane, int id)
...@@ -667,6 +758,7 @@ struct drm_crtc *mdp5_crtc_init(struct drm_device *dev, ...@@ -667,6 +758,7 @@ struct drm_crtc *mdp5_crtc_init(struct drm_device *dev,
spin_lock_init(&mdp5_crtc->lm_lock); spin_lock_init(&mdp5_crtc->lm_lock);
spin_lock_init(&mdp5_crtc->cursor.lock); spin_lock_init(&mdp5_crtc->cursor.lock);
init_completion(&mdp5_crtc->pp_completion);
mdp5_crtc->vblank.irq = mdp5_crtc_vblank_irq; mdp5_crtc->vblank.irq = mdp5_crtc_vblank_irq;
mdp5_crtc->err.irq = mdp5_crtc_err_irq; mdp5_crtc->err.irq = mdp5_crtc_err_irq;
......
...@@ -392,8 +392,10 @@ static u32 fix_sw_flush(struct mdp5_ctl *ctl, u32 flush_mask) ...@@ -392,8 +392,10 @@ static u32 fix_sw_flush(struct mdp5_ctl *ctl, u32 flush_mask)
* CTL registers need to be flushed in some circumstances; if that is the * CTL registers need to be flushed in some circumstances; if that is the
* case, some trigger bits will be present in both flush mask and * case, some trigger bits will be present in both flush mask and
* ctl->pending_ctl_trigger. * ctl->pending_ctl_trigger.
*
* Return H/W flushed bit mask.
*/ */
int mdp5_ctl_commit(struct mdp5_ctl *ctl, u32 flush_mask) u32 mdp5_ctl_commit(struct mdp5_ctl *ctl, u32 flush_mask)
{ {
struct mdp5_ctl_manager *ctl_mgr = ctl->ctlm; struct mdp5_ctl_manager *ctl_mgr = ctl->ctlm;
struct op_mode *pipeline = &ctl->pipeline; struct op_mode *pipeline = &ctl->pipeline;
...@@ -424,7 +426,12 @@ int mdp5_ctl_commit(struct mdp5_ctl *ctl, u32 flush_mask) ...@@ -424,7 +426,12 @@ int mdp5_ctl_commit(struct mdp5_ctl *ctl, u32 flush_mask)
refill_start_mask(ctl); refill_start_mask(ctl);
} }
return 0; return flush_mask;
}
u32 mdp5_ctl_get_commit_status(struct mdp5_ctl *ctl)
{
return ctl_read(ctl, REG_MDP5_CTL_FLUSH(ctl->id));
} }
void mdp5_ctl_release(struct mdp5_ctl *ctl) void mdp5_ctl_release(struct mdp5_ctl *ctl)
......
...@@ -88,7 +88,8 @@ u32 mdp_ctl_flush_mask_cursor(int cursor_id); ...@@ -88,7 +88,8 @@ u32 mdp_ctl_flush_mask_cursor(int cursor_id);
u32 mdp_ctl_flush_mask_encoder(struct mdp5_interface *intf); u32 mdp_ctl_flush_mask_encoder(struct mdp5_interface *intf);
/* @flush_mask: see CTL flush masks definitions below */ /* @flush_mask: see CTL flush masks definitions below */
int mdp5_ctl_commit(struct mdp5_ctl *ctl, u32 flush_mask); u32 mdp5_ctl_commit(struct mdp5_ctl *ctl, u32 flush_mask);
u32 mdp5_ctl_get_commit_status(struct mdp5_ctl *ctl);
void mdp5_ctl_release(struct mdp5_ctl *ctl); void mdp5_ctl_release(struct mdp5_ctl *ctl);
......
...@@ -36,7 +36,7 @@ static struct mdp5_kms *get_kms(struct drm_encoder *encoder) ...@@ -36,7 +36,7 @@ static struct mdp5_kms *get_kms(struct drm_encoder *encoder)
return to_mdp5_kms(to_mdp_kms(priv->kms)); return to_mdp5_kms(to_mdp_kms(priv->kms));
} }
#ifdef CONFIG_MSM_BUS_SCALING #ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING
#include <mach/board.h> #include <mach/board.h>
#include <mach/msm_bus.h> #include <mach/msm_bus.h>
#include <mach/msm_bus_board.h> #include <mach/msm_bus_board.h>
...@@ -144,10 +144,14 @@ static void mdp5_encoder_mode_set(struct drm_encoder *encoder, ...@@ -144,10 +144,14 @@ static void mdp5_encoder_mode_set(struct drm_encoder *encoder,
mode->type, mode->flags); mode->type, mode->flags);
ctrl_pol = 0; ctrl_pol = 0;
/* DSI controller cannot handle active-low sync signals. */
if (mdp5_encoder->intf.type != INTF_DSI) {
if (mode->flags & DRM_MODE_FLAG_NHSYNC) if (mode->flags & DRM_MODE_FLAG_NHSYNC)
ctrl_pol |= MDP5_INTF_POLARITY_CTL_HSYNC_LOW; ctrl_pol |= MDP5_INTF_POLARITY_CTL_HSYNC_LOW;
if (mode->flags & DRM_MODE_FLAG_NVSYNC) if (mode->flags & DRM_MODE_FLAG_NVSYNC)
ctrl_pol |= MDP5_INTF_POLARITY_CTL_VSYNC_LOW; ctrl_pol |= MDP5_INTF_POLARITY_CTL_VSYNC_LOW;
}
/* probably need to get DATA_EN polarity from panel.. */ /* probably need to get DATA_EN polarity from panel.. */
dtv_hsync_skew = 0; /* get this from panel? */ dtv_hsync_skew = 0; /* get this from panel? */
...@@ -304,9 +308,9 @@ int mdp5_encoder_set_split_display(struct drm_encoder *encoder, ...@@ -304,9 +308,9 @@ int mdp5_encoder_set_split_display(struct drm_encoder *encoder,
* to use the master's enable signal for the slave encoder. * to use the master's enable signal for the slave encoder.
*/ */
if (intf_num == 1) if (intf_num == 1)
data |= MDP5_SPLIT_DPL_LOWER_INTF2_TG_SYNC; data |= MDP5_MDP_SPLIT_DPL_LOWER_INTF2_TG_SYNC;
else if (intf_num == 2) else if (intf_num == 2)
data |= MDP5_SPLIT_DPL_LOWER_INTF1_TG_SYNC; data |= MDP5_MDP_SPLIT_DPL_LOWER_INTF1_TG_SYNC;
else else
return -EINVAL; return -EINVAL;
...@@ -315,9 +319,9 @@ int mdp5_encoder_set_split_display(struct drm_encoder *encoder, ...@@ -315,9 +319,9 @@ int mdp5_encoder_set_split_display(struct drm_encoder *encoder,
mdp5_write(mdp5_kms, REG_MDP5_MDP_SPARE_0(0), mdp5_write(mdp5_kms, REG_MDP5_MDP_SPARE_0(0),
MDP5_MDP_SPARE_0_SPLIT_DPL_SINGLE_FLUSH_EN); MDP5_MDP_SPARE_0_SPLIT_DPL_SINGLE_FLUSH_EN);
/* Dumb Panel, Sync mode */ /* Dumb Panel, Sync mode */
mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_UPPER, 0); mdp5_write(mdp5_kms, REG_MDP5_MDP_SPLIT_DPL_UPPER(0), 0);
mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_LOWER, data); mdp5_write(mdp5_kms, REG_MDP5_MDP_SPLIT_DPL_LOWER(0), data);
mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_EN, 1); mdp5_write(mdp5_kms, REG_MDP5_MDP_SPLIT_DPL_EN(0), 1);
mdp5_disable(mdp5_kms); mdp5_disable(mdp5_kms);
return 0; return 0;
......
...@@ -80,6 +80,12 @@ static void mdp5_complete_commit(struct msm_kms *kms, struct drm_atomic_state *s ...@@ -80,6 +80,12 @@ static void mdp5_complete_commit(struct msm_kms *kms, struct drm_atomic_state *s
mdp5_disable(mdp5_kms); mdp5_disable(mdp5_kms);
} }
static void mdp5_wait_for_crtc_commit_done(struct msm_kms *kms,
struct drm_crtc *crtc)
{
mdp5_crtc_wait_for_commit_done(crtc);
}
static long mdp5_round_pixclk(struct msm_kms *kms, unsigned long rate, static long mdp5_round_pixclk(struct msm_kms *kms, unsigned long rate,
struct drm_encoder *encoder) struct drm_encoder *encoder)
{ {
...@@ -141,6 +147,7 @@ static const struct mdp_kms_funcs kms_funcs = { ...@@ -141,6 +147,7 @@ static const struct mdp_kms_funcs kms_funcs = {
.disable_vblank = mdp5_disable_vblank, .disable_vblank = mdp5_disable_vblank,
.prepare_commit = mdp5_prepare_commit, .prepare_commit = mdp5_prepare_commit,
.complete_commit = mdp5_complete_commit, .complete_commit = mdp5_complete_commit,
.wait_for_crtc_commit_done = mdp5_wait_for_crtc_commit_done,
.get_format = mdp_get_format, .get_format = mdp_get_format,
.round_pixclk = mdp5_round_pixclk, .round_pixclk = mdp5_round_pixclk,
.set_split_display = mdp5_set_split_display, .set_split_display = mdp5_set_split_display,
......
...@@ -237,6 +237,7 @@ int mdp5_crtc_get_lm(struct drm_crtc *crtc); ...@@ -237,6 +237,7 @@ int mdp5_crtc_get_lm(struct drm_crtc *crtc);
struct mdp5_ctl *mdp5_crtc_get_ctl(struct drm_crtc *crtc); struct mdp5_ctl *mdp5_crtc_get_ctl(struct drm_crtc *crtc);
void mdp5_crtc_cancel_pending_flip(struct drm_crtc *crtc, struct drm_file *file); void mdp5_crtc_cancel_pending_flip(struct drm_crtc *crtc, struct drm_file *file);
void mdp5_crtc_set_intf(struct drm_crtc *crtc, struct mdp5_interface *intf); void mdp5_crtc_set_intf(struct drm_crtc *crtc, struct mdp5_interface *intf);
void mdp5_crtc_wait_for_commit_done(struct drm_crtc *crtc);
struct drm_crtc *mdp5_crtc_init(struct drm_device *dev, struct drm_crtc *mdp5_crtc_init(struct drm_device *dev,
struct drm_plane *plane, int id); struct drm_plane *plane, int id);
......
...@@ -10,17 +10,17 @@ git clone https://github.com/freedreno/envytools.git ...@@ -10,17 +10,17 @@ git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are: The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2014-12-05 15:34:49) - /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2014-12-05 15:34:49)
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20908 bytes, from 2014-12-08 16:13:00) - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-03-24 22:05:22)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2357 bytes, from 2014-12-08 16:13:00) - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2352 bytes, from 2015-04-12 15:02:42)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 27208 bytes, from 2015-01-13 23:56:11) - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 35083 bytes, from 2015-04-12 15:04:03)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43) - /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 22094 bytes, from 2015-05-12 12:45:23)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32) - /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2014-10-31 16:48:57) - /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2014-10-31 16:48:57)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12) - /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 26848 bytes, from 2015-01-13 23:55:57) - /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29012 bytes, from 2015-05-12 12:45:23)
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 8253 bytes, from 2014-12-08 16:13:00) - /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-12 12:45:23)
Copyright (C) 2013-2014 by the following authors: Copyright (C) 2013-2015 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark) - Rob Clark <robdclark@gmail.com> (robclark)
Permission is hereby granted, free of charge, to any person obtaining Permission is hereby granted, free of charge, to any person obtaining
...@@ -52,7 +52,7 @@ enum mdp_chroma_samp_type { ...@@ -52,7 +52,7 @@ enum mdp_chroma_samp_type {
CHROMA_420 = 3, CHROMA_420 = 3,
}; };
enum mdp_sspp_fetch_type { enum mdp_fetch_type {
MDP_PLANE_INTERLEAVED = 0, MDP_PLANE_INTERLEAVED = 0,
MDP_PLANE_PLANAR = 1, MDP_PLANE_PLANAR = 1,
MDP_PLANE_PSEUDO_PLANAR = 2, MDP_PLANE_PSEUDO_PLANAR = 2,
......
...@@ -96,6 +96,12 @@ static const struct mdp_format formats[] = { ...@@ -96,6 +96,12 @@ static const struct mdp_format formats[] = {
/* name a r g b e0 e1 e2 e3 alpha tight cpp cnt ... */ /* name a r g b e0 e1 e2 e3 alpha tight cpp cnt ... */
FMT(ARGB8888, 8, 8, 8, 8, 1, 0, 2, 3, true, true, 4, 4, FMT(ARGB8888, 8, 8, 8, 8, 1, 0, 2, 3, true, true, 4, 4,
MDP_PLANE_INTERLEAVED, CHROMA_RGB), MDP_PLANE_INTERLEAVED, CHROMA_RGB),
FMT(ABGR8888, 8, 8, 8, 8, 2, 0, 1, 3, true, true, 4, 4,
MDP_PLANE_INTERLEAVED, CHROMA_RGB),
FMT(RGBA8888, 8, 8, 8, 8, 3, 1, 0, 2, true, true, 4, 4,
MDP_PLANE_INTERLEAVED, CHROMA_RGB),
FMT(BGRA8888, 8, 8, 8, 8, 3, 2, 0, 1, true, true, 4, 4,
MDP_PLANE_INTERLEAVED, CHROMA_RGB),
FMT(XRGB8888, 8, 8, 8, 8, 1, 0, 2, 3, false, true, 4, 4, FMT(XRGB8888, 8, 8, 8, 8, 1, 0, 2, 3, false, true, 4, 4,
MDP_PLANE_INTERLEAVED, CHROMA_RGB), MDP_PLANE_INTERLEAVED, CHROMA_RGB),
FMT(RGB888, 0, 8, 8, 8, 1, 0, 2, 0, false, true, 3, 3, FMT(RGB888, 0, 8, 8, 8, 1, 0, 2, 0, false, true, 3, 3,
......
...@@ -88,7 +88,7 @@ struct mdp_format { ...@@ -88,7 +88,7 @@ struct mdp_format {
uint8_t unpack[4]; uint8_t unpack[4];
bool alpha_enable, unpack_tight; bool alpha_enable, unpack_tight;
uint8_t cpp, unpack_count; uint8_t cpp, unpack_count;
enum mdp_sspp_fetch_type fetch_type; enum mdp_fetch_type fetch_type;
enum mdp_chroma_samp_type chroma_sample; enum mdp_chroma_samp_type chroma_sample;
}; };
#define to_mdp_format(x) container_of(x, struct mdp_format, base) #define to_mdp_format(x) container_of(x, struct mdp_format, base)
......
This diff is collapsed.
This diff is collapsed.
...@@ -165,7 +165,7 @@ int msm_atomic_commit(struct drm_device *dev, ...@@ -165,7 +165,7 @@ int msm_atomic_commit(struct drm_device *dev,
int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu); int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu);
int msm_wait_fence_interruptable(struct drm_device *dev, uint32_t fence, int msm_wait_fence_interruptable(struct drm_device *dev, uint32_t fence,
struct timespec *timeout); ktime_t *timeout);
int msm_queue_fence_cb(struct drm_device *dev, int msm_queue_fence_cb(struct drm_device *dev,
struct msm_fence_cb *cb, uint32_t fence); struct msm_fence_cb *cb, uint32_t fence);
void msm_update_fence(struct drm_device *dev, uint32_t fence); void msm_update_fence(struct drm_device *dev, uint32_t fence);
...@@ -205,7 +205,7 @@ void msm_gem_move_to_active(struct drm_gem_object *obj, ...@@ -205,7 +205,7 @@ void msm_gem_move_to_active(struct drm_gem_object *obj,
struct msm_gpu *gpu, bool write, uint32_t fence); struct msm_gpu *gpu, bool write, uint32_t fence);
void msm_gem_move_to_inactive(struct drm_gem_object *obj); void msm_gem_move_to_inactive(struct drm_gem_object *obj);
int msm_gem_cpu_prep(struct drm_gem_object *obj, uint32_t op, int msm_gem_cpu_prep(struct drm_gem_object *obj, uint32_t op,
struct timespec *timeout); ktime_t *timeout);
int msm_gem_cpu_fini(struct drm_gem_object *obj); int msm_gem_cpu_fini(struct drm_gem_object *obj);
void msm_gem_free_object(struct drm_gem_object *obj); void msm_gem_free_object(struct drm_gem_object *obj);
int msm_gem_new_handle(struct drm_device *dev, struct drm_file *file, int msm_gem_new_handle(struct drm_device *dev, struct drm_file *file,
......
This diff is collapsed.
...@@ -96,6 +96,7 @@ static inline uint32_t msm_gem_fence(struct msm_gem_object *msm_obj, ...@@ -96,6 +96,7 @@ static inline uint32_t msm_gem_fence(struct msm_gem_object *msm_obj,
struct msm_gem_submit { struct msm_gem_submit {
struct drm_device *dev; struct drm_device *dev;
struct msm_gpu *gpu; struct msm_gpu *gpu;
struct list_head node; /* node in gpu submit_list */
struct list_head bo_list; struct list_head bo_list;
struct ww_acquire_ctx ticket; struct ww_acquire_ctx ticket;
uint32_t fence; uint32_t fence;
......
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment