Commit b9b9db02 authored by Xingyu Chen's avatar Xingyu Chen Committed by Kevin Hilman

ARM: dts: meson: drop "sana" clock from SAR ADC

The SAR ADC modules doesn't require The "sana" clock.
Acked-by: default avatarMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: default avatarXingyu Chen <xingyu.chen@amlogic.com>
Signed-off-by: default avatarYixun Lan <yixun.lan@amlogic.com>
Tested-by: default avatarKevin Hilman <khilman@baylibre.com>
Signed-off-by: default avatarKevin Hilman <khilman@baylibre.com>
parent 6844e968
...@@ -324,9 +324,8 @@ &pwm_cd { ...@@ -324,9 +324,8 @@ &pwm_cd {
&saradc { &saradc {
compatible = "amlogic,meson8-saradc", "amlogic,meson-saradc"; compatible = "amlogic,meson8-saradc", "amlogic,meson-saradc";
clocks = <&clkc CLKID_XTAL>, clocks = <&clkc CLKID_XTAL>,
<&clkc CLKID_SAR_ADC>, <&clkc CLKID_SAR_ADC>;
<&clkc CLKID_SANA>; clock-names = "clkin", "core";
clock-names = "clkin", "core", "sana";
}; };
&sdio { &sdio {
......
...@@ -239,9 +239,8 @@ &pwm_cd { ...@@ -239,9 +239,8 @@ &pwm_cd {
&saradc { &saradc {
compatible = "amlogic,meson8b-saradc", "amlogic,meson-saradc"; compatible = "amlogic,meson8b-saradc", "amlogic,meson-saradc";
clocks = <&clkc CLKID_XTAL>, clocks = <&clkc CLKID_XTAL>,
<&clkc CLKID_SAR_ADC>, <&clkc CLKID_SAR_ADC>;
<&clkc CLKID_SANA>; clock-names = "clkin", "core";
clock-names = "clkin", "core", "sana";
}; };
&sdio { &sdio {
......
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