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Commit bc44275b authored by Peter De Schrijver's avatar Peter De Schrijver
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clk: tegra: add locking to periph clks 

Tegra124 has periph clocks which share the hw register. Hence locking is
required.
Signed-off-by: default avatarPeter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 2b239077
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Showing with 24 additions and 19 deletions
drivers/clk/tegra/clk-tegra-periph.c
View file @ bc44275b
...@@ -118,75 +118,78 @@ ...@@ -118,75 +118,78 @@
_clk_num, _gate_flags, _clk_id) \ _clk_num, _gate_flags, _clk_id) \
TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\ TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \ 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \
_clk_num, _gate_flags, _clk_id, _parents##_idx, 0) _clk_num, _gate_flags, _clk_id, _parents##_idx, 0,\
NULL)
#define MUX_FLAGS(_name, _parents, _offset,\ #define MUX_FLAGS(_name, _parents, _offset,\
_clk_num, _gate_flags, _clk_id, flags)\ _clk_num, _gate_flags, _clk_id, flags)\
TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\ TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\ 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
_clk_num, _gate_flags, _clk_id, _parents##_idx, flags) _clk_num, _gate_flags, _clk_id, _parents##_idx, flags,\
NULL)
#define MUX8(_name, _parents, _offset, \ #define MUX8(_name, _parents, _offset, \
_clk_num, _gate_flags, _clk_id) \ _clk_num, _gate_flags, _clk_id) \
TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\ TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\ 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
_clk_num, _gate_flags, _clk_id, _parents##_idx, 0) _clk_num, _gate_flags, _clk_id, _parents##_idx, 0,\
NULL)
#define INT(_name, _parents, _offset, \ #define INT(_name, _parents, _offset, \
_clk_num, _gate_flags, _clk_id) \ _clk_num, _gate_flags, _clk_id) \
TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\ TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \ 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \
TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags,\ TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags,\
_clk_id, _parents##_idx, 0) _clk_id, _parents##_idx, 0, NULL)
#define INT_FLAGS(_name, _parents, _offset,\ #define INT_FLAGS(_name, _parents, _offset,\
_clk_num, _gate_flags, _clk_id, flags)\ _clk_num, _gate_flags, _clk_id, flags)\
TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\ TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \ 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \
TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags,\ TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags,\
_clk_id, _parents##_idx, flags) _clk_id, _parents##_idx, flags, NULL)
#define INT8(_name, _parents, _offset,\ #define INT8(_name, _parents, _offset,\
_clk_num, _gate_flags, _clk_id) \ _clk_num, _gate_flags, _clk_id) \
TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\ TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \ 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \
TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags,\ TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags,\
_clk_id, _parents##_idx, 0) _clk_id, _parents##_idx, 0, NULL)
#define UART(_name, _parents, _offset,\ #define UART(_name, _parents, _offset,\
_clk_num, _clk_id) \ _clk_num, _clk_id) \
TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\ TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
30, MASK(2), 0, 0, 16, 1, TEGRA_DIVIDER_UART| \ 30, MASK(2), 0, 0, 16, 1, TEGRA_DIVIDER_UART| \
TEGRA_DIVIDER_ROUND_UP, _clk_num, 0, _clk_id,\ TEGRA_DIVIDER_ROUND_UP, _clk_num, 0, _clk_id,\
_parents##_idx, 0) _parents##_idx, 0, NULL)
#define I2C(_name, _parents, _offset,\ #define I2C(_name, _parents, _offset,\
_clk_num, _clk_id) \ _clk_num, _clk_id) \
TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\ TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
30, MASK(2), 0, 0, 16, 0, TEGRA_DIVIDER_ROUND_UP,\ 30, MASK(2), 0, 0, 16, 0, TEGRA_DIVIDER_ROUND_UP,\
_clk_num, 0, _clk_id, _parents##_idx, 0) _clk_num, 0, _clk_id, _parents##_idx, 0, NULL)
#define XUSB(_name, _parents, _offset, \ #define XUSB(_name, _parents, _offset, \
_clk_num, _gate_flags, _clk_id) \ _clk_num, _gate_flags, _clk_id) \
TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset, \ TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset, \
29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \ 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \
TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags,\ TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags,\
_clk_id, _parents##_idx, 0) _clk_id, _parents##_idx, 0, NULL)
#define AUDIO(_name, _offset, _clk_num,\ #define AUDIO(_name, _offset, _clk_num,\
_gate_flags, _clk_id) \ _gate_flags, _clk_id) \
TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, mux_d_audio_clk, \ TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, mux_d_audio_clk, \
_offset, 16, 0xE01F, 0, 0, 8, 1, \ _offset, 16, 0xE01F, 0, 0, 8, 1, \
TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags, \ TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags, \
_clk_id, mux_d_audio_clk_idx, 0) _clk_id, mux_d_audio_clk_idx, 0, NULL)
#define NODIV(_name, _parents, _offset, \ #define NODIV(_name, _parents, _offset, \
_mux_shift, _mux_mask, _clk_num, \ _mux_shift, _mux_mask, _clk_num, \
_gate_flags, _clk_id) \ _gate_flags, _clk_id, _lock) \
TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\ TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
_mux_shift, _mux_mask, 0, 0, 0, 0, 0,\ _mux_shift, _mux_mask, 0, 0, 0, 0, 0,\
_clk_num, (_gate_flags) | TEGRA_PERIPH_NO_DIV,\ _clk_num, (_gate_flags) | TEGRA_PERIPH_NO_DIV,\
_clk_id, _parents##_idx, 0) _clk_id, _parents##_idx, 0, _lock)
#define GATE(_name, _parent_name, \ #define GATE(_name, _parent_name, \
_clk_num, _gate_flags, _clk_id, _flags) \ _clk_num, _gate_flags, _clk_id, _flags) \
...@@ -195,7 +198,7 @@ ...@@ -195,7 +198,7 @@
.clk_id = _clk_id, \ .clk_id = _clk_id, \
.p.parent_name = _parent_name, \ .p.parent_name = _parent_name, \
.periph = TEGRA_CLK_PERIPH(0, 0, 0, 0, 0, 0, 0, \ .periph = TEGRA_CLK_PERIPH(0, 0, 0, 0, 0, 0, 0, \
_clk_num, _gate_flags, 0), \ _clk_num, _gate_flags, 0, NULL), \
.flags = _flags \ .flags = _flags \
} }
...@@ -414,8 +417,8 @@ static struct tegra_periph_init_data periph_clks[] = { ...@@ -414,8 +417,8 @@ static struct tegra_periph_init_data periph_clks[] = {
MUX8("soc_therm", mux_pllm_pllc_pllp_plla, CLK_SOURCE_SOC_THERM, 78, TEGRA_PERIPH_ON_APB, tegra_clk_soc_therm), MUX8("soc_therm", mux_pllm_pllc_pllp_plla, CLK_SOURCE_SOC_THERM, 78, TEGRA_PERIPH_ON_APB, tegra_clk_soc_therm),
MUX8("vi_sensor", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR, 20, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor_8), MUX8("vi_sensor", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR, 20, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor_8),
MUX_FLAGS("csite", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_CSITE, 73, TEGRA_PERIPH_ON_APB, tegra_clk_csite, CLK_IGNORE_UNUSED), MUX_FLAGS("csite", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_CSITE, 73, TEGRA_PERIPH_ON_APB, tegra_clk_csite, CLK_IGNORE_UNUSED),
NODIV("disp1", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP1, 29, 7, 27, 0, tegra_clk_disp1), NODIV("disp1", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP1, 29, 7, 27, 0, tegra_clk_disp1, NULL),
NODIV("disp2", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP2, 29, 7, 26, 0, tegra_clk_disp2), NODIV("disp2", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP2, 29, 7, 26, 0, tegra_clk_disp2, NULL),
UART("uarta", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTA, 6, tegra_clk_uarta), UART("uarta", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTA, 6, tegra_clk_uarta),
UART("uartb", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTB, 7, tegra_clk_uartb), UART("uartb", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTB, 7, tegra_clk_uartb),
UART("uartc", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTC, 55, tegra_clk_uartc), UART("uartc", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTC, 55, tegra_clk_uartc),
......
drivers/clk/tegra/clk.h
View file @ bc44275b
...@@ -439,19 +439,21 @@ struct clk *tegra_clk_register_periph_nodiv(const char *name, ...@@ -439,19 +439,21 @@ struct clk *tegra_clk_register_periph_nodiv(const char *name,
#define TEGRA_CLK_PERIPH(_mux_shift, _mux_mask, _mux_flags, \ #define TEGRA_CLK_PERIPH(_mux_shift, _mux_mask, _mux_flags, \
_div_shift, _div_width, _div_frac_width, \ _div_shift, _div_width, _div_frac_width, \
_div_flags, _clk_num,\ _div_flags, _clk_num,\
_gate_flags, _table) \ _gate_flags, _table, _lock) \
{ \ { \
.mux = { \ .mux = { \
.flags = _mux_flags, \ .flags = _mux_flags, \
.shift = _mux_shift, \ .shift = _mux_shift, \
.mask = _mux_mask, \ .mask = _mux_mask, \
.table = _table, \ .table = _table, \
.lock = _lock, \
}, \ }, \
.divider = { \ .divider = { \
.flags = _div_flags, \ .flags = _div_flags, \
.shift = _div_shift, \ .shift = _div_shift, \
.width = _div_width, \ .width = _div_width, \
.frac_width = _div_frac_width, \ .frac_width = _div_frac_width, \
.lock = _lock, \
}, \ }, \
.gate = { \ .gate = { \
.flags = _gate_flags, \ .flags = _gate_flags, \
...@@ -481,7 +483,7 @@ struct tegra_periph_init_data { ...@@ -481,7 +483,7 @@ struct tegra_periph_init_data {
_mux_shift, _mux_mask, _mux_flags, _div_shift, \ _mux_shift, _mux_mask, _mux_flags, _div_shift, \
_div_width, _div_frac_width, _div_flags, \ _div_width, _div_frac_width, _div_flags, \
_clk_num, _gate_flags, _clk_id, _table, \ _clk_num, _gate_flags, _clk_id, _table, \
_flags) \ _flags, _lock) \
{ \ { \
.name = _name, \ .name = _name, \
.clk_id = _clk_id, \ .clk_id = _clk_id, \
...@@ -491,7 +493,7 @@ struct tegra_periph_init_data { ...@@ -491,7 +493,7 @@ struct tegra_periph_init_data {
_mux_flags, _div_shift, \ _mux_flags, _div_shift, \
_div_width, _div_frac_width, \ _div_width, _div_frac_width, \
_div_flags, _clk_num, \ _div_flags, _clk_num, \
_gate_flags, _table), \ _gate_flags, _table, _lock), \
.offset = _offset, \ .offset = _offset, \
.con_id = _con_id, \ .con_id = _con_id, \
.dev_id = _dev_id, \ .dev_id = _dev_id, \
...@@ -506,7 +508,7 @@ struct tegra_periph_init_data { ...@@ -506,7 +508,7 @@ struct tegra_periph_init_data {
_mux_shift, BIT(_mux_width) - 1, _mux_flags, \ _mux_shift, BIT(_mux_width) - 1, _mux_flags, \
_div_shift, _div_width, _div_frac_width, _div_flags, \ _div_shift, _div_width, _div_frac_width, _div_flags, \
_clk_num, _gate_flags, _clk_id,\ _clk_num, _gate_flags, _clk_id,\
NULL, 0) NULL, 0, NULL)
/** /**
* struct clk_super_mux - super clock * struct clk_super_mux - super clock
......
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