Commit bc4d6daf authored by Monam Agarwal's avatar Monam Agarwal Committed by Greg Kroah-Hartman

Staging: cxt1e1: Fix no spaces at the start of a line in functions.c

This patch fixes the following checkpatch.pl warning in functions.c
WARNING: please no spaces at the start of a line in
Signed-off-by: default avatarMonam Agarwal <monamagarwal123@gmail.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 223eaa37
...@@ -25,7 +25,7 @@ ...@@ -25,7 +25,7 @@
#include "pmcc4.h" #include "pmcc4.h"
#if defined(CONFIG_SBE_HDLC_V7) || defined(CONFIG_SBE_WAN256T3_HDLC_V7) || \ #if defined(CONFIG_SBE_HDLC_V7) || defined(CONFIG_SBE_WAN256T3_HDLC_V7) || \
defined(CONFIG_SBE_HDLC_V7_MODULE) || defined(CONFIG_SBE_WAN256T3_HDLC_V7_MODULE) defined(CONFIG_SBE_HDLC_V7_MODULE) || defined(CONFIG_SBE_WAN256T3_HDLC_V7_MODULE)
#define _v7_hdlc_ 1 #define _v7_hdlc_ 1
#else #else
#define _v7_hdlc_ 0 #define _v7_hdlc_ 0
...@@ -56,16 +56,16 @@ u_int32_t ...@@ -56,16 +56,16 @@ u_int32_t
pci_read_32 (u_int32_t *p) pci_read_32 (u_int32_t *p)
{ {
#ifdef FLOW_DEBUG #ifdef FLOW_DEBUG
u_int32_t v; u_int32_t v;
FLUSH_PCI_READ (); FLUSH_PCI_READ ();
v = le32_to_cpu (*p); v = le32_to_cpu (*p);
if (cxt1e1_log_level >= LOG_DEBUG) if (cxt1e1_log_level >= LOG_DEBUG)
pr_info("pci_read : %x = %x\n", (u_int32_t) p, v); pr_info("pci_read : %x = %x\n", (u_int32_t) p, v);
return v; return v;
#else #else
FLUSH_PCI_READ (); /* */ FLUSH_PCI_READ (); /* */
return le32_to_cpu (*p); return le32_to_cpu (*p);
#endif #endif
} }
...@@ -73,18 +73,18 @@ void ...@@ -73,18 +73,18 @@ void
pci_write_32 (u_int32_t *p, u_int32_t v) pci_write_32 (u_int32_t *p, u_int32_t v)
{ {
#ifdef FLOW_DEBUG #ifdef FLOW_DEBUG
if (cxt1e1_log_level >= LOG_DEBUG) if (cxt1e1_log_level >= LOG_DEBUG)
pr_info("pci_write: %x = %x\n", (u_int32_t) p, v); pr_info("pci_write: %x = %x\n", (u_int32_t) p, v);
#endif #endif
*p = cpu_to_le32 (v); *p = cpu_to_le32 (v);
FLUSH_PCI_WRITE (); /* This routine is called from routines FLUSH_PCI_WRITE (); /* This routine is called from routines
* which do multiple register writes * which do multiple register writes
* which themselves need flushing between * which themselves need flushing between
* writes in order to guarantee write * writes in order to guarantee write
* ordering. It is less code-cumbersome * ordering. It is less code-cumbersome
* to flush here-in then to investigate * to flush here-in then to investigate
* and code the many other register * and code the many other register
* writing routines. */ * writing routines. */
} }
#endif #endif
...@@ -92,10 +92,10 @@ pci_write_32 (u_int32_t *p, u_int32_t v) ...@@ -92,10 +92,10 @@ pci_write_32 (u_int32_t *p, u_int32_t v)
void void
pci_flush_write (ci_t *ci) pci_flush_write (ci_t *ci)
{ {
volatile u_int32_t v; volatile u_int32_t v;
/* issue a PCI read to flush PCI write thru bridge */ /* issue a PCI read to flush PCI write thru bridge */
v = *(u_int32_t *) &ci->reg->glcd; /* any address would do */ v = *(u_int32_t *) &ci->reg->glcd; /* any address would do */
/* /*
* return nothing, this just reads PCI bridge interface to flush * return nothing, this just reads PCI bridge interface to flush
...@@ -107,53 +107,49 @@ pci_flush_write (ci_t *ci) ...@@ -107,53 +107,49 @@ pci_flush_write (ci_t *ci)
static void static void
watchdog_func (unsigned long arg) watchdog_func (unsigned long arg)
{ {
struct watchdog *wd = (void *) arg; struct watchdog *wd = (void *) arg;
if (drvr_state != SBE_DRVR_AVAILABLE) if (drvr_state != SBE_DRVR_AVAILABLE) {
{ if (cxt1e1_log_level >= LOG_MONITOR)
if (cxt1e1_log_level >= LOG_MONITOR) pr_warning("%s: drvr not available (%x)\n", __func__, drvr_state);
pr_warning("%s: drvr not available (%x)\n", __func__, drvr_state); return;
return; }
} schedule_work (&wd->work);
schedule_work (&wd->work); mod_timer (&wd->h, jiffies + wd->ticks);
mod_timer (&wd->h, jiffies + wd->ticks);
} }
int OS_init_watchdog(struct watchdog *wdp, void (*f) (void *), void *c, int usec) int OS_init_watchdog(struct watchdog *wdp, void (*f) (void *), void *c, int usec)
{ {
wdp->func = f; wdp->func = f;
wdp->softc = c; wdp->softc = c;
wdp->ticks = (HZ) * (usec / 1000) / 1000; wdp->ticks = (HZ) * (usec / 1000) / 1000;
INIT_WORK(&wdp->work, (void *)f); INIT_WORK(&wdp->work, (void *)f);
init_timer (&wdp->h); init_timer (&wdp->h);
{ {
ci_t *ci = (ci_t *) c; ci_t *ci = (ci_t *) c;
wdp->h.data = (unsigned long) &ci->wd; wdp->h.data = (unsigned long) &ci->wd;
} }
wdp->h.function = watchdog_func; wdp->h.function = watchdog_func;
return 0; return 0;
} }
void void
OS_uwait (int usec, char *description) OS_uwait (int usec, char *description)
{ {
int tmp; int tmp;
if (usec >= 1000) if (usec >= 1000) {
{ mdelay (usec / 1000);
mdelay (usec / 1000); /* now delay residual */
/* now delay residual */ tmp = (usec / 1000) * 1000; /* round */
tmp = (usec / 1000) * 1000; /* round */ tmp = usec - tmp; /* residual */
tmp = usec - tmp; /* residual */ if (tmp) { /* wait on residual */
if (tmp) udelay (tmp);
{ /* wait on residual */ }
udelay (tmp); } else {
} udelay (usec);
} else }
{
udelay (usec);
}
} }
/* dummy short delay routine called as a subroutine so that compiler /* dummy short delay routine called as a subroutine so that compiler
...@@ -164,9 +160,9 @@ void ...@@ -164,9 +160,9 @@ void
OS_uwait_dummy (void) OS_uwait_dummy (void)
{ {
#ifndef USE_MAX_INT_DELAY #ifndef USE_MAX_INT_DELAY
dummy++; dummy++;
#else #else
udelay (1); udelay (1);
#endif #endif
} }
...@@ -174,83 +170,82 @@ OS_uwait_dummy (void) ...@@ -174,83 +170,82 @@ OS_uwait_dummy (void)
void void
OS_sem_init (void *sem, int state) OS_sem_init (void *sem, int state)
{ {
switch (state) switch (state) {
{ case SEM_TAKEN:
case SEM_TAKEN: sema_init((struct semaphore *) sem, 0);
sema_init((struct semaphore *) sem, 0); break;
break; case SEM_AVAILABLE:
case SEM_AVAILABLE:
sema_init((struct semaphore *) sem, 1); sema_init((struct semaphore *) sem, 1);
break; break;
default: /* otherwise, set sem.count to state's default: /* otherwise, set sem.count to state's
* value */ * value */
sema_init (sem, state); sema_init (sem, state);
break; break;
} }
} }
int int
sd_line_is_ok (void *user) sd_line_is_ok (void *user)
{ {
struct net_device *ndev = (struct net_device *) user; struct net_device *ndev = (struct net_device *) user;
return netif_carrier_ok (ndev); return netif_carrier_ok (ndev);
} }
void void
sd_line_is_up (void *user) sd_line_is_up (void *user)
{ {
struct net_device *ndev = (struct net_device *) user; struct net_device *ndev = (struct net_device *) user;
netif_carrier_on (ndev); netif_carrier_on (ndev);
return; return;
} }
void void
sd_line_is_down (void *user) sd_line_is_down (void *user)
{ {
struct net_device *ndev = (struct net_device *) user; struct net_device *ndev = (struct net_device *) user;
netif_carrier_off (ndev); netif_carrier_off (ndev);
return; return;
} }
void void
sd_disable_xmit (void *user) sd_disable_xmit (void *user)
{ {
struct net_device *dev = (struct net_device *) user; struct net_device *dev = (struct net_device *) user;
netif_stop_queue (dev); netif_stop_queue (dev);
return; return;
} }
void void
sd_enable_xmit (void *user) sd_enable_xmit (void *user)
{ {
struct net_device *dev = (struct net_device *) user; struct net_device *dev = (struct net_device *) user;
netif_wake_queue (dev); netif_wake_queue (dev);
return; return;
} }
int int
sd_queue_stopped (void *user) sd_queue_stopped (void *user)
{ {
struct net_device *ndev = (struct net_device *) user; struct net_device *ndev = (struct net_device *) user;
return netif_queue_stopped (ndev); return netif_queue_stopped (ndev);
} }
void sd_recv_consume(void *token, size_t len, void *user) void sd_recv_consume(void *token, size_t len, void *user)
{ {
struct net_device *ndev = user; struct net_device *ndev = user;
struct sk_buff *skb = token; struct sk_buff *skb = token;
skb->dev = ndev; skb->dev = ndev;
skb_put (skb, len); skb_put (skb, len);
skb->protocol = hdlc_type_trans(skb, ndev); skb->protocol = hdlc_type_trans(skb, ndev);
netif_rx(skb); netif_rx(skb);
} }
...@@ -265,75 +260,74 @@ extern ci_t *CI; /* dummy pointer to board ZERO's data */ ...@@ -265,75 +260,74 @@ extern ci_t *CI; /* dummy pointer to board ZERO's data */
void void
VMETRO_TRIGGER (ci_t *ci, int x) VMETRO_TRIGGER (ci_t *ci, int x)
{ {
struct s_comet_reg *comet; struct s_comet_reg *comet;
volatile u_int32_t data; volatile u_int32_t data;
comet = ci->port[0].cometbase; /* default to COMET # 0 */ comet = ci->port[0].cometbase; /* default to COMET # 0 */
switch (x) switch (x) {
{ default:
default: case 0:
case 0: data = pci_read_32 ((u_int32_t *) &comet->__res24); /* 0x90 */
data = pci_read_32 ((u_int32_t *) &comet->__res24); /* 0x90 */ break;
break; case 1:
case 1: data = pci_read_32 ((u_int32_t *) &comet->__res25); /* 0x94 */
data = pci_read_32 ((u_int32_t *) &comet->__res25); /* 0x94 */ break;
break; case 2:
case 2: data = pci_read_32 ((u_int32_t *) &comet->__res26); /* 0x98 */
data = pci_read_32 ((u_int32_t *) &comet->__res26); /* 0x98 */ break;
break; case 3:
case 3: data = pci_read_32 ((u_int32_t *) &comet->__res27); /* 0x9C */
data = pci_read_32 ((u_int32_t *) &comet->__res27); /* 0x9C */ break;
break; case 4:
case 4: data = pci_read_32 ((u_int32_t *) &comet->__res88); /* 0x220 */
data = pci_read_32 ((u_int32_t *) &comet->__res88); /* 0x220 */ break;
break; case 5:
case 5: data = pci_read_32 ((u_int32_t *) &comet->__res89); /* 0x224 */
data = pci_read_32 ((u_int32_t *) &comet->__res89); /* 0x224 */ break;
break; case 6:
case 6: data = pci_read_32 ((u_int32_t *) &comet->__res8A); /* 0x228 */
data = pci_read_32 ((u_int32_t *) &comet->__res8A); /* 0x228 */ break;
break; case 7:
case 7: data = pci_read_32 ((u_int32_t *) &comet->__res8B); /* 0x22C */
data = pci_read_32 ((u_int32_t *) &comet->__res8B); /* 0x22C */ break;
break; case 8:
case 8: data = pci_read_32 ((u_int32_t *) &comet->__resA0); /* 0x280 */
data = pci_read_32 ((u_int32_t *) &comet->__resA0); /* 0x280 */ break;
break; case 9:
case 9: data = pci_read_32 ((u_int32_t *) &comet->__resA1); /* 0x284 */
data = pci_read_32 ((u_int32_t *) &comet->__resA1); /* 0x284 */ break;
break; case 10:
case 10: data = pci_read_32 ((u_int32_t *) &comet->__resA2); /* 0x288 */
data = pci_read_32 ((u_int32_t *) &comet->__resA2); /* 0x288 */ break;
break; case 11:
case 11: data = pci_read_32 ((u_int32_t *) &comet->__resA3); /* 0x28C */
data = pci_read_32 ((u_int32_t *) &comet->__resA3); /* 0x28C */ break;
break; case 12:
case 12: data = pci_read_32 ((u_int32_t *) &comet->__resA4); /* 0x290 */
data = pci_read_32 ((u_int32_t *) &comet->__resA4); /* 0x290 */ break;
break; case 13:
case 13: data = pci_read_32 ((u_int32_t *) &comet->__resA5); /* 0x294 */
data = pci_read_32 ((u_int32_t *) &comet->__resA5); /* 0x294 */ break;
break; case 14:
case 14: data = pci_read_32 ((u_int32_t *) &comet->__resA6); /* 0x298 */
data = pci_read_32 ((u_int32_t *) &comet->__resA6); /* 0x298 */ break;
break; case 15:
case 15: data = pci_read_32 ((u_int32_t *) &comet->__resA7); /* 0x29C */
data = pci_read_32 ((u_int32_t *) &comet->__resA7); /* 0x29C */ break;
break; case 16:
case 16: data = pci_read_32 ((u_int32_t *) &comet->__res74); /* 0x1D0 */
data = pci_read_32 ((u_int32_t *) &comet->__res74); /* 0x1D0 */ break;
break; case 17:
case 17: data = pci_read_32 ((u_int32_t *) &comet->__res75); /* 0x1D4 */
data = pci_read_32 ((u_int32_t *) &comet->__res75); /* 0x1D4 */ break;
break; case 18:
case 18: data = pci_read_32 ((u_int32_t *) &comet->__res76); /* 0x1D8 */
data = pci_read_32 ((u_int32_t *) &comet->__res76); /* 0x1D8 */ break;
break; case 19:
case 19: data = pci_read_32 ((u_int32_t *) &comet->__res77); /* 0x1DC */
data = pci_read_32 ((u_int32_t *) &comet->__res77); /* 0x1DC */ break;
break; }
}
} }
......
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