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Commit bc8bf90a authored by Nick Robinson's avatar Nick Robinson Committed by Greg Kroah-Hartman
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Staging: comedi: Fix checpatch.pl issues in file rtd520.c 

This patch fixes the checkpatch errors listed below:

ERROR: code indent should use tabs where possible
WARNING: space prohibited between function name and open parenthesis '('
WARNING: please, no spaces at the start of a line
WARNING: braces {} are not necessary for single statement blocks
WARNING: printk() should include KERN_ facility level
Signed-off-by: default avatarNick Robinson <nr33@msstate.edu>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@suse.de>
parent e80528b7
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Showing with 157 additions and 164 deletions
drivers/staging/comedi/drivers/rtd520.c
View file @ bc8bf90a
...@@ -136,7 +136,7 @@ Configuration options: ...@@ -136,7 +136,7 @@ Configuration options:
#define RTD_DMA_TIMEOUT 33000 /* 1 msec */ #define RTD_DMA_TIMEOUT 33000 /* 1 msec */
#else #else
/* by delaying, power and electrical noise are reduced somewhat */ /* by delaying, power and electrical noise are reduced somewhat */
#define WAIT_QUIETLY udelay (1) #define WAIT_QUIETLY udelay(1)
#define RTD_ADC_TIMEOUT 2000 /* in usec */ #define RTD_ADC_TIMEOUT 2000 /* in usec */
#define RTD_DAC_TIMEOUT 2000 /* in usec */ #define RTD_DAC_TIMEOUT 2000 /* in usec */
#define RTD_DMA_TIMEOUT 1000 /* in usec */ #define RTD_DMA_TIMEOUT 1000 /* in usec */
...@@ -414,296 +414,296 @@ struct rtdPrivate { ...@@ -414,296 +414,296 @@ struct rtdPrivate {
/* Reset board */ /* Reset board */
#define RtdResetBoard(dev) \ #define RtdResetBoard(dev) \
writel (0, devpriv->las0+LAS0_BOARD_RESET) writel(0, devpriv->las0+LAS0_BOARD_RESET)
/* Reset channel gain table read pointer */ /* Reset channel gain table read pointer */
#define RtdResetCGT(dev) \ #define RtdResetCGT(dev) \
writel (0, devpriv->las0+LAS0_CGT_RESET) writel(0, devpriv->las0+LAS0_CGT_RESET)
/* Reset channel gain table read and write pointers */ /* Reset channel gain table read and write pointers */
#define RtdClearCGT(dev) \ #define RtdClearCGT(dev) \
writel (0, devpriv->las0+LAS0_CGT_CLEAR) writel(0, devpriv->las0+LAS0_CGT_CLEAR)
/* Reset channel gain table read and write pointers */ /* Reset channel gain table read and write pointers */
#define RtdEnableCGT(dev, v) \ #define RtdEnableCGT(dev, v) \
writel ((v > 0) ? 1 : 0, devpriv->las0+LAS0_CGT_ENABLE) writel((v > 0) ? 1 : 0, devpriv->las0+LAS0_CGT_ENABLE)
/* Write channel gain table entry */ /* Write channel gain table entry */
#define RtdWriteCGTable(dev, v) \ #define RtdWriteCGTable(dev, v) \
writel (v, devpriv->las0+LAS0_CGT_WRITE) writel(v, devpriv->las0+LAS0_CGT_WRITE)
/* Write Channel Gain Latch */ /* Write Channel Gain Latch */
#define RtdWriteCGLatch(dev, v) \ #define RtdWriteCGLatch(dev, v) \
writel (v, devpriv->las0+LAS0_CGL_WRITE) writel(v, devpriv->las0+LAS0_CGL_WRITE)
/* Reset ADC FIFO */ /* Reset ADC FIFO */
#define RtdAdcClearFifo(dev) \ #define RtdAdcClearFifo(dev) \
writel (0, devpriv->las0+LAS0_ADC_FIFO_CLEAR) writel(0, devpriv->las0+LAS0_ADC_FIFO_CLEAR)
/* Set ADC start conversion source select (write only) */ /* Set ADC start conversion source select (write only) */
#define RtdAdcConversionSource(dev, v) \ #define RtdAdcConversionSource(dev, v) \
writel (v, devpriv->las0+LAS0_ADC_CONVERSION) writel(v, devpriv->las0+LAS0_ADC_CONVERSION)
/* Set burst start source select (write only) */ /* Set burst start source select (write only) */
#define RtdBurstStartSource(dev, v) \ #define RtdBurstStartSource(dev, v) \
writel (v, devpriv->las0+LAS0_BURST_START) writel(v, devpriv->las0+LAS0_BURST_START)
/* Set Pacer start source select (write only) */ /* Set Pacer start source select (write only) */
#define RtdPacerStartSource(dev, v) \ #define RtdPacerStartSource(dev, v) \
writel (v, devpriv->las0+LAS0_PACER_START) writel(v, devpriv->las0+LAS0_PACER_START)
/* Set Pacer stop source select (write only) */ /* Set Pacer stop source select (write only) */
#define RtdPacerStopSource(dev, v) \ #define RtdPacerStopSource(dev, v) \
writel (v, devpriv->las0+LAS0_PACER_STOP) writel(v, devpriv->las0+LAS0_PACER_STOP)
/* Set Pacer clock source select (write only) 0=external 1=internal */ /* Set Pacer clock source select (write only) 0=external 1=internal */
#define RtdPacerClockSource(dev, v) \ #define RtdPacerClockSource(dev, v) \
writel ((v > 0) ? 1 : 0, devpriv->las0+LAS0_PACER_SELECT) writel((v > 0) ? 1 : 0, devpriv->las0+LAS0_PACER_SELECT)
/* Set sample counter source select (write only) */ /* Set sample counter source select (write only) */
#define RtdAdcSampleCounterSource(dev, v) \ #define RtdAdcSampleCounterSource(dev, v) \
writel (v, devpriv->las0+LAS0_ADC_SCNT_SRC) writel(v, devpriv->las0+LAS0_ADC_SCNT_SRC)
/* Set Pacer trigger mode select (write only) 0=single cycle, 1=repeat */ /* Set Pacer trigger mode select (write only) 0=single cycle, 1=repeat */
#define RtdPacerTriggerMode(dev, v) \ #define RtdPacerTriggerMode(dev, v) \
writel ((v > 0) ? 1 : 0, devpriv->las0+LAS0_PACER_REPEAT) writel((v > 0) ? 1 : 0, devpriv->las0+LAS0_PACER_REPEAT)
/* Set About counter stop enable (write only) */ /* Set About counter stop enable (write only) */
#define RtdAboutStopEnable(dev, v) \ #define RtdAboutStopEnable(dev, v) \
writel ((v > 0) ? 1 : 0, devpriv->las0+LAS0_ACNT_STOP_ENABLE) writel((v > 0) ? 1 : 0, devpriv->las0+LAS0_ACNT_STOP_ENABLE)
/* Set external trigger polarity (write only) 0=positive edge, 1=negative */ /* Set external trigger polarity (write only) 0=positive edge, 1=negative */
#define RtdTriggerPolarity(dev, v) \ #define RtdTriggerPolarity(dev, v) \
writel ((v > 0) ? 1 : 0, devpriv->las0+LAS0_ETRG_POLARITY) writel((v > 0) ? 1 : 0, devpriv->las0+LAS0_ETRG_POLARITY)
/* Start single ADC conversion */ /* Start single ADC conversion */
#define RtdAdcStart(dev) \ #define RtdAdcStart(dev) \
writew (0, devpriv->las0+LAS0_ADC) writew(0, devpriv->las0+LAS0_ADC)
/* Read one ADC data value (12bit (with sign extend) as 16bit) */ /* Read one ADC data value (12bit (with sign extend) as 16bit) */
/* Note: matches what DMA would get. Actual value >> 3 */ /* Note: matches what DMA would get. Actual value >> 3 */
#define RtdAdcFifoGet(dev) \ #define RtdAdcFifoGet(dev) \
readw (devpriv->las1+LAS1_ADC_FIFO) readw(devpriv->las1+LAS1_ADC_FIFO)
/* Read two ADC data values (DOESNT WORK) */ /* Read two ADC data values (DOESNT WORK) */
#define RtdAdcFifoGet2(dev) \ #define RtdAdcFifoGet2(dev) \
readl (devpriv->las1+LAS1_ADC_FIFO) readl(devpriv->las1+LAS1_ADC_FIFO)
/* FIFO status */ /* FIFO status */
#define RtdFifoStatus(dev) \ #define RtdFifoStatus(dev) \
readl (devpriv->las0+LAS0_ADC) readl(devpriv->las0+LAS0_ADC)
/* pacer start/stop read=start, write=stop*/ /* pacer start/stop read=start, write=stop*/
#define RtdPacerStart(dev) \ #define RtdPacerStart(dev) \
readl (devpriv->las0+LAS0_PACER) readl(devpriv->las0+LAS0_PACER)
#define RtdPacerStop(dev) \ #define RtdPacerStop(dev) \
writel (0, devpriv->las0+LAS0_PACER) writel(0, devpriv->las0+LAS0_PACER)
/* Interrupt status */ /* Interrupt status */
#define RtdInterruptStatus(dev) \ #define RtdInterruptStatus(dev) \
readw (devpriv->las0+LAS0_IT) readw(devpriv->las0+LAS0_IT)
/* Interrupt mask */ /* Interrupt mask */
#define RtdInterruptMask(dev, v) \ #define RtdInterruptMask(dev, v) \
writew ((devpriv->intMask = (v)), devpriv->las0+LAS0_IT) writew((devpriv->intMask = (v)), devpriv->las0+LAS0_IT)
/* Interrupt status clear (only bits set in mask) */ /* Interrupt status clear (only bits set in mask) */
#define RtdInterruptClear(dev) \ #define RtdInterruptClear(dev) \
readw (devpriv->las0+LAS0_CLEAR) readw(devpriv->las0+LAS0_CLEAR)
/* Interrupt clear mask */ /* Interrupt clear mask */
#define RtdInterruptClearMask(dev, v) \ #define RtdInterruptClearMask(dev, v) \
writew ((devpriv->intClearMask = (v)), devpriv->las0+LAS0_CLEAR) writew((devpriv->intClearMask = (v)), devpriv->las0+LAS0_CLEAR)
/* Interrupt overrun status */ /* Interrupt overrun status */
#define RtdInterruptOverrunStatus(dev) \ #define RtdInterruptOverrunStatus(dev) \
readl (devpriv->las0+LAS0_OVERRUN) readl(devpriv->las0+LAS0_OVERRUN)
/* Interrupt overrun clear */ /* Interrupt overrun clear */
#define RtdInterruptOverrunClear(dev) \ #define RtdInterruptOverrunClear(dev) \
writel (0, devpriv->las0+LAS0_OVERRUN) writel(0, devpriv->las0+LAS0_OVERRUN)
/* Pacer counter, 24bit */ /* Pacer counter, 24bit */
#define RtdPacerCount(dev) \ #define RtdPacerCount(dev) \
readl (devpriv->las0+LAS0_PCLK) readl(devpriv->las0+LAS0_PCLK)
#define RtdPacerCounter(dev, v) \ #define RtdPacerCounter(dev, v) \
writel ((v) & 0xffffff, devpriv->las0+LAS0_PCLK) writel((v) & 0xffffff, devpriv->las0+LAS0_PCLK)
/* Burst counter, 10bit */ /* Burst counter, 10bit */
#define RtdBurstCount(dev) \ #define RtdBurstCount(dev) \
readl (devpriv->las0+LAS0_BCLK) readl(devpriv->las0+LAS0_BCLK)
#define RtdBurstCounter(dev, v) \ #define RtdBurstCounter(dev, v) \
writel ((v) & 0x3ff, devpriv->las0+LAS0_BCLK) writel((v) & 0x3ff, devpriv->las0+LAS0_BCLK)
/* Delay counter, 16bit */ /* Delay counter, 16bit */
#define RtdDelayCount(dev) \ #define RtdDelayCount(dev) \
readl (devpriv->las0+LAS0_DCLK) readl(devpriv->las0+LAS0_DCLK)
#define RtdDelayCounter(dev, v) \ #define RtdDelayCounter(dev, v) \
writel ((v) & 0xffff, devpriv->las0+LAS0_DCLK) writel((v) & 0xffff, devpriv->las0+LAS0_DCLK)
/* About counter, 16bit */ /* About counter, 16bit */
#define RtdAboutCount(dev) \ #define RtdAboutCount(dev) \
readl (devpriv->las0+LAS0_ACNT) readl(devpriv->las0+LAS0_ACNT)
#define RtdAboutCounter(dev, v) \ #define RtdAboutCounter(dev, v) \
writel ((v) & 0xffff, devpriv->las0+LAS0_ACNT) writel((v) & 0xffff, devpriv->las0+LAS0_ACNT)
/* ADC sample counter, 10bit */ /* ADC sample counter, 10bit */
#define RtdAdcSampleCount(dev) \ #define RtdAdcSampleCount(dev) \
readl (devpriv->las0+LAS0_ADC_SCNT) readl(devpriv->las0+LAS0_ADC_SCNT)
#define RtdAdcSampleCounter(dev, v) \ #define RtdAdcSampleCounter(dev, v) \
writel ((v) & 0x3ff, devpriv->las0+LAS0_ADC_SCNT) writel((v) & 0x3ff, devpriv->las0+LAS0_ADC_SCNT)
/* User Timer/Counter (8254) */ /* User Timer/Counter (8254) */
#define RtdUtcCounterGet(dev, n) \ #define RtdUtcCounterGet(dev, n) \
readb (devpriv->las0 \ readb(devpriv->las0 \
+ ((n <= 0) ? LAS0_UTC0 : ((1 == n) ? LAS0_UTC1 : LAS0_UTC2))) + ((n <= 0) ? LAS0_UTC0 : ((1 == n) ? LAS0_UTC1 : LAS0_UTC2)))
#define RtdUtcCounterPut(dev, n, v) \ #define RtdUtcCounterPut(dev, n, v) \
writeb ((v) & 0xff, devpriv->las0 \ writeb((v) & 0xff, devpriv->las0 \
+ ((n <= 0) ? LAS0_UTC0 : ((1 == n) ? LAS0_UTC1 : LAS0_UTC2))) + ((n <= 0) ? LAS0_UTC0 : ((1 == n) ? LAS0_UTC1 : LAS0_UTC2)))
/* Set UTC (8254) control byte */ /* Set UTC (8254) control byte */
#define RtdUtcCtrlPut(dev, n, v) \ #define RtdUtcCtrlPut(dev, n, v) \
writeb (devpriv->utcCtrl[(n) & 3] = (((n) & 3) << 6) | ((v) & 0x3f), \ writeb(devpriv->utcCtrl[(n) & 3] = (((n) & 3) << 6) | ((v) & 0x3f), \
devpriv->las0 + LAS0_UTC_CTRL) devpriv->las0 + LAS0_UTC_CTRL)
/* Set UTCn clock source (write only) */ /* Set UTCn clock source (write only) */
#define RtdUtcClockSource(dev, n, v) \ #define RtdUtcClockSource(dev, n, v) \
writew (v, devpriv->las0 \ writew(v, devpriv->las0 \
+ ((n <= 0) ? LAS0_UTC0_CLOCK : \ + ((n <= 0) ? LAS0_UTC0_CLOCK : \
((1 == n) ? LAS0_UTC1_CLOCK : LAS0_UTC2_CLOCK))) ((1 == n) ? LAS0_UTC1_CLOCK : LAS0_UTC2_CLOCK)))
/* Set UTCn gate source (write only) */ /* Set UTCn gate source (write only) */
#define RtdUtcGateSource(dev, n, v) \ #define RtdUtcGateSource(dev, n, v) \
writew (v, devpriv->las0 \ writew(v, devpriv->las0 \
+ ((n <= 0) ? LAS0_UTC0_GATE : \ + ((n <= 0) ? LAS0_UTC0_GATE : \
((1 == n) ? LAS0_UTC1_GATE : LAS0_UTC2_GATE))) ((1 == n) ? LAS0_UTC1_GATE : LAS0_UTC2_GATE)))
/* User output N source select (write only) */ /* User output N source select (write only) */
#define RtdUsrOutSource(dev, n, v) \ #define RtdUsrOutSource(dev, n, v) \
writel (v, devpriv->las0+((n <= 0) ? LAS0_UOUT0_SELECT : LAS0_UOUT1_SELECT)) writel(v, devpriv->las0+((n <= 0) ? LAS0_UOUT0_SELECT : LAS0_UOUT1_SELECT))
/* Digital IO */ /* Digital IO */
#define RtdDio0Read(dev) \ #define RtdDio0Read(dev) \
(readw (devpriv->las0+LAS0_DIO0) & 0xff) (readw(devpriv->las0+LAS0_DIO0) & 0xff)
#define RtdDio0Write(dev, v) \ #define RtdDio0Write(dev, v) \
writew ((v) & 0xff, devpriv->las0+LAS0_DIO0) writew((v) & 0xff, devpriv->las0+LAS0_DIO0)
#define RtdDio1Read(dev) \ #define RtdDio1Read(dev) \
(readw (devpriv->las0+LAS0_DIO1) & 0xff) (readw(devpriv->las0+LAS0_DIO1) & 0xff)
#define RtdDio1Write(dev, v) \ #define RtdDio1Write(dev, v) \
writew ((v) & 0xff, devpriv->las0+LAS0_DIO1) writew((v) & 0xff, devpriv->las0+LAS0_DIO1)
#define RtdDioStatusRead(dev) \ #define RtdDioStatusRead(dev) \
(readw (devpriv->las0+LAS0_DIO_STATUS) & 0xff) (readw(devpriv->las0+LAS0_DIO_STATUS) & 0xff)
#define RtdDioStatusWrite(dev, v) \ #define RtdDioStatusWrite(dev, v) \
writew ((devpriv->dioStatus = (v)), devpriv->las0+LAS0_DIO_STATUS) writew((devpriv->dioStatus = (v)), devpriv->las0+LAS0_DIO_STATUS)
#define RtdDio0CtrlRead(dev) \ #define RtdDio0CtrlRead(dev) \
(readw (devpriv->las0+LAS0_DIO0_CTRL) & 0xff) (readw(devpriv->las0+LAS0_DIO0_CTRL) & 0xff)
#define RtdDio0CtrlWrite(dev, v) \ #define RtdDio0CtrlWrite(dev, v) \
writew ((v) & 0xff, devpriv->las0+LAS0_DIO0_CTRL) writew((v) & 0xff, devpriv->las0+LAS0_DIO0_CTRL)
/* Digital to Analog converter */ /* Digital to Analog converter */
/* Write one data value (sign + 12bit + marker bits) */ /* Write one data value (sign + 12bit + marker bits) */
/* Note: matches what DMA would put. Actual value << 3 */ /* Note: matches what DMA would put. Actual value << 3 */
#define RtdDacFifoPut(dev, n, v) \ #define RtdDacFifoPut(dev, n, v) \
writew ((v), devpriv->las1 +(((n) == 0) ? LAS1_DAC1_FIFO : LAS1_DAC2_FIFO)) writew((v), devpriv->las1 + (((n) == 0) ? LAS1_DAC1_FIFO : LAS1_DAC2_FIFO))
/* Start single DAC conversion */ /* Start single DAC conversion */
#define RtdDacUpdate(dev, n) \ #define RtdDacUpdate(dev, n) \
writew (0, devpriv->las0 +(((n) == 0) ? LAS0_DAC1 : LAS0_DAC2)) writew(0, devpriv->las0 + (((n) == 0) ? LAS0_DAC1 : LAS0_DAC2))
/* Start single DAC conversion on both DACs */ /* Start single DAC conversion on both DACs */
#define RtdDacBothUpdate(dev) \ #define RtdDacBothUpdate(dev) \
writew (0, devpriv->las0+LAS0_DAC) writew(0, devpriv->las0+LAS0_DAC)
/* Set DAC output type and range */ /* Set DAC output type and range */
#define RtdDacRange(dev, n, v) \ #define RtdDacRange(dev, n, v) \
writew ((v) & 7, devpriv->las0 \ writew((v) & 7, devpriv->las0 \
+(((n) == 0) ? LAS0_DAC1_CTRL : LAS0_DAC2_CTRL)) +(((n) == 0) ? LAS0_DAC1_CTRL : LAS0_DAC2_CTRL))
/* Reset DAC FIFO */ /* Reset DAC FIFO */
#define RtdDacClearFifo(dev, n) \ #define RtdDacClearFifo(dev, n) \
writel (0, devpriv->las0+(((n) == 0) ? LAS0_DAC1_RESET : LAS0_DAC2_RESET)) writel(0, devpriv->las0+(((n) == 0) ? LAS0_DAC1_RESET : LAS0_DAC2_RESET))
/* Set source for DMA 0 (write only, shadow?) */ /* Set source for DMA 0 (write only, shadow?) */
#define RtdDma0Source(dev, n) \ #define RtdDma0Source(dev, n) \
writel ((n) & 0xf, devpriv->las0+LAS0_DMA0_SRC) writel((n) & 0xf, devpriv->las0+LAS0_DMA0_SRC)
/* Set source for DMA 1 (write only, shadow?) */ /* Set source for DMA 1 (write only, shadow?) */
#define RtdDma1Source(dev, n) \ #define RtdDma1Source(dev, n) \
writel ((n) & 0xf, devpriv->las0+LAS0_DMA1_SRC) writel((n) & 0xf, devpriv->las0+LAS0_DMA1_SRC)
/* Reset board state for DMA 0 */ /* Reset board state for DMA 0 */
#define RtdDma0Reset(dev) \ #define RtdDma0Reset(dev) \
writel (0, devpriv->las0+LAS0_DMA0_RESET) writel(0, devpriv->las0+LAS0_DMA0_RESET)
/* Reset board state for DMA 1 */ /* Reset board state for DMA 1 */
#define RtdDma1Reset(dev) \ #define RtdDma1Reset(dev) \
writel (0, devpriv->las0+LAS0_DMA1_SRC) writel(0, devpriv->las0+LAS0_DMA1_SRC)
/* PLX9080 interrupt mask and status */ /* PLX9080 interrupt mask and status */
#define RtdPlxInterruptRead(dev) \ #define RtdPlxInterruptRead(dev) \
readl (devpriv->lcfg+LCFG_ITCSR) readl(devpriv->lcfg+LCFG_ITCSR)
#define RtdPlxInterruptWrite(dev, v) \ #define RtdPlxInterruptWrite(dev, v) \
writel (v, devpriv->lcfg+LCFG_ITCSR) writel(v, devpriv->lcfg+LCFG_ITCSR)
/* Set mode for DMA 0 */ /* Set mode for DMA 0 */
#define RtdDma0Mode(dev, m) \ #define RtdDma0Mode(dev, m) \
writel ((m), devpriv->lcfg+LCFG_DMAMODE0) writel((m), devpriv->lcfg+LCFG_DMAMODE0)
/* Set PCI address for DMA 0 */ /* Set PCI address for DMA 0 */
#define RtdDma0PciAddr(dev, a) \ #define RtdDma0PciAddr(dev, a) \
writel ((a), devpriv->lcfg+LCFG_DMAPADR0) writel((a), devpriv->lcfg+LCFG_DMAPADR0)
/* Set local address for DMA 0 */ /* Set local address for DMA 0 */
#define RtdDma0LocalAddr(dev, a) \ #define RtdDma0LocalAddr(dev, a) \
writel ((a), devpriv->lcfg+LCFG_DMALADR0) writel((a), devpriv->lcfg+LCFG_DMALADR0)
/* Set byte count for DMA 0 */ /* Set byte count for DMA 0 */
#define RtdDma0Count(dev, c) \ #define RtdDma0Count(dev, c) \
writel ((c), devpriv->lcfg+LCFG_DMASIZ0) writel((c), devpriv->lcfg+LCFG_DMASIZ0)
/* Set next descriptor for DMA 0 */ /* Set next descriptor for DMA 0 */
#define RtdDma0Next(dev, a) \ #define RtdDma0Next(dev, a) \
writel ((a), devpriv->lcfg+LCFG_DMADPR0) writel((a), devpriv->lcfg+LCFG_DMADPR0)
/* Set mode for DMA 1 */ /* Set mode for DMA 1 */
#define RtdDma1Mode(dev, m) \ #define RtdDma1Mode(dev, m) \
writel ((m), devpriv->lcfg+LCFG_DMAMODE1) writel((m), devpriv->lcfg+LCFG_DMAMODE1)
/* Set PCI address for DMA 1 */ /* Set PCI address for DMA 1 */
#define RtdDma1PciAddr(dev, a) \ #define RtdDma1PciAddr(dev, a) \
writel ((a), devpriv->lcfg+LCFG_DMAADR1) writel((a), devpriv->lcfg+LCFG_DMAADR1)
/* Set local address for DMA 1 */ /* Set local address for DMA 1 */
#define RtdDma1LocalAddr(dev, a) \ #define RtdDma1LocalAddr(dev, a) \
writel ((a), devpriv->lcfg+LCFG_DMALADR1) writel((a), devpriv->lcfg+LCFG_DMALADR1)
/* Set byte count for DMA 1 */ /* Set byte count for DMA 1 */
#define RtdDma1Count(dev, c) \ #define RtdDma1Count(dev, c) \
writel ((c), devpriv->lcfg+LCFG_DMASIZ1) writel((c), devpriv->lcfg+LCFG_DMASIZ1)
/* Set next descriptor for DMA 1 */ /* Set next descriptor for DMA 1 */
#define RtdDma1Next(dev, a) \ #define RtdDma1Next(dev, a) \
writel ((a), devpriv->lcfg+LCFG_DMADPR1) writel((a), devpriv->lcfg+LCFG_DMADPR1)
/* Set control for DMA 0 (write only, shadow?) */ /* Set control for DMA 0 (write only, shadow?) */
#define RtdDma0Control(dev, n) \ #define RtdDma0Control(dev, n) \
writeb (devpriv->dma0Control = (n), devpriv->lcfg+LCFG_DMACSR0) writeb(devpriv->dma0Control = (n), devpriv->lcfg+LCFG_DMACSR0)
/* Get status for DMA 0 */ /* Get status for DMA 0 */
#define RtdDma0Status(dev) \ #define RtdDma0Status(dev) \
readb (devpriv->lcfg+LCFG_DMACSR0) readb(devpriv->lcfg+LCFG_DMACSR0)
/* Set control for DMA 1 (write only, shadow?) */ /* Set control for DMA 1 (write only, shadow?) */
#define RtdDma1Control(dev, n) \ #define RtdDma1Control(dev, n) \
writeb (devpriv->dma1Control = (n), devpriv->lcfg+LCFG_DMACSR1) writeb(devpriv->dma1Control = (n), devpriv->lcfg+LCFG_DMACSR1)
/* Get status for DMA 1 */ /* Get status for DMA 1 */
#define RtdDma1Status(dev) \ #define RtdDma1Status(dev) \
readb (devpriv->lcfg+LCFG_DMACSR1) readb(devpriv->lcfg+LCFG_DMACSR1)
/* /*
* The struct comedi_driver structure tells the Comedi core module * The struct comedi_driver structure tells the Comedi core module
...@@ -760,9 +760,9 @@ static int rtd_attach(struct comedi_device *dev, struct comedi_devconfig *it) ...@@ -760,9 +760,9 @@ static int rtd_attach(struct comedi_device *dev, struct comedi_devconfig *it)
int index; int index;
#endif #endif
printk("comedi%d: rtd520 attaching.\n", dev->minor); printk(KERN_INFO "comedi%d: rtd520 attaching.\n", dev->minor);
#if defined (CONFIG_COMEDI_DEBUG) && defined (USE_DMA) #if defined(CONFIG_COMEDI_DEBUG) && defined(USE_DMA)
/* You can set this a load time: modprobe comedi comedi_debug=1 */ /* You can set this a load time: modprobe comedi comedi_debug=1 */
if (0 == comedi_debug) /* force DMA debug printks */ if (0 == comedi_debug) /* force DMA debug printks */
comedi_debug = 1; comedi_debug = 1;
...@@ -800,10 +800,10 @@ static int rtd_attach(struct comedi_device *dev, struct comedi_devconfig *it) ...@@ -800,10 +800,10 @@ static int rtd_attach(struct comedi_device *dev, struct comedi_devconfig *it)
} }
if (!pcidev) { if (!pcidev) {
if (it->options[0] && it->options[1]) { if (it->options[0] && it->options[1]) {
printk("No RTD card at bus=%d slot=%d.\n", printk(KERN_INFO "No RTD card at bus=%d slot=%d.\n",
it->options[0], it->options[1]); it->options[0], it->options[1]);
} else { } else {
printk("No RTD card found.\n"); printk(KERN_INFO "No RTD card found.\n");
} }
return -EIO; return -EIO;
} }
...@@ -812,7 +812,7 @@ static int rtd_attach(struct comedi_device *dev, struct comedi_devconfig *it) ...@@ -812,7 +812,7 @@ static int rtd_attach(struct comedi_device *dev, struct comedi_devconfig *it)
ret = comedi_pci_enable(pcidev, DRV_NAME); ret = comedi_pci_enable(pcidev, DRV_NAME);
if (ret < 0) { if (ret < 0) {
printk("Failed to enable PCI device and request regions.\n"); printk(KERN_INFO "Failed to enable PCI device and request regions.\n");
return ret; return ret;
} }
devpriv->got_regions = 1; devpriv->got_regions = 1;
...@@ -830,9 +830,9 @@ static int rtd_attach(struct comedi_device *dev, struct comedi_devconfig *it) ...@@ -830,9 +830,9 @@ static int rtd_attach(struct comedi_device *dev, struct comedi_devconfig *it)
devpriv->las1 = ioremap_nocache(physLas1, LAS1_PCISIZE); devpriv->las1 = ioremap_nocache(physLas1, LAS1_PCISIZE);
devpriv->lcfg = ioremap_nocache(physLcfg, LCFG_PCISIZE); devpriv->lcfg = ioremap_nocache(physLcfg, LCFG_PCISIZE);
if (!devpriv->las0 || !devpriv->las1 || !devpriv->lcfg) { if (!devpriv->las0 || !devpriv->las1 || !devpriv->lcfg)
return -ENOMEM; return -ENOMEM;
}
DPRINTK("%s: LAS0=%llx, LAS1=%llx, CFG=%llx.\n", dev->board_name, DPRINTK("%s: LAS0=%llx, LAS1=%llx, CFG=%llx.\n", dev->board_name,
(unsigned long long)physLas0, (unsigned long long)physLas1, (unsigned long long)physLas0, (unsigned long long)physLas1,
...@@ -849,7 +849,7 @@ static int rtd_attach(struct comedi_device *dev, struct comedi_devconfig *it) ...@@ -849,7 +849,7 @@ static int rtd_attach(struct comedi_device *dev, struct comedi_devconfig *it)
pci_read_config_byte(devpriv->pci_dev, pci_read_config_byte(devpriv->pci_dev,
PCI_LATENCY_TIMER, &pci_latency); PCI_LATENCY_TIMER, &pci_latency);
if (pci_latency < 32) { if (pci_latency < 32) {
printk("%s: PCI latency changed from %d to %d\n", printk(KERN_INFO "%s: PCI latency changed from %d to %d\n",
dev->board_name, pci_latency, 32); dev->board_name, pci_latency, 32);
pci_write_config_byte(devpriv->pci_dev, pci_write_config_byte(devpriv->pci_dev,
PCI_LATENCY_TIMER, 32); PCI_LATENCY_TIMER, 32);
...@@ -875,9 +875,9 @@ static int rtd_attach(struct comedi_device *dev, struct comedi_devconfig *it) ...@@ -875,9 +875,9 @@ static int rtd_attach(struct comedi_device *dev, struct comedi_devconfig *it)
* Allocate the subdevice structures. alloc_subdevice() is a * Allocate the subdevice structures. alloc_subdevice() is a
* convenient macro defined in comedidev.h. * convenient macro defined in comedidev.h.
*/ */
if (alloc_subdevices(dev, 4) < 0) { if (alloc_subdevices(dev, 4) < 0)
return -ENOMEM; return -ENOMEM;
}
s = dev->subdevices + 0; s = dev->subdevices + 0;
dev->read_subdev = s; dev->read_subdev = s;
...@@ -887,11 +887,11 @@ static int rtd_attach(struct comedi_device *dev, struct comedi_devconfig *it) ...@@ -887,11 +887,11 @@ static int rtd_attach(struct comedi_device *dev, struct comedi_devconfig *it)
SDF_READABLE | SDF_GROUND | SDF_COMMON | SDF_DIFF | SDF_CMD_READ; SDF_READABLE | SDF_GROUND | SDF_COMMON | SDF_DIFF | SDF_CMD_READ;
s->n_chan = thisboard->aiChans; s->n_chan = thisboard->aiChans;
s->maxdata = (1 << thisboard->aiBits) - 1; s->maxdata = (1 << thisboard->aiBits) - 1;
if (thisboard->aiMaxGain <= 32) { if (thisboard->aiMaxGain <= 32)
s->range_table = &rtd_ai_7520_range; s->range_table = &rtd_ai_7520_range;
} else { else
s->range_table = &rtd_ai_4520_range; s->range_table = &rtd_ai_4520_range;
}
s->len_chanlist = RTD_MAX_CHANLIST; /* devpriv->fifoLen */ s->len_chanlist = RTD_MAX_CHANLIST; /* devpriv->fifoLen */
s->insn_read = rtd_ai_rinsn; s->insn_read = rtd_ai_rinsn;
s->do_cmd = rtd_ai_cmd; s->do_cmd = rtd_ai_cmd;
...@@ -961,9 +961,9 @@ static int rtd_attach(struct comedi_device *dev, struct comedi_devconfig *it) ...@@ -961,9 +961,9 @@ static int rtd_attach(struct comedi_device *dev, struct comedi_devconfig *it)
printk("( irq=%u )", dev->irq); printk("( irq=%u )", dev->irq);
ret = rtd520_probe_fifo_depth(dev); ret = rtd520_probe_fifo_depth(dev);
if (ret < 0) { if (ret < 0)
return ret; return ret;
}
devpriv->fifoLen = ret; devpriv->fifoLen = ret;
printk("( fifoLen=%d )", devpriv->fifoLen); printk("( fifoLen=%d )", devpriv->fifoLen);
...@@ -1028,7 +1028,7 @@ static int rtd_attach(struct comedi_device *dev, struct comedi_devconfig *it) ...@@ -1028,7 +1028,7 @@ static int rtd_attach(struct comedi_device *dev, struct comedi_devconfig *it)
RtdDma0Mode(dev, DMA_MODE_BITS); RtdDma0Mode(dev, DMA_MODE_BITS);
RtdDma0Source(dev, DMAS_ADFIFO_HALF_FULL); /* set DMA trigger source */ RtdDma0Source(dev, DMAS_ADFIFO_HALF_FULL); /* set DMA trigger source */
} else { } else {
printk("( no IRQ->no DMA )"); printk(KERN_INFO "( no IRQ->no DMA )");
} }
#endif /* USE_DMA */ #endif /* USE_DMA */
...@@ -1071,18 +1071,18 @@ static int rtd_attach(struct comedi_device *dev, struct comedi_devconfig *it) ...@@ -1071,18 +1071,18 @@ static int rtd_attach(struct comedi_device *dev, struct comedi_devconfig *it)
} }
/* release all regions that were allocated */ /* release all regions that were allocated */
if (devpriv->las0) { if (devpriv->las0)
iounmap(devpriv->las0); iounmap(devpriv->las0);
}
if (devpriv->las1) { if (devpriv->las1)
iounmap(devpriv->las1); iounmap(devpriv->las1);
}
if (devpriv->lcfg) { if (devpriv->lcfg)
iounmap(devpriv->lcfg); iounmap(devpriv->lcfg);
}
if (devpriv->pci_dev) { if (devpriv->pci_dev)
pci_dev_put(devpriv->pci_dev); pci_dev_put(devpriv->pci_dev);
}
return ret; return ret;
#endif #endif
} }
...@@ -1158,24 +1158,24 @@ static int rtd_detach(struct comedi_device *dev) ...@@ -1158,24 +1158,24 @@ static int rtd_detach(struct comedi_device *dev)
} }
/* release all regions that were allocated */ /* release all regions that were allocated */
if (devpriv->las0) { if (devpriv->las0)
iounmap(devpriv->las0); iounmap(devpriv->las0);
}
if (devpriv->las1) { if (devpriv->las1)
iounmap(devpriv->las1); iounmap(devpriv->las1);
}
if (devpriv->lcfg) { if (devpriv->lcfg)
iounmap(devpriv->lcfg); iounmap(devpriv->lcfg);
}
if (devpriv->pci_dev) { if (devpriv->pci_dev) {
if (devpriv->got_regions) { if (devpriv->got_regions)
comedi_pci_disable(devpriv->pci_dev); comedi_pci_disable(devpriv->pci_dev);
}
pci_dev_put(devpriv->pci_dev); pci_dev_put(devpriv->pci_dev);
} }
} }
printk("comedi%d: rtd520: removed.\n", dev->minor); printk(KERN_INFO "comedi%d: rtd520: removed.\n", dev->minor);
return 0; return 0;
} }
...@@ -1275,13 +1275,13 @@ static int rtd520_probe_fifo_depth(struct comedi_device *dev) ...@@ -1275,13 +1275,13 @@ static int rtd520_probe_fifo_depth(struct comedi_device *dev)
} }
} }
if (i == limit) { if (i == limit) {
printk("\ncomedi: %s: failed to probe fifo size.\n", DRV_NAME); printk(KERN_INFO "\ncomedi: %s: failed to probe fifo size.\n", DRV_NAME);
return -EIO; return -EIO;
} }
RtdAdcClearFifo(dev); RtdAdcClearFifo(dev);
if (fifo_size != 0x400 && fifo_size != 0x2000) { if (fifo_size != 0x400 && fifo_size != 0x2000) {
printk printk
("\ncomedi: %s: unexpected fifo size of %i, expected 1024 or 8192.\n", (KERN_INFO "\ncomedi: %s: unexpected fifo size of %i, expected 1024 or 8192.\n",
DRV_NAME, fifo_size); DRV_NAME, fifo_size);
return -EIO; return -EIO;
} }
...@@ -1335,12 +1335,11 @@ static int rtd_ai_rinsn(struct comedi_device *dev, ...@@ -1335,12 +1335,11 @@ static int rtd_ai_rinsn(struct comedi_device *dev,
d = RtdAdcFifoGet(dev); /* get 2s comp value */ d = RtdAdcFifoGet(dev); /* get 2s comp value */
/*printk ("rtd520: Got 0x%x after %d usec\n", d, ii+1); */ /*printk ("rtd520: Got 0x%x after %d usec\n", d, ii+1); */
d = d >> 3; /* low 3 bits are marker lines */ d = d >> 3; /* low 3 bits are marker lines */
if (CHAN_ARRAY_TEST(devpriv->chanBipolar, 0)) { if (CHAN_ARRAY_TEST(devpriv->chanBipolar, 0))
data[n] = d + 2048; /* convert to comedi unsigned data */ data[n] = d + 2048; /* convert to comedi unsigned data */
} else { else
data[n] = d; data[n] = d;
} }
}
/* return the number of samples read/written */ /* return the number of samples read/written */
return n; return n;
...@@ -1375,11 +1374,11 @@ static int ai_read_n(struct comedi_device *dev, struct comedi_subdevice *s, ...@@ -1375,11 +1374,11 @@ static int ai_read_n(struct comedi_device *dev, struct comedi_subdevice *s,
d = RtdAdcFifoGet(dev); /* get 2s comp value */ d = RtdAdcFifoGet(dev); /* get 2s comp value */
d = d >> 3; /* low 3 bits are marker lines */ d = d >> 3; /* low 3 bits are marker lines */
if (CHAN_ARRAY_TEST(devpriv->chanBipolar, s->async->cur_chan)) { if (CHAN_ARRAY_TEST(devpriv->chanBipolar, s->async->cur_chan))
sample = d + 2048; /* convert to comedi unsigned data */ sample = d + 2048; /* convert to comedi unsigned data */
} else { else
sample = d; sample = d;
}
if (!comedi_buf_put(s->async, sample)) if (!comedi_buf_put(s->async, sample))
return -1; return -1;
...@@ -1403,11 +1402,11 @@ static int ai_read_dregs(struct comedi_device *dev, struct comedi_subdevice *s) ...@@ -1403,11 +1402,11 @@ static int ai_read_dregs(struct comedi_device *dev, struct comedi_subdevice *s)
} }
d = d >> 3; /* low 3 bits are marker lines */ d = d >> 3; /* low 3 bits are marker lines */
if (CHAN_ARRAY_TEST(devpriv->chanBipolar, s->async->cur_chan)) { if (CHAN_ARRAY_TEST(devpriv->chanBipolar, s->async->cur_chan))
sample = d + 2048; /* convert to comedi unsigned data */ sample = d + 2048; /* convert to comedi unsigned data */
} else { else
sample = d; sample = d;
}
if (!comedi_buf_put(s->async, sample)) if (!comedi_buf_put(s->async, sample))
return -1; return -1;
...@@ -1493,9 +1492,9 @@ static int ai_process_dma(struct comedi_device *dev, struct comedi_subdevice *s) ...@@ -1493,9 +1492,9 @@ static int ai_process_dma(struct comedi_device *dev, struct comedi_subdevice *s)
if (CHAN_ARRAY_TEST(devpriv->chanBipolar, s->async->cur_chan)) { if (CHAN_ARRAY_TEST(devpriv->chanBipolar, s->async->cur_chan)) {
sample = (*dp >> 3) + 2048; /* convert to comedi unsigned data */ sample = (*dp >> 3) + 2048; /* convert to comedi unsigned data */
} else { else
sample = *dp >> 3; /* low 3 bits are marker lines */ sample = *dp >> 3; /* low 3 bits are marker lines */
}
*dp++ = sample; /* put processed value back */ *dp++ = sample; /* put processed value back */
if (++s->async->cur_chan >= s->async->cmd.chanlist_len) if (++s->async->cur_chan >= s->async->cmd.chanlist_len)
...@@ -1546,9 +1545,8 @@ static irqreturn_t rtd_interrupt(int irq, /* interrupt number (ignored) */ ...@@ -1546,9 +1545,8 @@ static irqreturn_t rtd_interrupt(int irq, /* interrupt number (ignored) */
u16 fifoStatus; u16 fifoStatus;
struct comedi_subdevice *s = dev->subdevices + 0; /* analog in subdevice */ struct comedi_subdevice *s = dev->subdevices + 0; /* analog in subdevice */
if (!dev->attached) { if (!dev->attached)
return IRQ_NONE; return IRQ_NONE;
}
devpriv->intCount++; /* DEBUG statistics */ devpriv->intCount++; /* DEBUG statistics */
...@@ -1594,9 +1592,8 @@ static irqreturn_t rtd_interrupt(int irq, /* interrupt number (ignored) */ ...@@ -1594,9 +1592,8 @@ static irqreturn_t rtd_interrupt(int irq, /* interrupt number (ignored) */
status = RtdInterruptStatus(dev); status = RtdInterruptStatus(dev);
/* if interrupt was not caused by our board, or handled above */ /* if interrupt was not caused by our board, or handled above */
if (0 == status) { if (0 == status)
return IRQ_HANDLED; return IRQ_HANDLED;
}
if (status & IRQM_ADC_ABOUT_CNT) { /* sample count -> read FIFO */ if (status & IRQM_ADC_ABOUT_CNT) { /* sample count -> read FIFO */
/* since the priority interrupt controller may have queued a sample /* since the priority interrupt controller may have queued a sample
...@@ -1734,33 +1731,32 @@ static int rtd_ai_cmdtest(struct comedi_device *dev, ...@@ -1734,33 +1731,32 @@ static int rtd_ai_cmdtest(struct comedi_device *dev,
tmp = cmd->start_src; tmp = cmd->start_src;
cmd->start_src &= TRIG_NOW; cmd->start_src &= TRIG_NOW;
if (!cmd->start_src || tmp != cmd->start_src) { if (!cmd->start_src || tmp != cmd->start_src)
err++; err++;
}
tmp = cmd->scan_begin_src; tmp = cmd->scan_begin_src;
cmd->scan_begin_src &= TRIG_TIMER | TRIG_EXT; cmd->scan_begin_src &= TRIG_TIMER | TRIG_EXT;
if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src) { if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src)
err++; err++;
}
tmp = cmd->convert_src; tmp = cmd->convert_src;
cmd->convert_src &= TRIG_TIMER | TRIG_EXT; cmd->convert_src &= TRIG_TIMER | TRIG_EXT;
if (!cmd->convert_src || tmp != cmd->convert_src) { if (!cmd->convert_src || tmp != cmd->convert_src)
err++; err++;
}
tmp = cmd->scan_end_src; tmp = cmd->scan_end_src;
cmd->scan_end_src &= TRIG_COUNT; cmd->scan_end_src &= TRIG_COUNT;
if (!cmd->scan_end_src || tmp != cmd->scan_end_src) { if (!cmd->scan_end_src || tmp != cmd->scan_end_src)
err++; err++;
}
tmp = cmd->stop_src; tmp = cmd->stop_src;
cmd->stop_src &= TRIG_COUNT | TRIG_NONE; cmd->stop_src &= TRIG_COUNT | TRIG_NONE;
if (!cmd->stop_src || tmp != cmd->stop_src) { if (!cmd->stop_src || tmp != cmd->stop_src)
err++; err++;
}
if (err) if (err)
return 1; return 1;
...@@ -1772,16 +1768,14 @@ static int rtd_ai_cmdtest(struct comedi_device *dev, ...@@ -1772,16 +1768,14 @@ static int rtd_ai_cmdtest(struct comedi_device *dev,
cmd->scan_begin_src != TRIG_EXT) { cmd->scan_begin_src != TRIG_EXT) {
err++; err++;
} }
if (cmd->convert_src != TRIG_TIMER && cmd->convert_src != TRIG_EXT) { if (cmd->convert_src != TRIG_TIMER && cmd->convert_src != TRIG_EXT)
err++; err++;
}
if (cmd->stop_src != TRIG_COUNT && cmd->stop_src != TRIG_NONE) { if (cmd->stop_src != TRIG_COUNT && cmd->stop_src != TRIG_NONE)
err++; err++;
}
if (err) { if (err)
return 2; return 2;
}
/* step 3: make sure arguments are trivially compatible */ /* step 3: make sure arguments are trivially compatible */
...@@ -1882,9 +1876,9 @@ static int rtd_ai_cmdtest(struct comedi_device *dev, ...@@ -1882,9 +1876,9 @@ static int rtd_ai_cmdtest(struct comedi_device *dev,
} }
} }
if (err) { if (err)
return 3; return 3;
}
/* step 4: fix up any arguments */ /* step 4: fix up any arguments */
...@@ -1896,17 +1890,17 @@ static int rtd_ai_cmdtest(struct comedi_device *dev, ...@@ -1896,17 +1890,17 @@ static int rtd_ai_cmdtest(struct comedi_device *dev,
tmp = cmd->scan_begin_arg; tmp = cmd->scan_begin_arg;
rtd_ns_to_timer(&cmd->scan_begin_arg, rtd_ns_to_timer(&cmd->scan_begin_arg,
cmd->flags & TRIG_ROUND_MASK); cmd->flags & TRIG_ROUND_MASK);
if (tmp != cmd->scan_begin_arg) { if (tmp != cmd->scan_begin_arg)
err++; err++;
}
} }
if (cmd->convert_src == TRIG_TIMER) { if (cmd->convert_src == TRIG_TIMER) {
tmp = cmd->convert_arg; tmp = cmd->convert_arg;
rtd_ns_to_timer(&cmd->convert_arg, rtd_ns_to_timer(&cmd->convert_arg,
cmd->flags & TRIG_ROUND_MASK); cmd->flags & TRIG_ROUND_MASK);
if (tmp != cmd->convert_arg) { if (tmp != cmd->convert_arg)
err++; err++;
}
if (cmd->scan_begin_src == TRIG_TIMER if (cmd->scan_begin_src == TRIG_TIMER
&& (cmd->scan_begin_arg && (cmd->scan_begin_arg
< (cmd->convert_arg * cmd->scan_end_arg))) { < (cmd->convert_arg * cmd->scan_end_arg))) {
...@@ -1916,9 +1910,8 @@ static int rtd_ai_cmdtest(struct comedi_device *dev, ...@@ -1916,9 +1910,8 @@ static int rtd_ai_cmdtest(struct comedi_device *dev,
} }
} }
if (err) { if (err)
return 4; return 4;
}
return 0; return 0;
} }
...@@ -2221,7 +2214,7 @@ static int rtd_ao_winsn(struct comedi_device *dev, ...@@ -2221,7 +2214,7 @@ static int rtd_ao_winsn(struct comedi_device *dev,
/* VERIFY: comedi range and offset conversions */ /* VERIFY: comedi range and offset conversions */
if ((range > 1) /* bipolar */ if ((range > 1) /* bipolar */
&&(data[i] < 2048)) { && (data[i] < 2048)) {
/* offset and sign extend */ /* offset and sign extend */
val = (((int)data[i]) - 2048) << 3; val = (((int)data[i]) - 2048) << 3;
} else { /* unipolor */ } else { /* unipolor */
...@@ -2267,9 +2260,9 @@ static int rtd_ao_rinsn(struct comedi_device *dev, ...@@ -2267,9 +2260,9 @@ static int rtd_ao_rinsn(struct comedi_device *dev,
int i; int i;
int chan = CR_CHAN(insn->chanspec); int chan = CR_CHAN(insn->chanspec);
for (i = 0; i < insn->n; i++) { for (i = 0; i < insn->n; i++)
data[i] = devpriv->aoValue[chan]; data[i] = devpriv->aoValue[chan];
}
return i; return i;
} }
......
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