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Commit bc8e81a5 authored by Linus Walleij's avatar Linus Walleij
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Merge tag 'renesas-pinctrl-for-v5.19-tag1' of... 

Merge tag 'renesas-pinctrl-for-v5.19-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel

pinctrl: renesas: Updates for v5.19

  - Add support for the new RZ/G2UL SoC,
  - Add drive-strength support for R-Car E3,
  - Add RPC/QSPI pin groups on R-Car E3 and E3,
  - Miscellaneous fixes and improvements.
parents a6a5c173 f7bc5f52
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Showing with 362 additions and 153 deletions
Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
View file @ bc8e81a5
...@@ -11,8 +11,8 @@ maintainers: ...@@ -11,8 +11,8 @@ maintainers:
- Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
description: description:
The Renesas SoCs of the RZ/{G2L,V2L} series feature a combined Pin and GPIO The Renesas SoCs of the RZ/{G2L,V2L} alike series feature a combined Pin and
controller. GPIO controller.
Pin multiplexing and GPIO configuration is performed on a per-pin basis. Pin multiplexing and GPIO configuration is performed on a per-pin basis.
Each port features up to 8 pins, each of them configurable for GPIO function Each port features up to 8 pins, each of them configurable for GPIO function
(port mode) or in alternate function mode. (port mode) or in alternate function mode.
...@@ -23,6 +23,7 @@ properties: ...@@ -23,6 +23,7 @@ properties:
oneOf: oneOf:
- items: - items:
- enum: - enum:
- renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2}
- renesas,r9a07g044-pinctrl # RZ/G2{L,LC} - renesas,r9a07g044-pinctrl # RZ/G2{L,LC}
- items: - items:
......
drivers/pinctrl/renesas/Kconfig
View file @ bc8e81a5
...@@ -38,8 +38,7 @@ config PINCTRL_RENESAS ...@@ -38,8 +38,7 @@ config PINCTRL_RENESAS
select PINCTRL_PFC_R8A77995 if ARCH_R8A77995 select PINCTRL_PFC_R8A77995 if ARCH_R8A77995
select PINCTRL_PFC_R8A779A0 if ARCH_R8A779A0 select PINCTRL_PFC_R8A779A0 if ARCH_R8A779A0
select PINCTRL_PFC_R8A779F0 if ARCH_R8A779F0 select PINCTRL_PFC_R8A779F0 if ARCH_R8A779F0
select PINCTRL_RZG2L if ARCH_R9A07G044 select PINCTRL_RZG2L if ARCH_RZG2L
select PINCTRL_RZG2L if ARCH_R9A07G054
select PINCTRL_PFC_SH7203 if CPU_SUBTYPE_SH7203 select PINCTRL_PFC_SH7203 if CPU_SUBTYPE_SH7203
select PINCTRL_PFC_SH7264 if CPU_SUBTYPE_SH7264 select PINCTRL_PFC_SH7264 if CPU_SUBTYPE_SH7264
select PINCTRL_PFC_SH7269 if CPU_SUBTYPE_SH7269 select PINCTRL_PFC_SH7269 if CPU_SUBTYPE_SH7269
...@@ -184,14 +183,14 @@ config PINCTRL_RZA2 ...@@ -184,14 +183,14 @@ config PINCTRL_RZA2
This selects GPIO and pinctrl driver for Renesas RZ/A2 platforms. This selects GPIO and pinctrl driver for Renesas RZ/A2 platforms.
config PINCTRL_RZG2L config PINCTRL_RZG2L
bool "pin control support for RZ/{G2L,V2L}" if COMPILE_TEST bool "pin control support for RZ/{G2L,G2UL,V2L}" if COMPILE_TEST
depends on OF depends on OF
select GPIOLIB select GPIOLIB
select GENERIC_PINCTRL_GROUPS select GENERIC_PINCTRL_GROUPS
select GENERIC_PINMUX_FUNCTIONS select GENERIC_PINMUX_FUNCTIONS
select GENERIC_PINCONF select GENERIC_PINCONF
help help
This selects GPIO and pinctrl driver for Renesas RZ/{G2L,V2L} This selects GPIO and pinctrl driver for Renesas RZ/{G2L,G2UL,V2L}
platforms. platforms.
config PINCTRL_PFC_R8A77470 config PINCTRL_PFC_R8A77470
......
drivers/pinctrl/renesas/core.c
View file @ bc8e81a5
...@@ -1007,7 +1007,18 @@ static void __init sh_pfc_compare_groups(const char *drvname, ...@@ -1007,7 +1007,18 @@ static void __init sh_pfc_compare_groups(const char *drvname,
static void __init sh_pfc_check_info(const struct sh_pfc_soc_info *info) static void __init sh_pfc_check_info(const struct sh_pfc_soc_info *info)
{ {
const struct pinmux_drive_reg *drive_regs = info->drive_regs; const struct pinmux_drive_reg *drive_regs = info->drive_regs;
#define drive_nfields ARRAY_SIZE(drive_regs->fields)
#define drive_ofs(i) drive_regs[(i) / drive_nfields]
#define drive_reg(i) drive_ofs(i).reg
#define drive_bit(i) ((i) % drive_nfields)
#define drive_field(i) drive_ofs(i).fields[drive_bit(i)]
const struct pinmux_bias_reg *bias_regs = info->bias_regs; const struct pinmux_bias_reg *bias_regs = info->bias_regs;
#define bias_npins ARRAY_SIZE(bias_regs->pins)
#define bias_ofs(i) bias_regs[(i) / bias_npins]
#define bias_puen(i) bias_ofs(i).puen
#define bias_pud(i) bias_ofs(i).pud
#define bias_bit(i) ((i) % bias_npins)
#define bias_pin(i) bias_ofs(i).pins[bias_bit(i)]
const char *drvname = info->name; const char *drvname = info->name;
unsigned int *refcnts; unsigned int *refcnts;
unsigned int i, j, k; unsigned int i, j, k;
...@@ -1076,17 +1087,17 @@ static void __init sh_pfc_check_info(const struct sh_pfc_soc_info *info) ...@@ -1076,17 +1087,17 @@ static void __init sh_pfc_check_info(const struct sh_pfc_soc_info *info)
if (!drive_regs) { if (!drive_regs) {
sh_pfc_err_once(drive, "SH_PFC_PIN_CFG_DRIVE_STRENGTH flag set but drive_regs missing\n"); sh_pfc_err_once(drive, "SH_PFC_PIN_CFG_DRIVE_STRENGTH flag set but drive_regs missing\n");
} else { } else {
for (j = 0; drive_regs[j / 8].reg; j++) { for (j = 0; drive_reg(j); j++) {
if (!drive_regs[j / 8].fields[j % 8].pin && if (!drive_field(j).pin &&
!drive_regs[j / 8].fields[j % 8].offset && !drive_field(j).offset &&
!drive_regs[j / 8].fields[j % 8].size) !drive_field(j).size)
continue; continue;
if (drive_regs[j / 8].fields[j % 8].pin == pin->pin) if (drive_field(j).pin == pin->pin)
break; break;
} }
if (!drive_regs[j / 8].reg) if (!drive_reg(j))
sh_pfc_err("pin %s: SH_PFC_PIN_CFG_DRIVE_STRENGTH flag set but not in drive_regs\n", sh_pfc_err("pin %s: SH_PFC_PIN_CFG_DRIVE_STRENGTH flag set but not in drive_regs\n",
pin->name); pin->name);
} }
...@@ -1164,20 +1175,17 @@ static void __init sh_pfc_check_info(const struct sh_pfc_soc_info *info) ...@@ -1164,20 +1175,17 @@ static void __init sh_pfc_check_info(const struct sh_pfc_soc_info *info)
for (i = 0; drive_regs && drive_regs[i].reg; i++) for (i = 0; drive_regs && drive_regs[i].reg; i++)
sh_pfc_check_drive_reg(info, &drive_regs[i]); sh_pfc_check_drive_reg(info, &drive_regs[i]);
for (i = 0; drive_regs && drive_regs[i / 8].reg; i++) { for (i = 0; drive_regs && drive_reg(i); i++) {
if (!drive_regs[i / 8].fields[i % 8].pin && if (!drive_field(i).pin && !drive_field(i).offset &&
!drive_regs[i / 8].fields[i % 8].offset && !drive_field(i).size)
!drive_regs[i / 8].fields[i % 8].size)
continue; continue;
for (j = 0; j < i; j++) { for (j = 0; j < i; j++) {
if (drive_regs[i / 8].fields[i % 8].pin == if (drive_field(i).pin == drive_field(j).pin &&
drive_regs[j / 8].fields[j % 8].pin && drive_field(j).offset && drive_field(j).size) {
drive_regs[j / 8].fields[j % 8].offset && sh_pfc_err("drive_reg 0x%x:%zu/0x%x:%zu: pin conflict\n",
drive_regs[j / 8].fields[j % 8].size) { drive_reg(i), drive_bit(i),
sh_pfc_err("drive_reg 0x%x:%u/0x%x:%u: pin conflict\n", drive_reg(j), drive_bit(j));
drive_regs[i / 8].reg, i % 8,
drive_regs[j / 8].reg, j % 8);
} }
} }
} }
...@@ -1186,26 +1194,23 @@ static void __init sh_pfc_check_info(const struct sh_pfc_soc_info *info) ...@@ -1186,26 +1194,23 @@ static void __init sh_pfc_check_info(const struct sh_pfc_soc_info *info)
for (i = 0; bias_regs && (bias_regs[i].puen || bias_regs[i].pud); i++) for (i = 0; bias_regs && (bias_regs[i].puen || bias_regs[i].pud); i++)
sh_pfc_check_bias_reg(info, &bias_regs[i]); sh_pfc_check_bias_reg(info, &bias_regs[i]);
for (i = 0; bias_regs && for (i = 0; bias_regs && (bias_puen(i) || bias_pud(i)); i++) {
(bias_regs[i / 32].puen || bias_regs[i / 32].pud); i++) { if (bias_pin(i) == SH_PFC_PIN_NONE)
if (bias_regs[i / 32].pins[i % 32] == SH_PFC_PIN_NONE)
continue; continue;
for (j = 0; j < i; j++) { for (j = 0; j < i; j++) {
if (bias_regs[i / 32].pins[i % 32] != if (bias_pin(i) != bias_pin(j))
bias_regs[j / 32].pins[j % 32])
continue; continue;
if (bias_regs[i / 32].puen && bias_regs[j / 32].puen) if (bias_puen(i) && bias_puen(j))
sh_pfc_err("bias_reg 0x%x:%u/0x%x:%u: pin conflict\n", sh_pfc_err("bias_reg 0x%x:%zu/0x%x:%zu: pin conflict\n",
bias_regs[i / 32].puen, i % 32, bias_puen(i), bias_bit(i),
bias_regs[j / 32].puen, j % 32); bias_puen(j), bias_bit(j));
if (bias_regs[i / 32].pud && bias_regs[j / 32].pud) if (bias_pud(i) && bias_pud(j))
sh_pfc_err("bias_reg 0x%x:%u/0x%x:%u: pin conflict\n", sh_pfc_err("bias_reg 0x%x:%zu/0x%x:%zu: pin conflict\n",
bias_regs[i / 32].pud, i % 32, bias_pud(i), bias_bit(i),
bias_regs[j / 32].pud, j % 32); bias_pud(j), bias_bit(j));
} }
} }
/* Check ioctrl registers */ /* Check ioctrl registers */
......
drivers/pinctrl/renesas/gpio.c
View file @ bc8e81a5
...@@ -8,7 +8,6 @@ ...@@ -8,7 +8,6 @@
#include <linux/device.h> #include <linux/device.h>
#include <linux/gpio/driver.h> #include <linux/gpio/driver.h>
#include <linux/init.h>
#include <linux/module.h> #include <linux/module.h>
#include <linux/pinctrl/consumer.h> #include <linux/pinctrl/consumer.h>
#include <linux/slab.h> #include <linux/slab.h>
......
drivers/pinctrl/renesas/pfc-emev2.c
View file @ bc8e81a5
...@@ -4,7 +4,6 @@ ...@@ -4,7 +4,6 @@
* *
* Copyright (C) 2015 Niklas Söderlund * Copyright (C) 2015 Niklas Söderlund
*/ */
#include <linux/init.h>
#include <linux/kernel.h> #include <linux/kernel.h>
#include "sh_pfc.h" #include "sh_pfc.h"
......
drivers/pinctrl/renesas/pfc-r8a77990.c
View file @ bc8e81a5
...@@ -22,12 +22,12 @@ ...@@ -22,12 +22,12 @@
PORT_GP_CFG_18(0, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_18(0, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_23(1, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_23(1, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_26(2, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_26(2, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \ PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_11(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \ PORT_GP_CFG_11(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
PORT_GP_CFG_20(5, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_20(5, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_9(6, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_9(6, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(6, 9, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ PORT_GP_CFG_1(6, 9, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
...@@ -2827,16 +2827,6 @@ static const unsigned int qspi0_ctrl_pins[] = { ...@@ -2827,16 +2827,6 @@ static const unsigned int qspi0_ctrl_pins[] = {
static const unsigned int qspi0_ctrl_mux[] = { static const unsigned int qspi0_ctrl_mux[] = {
QSPI0_SPCLK_MARK, QSPI0_SSL_MARK, QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
}; };
static const unsigned int qspi0_data_pins[] = {
/* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
/* QSPI0_IO2, QSPI0_IO3 */
RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
};
static const unsigned int qspi0_data_mux[] = {
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
QSPI0_IO2_MARK, QSPI0_IO3_MARK,
};
/* - QSPI1 ------------------------------------------------------------------ */ /* - QSPI1 ------------------------------------------------------------------ */
static const unsigned int qspi1_ctrl_pins[] = { static const unsigned int qspi1_ctrl_pins[] = {
/* QSPI1_SPCLK, QSPI1_SSL */ /* QSPI1_SPCLK, QSPI1_SSL */
...@@ -2845,16 +2835,51 @@ static const unsigned int qspi1_ctrl_pins[] = { ...@@ -2845,16 +2835,51 @@ static const unsigned int qspi1_ctrl_pins[] = {
static const unsigned int qspi1_ctrl_mux[] = { static const unsigned int qspi1_ctrl_mux[] = {
QSPI1_SPCLK_MARK, QSPI1_SSL_MARK, QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
}; };
static const unsigned int qspi1_data_pins[] = {
/* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */ /* - RPC -------------------------------------------------------------------- */
static const unsigned int rpc_clk_pins[] = {
/* Octal-SPI flash: C/SCLK */
/* HyperFlash: CK, CK# */
RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 6),
};
static const unsigned int rpc_clk_mux[] = {
QSPI0_SPCLK_MARK, QSPI1_SPCLK_MARK,
};
static const unsigned int rpc_ctrl_pins[] = {
/* Octal-SPI flash: S#/CS, DQS */
/* HyperFlash: CS#, RDS */
RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 11),
};
static const unsigned int rpc_ctrl_mux[] = {
QSPI0_SSL_MARK, QSPI1_SSL_MARK,
};
static const unsigned int rpc_data_pins[] = {
/* DQ[0:7] */
RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
/* QSPI1_IO2, QSPI1_IO3 */
RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
}; };
static const unsigned int qspi1_data_mux[] = { static const unsigned int rpc_data_mux[] = {
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
QSPI0_IO2_MARK, QSPI0_IO3_MARK,
QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
QSPI1_IO2_MARK, QSPI1_IO3_MARK, QSPI1_IO2_MARK, QSPI1_IO3_MARK,
}; };
static const unsigned int rpc_reset_pins[] = {
/* RPC_RESET# */
RCAR_GP_PIN(2, 13),
};
static const unsigned int rpc_reset_mux[] = {
RPC_RESET_N_MARK,
};
static const unsigned int rpc_int_pins[] = {
/* RPC_INT# */
RCAR_GP_PIN(2, 12),
};
static const unsigned int rpc_int_mux[] = {
RPC_INT_N_MARK,
};
/* - SCIF0 ------------------------------------------------------------------ */ /* - SCIF0 ------------------------------------------------------------------ */
static const unsigned int scif0_data_a_pins[] = { static const unsigned int scif0_data_a_pins[] = {
...@@ -3758,7 +3783,7 @@ static const unsigned int vin5_clk_b_mux[] = { ...@@ -3758,7 +3783,7 @@ static const unsigned int vin5_clk_b_mux[] = {
}; };
static const struct { static const struct {
struct sh_pfc_pin_group common[255]; struct sh_pfc_pin_group common[261];
#ifdef CONFIG_PINCTRL_PFC_R8A77990 #ifdef CONFIG_PINCTRL_PFC_R8A77990
struct sh_pfc_pin_group automotive[22]; struct sh_pfc_pin_group automotive[22];
#endif #endif
...@@ -3907,11 +3932,17 @@ static const struct { ...@@ -3907,11 +3932,17 @@ static const struct {
SH_PFC_PIN_GROUP(pwm6_a), SH_PFC_PIN_GROUP(pwm6_a),
SH_PFC_PIN_GROUP(pwm6_b), SH_PFC_PIN_GROUP(pwm6_b),
SH_PFC_PIN_GROUP(qspi0_ctrl), SH_PFC_PIN_GROUP(qspi0_ctrl),
BUS_DATA_PIN_GROUP(qspi0_data, 2), SH_PFC_PIN_GROUP_SUBSET(qspi0_data2, rpc_data, 0, 2),
BUS_DATA_PIN_GROUP(qspi0_data, 4), SH_PFC_PIN_GROUP_SUBSET(qspi0_data4, rpc_data, 0, 4),
SH_PFC_PIN_GROUP(qspi1_ctrl), SH_PFC_PIN_GROUP(qspi1_ctrl),
BUS_DATA_PIN_GROUP(qspi1_data, 2), SH_PFC_PIN_GROUP_SUBSET(qspi1_data2, rpc_data, 4, 2),
BUS_DATA_PIN_GROUP(qspi1_data, 4), SH_PFC_PIN_GROUP_SUBSET(qspi1_data4, rpc_data, 4, 4),
BUS_DATA_PIN_GROUP(rpc_clk, 1),
BUS_DATA_PIN_GROUP(rpc_clk, 2),
SH_PFC_PIN_GROUP(rpc_ctrl),
SH_PFC_PIN_GROUP(rpc_data),
SH_PFC_PIN_GROUP(rpc_reset),
SH_PFC_PIN_GROUP(rpc_int),
SH_PFC_PIN_GROUP(scif0_data_a), SH_PFC_PIN_GROUP(scif0_data_a),
SH_PFC_PIN_GROUP(scif0_clk_a), SH_PFC_PIN_GROUP(scif0_clk_a),
SH_PFC_PIN_GROUP(scif0_ctrl_a), SH_PFC_PIN_GROUP(scif0_ctrl_a),
...@@ -4336,6 +4367,15 @@ static const char * const qspi1_groups[] = { ...@@ -4336,6 +4367,15 @@ static const char * const qspi1_groups[] = {
"qspi1_data4", "qspi1_data4",
}; };
static const char * const rpc_groups[] = {
"rpc_clk1",
"rpc_clk2",
"rpc_ctrl",
"rpc_data",
"rpc_reset",
"rpc_int",
};
static const char * const scif0_groups[] = { static const char * const scif0_groups[] = {
"scif0_data_a", "scif0_data_a",
"scif0_clk_a", "scif0_clk_a",
...@@ -4492,7 +4532,7 @@ static const char * const vin5_groups[] = { ...@@ -4492,7 +4532,7 @@ static const char * const vin5_groups[] = {
}; };
static const struct { static const struct {
struct sh_pfc_function common[49]; struct sh_pfc_function common[50];
#ifdef CONFIG_PINCTRL_PFC_R8A77990 #ifdef CONFIG_PINCTRL_PFC_R8A77990
struct sh_pfc_function automotive[5]; struct sh_pfc_function automotive[5];
#endif #endif
...@@ -4531,6 +4571,7 @@ static const struct { ...@@ -4531,6 +4571,7 @@ static const struct {
SH_PFC_FUNCTION(pwm6), SH_PFC_FUNCTION(pwm6),
SH_PFC_FUNCTION(qspi0), SH_PFC_FUNCTION(qspi0),
SH_PFC_FUNCTION(qspi1), SH_PFC_FUNCTION(qspi1),
SH_PFC_FUNCTION(rpc),
SH_PFC_FUNCTION(scif0), SH_PFC_FUNCTION(scif0),
SH_PFC_FUNCTION(scif1), SH_PFC_FUNCTION(scif1),
SH_PFC_FUNCTION(scif2), SH_PFC_FUNCTION(scif2),
...@@ -5030,6 +5071,39 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { ...@@ -5030,6 +5071,39 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
{ }, { },
}; };
static const struct pinmux_drive_reg pinmux_drive_regs[] = {
{ PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
{ RCAR_GP_PIN(3, 0), 18, 2 }, /* SD0_CLK */
{ RCAR_GP_PIN(3, 1), 15, 2 }, /* SD0_CMD */
{ RCAR_GP_PIN(3, 2), 12, 2 }, /* SD0_DAT0 */
{ RCAR_GP_PIN(3, 3), 9, 2 }, /* SD0_DAT1 */
{ RCAR_GP_PIN(3, 4), 6, 2 }, /* SD0_DAT2 */
{ RCAR_GP_PIN(3, 5), 3, 2 }, /* SD0_DAT3 */
{ RCAR_GP_PIN(3, 6), 0, 2 }, /* SD1_CLK */
} },
{ PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
{ RCAR_GP_PIN(3, 7), 29, 2 }, /* SD1_CMD */
{ RCAR_GP_PIN(3, 8), 26, 2 }, /* SD1_DAT0 */
{ RCAR_GP_PIN(3, 9), 23, 2 }, /* SD1_DAT1 */
{ RCAR_GP_PIN(3, 10), 20, 2 }, /* SD1_DAT2 */
{ RCAR_GP_PIN(3, 11), 17, 2 }, /* SD1_DAT3 */
{ RCAR_GP_PIN(4, 0), 14, 2 }, /* SD3_CLK */
{ RCAR_GP_PIN(4, 1), 11, 2 }, /* SD3_CMD */
{ RCAR_GP_PIN(4, 2), 8, 2 }, /* SD3_DAT0 */
{ RCAR_GP_PIN(4, 3), 5, 2 }, /* SD3_DAT1 */
{ RCAR_GP_PIN(4, 4), 2, 2 }, /* SD3_DAT2 */
} },
{ PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
{ RCAR_GP_PIN(4, 5), 29, 2 }, /* SD3_DAT3 */
{ RCAR_GP_PIN(4, 6), 26, 2 }, /* SD3_DAT4 */
{ RCAR_GP_PIN(4, 7), 23, 2 }, /* SD3_DAT5 */
{ RCAR_GP_PIN(4, 8), 20, 2 }, /* SD3_DAT6 */
{ RCAR_GP_PIN(4, 9), 17, 2 }, /* SD3_DAT7 */
{ RCAR_GP_PIN(4, 10), 14, 2 }, /* SD3_DS */
} },
{ },
};
enum ioctrl_regs { enum ioctrl_regs {
POCCTRL0, POCCTRL0,
TDSELCTRL, TDSELCTRL,
...@@ -5286,6 +5360,7 @@ const struct sh_pfc_soc_info r8a774c0_pinmux_info = { ...@@ -5286,6 +5360,7 @@ const struct sh_pfc_soc_info r8a774c0_pinmux_info = {
.nr_functions = ARRAY_SIZE(pinmux_functions.common), .nr_functions = ARRAY_SIZE(pinmux_functions.common),
.cfg_regs = pinmux_config_regs, .cfg_regs = pinmux_config_regs,
.drive_regs = pinmux_drive_regs,
.bias_regs = pinmux_bias_regs, .bias_regs = pinmux_bias_regs,
.ioctrl_regs = pinmux_ioctrl_regs, .ioctrl_regs = pinmux_ioctrl_regs,
...@@ -5312,6 +5387,7 @@ const struct sh_pfc_soc_info r8a77990_pinmux_info = { ...@@ -5312,6 +5387,7 @@ const struct sh_pfc_soc_info r8a77990_pinmux_info = {
ARRAY_SIZE(pinmux_functions.automotive), ARRAY_SIZE(pinmux_functions.automotive),
.cfg_regs = pinmux_config_regs, .cfg_regs = pinmux_config_regs,
.drive_regs = pinmux_drive_regs,
.bias_regs = pinmux_bias_regs, .bias_regs = pinmux_bias_regs,
.ioctrl_regs = pinmux_ioctrl_regs, .ioctrl_regs = pinmux_ioctrl_regs,
......
drivers/pinctrl/renesas/pfc-r8a77995.c
View file @ bc8e81a5
...@@ -1682,6 +1682,68 @@ static const unsigned int pwm3_c_mux[] = { ...@@ -1682,6 +1682,68 @@ static const unsigned int pwm3_c_mux[] = {
PWM3_C_MARK, PWM3_C_MARK,
}; };
/* - QSPI0 ------------------------------------------------------------------ */
static const unsigned int qspi0_ctrl_pins[] = {
/* QSPI0_SPCLK, QSPI0_SSL */
RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 5),
};
static const unsigned int qspi0_ctrl_mux[] = {
QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
};
/* - QSPI1 ------------------------------------------------------------------ */
static const unsigned int qspi1_ctrl_pins[] = {
/* QSPI1_SPCLK, QSPI1_SSL */
RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 11),
};
static const unsigned int qspi1_ctrl_mux[] = {
QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
};
/* - RPC -------------------------------------------------------------------- */
static const unsigned int rpc_clk_pins[] = {
/* Octal-SPI flash: C/SCLK */
/* HyperFlash: CK, CK# */
RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 6),
};
static const unsigned int rpc_clk_mux[] = {
QSPI0_SPCLK_MARK, QSPI1_SPCLK_MARK,
};
static const unsigned int rpc_ctrl_pins[] = {
/* Octal-SPI flash: S#/CS, DQS */
/* HyperFlash: CS#, RDS */
RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 11),
};
static const unsigned int rpc_ctrl_mux[] = {
QSPI0_SSL_MARK, QSPI1_SSL_MARK,
};
static const unsigned int rpc_data_pins[] = {
/* DQ[0:7] */
RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2),
RCAR_GP_PIN(6, 3), RCAR_GP_PIN(6, 4),
RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 8),
RCAR_GP_PIN(6, 9), RCAR_GP_PIN(6, 10),
};
static const unsigned int rpc_data_mux[] = {
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
QSPI0_IO2_MARK, QSPI0_IO3_MARK,
QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
QSPI1_IO2_MARK, QSPI1_IO3_MARK,
};
static const unsigned int rpc_reset_pins[] = {
/* RPC_RESET# */
RCAR_GP_PIN(6, 12),
};
static const unsigned int rpc_reset_mux[] = {
RPC_RESET_N_MARK,
};
static const unsigned int rpc_int_pins[] = {
/* RPC_INT# */
RCAR_GP_PIN(6, 13),
};
static const unsigned int rpc_int_mux[] = {
RPC_INT_N_MARK,
};
/* - SCIF0 ------------------------------------------------------------------ */ /* - SCIF0 ------------------------------------------------------------------ */
static const unsigned int scif0_data_a_pins[] = { static const unsigned int scif0_data_a_pins[] = {
/* RX, TX */ /* RX, TX */
...@@ -2085,6 +2147,18 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { ...@@ -2085,6 +2147,18 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(pwm3_a), SH_PFC_PIN_GROUP(pwm3_a),
SH_PFC_PIN_GROUP(pwm3_b), SH_PFC_PIN_GROUP(pwm3_b),
SH_PFC_PIN_GROUP(pwm3_c), SH_PFC_PIN_GROUP(pwm3_c),
SH_PFC_PIN_GROUP(qspi0_ctrl),
SH_PFC_PIN_GROUP_SUBSET(qspi0_data2, rpc_data, 0, 2),
SH_PFC_PIN_GROUP_SUBSET(qspi0_data4, rpc_data, 0, 4),
SH_PFC_PIN_GROUP(qspi1_ctrl),
SH_PFC_PIN_GROUP_SUBSET(qspi1_data2, rpc_data, 4, 2),
SH_PFC_PIN_GROUP_SUBSET(qspi1_data4, rpc_data, 4, 4),
BUS_DATA_PIN_GROUP(rpc_clk, 1),
BUS_DATA_PIN_GROUP(rpc_clk, 2),
SH_PFC_PIN_GROUP(rpc_ctrl),
SH_PFC_PIN_GROUP(rpc_data),
SH_PFC_PIN_GROUP(rpc_reset),
SH_PFC_PIN_GROUP(rpc_int),
SH_PFC_PIN_GROUP(scif0_data_a), SH_PFC_PIN_GROUP(scif0_data_a),
SH_PFC_PIN_GROUP(scif0_clk_a), SH_PFC_PIN_GROUP(scif0_clk_a),
SH_PFC_PIN_GROUP(scif0_data_b), SH_PFC_PIN_GROUP(scif0_data_b),
...@@ -2277,6 +2351,27 @@ static const char * const pwm3_groups[] = { ...@@ -2277,6 +2351,27 @@ static const char * const pwm3_groups[] = {
"pwm3_c", "pwm3_c",
}; };
static const char * const qspi0_groups[] = {
"qspi0_ctrl",
"qspi0_data2",
"qspi0_data4",
};
static const char * const qspi1_groups[] = {
"qspi1_ctrl",
"qspi1_data2",
"qspi1_data4",
};
static const char * const rpc_groups[] = {
"rpc_clk1",
"rpc_clk2",
"rpc_ctrl",
"rpc_data",
"rpc_reset",
"rpc_int",
};
static const char * const scif0_groups[] = { static const char * const scif0_groups[] = {
"scif0_data_a", "scif0_data_a",
"scif0_clk_a", "scif0_clk_a",
...@@ -2373,6 +2468,9 @@ static const struct sh_pfc_function pinmux_functions[] = { ...@@ -2373,6 +2468,9 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(pwm1), SH_PFC_FUNCTION(pwm1),
SH_PFC_FUNCTION(pwm2), SH_PFC_FUNCTION(pwm2),
SH_PFC_FUNCTION(pwm3), SH_PFC_FUNCTION(pwm3),
SH_PFC_FUNCTION(qspi0),
SH_PFC_FUNCTION(qspi1),
SH_PFC_FUNCTION(rpc),
SH_PFC_FUNCTION(scif0), SH_PFC_FUNCTION(scif0),
SH_PFC_FUNCTION(scif1), SH_PFC_FUNCTION(scif1),
SH_PFC_FUNCTION(scif2), SH_PFC_FUNCTION(scif2),
......
drivers/pinctrl/renesas/pfc-sh7722.c
View file @ bc8e81a5
// SPDX-License-Identifier: GPL-2.0 // SPDX-License-Identifier: GPL-2.0
#include <linux/init.h>
#include <linux/kernel.h> #include <linux/kernel.h>
#include <cpu/sh7722.h> #include <cpu/sh7722.h>
......
drivers/pinctrl/renesas/pfc-sh7723.c
View file @ bc8e81a5
...@@ -5,7 +5,6 @@ ...@@ -5,7 +5,6 @@
* Copyright (C) 2008 Magnus Damm * Copyright (C) 2008 Magnus Damm
*/ */
#include <linux/init.h>
#include <linux/kernel.h> #include <linux/kernel.h>
#include <cpu/sh7723.h> #include <cpu/sh7723.h>
......
drivers/pinctrl/renesas/pfc-sh7724.c
View file @ bc8e81a5
...@@ -10,7 +10,6 @@ ...@@ -10,7 +10,6 @@
* Copyright (C) 2008 Magnus Damm * Copyright (C) 2008 Magnus Damm
*/ */
#include <linux/init.h>
#include <linux/kernel.h> #include <linux/kernel.h>
#include <cpu/sh7724.h> #include <cpu/sh7724.h>
......
drivers/pinctrl/renesas/pfc-sh7734.c
View file @ bc8e81a5
...@@ -5,7 +5,6 @@ ...@@ -5,7 +5,6 @@
* Copyright (C) 2012 Renesas Solutions Corp. * Copyright (C) 2012 Renesas Solutions Corp.
* Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> * Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
*/ */
#include <linux/init.h>
#include <linux/kernel.h> #include <linux/kernel.h>
#include <cpu/sh7734.h> #include <cpu/sh7734.h>
......
drivers/pinctrl/renesas/pfc-sh7757.c
View file @ bc8e81a5
...@@ -10,7 +10,6 @@ ...@@ -10,7 +10,6 @@
* Copyright (C) 2008 Magnus Damm * Copyright (C) 2008 Magnus Damm
*/ */
#include <linux/init.h>
#include <linux/kernel.h> #include <linux/kernel.h>
#include <cpu/sh7757.h> #include <cpu/sh7757.h>
......
drivers/pinctrl/renesas/pfc-sh7785.c
View file @ bc8e81a5
...@@ -5,7 +5,6 @@ ...@@ -5,7 +5,6 @@
* Copyright (C) 2008 Magnus Damm * Copyright (C) 2008 Magnus Damm
*/ */
#include <linux/init.h>
#include <linux/kernel.h> #include <linux/kernel.h>
#include <cpu/sh7785.h> #include <cpu/sh7785.h>
......
drivers/pinctrl/renesas/pfc-sh7786.c
View file @ bc8e81a5
...@@ -10,7 +10,6 @@ ...@@ -10,7 +10,6 @@
* Copyright (C) 2008 Magnus Damm * Copyright (C) 2008 Magnus Damm
*/ */
#include <linux/init.h>
#include <linux/kernel.h> #include <linux/kernel.h>
#include <cpu/sh7786.h> #include <cpu/sh7786.h>
......
drivers/pinctrl/renesas/pfc-shx3.c
View file @ bc8e81a5
...@@ -4,7 +4,6 @@ ...@@ -4,7 +4,6 @@
* *
* Copyright (C) 2010 Paul Mundt * Copyright (C) 2010 Paul Mundt
*/ */
#include <linux/init.h>
#include <linux/kernel.h> #include <linux/kernel.h>
#include <cpu/shx3.h> #include <cpu/shx3.h>
......
drivers/pinctrl/renesas/pinctrl-rzg2l.c
View file @ bc8e81a5
...@@ -996,83 +996,112 @@ static const u32 rzg2l_gpio_configs[] = { ...@@ -996,83 +996,112 @@ static const u32 rzg2l_gpio_configs[] = {
RZG2L_GPIO_PORT_PACK(5, 0x40, RZG2L_MPXED_PIN_FUNCS), RZG2L_GPIO_PORT_PACK(5, 0x40, RZG2L_MPXED_PIN_FUNCS),
}; };
static struct rzg2l_dedicated_configs rzg2l_dedicated_pins[] = { static const u32 r9a07g043_gpio_configs[] = {
{ "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0, RZG2L_GPIO_PORT_PACK(4, 0x10, RZG2L_MPXED_PIN_FUNCS),
(PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL)) }, RZG2L_GPIO_PORT_PACK(5, 0x11, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
{ "TMS/SWDIO", RZG2L_SINGLE_PIN_PACK(0x2, 0, RZG2L_GPIO_PORT_PACK(4, 0x12, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
(PIN_CFG_SR | PIN_CFG_IOLH_A | PIN_CFG_IEN)) }, RZG2L_GPIO_PORT_PACK(4, 0x13, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
{ "TDO", RZG2L_SINGLE_PIN_PACK(0x3, 0, RZG2L_GPIO_PORT_PACK(6, 0x14, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
(PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_IEN)) }, RZG2L_GPIO_PORT_PACK(5, 0x15, RZG2L_MPXED_PIN_FUNCS),
{ "AUDIO_CLK1", RZG2L_SINGLE_PIN_PACK(0x4, 0, PIN_CFG_IEN) }, RZG2L_GPIO_PORT_PACK(5, 0x16, RZG2L_MPXED_PIN_FUNCS),
{ "AUDIO_CLK2", RZG2L_SINGLE_PIN_PACK(0x4, 1, PIN_CFG_IEN) }, RZG2L_GPIO_PORT_PACK(5, 0x17, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
{ "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x6, 0, RZG2L_GPIO_PORT_PACK(5, 0x18, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD0)) }, RZG2L_GPIO_PORT_PACK(4, 0x19, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
{ "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x6, 1, RZG2L_GPIO_PORT_PACK(5, 0x1a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, RZG2L_GPIO_PORT_PACK(4, 0x1b, RZG2L_MPXED_PIN_FUNCS),
{ "SD0_RST#", RZG2L_SINGLE_PIN_PACK(0x6, 2, RZG2L_GPIO_PORT_PACK(2, 0x1c, RZG2L_MPXED_PIN_FUNCS),
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD0)) }, RZG2L_GPIO_PORT_PACK(5, 0x1d, RZG2L_MPXED_PIN_FUNCS),
{ "SD0_DATA0", RZG2L_SINGLE_PIN_PACK(0x7, 0, RZG2L_GPIO_PORT_PACK(3, 0x1e, RZG2L_MPXED_PIN_FUNCS),
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, RZG2L_GPIO_PORT_PACK(4, 0x1f, RZG2L_MPXED_PIN_FUNCS),
{ "SD0_DATA1", RZG2L_SINGLE_PIN_PACK(0x7, 1, RZG2L_GPIO_PORT_PACK(2, 0x20, RZG2L_MPXED_PIN_FUNCS),
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, RZG2L_GPIO_PORT_PACK(4, 0x21, RZG2L_MPXED_PIN_FUNCS),
{ "SD0_DATA2", RZG2L_SINGLE_PIN_PACK(0x7, 2, RZG2L_GPIO_PORT_PACK(6, 0x22, RZG2L_MPXED_PIN_FUNCS),
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, };
{ "SD0_DATA3", RZG2L_SINGLE_PIN_PACK(0x7, 3,
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, static struct {
{ "SD0_DATA4", RZG2L_SINGLE_PIN_PACK(0x7, 4, struct rzg2l_dedicated_configs common[35];
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, struct rzg2l_dedicated_configs rzg2l_pins[7];
{ "SD0_DATA5", RZG2L_SINGLE_PIN_PACK(0x7, 5, } rzg2l_dedicated_pins = {
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, .common = {
{ "SD0_DATA6", RZG2L_SINGLE_PIN_PACK(0x7, 6, { "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0,
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, (PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL)) },
{ "SD0_DATA7", RZG2L_SINGLE_PIN_PACK(0x7, 7, { "TMS/SWDIO", RZG2L_SINGLE_PIN_PACK(0x2, 0,
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, (PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_IEN)) },
{ "SD1_CLK", RZG2L_SINGLE_PIN_PACK(0x8, 0, { "TDO", RZG2L_SINGLE_PIN_PACK(0x3, 0,
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD1)) }, (PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_IEN)) },
{ "SD1_CMD", RZG2L_SINGLE_PIN_PACK(0x8, 1, { "AUDIO_CLK1", RZG2L_SINGLE_PIN_PACK(0x4, 0, PIN_CFG_IEN) },
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, { "AUDIO_CLK2", RZG2L_SINGLE_PIN_PACK(0x4, 1, PIN_CFG_IEN) },
{ "SD1_DATA0", RZG2L_SINGLE_PIN_PACK(0x9, 0, { "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x6, 0,
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD0)) },
{ "SD1_DATA1", RZG2L_SINGLE_PIN_PACK(0x9, 1, { "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x6, 1,
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
{ "SD1_DATA2", RZG2L_SINGLE_PIN_PACK(0x9, 2, { "SD0_RST#", RZG2L_SINGLE_PIN_PACK(0x6, 2,
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD0)) },
{ "SD1_DATA3", RZG2L_SINGLE_PIN_PACK(0x9, 3, { "SD0_DATA0", RZG2L_SINGLE_PIN_PACK(0x7, 0,
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
{ "QSPI0_SPCLK", RZG2L_SINGLE_PIN_PACK(0xa, 0, { "SD0_DATA1", RZG2L_SINGLE_PIN_PACK(0x7, 1,
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
{ "QSPI0_IO0", RZG2L_SINGLE_PIN_PACK(0xa, 1, { "SD0_DATA2", RZG2L_SINGLE_PIN_PACK(0x7, 2,
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
{ "QSPI0_IO1", RZG2L_SINGLE_PIN_PACK(0xa, 2, { "SD0_DATA3", RZG2L_SINGLE_PIN_PACK(0x7, 3,
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
{ "QSPI0_IO2", RZG2L_SINGLE_PIN_PACK(0xa, 3, { "SD0_DATA4", RZG2L_SINGLE_PIN_PACK(0x7, 4,
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
{ "QSPI0_IO3", RZG2L_SINGLE_PIN_PACK(0xa, 4, { "SD0_DATA5", RZG2L_SINGLE_PIN_PACK(0x7, 5,
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
{ "QSPI0_SSL", RZG2L_SINGLE_PIN_PACK(0xa, 5, { "SD0_DATA6", RZG2L_SINGLE_PIN_PACK(0x7, 6,
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
{ "QSPI1_SPCLK", RZG2L_SINGLE_PIN_PACK(0xb, 0, { "SD0_DATA7", RZG2L_SINGLE_PIN_PACK(0x7, 7,
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
{ "QSPI1_IO0", RZG2L_SINGLE_PIN_PACK(0xb, 1, { "SD1_CLK", RZG2L_SINGLE_PIN_PACK(0x8, 0,
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD1)) },
{ "QSPI1_IO1", RZG2L_SINGLE_PIN_PACK(0xb, 2, { "SD1_CMD", RZG2L_SINGLE_PIN_PACK(0x8, 1,
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) },
{ "QSPI1_IO2", RZG2L_SINGLE_PIN_PACK(0xb, 3, { "SD1_DATA0", RZG2L_SINGLE_PIN_PACK(0x9, 0,
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) },
{ "QSPI1_IO3", RZG2L_SINGLE_PIN_PACK(0xb, 4, { "SD1_DATA1", RZG2L_SINGLE_PIN_PACK(0x9, 1,
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) },
{ "QSPI1_SSL", RZG2L_SINGLE_PIN_PACK(0xb, 5, { "SD1_DATA2", RZG2L_SINGLE_PIN_PACK(0x9, 2,
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) },
{ "QSPI_RESET#", RZG2L_SINGLE_PIN_PACK(0xc, 0, { "SD1_DATA3", RZG2L_SINGLE_PIN_PACK(0x9, 3,
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) },
{ "QSPI_WP#", RZG2L_SINGLE_PIN_PACK(0xc, 1, { "QSPI0_SPCLK", RZG2L_SINGLE_PIN_PACK(0xa, 0,
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
{ "QSPI_INT#", RZG2L_SINGLE_PIN_PACK(0xc, 2, (PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, { "QSPI0_IO0", RZG2L_SINGLE_PIN_PACK(0xa, 1,
{ "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0xd, 0, (PIN_CFG_IOLH_A | PIN_CFG_SR)) }, (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
{ "RIIC0_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 0, PIN_CFG_IEN) }, { "QSPI0_IO1", RZG2L_SINGLE_PIN_PACK(0xa, 2,
{ "RIIC0_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 1, PIN_CFG_IEN) }, (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
{ "RIIC1_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 2, PIN_CFG_IEN) }, { "QSPI0_IO2", RZG2L_SINGLE_PIN_PACK(0xa, 3,
{ "RIIC1_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 3, PIN_CFG_IEN) }, (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
{ "QSPI0_IO3", RZG2L_SINGLE_PIN_PACK(0xa, 4,
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
{ "QSPI0_SSL", RZG2L_SINGLE_PIN_PACK(0xa, 5,
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
{ "QSPI_RESET#", RZG2L_SINGLE_PIN_PACK(0xc, 0,
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
{ "QSPI_WP#", RZG2L_SINGLE_PIN_PACK(0xc, 1,
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
{ "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0xd, 0, (PIN_CFG_IOLH_A | PIN_CFG_SR)) },
{ "RIIC0_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 0, PIN_CFG_IEN) },
{ "RIIC0_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 1, PIN_CFG_IEN) },
{ "RIIC1_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 2, PIN_CFG_IEN) },
{ "RIIC1_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 3, PIN_CFG_IEN) },
},
.rzg2l_pins = {
{ "QSPI_INT#", RZG2L_SINGLE_PIN_PACK(0xc, 2, (PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
{ "QSPI1_SPCLK", RZG2L_SINGLE_PIN_PACK(0xb, 0,
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
{ "QSPI1_IO0", RZG2L_SINGLE_PIN_PACK(0xb, 1,
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
{ "QSPI1_IO1", RZG2L_SINGLE_PIN_PACK(0xb, 2,
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
{ "QSPI1_IO2", RZG2L_SINGLE_PIN_PACK(0xb, 3,
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
{ "QSPI1_IO3", RZG2L_SINGLE_PIN_PACK(0xb, 4,
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
{ "QSPI1_SSL", RZG2L_SINGLE_PIN_PACK(0xb, 5,
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
}
}; };
static int rzg2l_gpio_register(struct rzg2l_pinctrl *pctrl) static int rzg2l_gpio_register(struct rzg2l_pinctrl *pctrl)
...@@ -1250,15 +1279,28 @@ static int rzg2l_pinctrl_probe(struct platform_device *pdev) ...@@ -1250,15 +1279,28 @@ static int rzg2l_pinctrl_probe(struct platform_device *pdev)
return 0; return 0;
} }
static struct rzg2l_pinctrl_data r9a07g043_data = {
.port_pins = rzg2l_gpio_names,
.port_pin_configs = r9a07g043_gpio_configs,
.dedicated_pins = rzg2l_dedicated_pins.common,
.n_port_pins = ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT,
.n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common),
};
static struct rzg2l_pinctrl_data r9a07g044_data = { static struct rzg2l_pinctrl_data r9a07g044_data = {
.port_pins = rzg2l_gpio_names, .port_pins = rzg2l_gpio_names,
.port_pin_configs = rzg2l_gpio_configs, .port_pin_configs = rzg2l_gpio_configs,
.dedicated_pins = rzg2l_dedicated_pins, .dedicated_pins = rzg2l_dedicated_pins.common,
.n_port_pins = ARRAY_SIZE(rzg2l_gpio_names), .n_port_pins = ARRAY_SIZE(rzg2l_gpio_names),
.n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins), .n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common) +
ARRAY_SIZE(rzg2l_dedicated_pins.rzg2l_pins),
}; };
static const struct of_device_id rzg2l_pinctrl_of_table[] = { static const struct of_device_id rzg2l_pinctrl_of_table[] = {
{
.compatible = "renesas,r9a07g043-pinctrl",
.data = &r9a07g043_data,
},
{ {
.compatible = "renesas,r9a07g044-pinctrl", .compatible = "renesas,r9a07g044-pinctrl",
.data = &r9a07g044_data, .data = &r9a07g044_data,
......
drivers/pinctrl/renesas/pinctrl.c
View file @ bc8e81a5
...@@ -9,7 +9,6 @@ ...@@ -9,7 +9,6 @@
#include <linux/device.h> #include <linux/device.h>
#include <linux/err.h> #include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h> #include <linux/io.h>
#include <linux/module.h> #include <linux/module.h>
#include <linux/of.h> #include <linux/of.h>
......
drivers/pinctrl/renesas/sh_pfc.h
View file @ bc8e81a5
...@@ -132,9 +132,8 @@ struct pinmux_cfg_reg { ...@@ -132,9 +132,8 @@ struct pinmux_cfg_reg {
.reg = r, .reg_width = r_width, \ .reg = r, .reg_width = r_width, \
.field_width = f_width + BUILD_BUG_ON_ZERO(r_width % f_width) + \ .field_width = f_width + BUILD_BUG_ON_ZERO(r_width % f_width) + \
BUILD_BUG_ON_ZERO(sizeof((const u16 []) { ids }) / sizeof(u16) != \ BUILD_BUG_ON_ZERO(sizeof((const u16 []) { ids }) / sizeof(u16) != \
(r_width / f_width) * (1 << f_width)), \ (r_width / f_width) << f_width), \
.enum_ids = (const u16 [(r_width / f_width) * (1 << f_width)]) \ .enum_ids = (const u16 [(r_width / f_width) << f_width]) { ids }
{ ids }
/* /*
* Describe a config register consisting of several fields of different widths * Describe a config register consisting of several fields of different widths
...@@ -162,7 +161,7 @@ struct pinmux_drive_reg_field { ...@@ -162,7 +161,7 @@ struct pinmux_drive_reg_field {
struct pinmux_drive_reg { struct pinmux_drive_reg {
u32 reg; u32 reg;
const struct pinmux_drive_reg_field fields[8]; const struct pinmux_drive_reg_field fields[10];
}; };
#define PINMUX_DRIVE_REG(name, r) \ #define PINMUX_DRIVE_REG(name, r) \
......
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