Commit bc9d1c71 authored by Russell King's avatar Russell King

Merge flint.arm.linux.org.uk:/usr/src/linux-bk-2.5/linux-2.5-rmk-patchtest

into flint.arm.linux.org.uk:/usr/src/linux-bk-2.5/linux-2.5-rmk
parents 4b52933b a79b77ec
......@@ -16,6 +16,7 @@
#include <linux/config.h>
#include "entry-header.S"
#include <asm/thread_info.h>
#include <asm/glue.h>
#ifdef IOC_BASE
......@@ -681,12 +682,12 @@ __dabt_svc: sub sp, sp, #S_FRAME_SIZE
/*
* This routine must not corrupt r9
*/
#ifdef MULTI_CPU
#ifdef MULTI_ABORT
ldr r4, .LCprocfns @ pass r0, r3 to
mov lr, pc @ processor code
ldr pc, [r4] @ call processor specific code
#else
bl cpu_data_abort
bl CPU_ABORT_HANDLER
#endif
msr cpsr_c, r9
mov r2, sp
......@@ -799,7 +800,7 @@ __pabt_svc: sub sp, sp, #S_FRAME_SIZE
.LCirq: .word __temp_irq
.LCund: .word __temp_und
.LCabt: .word __temp_abt
#ifdef MULTI_CPU
#ifdef MULTI_ABORT
.LCprocfns: .word SYMBOL_NAME(processor)
#endif
.LCfp: .word SYMBOL_NAME(fp_enter)
......@@ -823,12 +824,12 @@ __dabt_usr: sub sp, sp, #S_FRAME_SIZE @ Allocate frame size in one go
alignment_trap r7, r7, __temp_abt
zero_fp
mov r0, r2 @ remove once everyones in sync
#ifdef MULTI_CPU
#ifdef MULTI_ABORT
ldr r4, .LCprocfns @ pass r0, r3 to
mov lr, pc @ processor code
ldr pc, [r4] @ call processor specific code
#else
bl cpu_data_abort
bl CPU_ABORT_HANDLER
#endif
set_cpsr_c r2, #MODE_SVC @ Enable interrupts
mov r2, sp
......
......@@ -76,6 +76,9 @@ struct processor processor;
#ifdef MULTI_TLB
struct cpu_tlb_fns cpu_tlb;
#endif
#ifdef MULTI_USER
struct cpu_user_fns cpu_user;
#endif
unsigned char aux_device_present;
char elf_platform[ELF_PLATFORM_SIZE];
......@@ -248,6 +251,9 @@ static void __init setup_processor(void)
#ifdef MULTI_TLB
cpu_tlb = *list->tlb;
#endif
#ifdef MULTI_USER
cpu_user = *list->user;
#endif
printk("Processor: %s %s revision %d\n",
proc_info.manufacturer, proc_info.cpu_name,
......
......@@ -113,7 +113,6 @@ static int __init integrator_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
extern void pci_v3_init(void *);
struct hw_pci integrator_pci __initdata = {
mem_offset: 0x40000000,
swizzle: integrator_swizzle,
map_irq: integrator_map_irq,
setup: pci_v3_setup,
......
......@@ -435,7 +435,7 @@ static int __init pci_v3_setup_resources(struct resource **resource)
resource[1] = &non_mem;
resource[2] = &pre_mem;
return 0;
return 1;
}
/*
......@@ -529,8 +529,10 @@ int __init pci_v3_setup(int nr, struct pci_sys_data *sys)
{
int ret = 0;
if (nr == 0)
if (nr == 0) {
sys->mem_offset = 0x40000000;
ret = pci_v3_setup_resources(sys->resource);
}
return ret;
}
......@@ -634,7 +636,6 @@ void __init pci_v3_preinit(void)
void __init pci_v3_postinit(void)
{
unsigned int pci_cmd;
int ret;
pci_cmd = PCI_COMMAND_MEMORY |
PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE;
......
......@@ -47,23 +47,44 @@ static u_long iq80310_read_timer (void)
u_long b0, b1, b2, b3, val;
b0 = *la0; b1 = *la1; b2 = *la2; b3 = *la3;
b0 = (((b0 & 0x20) >> 1) | (b0 & 0x1f));
b1 = (((b1 & 0x20) >> 1) | (b1 & 0x1f));
b2 = (((b2 & 0x20) >> 1) | (b2 & 0x1f));
b0 = (((b0 & 0x40) >> 1) | (b0 & 0x1f));
b1 = (((b1 & 0x40) >> 1) | (b1 & 0x1f));
b2 = (((b2 & 0x40) >> 1) | (b2 & 0x1f));
b3 = (b3 & 0x0f);
val = ((b0 << 0) | (b1 << 6) | (b2 << 12) | (b3 << 18));
return val;
}
/* IRQs are disabled before entering here from do_gettimeofday() */
/*
* IRQs are disabled before entering here from do_gettimeofday().
* Note that the counter may wrap. When it does, 'elapsed' will
* be small, but we will have a pending interrupt.
*/
static unsigned long iq80310_gettimeoffset (void)
{
unsigned long elapsed, usec;
unsigned long elapsed, usec, tmp1;
unsigned int stat1, stat2;
/* We need elapsed timer ticks since last interrupt */
stat1 = *(volatile u8 *)IQ80310_INT_STAT;
elapsed = iq80310_read_timer();
stat2 = *(volatile u8 *)IQ80310_INT_STAT;
/*
* If an interrupt was pending before we read the timer,
* we've already wrapped. Factor this into the time.
* If an interrupt was pending after we read the timer,
* it may have wrapped between checking the interrupt
* status and reading the timer. Re-read the timer to
* be sure its value is after the wrap.
*/
if (stat1 & 1)
elapsed += LATCH;
else if (stat2 & 1)
elapsed = LATCH + iq80310_read_timer();
/* Now convert them to usec */
/*
* Now convert them to usec.
*/
usec = (unsigned long)(elapsed*tick)/LATCH;
return usec;
......@@ -92,9 +113,7 @@ static void iq80310_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
*
* -DS
*/
irq_exit(smp_processor_id(), irq);
do_timer(regs);
irq_enter(smp_processor_id(), irq);
}
extern unsigned long (*gettimeoffset)(void);
......@@ -116,4 +135,3 @@ void __init time_init(void)
*timer_en |= 2;
*timer_en |= 1;
}
#include <linux/linkage.h>
#include <asm/assembler.h>
/*
* Function: armv4_early_abort
* Function: v4_early_abort
*
* Params : r2 = address of aborted instruction
* : r3 = saved SPSR
......@@ -18,7 +18,7 @@
* picture. Unfortunately, this does happen. We live with it.
*/
.align 5
ENTRY(armv4_early_abort)
ENTRY(v4_early_abort)
mrc p15, 0, r1, c5, c0, 0 @ get FSR
mrc p15, 0, r0, c6, c0, 0 @ get FAR
ldr r3, [r2] @ read aborted ARM instruction
......
#include <linux/linkage.h>
#include <asm/assembler.h>
/*
* Function: armv4t_early_abort
* Function: v4t_early_abort
*
* Params : r2 = address of aborted instruction
* : r3 = saved SPSR
......@@ -18,7 +18,7 @@
* picture. Unfortunately, this does happen. We live with it.
*/
.align 5
ENTRY(armv4t_early_abort)
ENTRY(v4t_early_abort)
mrc p15, 0, r1, c5, c0, 0 @ get FSR
mrc p15, 0, r0, c6, c0, 0 @ get FAR
tst r3, #PSR_T_BIT
......
#include <linux/linkage.h>
#include <asm/assembler.h>
/*
* Function: armv5ej_early_abort
* Function: v5ej_early_abort
*
* Params : r2 = address of aborted instruction
* : r3 = saved SPSR
......@@ -18,7 +18,7 @@
* picture. Unfortunately, this does happen. We live with it.
*/
.align 5
ENTRY(armv5ej_early_abort)
ENTRY(v5ej_early_abort)
mrc p15, 0, r1, c5, c0, 0 @ get FSR
mrc p15, 0, r0, c6, c0, 0 @ get FAR
tst r3, #PSR_J_BIT
......
#include <linux/linkage.h>
#include <asm/assembler.h>
/*
* Function: armv4t_late_abort
* Function: v4t_late_abort
*
* Params : r2 = address of aborted instruction
* : r3 = saved SPSR
......@@ -17,7 +17,7 @@
* abort here if the I-TLB and D-TLB aren't seeing the same
* picture. Unfortunately, this does happen. We live with it.
*/
ENTRY(armv4t_late_abort)
ENTRY(v4t_late_abort)
tst r3, #PSR_T_BIT @ check for thumb mode
mrc p15, 0, r1, c5, c0, 0 @ get FSR
mrc p15, 0, r0, c6, c0, 0 @ get FAR
......
......@@ -20,7 +20,7 @@
*
* FIXME: do we need to handle cache stuff...
*/
ENTRY(armv3_copy_user_page)
ENTRY(v3_copy_user_page)
stmfd sp!, {r4, lr} @ 2
mov r2, #PAGE_SZ/64 @ 1
ldmia r1!, {r3, r4, ip, lr} @ 4+1
......@@ -42,7 +42,7 @@ ENTRY(armv3_copy_user_page)
*
* FIXME: do we need to handle cache stuff...
*/
ENTRY(armv3_clear_user_page)
ENTRY(v3_clear_user_page)
str lr, [sp, #-4]!
mov r1, #PAGE_SZ/64 @ 1
mov r2, #0 @ 1
......@@ -57,3 +57,8 @@ ENTRY(armv3_clear_user_page)
bne 1b @ 1
ldr pc, [sp], #4
.section ".text.init", #alloc, #execinstr
ENTRY(v3_user_fns)
.long v3_clear_user_page
.long v3_copy_user_page
......@@ -26,7 +26,7 @@
* instruction. If your processor does not supply this, you have to write your
* own copy_user_page that does the right thing.
*/
ENTRY(armv4_copy_user_page)
ENTRY(v4_copy_user_page)
stmfd sp!, {r4, lr} @ 2
mov r2, #PAGE_SZ/64 @ 1
ldmia r1!, {r3, r4, ip, lr} @ 4
......@@ -51,7 +51,7 @@ ENTRY(armv4_copy_user_page)
*
* Same story as above.
*/
ENTRY(armv4_clear_user_page)
ENTRY(v4_clear_user_page)
str lr, [sp, #-4]!
mov r1, #PAGE_SZ/64 @ 1
mov r2, #0 @ 1
......@@ -68,3 +68,10 @@ ENTRY(armv4_clear_user_page)
bne 1b @ 1
mcr p15, 0, r1, c7, c10, 4 @ 1 drain WB
ldr pc, [sp], #4
.section ".text.init", #alloc, #execinstr
ENTRY(v4_user_fns)
.long v4_clear_user_page
.long v4_copy_user_page
......@@ -26,7 +26,7 @@
* instruction. If your processor does not supply this, you have to write your
* own copy_user_page that does the right thing.
*/
ENTRY(armv4_mc_copy_user_page)
ENTRY(v4_mc_copy_user_page)
stmfd sp!, {r4, lr} @ 2
mov r4, r0
mov r0, r1
......@@ -53,7 +53,7 @@ ENTRY(armv4_mc_copy_user_page)
*
* Same story as above.
*/
ENTRY(armv4_mc_clear_user_page)
ENTRY(v4_mc_clear_user_page)
str lr, [sp, #-4]!
mov r1, #PAGE_SZ/64 @ 1
mov r2, #0 @ 1
......@@ -69,3 +69,10 @@ ENTRY(armv4_mc_clear_user_page)
subs r1, r1, #1 @ 1
bne 1b @ 1
ldr pc, [sp], #4
.section ".text.init", #alloc, #execinstr
ENTRY(v4_mc_user_fns)
.long v4_mc_clear_user_page
.long v4_mc_copy_user_page
......@@ -32,7 +32,7 @@
* page. We rely on the mini-cache being smaller than one page, so we'll
* cycle through the complete cache anyway.
*/
ENTRY(armv5te_copy_user_page)
ENTRY(v5te_mc_copy_user_page)
stmfd sp!, {r4, r5, lr}
mov r5, r0
mov r0, r1
......@@ -62,7 +62,7 @@ ENTRY(armv5te_copy_user_page)
* r0 = destination
* r1 = virtual user address of ultimate destination page
*/
ENTRY(armv5te_clear_user_page)
ENTRY(v5te_mc_clear_user_page)
str lr, [sp, #-4]!
mov r1, #PAGE_SZ/32
mov r2, #0
......@@ -77,3 +77,9 @@ ENTRY(armv5te_clear_user_page)
subs r1, r1, #1
bne 1b
ldr pc, [sp], #4
.section ".text.init", #alloc, #execinstr
ENTRY(v5te_mc_user_fns)
.long v5te_mc_clear_user_page
.long v5te_mc_copy_user_page
......@@ -608,7 +608,7 @@ __arm1020_setup:
*/
.type arm1020_processor_functions, #object
arm1020_processor_functions:
.word armv4t_early_abort
.word v4t_early_abort
.word cpu_arm1020_check_bugs
.word cpu_arm1020_proc_init
.word cpu_arm1020_proc_fin
......@@ -635,10 +635,6 @@ arm1020_processor_functions:
.word cpu_arm1020_set_pmd
.word cpu_arm1020_set_pte
/* misc */
.word armv4_clear_user_page
.word armv4_copy_user_page
.size arm1020_processor_functions, . - arm1020_processor_functions
.type cpu_arm1020_info, #object
......@@ -672,4 +668,5 @@ __arm1020_proc_info:
.long cpu_arm1020_info
.long arm1020_processor_functions
.long v4wbi_tlb_fns
.long v4_user_fns
.size __arm1020_proc_info, . - __arm1020_proc_info
......@@ -342,6 +342,7 @@ arm3_elf_name: .asciz "v2"
.long cpu_arm2_info
.long SYMBOL_NAME(arm2_processor_functions)
.long 0
.long 0
.long 0x41560250
.long 0xfffffff0
......@@ -353,6 +354,7 @@ arm3_elf_name: .asciz "v2"
.long cpu_arm250_info
.long SYMBOL_NAME(arm250_processor_functions)
.long 0
.long 0
.long 0x41560300
.long 0xfffffff0
......@@ -364,3 +366,5 @@ arm3_elf_name: .asciz "v2"
.long cpu_arm3_info
.long SYMBOL_NAME(arm3_processor_functions)
.long 0
.long 0
......@@ -373,10 +373,6 @@ ENTRY(arm6_processor_functions)
.word cpu_arm6_set_pmd
.word cpu_arm6_set_pte
/* other */
.word armv3_clear_user_page
.word armv3_copy_user_page
.size arm6_processor_functions, . - arm6_processor_functions
/*
......@@ -412,10 +408,6 @@ ENTRY(arm7_processor_functions)
.word cpu_arm7_set_pmd
.word cpu_arm7_set_pte
/* other */
.word armv3_clear_user_page
.word armv3_copy_user_page
.size arm7_processor_functions, . - arm7_processor_functions
.type cpu_arm6_info, #object
......@@ -465,6 +457,7 @@ __arm6_proc_info:
.long cpu_arm6_info
.long arm6_processor_functions
.long v3_tlb_fns
.long v3_user_fns
.size __arm6_proc_info, . - __arm6_proc_info
.type __arm610_proc_info, #object
......@@ -479,6 +472,7 @@ __arm610_proc_info:
.long cpu_arm610_info
.long arm6_processor_functions
.long v3_tlb_fns
.long v3_user_fns
.size __arm610_proc_info, . - __arm610_proc_info
.type __arm7_proc_info, #object
......@@ -493,6 +487,7 @@ __arm7_proc_info:
.long cpu_arm7_info
.long arm7_processor_functions
.long v3_tlb_fns
.long v3_user_fns
.size __arm7_proc_info, . - __arm7_proc_info
.type __arm710_proc_info, #object
......@@ -507,4 +502,5 @@ __arm710_proc_info:
.long cpu_arm710_info
.long arm7_processor_functions
.long v3_tlb_fns
.long v3_user_fns
.size __arm710_proc_info, . - __arm710_proc_info
......@@ -199,7 +199,7 @@ __arm720_setup: mov r0, #0
*/
.type arm720_processor_functions, #object
ENTRY(arm720_processor_functions)
.word armv4t_late_abort
.word v4t_late_abort
.word cpu_arm720_check_bugs
.word cpu_arm720_proc_init
.word cpu_arm720_proc_fin
......@@ -226,10 +226,6 @@ ENTRY(arm720_processor_functions)
.word cpu_arm720_set_pmd
.word cpu_arm720_set_pte
/* misc */
.word armv4_clear_user_page
.word armv4_copy_user_page
.size arm720_processor_functions, . - arm720_processor_functions
.type cpu_arm720_info, #object
......@@ -265,4 +261,5 @@ __arm720_proc_info:
.long cpu_arm720_info @ info
.long arm720_processor_functions
.long v4_tlb_fns
.long v4_user_fns
.size __arm720_proc_info, . - __arm720_proc_info
......@@ -511,7 +511,7 @@ __arm920_setup:
*/
.type arm920_processor_functions, #object
arm920_processor_functions:
.word armv4t_early_abort
.word v4t_early_abort
.word cpu_arm920_check_bugs
.word cpu_arm920_proc_init
.word cpu_arm920_proc_fin
......@@ -538,10 +538,6 @@ arm920_processor_functions:
.word cpu_arm920_set_pmd
.word cpu_arm920_set_pte
/* misc */
.word armv4_clear_user_page
.word armv4_copy_user_page
.size arm920_processor_functions, . - arm920_processor_functions
.type cpu_arm920_info, #object
......@@ -575,4 +571,5 @@ __arm920_proc_info:
.long cpu_arm920_info
.long arm920_processor_functions
.long v4wbi_tlb_fns
.long v4_user_fns
.size __arm920_proc_info, . - __arm920_proc_info
......@@ -512,7 +512,7 @@ __arm922_setup:
*/
.type arm922_processor_functions, #object
arm922_processor_functions:
.word armv4t_early_abort
.word v4t_early_abort
.word cpu_arm922_check_bugs
.word cpu_arm922_proc_init
.word cpu_arm922_proc_fin
......@@ -539,10 +539,6 @@ arm922_processor_functions:
.word cpu_arm922_set_pmd
.word cpu_arm922_set_pte
/* misc */
.word armv4_clear_user_page
.word armv4_copy_user_page
.size arm922_processor_functions, . - arm922_processor_functions
.type cpu_arm922_info, #object
......@@ -576,4 +572,5 @@ __arm922_proc_info:
.long cpu_arm922_info
.long arm922_processor_functions
.long v4wbi_tlb_fns
.long v4_user_fns
.size __arm922_proc_info, . - __arm922_proc_info
......@@ -549,7 +549,7 @@ __arm926_setup:
*/
.type arm926_processor_functions, #object
arm926_processor_functions:
.word armv5ej_early_abort
.word v5ej_early_abort
.word cpu_arm926_check_bugs
.word cpu_arm926_proc_init
.word cpu_arm926_proc_fin
......@@ -576,10 +576,6 @@ arm926_processor_functions:
.word cpu_arm926_set_pmd
.word cpu_arm926_set_pte
/* misc */
.word armv4_clear_user_page
.word armv4_copy_user_page
.size arm926_processor_functions, . - arm926_processor_functions
.type cpu_arm926_info, #object
......@@ -613,4 +609,5 @@ __arm926_proc_info:
.long cpu_arm926_info
.long arm926_processor_functions
.long v4wbi_tlb_fns
.long v4_user_fns
.size __arm926_proc_info, . - __arm926_proc_info
......@@ -538,7 +538,7 @@ __setup_common:
.type sa110_processor_functions, #object
ENTRY(sa110_processor_functions)
.word armv4_early_abort
.word v4_early_abort
.word cpu_sa110_check_bugs
.word cpu_sa110_proc_init
.word cpu_sa110_proc_fin
......@@ -565,10 +565,6 @@ ENTRY(sa110_processor_functions)
.word cpu_sa110_set_pmd
.word cpu_sa110_set_pte
/* misc */
.word armv4_clear_user_page
.word armv4_copy_user_page
.size sa110_processor_functions, . - sa110_processor_functions
.type cpu_sa110_info, #object
......@@ -610,10 +606,6 @@ ENTRY(sa1100_processor_functions)
.word cpu_sa1100_set_pmd
.word cpu_sa1100_set_pte
/* misc */
.word armv4_mc_clear_user_page
.word armv4_mc_copy_user_page
.size sa1100_processor_functions, . - sa1100_processor_functions
cpu_sa1100_info:
......@@ -651,6 +643,7 @@ __sa110_proc_info:
.long cpu_sa110_info
.long sa110_processor_functions
.long v4wb_tlb_fns
.long v4_user_fns
.size __sa110_proc_info, . - __sa110_proc_info
.type __sa1100_proc_info,#object
......@@ -665,6 +658,7 @@ __sa1100_proc_info:
.long cpu_sa1100_info
.long sa1100_processor_functions
.long v4wb_tlb_fns
.long v4_mc_user_fns
.size __sa1100_proc_info, . - __sa1100_proc_info
.type __sa1110_proc_info,#object
......@@ -679,4 +673,5 @@ __sa1110_proc_info:
.long cpu_sa1110_info
.long sa1100_processor_functions
.long v4wb_tlb_fns
.long v4_mc_user_fns
.size __sa1110_proc_info, . - __sa1110_proc_info
......@@ -695,7 +695,7 @@ __xscale_setup:
.type xscale_processor_functions, #object
ENTRY(xscale_processor_functions)
.word armv4t_early_abort
.word v4t_early_abort
.word cpu_xscale_check_bugs
.word cpu_xscale_proc_init
.word cpu_xscale_proc_fin
......@@ -722,10 +722,6 @@ ENTRY(xscale_processor_functions)
.word cpu_xscale_set_pmd
.word cpu_xscale_set_pte
/* misc */
.word armv5te_clear_user_page
.word armv5te_copy_user_page
.size xscale_processor_functions, . - xscale_processor_functions
.type cpu_80200_info, #object
......@@ -765,6 +761,7 @@ __80200_proc_info:
.long cpu_80200_info
.long xscale_processor_functions
.long v4wbi_tlb_fns
.long v5te_mc_user_fns
.size __80200_proc_info, . - __80200_proc_info
.type __pxa250_proc_info,#object
......@@ -779,6 +776,7 @@ __pxa250_proc_info:
.long cpu_pxa250_info
.long xscale_processor_functions
.long v4wbi_tlb_fns
.long v5te_mc_user_fns
.size __cotulla_proc_info, . - __cotulla_proc_info
.size __pxa250_proc_info, . - __pxa250_proc_info
......@@ -107,18 +107,12 @@ extern struct processor {
*/
void (*set_pte)(pte_t *ptep, pte_t pte);
} pgtable;
struct { /* other */
void (*clear_user_page)(void *page, unsigned long u_addr);
void (*copy_user_page)(void *to, void *from, unsigned long u_addr);
} misc;
} processor;
extern const struct processor arm6_processor_functions;
extern const struct processor arm7_processor_functions;
extern const struct processor sa110_processor_functions;
#define cpu_data_abort(pc) processor._data_abort(pc)
#define cpu_check_bugs() processor._check_bugs()
#define cpu_proc_init() processor._proc_init()
#define cpu_proc_fin() processor._proc_fin()
......@@ -141,9 +135,6 @@ extern const struct processor sa110_processor_functions;
#define cpu_set_pmd(pmdp, pmd) processor.pgtable.set_pmd(pmdp, pmd)
#define cpu_set_pte(ptep, pte) processor.pgtable.set_pte(ptep, pte)
#define cpu_copy_user_page(to,from,uaddr) processor.misc.copy_user_page(to,from,uaddr)
#define cpu_clear_user_page(page,uaddr) processor.misc.clear_user_page(page,uaddr)
#define cpu_switch_mm(pgd,tsk) cpu_set_pgd(__virt_to_phys((unsigned long)(pgd)))
#define cpu_get_pgd() \
......
......@@ -22,7 +22,6 @@
* function pointers for this lot. Otherwise, we can optimise the
* table away.
*/
#define cpu_data_abort __cpu_fn(CPU_ABRT,_abort)
#define cpu_check_bugs __cpu_fn(CPU_NAME,_check_bugs)
#define cpu_proc_init __cpu_fn(CPU_NAME,_proc_init)
#define cpu_proc_fin __cpu_fn(CPU_NAME,_proc_fin)
......@@ -40,8 +39,6 @@
#define cpu_set_pgd __cpu_fn(CPU_NAME,_set_pgd)
#define cpu_set_pmd __cpu_fn(CPU_NAME,_set_pmd)
#define cpu_set_pte __cpu_fn(CPU_NAME,_set_pte)
#define cpu_copy_user_page __cpu_fn(MMU_ARCH,_copy_user_page)
#define cpu_clear_user_page __cpu_fn(MMU_ARCH,_clear_user_page)
#ifndef __ASSEMBLY__
......@@ -74,9 +71,6 @@ extern void cpu_set_pgd(unsigned long pgd_phys);
extern void cpu_set_pmd(pmd_t *pmdp, pmd_t pmd);
extern void cpu_set_pte(pte_t *ptep, pte_t pte);
extern void cpu_copy_user_page(void *to, void *from, unsigned long u_addr);
extern void cpu_clear_user_page(void *page, unsigned long u_addr);
extern volatile void cpu_reset(unsigned long addr);
#define cpu_switch_mm(pgd,tsk) cpu_set_pgd(__virt_to_phys((unsigned long)(pgd)))
......
......@@ -24,14 +24,21 @@
#endif
#define __glue(name,fn) ____glue(name,fn)
/*
* Select MMU TLB handling.
*/
/*
* ARMv3 MMU
* MMU TLB Model
* =============
*
* We have the following to choose from:
* v3 - ARMv3
* v4 - ARMv4 without write buffer
* v4wb - ARMv4 with write buffer without I TLB flush entry instruction
* v4wbi - ARMv4 with write buffer with I TLB flush entry instruction
*/
#undef _TLB
#undef MULTI_TLB
#if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710)
# ifdef _TLB
# define MULTI_TLB 1
......@@ -40,9 +47,6 @@
# endif
#endif
/*
* ARMv4 MMU without write buffer
*/
#if defined(CONFIG_CPU_ARM720T)
# ifdef _TLB
# define MULTI_TLB 1
......@@ -51,9 +55,6 @@
# endif
#endif
/*
* ARMv4 MMU with write buffer, with invalidate I TLB entry instruction
*/
#if defined(CONFIG_CPU_ARM920T) || defined(CONFIG_CPU_ARM922T) || \
defined(CONFIG_CPU_ARM926T) || defined(CONFIG_CPU_ARM1020) || \
defined(CONFIG_CPU_XSCALE)
......@@ -64,9 +65,6 @@
# endif
#endif
/*
* ARMv4 MMU with write buffer, without invalidate I TLB entry instruction
*/
#if defined(CONFIG_CPU_SA110) || defined(CONFIG_CPU_SA1100)
# ifdef _TLB
# define MULTI_TLB 1
......@@ -75,4 +73,134 @@
# endif
#endif
#ifndef _TLB
#error Unknown TLB model
#endif
/*
* Data Abort Model
* ================
*
* We have the following to choose from:
* arm6 - ARM6 style
* arm7 - ARM7 style
* v4_early - ARMv4 without Thumb early abort handler
* v4t_late - ARMv4 with Thumb late abort handler
* v4t_early - ARMv4 with Thumb early abort handler
* v5ej_early - ARMv5 with Thumb and Java early abort handler
*/
#undef CPU_ABORT_HANDLER
#undef MULTI_ABORT
#if defined(CONFIG_CPU_ARM610)
# ifdef CPU_ABORT_HANDLER
# define MULTI_ABORT 1
# else
# define CPU_ABORT_HANDLER cpu_arm6_data_abort
# endif
#endif
#if defined(CONFIG_CPU_ARM710)
# ifdef CPU_ABORT_HANDLER
# define MULTI_ABORT 1
# else
# define CPU_ABORT_HANDLER cpu_arm7_data_abort
# endif
#endif
#if defined(CONFIG_CPU_ARM720T)
# ifdef CPU_ABORT_HANDLER
# define MULTI_ABORT 1
# else
# define CPU_ABORT_HANDLER v4t_late_abort
# endif
#endif
#if defined(CONFIG_CPU_SA110) || defined(CONFIG_CPU_SA1100)
# ifdef CPU_ABORT_HANDLER
# define MULTI_ABORT 1
# else
# define CPU_ABORT_HANDLER v4_early_abort
# endif
#endif
#if defined(CONFIG_CPU_ARM920T) || defined(CONFIG_CPU_ARM922T) || \
defined(CONFIG_CPU_ARM1020) || defined(CONFIG_CPU_XSCALE)
# ifdef CPU_ABORT_HANDLER
# define MULTI_ABORT 1
# else
# define CPU_ABORT_HANDLER v4t_early_abort
# endif
#endif
#if defined(CONFIG_CPU_ARM926T)
# ifdef CPU_ABORT_HANDLER
# define MULTI_ABORT 1
# else
# define CPU_ABORT_HANDLER v5ej_early_abort
# endif
#endif
#ifndef CPU_ABORT_HANDLER
#error Unknown data abort handler type
#endif
/*
* User Space Model
* ================
*
* This section selects the correct set of functions for dealing with
* page-based copying and clearing for user space for the particular
* processor(s) we're building for.
*
* We have the following to choose from:
* v3 - ARMv3
* v4 - ARMv4 without minicache
* v4_mc - ARMv4 with minicache
* v5te_mc - ARMv5TE with minicache
*/
#undef _USER
#undef MULTI_USER
#if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710)
# ifdef _USER
# define MULTI_USER 1
# else
# define _USER v3
# endif
#endif
#if defined(CONFIG_CPU_ARM720T) || defined(CONFIG_CPU_ARM920T) || \
defined(CONFIG_CPU_ARM922T) || defined(CONFIG_CPU_ARM926T) || \
defined(CONFIG_CPU_SA110) || defined(CONFIG_CPU_ARM1020)
# ifdef _USER
# define MULTI_USER 1
# else
# define _USER v4
# endif
#endif
#if defined(CONFIG_CPU_SA1100)
# ifdef _USER
# define MULTI_USER 1
# else
# define _USER v4_mc
# endif
#endif
#if defined(CONFIG_CPU_XSCALE)
# ifdef _USER
# define MULTI_USER 1
# else
# define _USER v5te_mc
# endif
#endif
#ifndef _USER
#error Unknown user operations model
#endif
#endif
......@@ -19,12 +19,6 @@ struct hw_pci {
/* Setup bus resources */
void (*setup_resources)(struct resource **);
/*
* This is the offset of PCI memory base registers
* to physical memory.
*/
unsigned long mem_offset;
/* IRQ swizzle */
u8 (*swizzle)(struct pci_dev *dev, u8 *pin);
......
......@@ -9,25 +9,49 @@
#ifdef __KERNEL__
#ifndef __ASSEMBLY__
#define STRICT_MM_TYPECHECKS
#include <asm/glue.h>
#define clear_page(page) memzero((void *)(page), PAGE_SIZE)
extern void copy_page(void *to, void *from);
struct cpu_user_fns {
void (*cpu_clear_user_page)(void *p, unsigned long user);
void (*cpu_copy_user_page)(void *to, const void *from,
unsigned long user);
};
#ifdef MULTI_USER
extern struct cpu_user_fns cpu_user;
#define __cpu_clear_user_page cpu_user.cpu_clear_user_page
#define __cpu_copy_user_page cpu_user.cpu_copy_user_page
#else
#define __cpu_clear_user_page __glue(_USER,_clear_user_page)
#define __cpu_copy_user_page __glue(_USER,_copy_user_page)
extern void __cpu_clear_user_page(void *p, unsigned long user);
extern void __cpu_copy_user_page(void *to, const void *from,
unsigned long user);
#endif
#define clear_user_page(addr,vaddr) \
do { \
preempt_disable(); \
cpu_clear_user_page(addr, vaddr); \
__cpu_clear_user_page(addr, vaddr); \
preempt_enable(); \
} while (0)
#define copy_user_page(to,from,vaddr) \
do { \
preempt_disable(); \
cpu_copy_user_page(to, from, vaddr); \
__cpu_copy_user_page(to, from, vaddr); \
preempt_enable(); \
} while (0)
#define clear_page(page) memzero((void *)(page), PAGE_SIZE)
extern void copy_page(void *to, void *from);
#undef STRICT_MM_TYPECHECKS
#ifdef STRICT_MM_TYPECHECKS
/*
* These are used to make use of C type-checking..
......
......@@ -28,8 +28,6 @@
/*
* CPU_NAME - the prefix for CPU related functions
* CPU_ABRT - the prefix for the CPU abort decoding function
* MMU_ARCH - the prefix for copy_user_page/clear_user_page
*/
#ifdef CONFIG_CPU_32
......@@ -40,8 +38,6 @@
# define MULTI_CPU
# else
# define CPU_NAME cpu_arm6
# define CPU_ABRT cpu_arm6
# define MMU_ARCH armv3
# endif
# endif
# ifdef CONFIG_CPU_ARM710
......@@ -50,8 +46,6 @@
# define MULTI_CPU
# else
# define CPU_NAME cpu_arm7
# define CPU_ABRT cpu_arm7
# define MMU_ARCH armv3
# endif
# endif
# ifdef CONFIG_CPU_ARM720T
......@@ -60,8 +54,6 @@
# define MULTI_CPU
# else
# define CPU_NAME cpu_arm720
# define CPU_ABRT armv4t_late
# define MMU_ARCH armv4
# endif
# endif
# ifdef CONFIG_CPU_ARM920T
......@@ -70,8 +62,6 @@
# define MULTI_CPU
# else
# define CPU_NAME cpu_arm920
# define CPU_ABRT armv4t_early
# define MMU_ARCH armv4
# endif
# endif
# ifdef CONFIG_CPU_ARM922T
......@@ -80,8 +70,6 @@
# define MULTI_CPU
# else
# define CPU_NAME cpu_arm922
# define CPU_ABRT armv4t_early
# define MMU_ARCH armv4
# endif
# endif
# ifdef CONFIG_CPU_ARM926T
......@@ -90,8 +78,6 @@
# define MULTI_CPU
# else
# define CPU_NAME cpu_arm926
# define CPU_ABRT armv5ej_early
# define MMU_ARCH armv4
# endif
# endif
# ifdef CONFIG_CPU_SA110
......@@ -100,8 +86,6 @@
# define MULTI_CPU
# else
# define CPU_NAME cpu_sa110
# define CPU_ABRT armv4_early
# define MMU_ARCH armv4
# endif
# endif
# ifdef CONFIG_CPU_SA1100
......@@ -110,8 +94,6 @@
# define MULTI_CPU
# else
# define CPU_NAME cpu_sa1100
# define CPU_ABRT armv4_early
# define MMU_ARCH armv4_mc
# endif
# endif
# ifdef CONFIG_CPU_ARM1020
......@@ -120,8 +102,6 @@
# define MULTI_CPU
# else
# define CPU_NAME cpu_arm1020
# define CPU_ABRT armv4t_early
# define MMU_ARCH armv4
# endif
# endif
# ifdef CONFIG_CPU_XSCALE
......@@ -130,8 +110,6 @@
# define MULTI_CPU
# else
# define CPU_NAME cpu_xscale
# define CPU_ABRT armv4t_early
# define MMU_ARCH armv5te
# endif
# endif
#endif
......
......@@ -15,6 +15,7 @@
#include <asm/proc-fns.h>
struct cpu_tlb_fns;
struct cpu_user_fns;
struct processor;
struct proc_info_item {
......@@ -42,11 +43,12 @@ struct proc_info_list {
struct proc_info_item *info;
struct processor *proc;
struct cpu_tlb_fns *tlb;
struct cpu_user_fns *user;
};
#endif /* __ASSEMBLY__ */
#define PROC_INFO_SZ 40
#define PROC_INFO_SZ 44
#define HWCAP_SWP 1
#define HWCAP_HALF 2
......
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