Commit bcace6f0 authored by Oded Gabbay's avatar Oded Gabbay

habanalabs/gaudi2: update f/w files

Update gaudi2 firmware files with the latest version.
There is no functional change.
Signed-off-by: default avatarOded Gabbay <ogabbay@kernel.org>
parent 2fd7db3c
...@@ -20,22 +20,25 @@ ...@@ -20,22 +20,25 @@
#define GAUDI2_NUM_MME 4 #define GAUDI2_NUM_MME 4
#define NUM_OF_GPIOS_PER_PORT 16
#define GAUDI2_WD_GPIO (62 % NUM_OF_GPIOS_PER_PORT)
#define GAUDI2_ARCPID_TX_MB_SIZE 0x1000 #define GAUDI2_ARCPID_TX_MB_SIZE 0x1000
#define GAUDI2_ARCPID_RX_MB_SIZE 0x400 #define GAUDI2_ARCPID_RX_MB_SIZE 0x400
#define GAUDI2_ARM_TX_MB_SIZE 0x400 #define GAUDI2_ARM_TX_MB_SIZE 0x400
#define GAUDI2_ARM_RX_MB_SIZE 0x1800 #define GAUDI2_ARM_RX_MB_SIZE 0x1800
#define GAUDI2_DCCM_BASE_ADDR 0x27020000 #define GAUDI2_DCCM_BASE_ADDR 0x27020000
#define GAUDI2_ARCPID_TX_MB_ADDR GAUDI2_DCCM_BASE_ADDR
#define GAUDI2_ARCPID_RX_MB_ADDR (GAUDI2_ARCPID_TX_MB_ADDR + \
GAUDI2_ARCPID_TX_MB_SIZE)
#define GAUDI2_ARM_TX_MB_ADDR GAUDI2_MAILBOX_BASE_ADDR #define GAUDI2_ARM_TX_MB_ADDR GAUDI2_MAILBOX_BASE_ADDR
#define GAUDI2_ARM_RX_MB_ADDR (GAUDI2_ARM_TX_MB_ADDR + \ #define GAUDI2_ARM_RX_MB_ADDR (GAUDI2_ARM_TX_MB_ADDR + \
GAUDI2_ARM_TX_MB_SIZE) GAUDI2_ARM_TX_MB_SIZE)
#define GAUDI2_ARCPID_TX_MB_ADDR (GAUDI2_ARM_RX_MB_ADDR + GAUDI2_ARM_RX_MB_SIZE)
#define GAUDI2_ARCPID_RX_MB_ADDR (GAUDI2_ARCPID_TX_MB_ADDR + GAUDI2_ARCPID_TX_MB_SIZE)
#define GAUDI2_ARM_TX_MB_OFFSET (GAUDI2_ARM_TX_MB_ADDR - \ #define GAUDI2_ARM_TX_MB_OFFSET (GAUDI2_ARM_TX_MB_ADDR - \
GAUDI2_SP_SRAM_BASE_ADDR) GAUDI2_SP_SRAM_BASE_ADDR)
...@@ -58,7 +61,9 @@ struct gaudi2_cold_rst_data { ...@@ -58,7 +61,9 @@ struct gaudi2_cold_rst_data {
u32 spsram_init_done : 1; u32 spsram_init_done : 1;
u32 fake_security_enable : 1; u32 fake_security_enable : 1;
u32 fake_sig_validation_en : 1; u32 fake_sig_validation_en : 1;
u32 reserved : 26; u32 bist_skip_enable : 1;
u32 bist_need_iatu_config : 1;
u32 reserved : 24;
}; };
__le32 data; __le32 data;
}; };
...@@ -77,10 +82,10 @@ enum gaudi2_rst_src { ...@@ -77,10 +82,10 @@ enum gaudi2_rst_src {
}; };
struct gaudi2_redundancy_ctx { struct gaudi2_redundancy_ctx {
int redundant_hbm; __le32 redundant_hbm;
int redundant_edma; __le32 redundant_edma;
int redundant_tpc; __le32 redundant_tpc;
int redundant_vdec; __le32 redundant_vdec;
__le64 hbm_mask; __le64 hbm_mask;
__le64 edma_mask; __le64 edma_mask;
__le64 tpc_mask; __le64 tpc_mask;
......
...@@ -24,14 +24,14 @@ ...@@ -24,14 +24,14 @@
#define mmGIC_HOST_HALT_IRQ_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_10 #define mmGIC_HOST_HALT_IRQ_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_10
#define mmGIC_HOST_INTS_IRQ_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_11 #define mmGIC_HOST_INTS_IRQ_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_11
#define mmGIC_HOST_SOFT_RST_IRQ_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_12 #define mmGIC_HOST_SOFT_RST_IRQ_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_12
#define mmEEPROM_COPY_LOCATION_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_13
#define mmCPU_RST_STATUS_TO_HOST mmPSOC_GLOBAL_CONF_SCRATCHPAD_14 #define mmCPU_RST_STATUS_TO_HOST mmPSOC_GLOBAL_CONF_SCRATCHPAD_14
#define mmENGINE_ARC_IRQ_CTRL_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_15
#define mmPID_CFG_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_18
/* /*
* TODO: mmGIC_RAZWI_STATUS_REG is temporary * Single scratchpad register used for all ARCs to notify dccm queue full event to FW.
* macro and to be removed after GAUDI2 PO * So a new event would overwrite any unhandled previous event. In other words, incase
* of multiple events before previous ones are handled, last one would be considered.
*/ */
#define mmENGINE_ARC_IRQ_CTRL_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_15
#define mmPID_CFG_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_18
#define mmGIC_RAZWI_STATUS_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_19 #define mmGIC_RAZWI_STATUS_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_19
#define mmCPU_BOOT_DEV_STS0 mmPSOC_GLOBAL_CONF_SCRATCHPAD_20 #define mmCPU_BOOT_DEV_STS0 mmPSOC_GLOBAL_CONF_SCRATCHPAD_20
#define mmCPU_BOOT_DEV_STS1 mmPSOC_GLOBAL_CONF_SCRATCHPAD_21 #define mmCPU_BOOT_DEV_STS1 mmPSOC_GLOBAL_CONF_SCRATCHPAD_21
...@@ -40,11 +40,10 @@ ...@@ -40,11 +40,10 @@
#define mmCPU_BOOT_ERR1 mmPSOC_GLOBAL_CONF_SCRATCHPAD_25 #define mmCPU_BOOT_ERR1 mmPSOC_GLOBAL_CONF_SCRATCHPAD_25
#define mmUPD_STS mmPSOC_GLOBAL_CONF_SCRATCHPAD_26 #define mmUPD_STS mmPSOC_GLOBAL_CONF_SCRATCHPAD_26
#define mmUPD_CMD mmPSOC_GLOBAL_CONF_SCRATCHPAD_27 #define mmUPD_CMD mmPSOC_GLOBAL_CONF_SCRATCHPAD_27
#define mmUBOOT_VER_OFFSET mmPSOC_GLOBAL_CONF_SCRATCHPAD_29 #define mmPPBOOT_VER_OFFSET mmPSOC_GLOBAL_CONF_SCRATCHPAD_28
#define mmRDWR_TEST mmPSOC_GLOBAL_CONF_SCRATCHPAD_30 #define mmRDWR_TEST mmPSOC_GLOBAL_CONF_SCRATCHPAD_30
#define mmBTL_ID mmPSOC_GLOBAL_CONF_SCRATCHPAD_31 #define mmBTL_ID mmPSOC_GLOBAL_CONF_SCRATCHPAD_31
#define mmRST_SRC mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_0 #define mmRST_SRC mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_0
#define mmPREBOOT_PCIE_EN mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_1
#define mmCOLD_RST_DATA mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_2 #define mmCOLD_RST_DATA mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_2
#define mmUPD_PENDING_STS mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_3 #define mmUPD_PENDING_STS mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_3
#define mmPID_CMD_REQ_REG mmPSOC_PID_PID_CMD_0 #define mmPID_CMD_REQ_REG mmPSOC_PID_PID_CMD_0
...@@ -55,5 +54,8 @@ ...@@ -55,5 +54,8 @@
#define mmPID_CMD_TELEMETRY_REG_0_HI mmPSOC_PID_PID_CMD_5 #define mmPID_CMD_TELEMETRY_REG_0_HI mmPSOC_PID_PID_CMD_5
#define mmPID_CMD_TELEMETRY_REG_1 mmPSOC_PID_PID_CMD_6 #define mmPID_CMD_TELEMETRY_REG_1 mmPSOC_PID_PID_CMD_6
#define mmPID_CMD_TELEMETRY_REG_1_HI mmPSOC_PID_PID_CMD_7 #define mmPID_CMD_TELEMETRY_REG_1_HI mmPSOC_PID_PID_CMD_7
#define mmWD_GPIO_OUTSET_REG mmPSOC_GPIO3_OUTENSET
#define mmWD_GPIO_DATAOUT_REG mmPSOC_GPIO3_DATAOUT
#define mmSTM_PROFILER_SPE_REG mmPSOC_STM_STMSPER
#endif /* GAUDI2_REG_MAP_H_ */ #endif /* GAUDI2_REG_MAP_H_ */
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