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Commit bdaad158 authored by Scott Feldman's avatar Scott Feldman Committed by Stephen Hemminger
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[e1000] misc whitespace cleanup, changelog 

* misc whitespace cleanup, changelog
parent 95625b88
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Showing with 164 additions and 155 deletions
drivers/net/e1000/e1000_hw.c
View file @ bdaad158
......@@ -41,7 +41,8 @@ static int32_t e1000_phy_force_speed_duplex(struct e1000_hw *hw);
static int32_t e1000_config_mac_to_phy(struct e1000_hw *hw);
static void e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl);
static void e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl);
static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data, uint16_t count);
static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data,
uint16_t count);
static uint16_t e1000_shift_in_mdi_bits(struct e1000_hw *hw);
static int32_t e1000_phy_reset_dsp(struct e1000_hw *hw);
static int32_t e1000_write_eeprom_spi(struct e1000_hw *hw, uint16_t offset,
......@@ -52,7 +53,8 @@ static int32_t e1000_write_eeprom_microwire(struct e1000_hw *hw,
static int32_t e1000_spi_eeprom_ready(struct e1000_hw *hw);
static void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t *eecd);
static void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t *eecd);
static void e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data, uint16_t count);
static void e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data,
uint16_t count);
static int32_t e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr,
uint16_t phy_data);
static int32_t e1000_read_phy_reg_ex(struct e1000_hw *hw,uint32_t reg_addr,
......@@ -257,7 +259,6 @@ e1000_set_mac_type(struct e1000_hw *hw)
return -E1000_ERR_MAC_TYPE;
}
return E1000_SUCCESS;
}
......@@ -342,12 +343,6 @@ e1000_reset_hw(struct e1000_hw *hw)
*/
msec_delay(10);
/* Issue a global reset to the MAC. This will reset the chip's
* transmit, receive, DMA, and link units. It will not effect
* the current PCI configuration. The global reset bit is self-
* clearing, and should clear within a microsecond.
*/
DEBUGOUT("Issuing a global reset to MAC\n");
ctrl = E1000_READ_REG(hw, CTRL);
/* Must reset the PHY before resetting the MAC */
......@@ -356,6 +351,13 @@ e1000_reset_hw(struct e1000_hw *hw)
msec_delay(5);
}
/* Issue a global reset to the MAC. This will reset the chip's
* transmit, receive, DMA, and link units. It will not effect
* the current PCI configuration. The global reset bit is self-
* clearing, and should clear within a microsecond.
*/
DEBUGOUT("Issuing a global reset to MAC\n");
switch(hw->mac_type) {
case e1000_82544:
case e1000_82540:
......@@ -3083,7 +3085,8 @@ e1000_shift_out_ee_bits(struct e1000_hw *hw,
* hw - Struct containing variables accessed by shared code
*****************************************************************************/
static uint16_t
e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count)
e1000_shift_in_ee_bits(struct e1000_hw *hw,
uint16_t count)
{
uint32_t eecd;
uint32_t i;
......@@ -4359,8 +4362,7 @@ e1000_update_adaptive(struct e1000_hw *hw)
DEBUGFUNC("e1000_update_adaptive");
if(hw->adaptive_ifs) {
if((hw->collision_delta * hw->ifs_ratio) >
hw->tx_packet_delta) {
if((hw->collision_delta * hw->ifs_ratio) > hw->tx_packet_delta) {
if(hw->tx_packet_delta > MIN_NUM_XMITS) {
hw->in_ifs_mode = TRUE;
if(hw->current_ifs_val < hw->ifs_max_val) {
......@@ -4372,8 +4374,7 @@ e1000_update_adaptive(struct e1000_hw *hw)
}
}
} else {
if((hw->in_ifs_mode == TRUE) &&
(hw->tx_packet_delta <= MIN_NUM_XMITS)) {
if(hw->in_ifs_mode && (hw->tx_packet_delta <= MIN_NUM_XMITS)) {
hw->current_ifs_val = 0;
hw->in_ifs_mode = FALSE;
E1000_WRITE_REG(hw, AIT, 0);
......
drivers/net/e1000/e1000_hw.h
View file @ bdaad158
......@@ -33,9 +33,9 @@
#ifndef _E1000_HW_H_
#define _E1000_HW_H_
#include "e1000_osdep.h"
/* Forward declarations of structures used by the shared code */
struct e1000_hw;
struct e1000_hw_stats;
......@@ -425,7 +425,7 @@ int32_t e1000_set_d3_lplu_state(struct e1000_hw *hw, boolean_t active);
E1000_IMS_RXSEQ | \
E1000_IMS_LSC)
/* The number of high/low register pairs in the RAR. The RAR (Receive Address
/* Number of high/low register pairs in the RAR. The RAR (Receive Address
* Registers) holds the directed and multicast addresses that we monitor. We
* reserve one of these spots for our directed address, allowing us room for
* E1000_RAR_ENTRIES - 1 multicast addresses.
......@@ -579,7 +579,7 @@ struct e1000_rar {
volatile uint32_t high; /* receive address high */
};
/* The number of entries in the Multicast Table Array (MTA). */
/* Number of entries in the Multicast Table Array (MTA). */
#define E1000_NUM_MTA_REGISTERS 128
/* IPv4 Address Table Entry */
......@@ -1546,7 +1546,7 @@ struct e1000_hw {
#define E1000_HDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE
#define E1000_COLD_SHIFT 12
/* The number of Transmit and Receive Descriptors must be a multiple of 8 */
/* Number of Transmit and Receive Descriptors must be a multiple of 8 */
#define REQ_TX_DESCRIPTOR_MULTIPLE 8
#define REQ_RX_DESCRIPTOR_MULTIPLE 8
......@@ -1613,35 +1613,30 @@ struct e1000_hw {
#define PCIX_STATUS_HI_MMRBC_2K 0x2
/* The number of bits that we need to shift right to move the "pause"
* bits from the EEPROM (bits 13:12) to the "pause" (bits 8:7) field
* in the TXCW register
/* Number of bits required to shift right the "pause" bits from the
* EEPROM (bits 13:12) to the "pause" (bits 8:7) field in the TXCW register.
*/
#define PAUSE_SHIFT 5
/* The number of bits that we need to shift left to move the "SWDPIO"
* bits from the EEPROM (bits 8:5) to the "SWDPIO" (bits 25:22) field
* in the CTRL register
/* Number of bits required to shift left the "SWDPIO" bits from the
* EEPROM (bits 8:5) to the "SWDPIO" (bits 25:22) field in the CTRL register.
*/
#define SWDPIO_SHIFT 17
/* The number of bits that we need to shift left to move the "SWDPIO_EXT"
* bits from the EEPROM word F (bits 7:4) to the bits 11:8 of The
* Extended CTRL register.
* in the CTRL register
/* Number of bits required to shift left the "SWDPIO_EXT" bits from the
* EEPROM word F (bits 7:4) to the bits 11:8 of The Extended CTRL register.
*/
#define SWDPIO__EXT_SHIFT 4
/* The number of bits that we need to shift left to move the "ILOS"
* bit from the EEPROM (bit 4) to the "ILOS" (bit 7) field
* in the CTRL register
/* Number of bits required to shift left the "ILOS" bit from the EEPROM
* (bit 4) to the "ILOS" (bit 7) field in the CTRL register.
*/
#define ILOS_SHIFT 3
#define RECEIVE_BUFFER_ALIGN_SIZE (256)
/* The number of milliseconds we wait for auto-negotiation to complete */
/* Number of milliseconds we wait for auto-negotiation to complete */
#define LINK_UP_TIMEOUT 500
#define E1000_TX_BUFFER_SIZE ((uint32_t)1514)
......@@ -1987,7 +1982,6 @@ struct e1000_hw {
#define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */
#define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */
/* IGP01E1000 Specific Port Config Register - R/W */
#define IGP01E1000_PSCFR_AUTO_MDIX_PAR_DETECT 0x0010
#define IGP01E1000_PSCFR_PRE_EN 0x0020
......@@ -2061,6 +2055,7 @@ struct e1000_hw {
#define IGP01E1000_GMII_FLEX_SPD 0x10 /* Enable flexible speed
* on Link-Up */
#define IGP01E1000_GMII_SPD 0x20 /* Enable SPD */
/* IGP01E1000 Analog Register */
#define IGP01E1000_ANALOG_SPARE_FUSE_STATUS 0x20D1
#define IGP01E1000_ANALOG_FUSE_STATUS 0x20D0
......
drivers/net/e1000/e1000_main.c
View file @ bdaad158
......@@ -29,6 +29,22 @@
#include "e1000.h"
/* Change Log
*
* 5.2.16 8/8/03
* o Added support for new controllers: 82545GM, 82546GB, 82541/7_B1
* o Bug fix: reset h/w before first EEPROM read because we don't know
* who may have been messing with the device before we got there.
* [Dave Johnson (ddj -a-t- cascv.brown.edu)]
* o Bug fix: read the correct work from EEPROM to detect programmed
* WoL settings.
* o Bug fix: TSO would hang if space left in FIFO was being miscalculated
* when mss dropped without a correspoding drop in the DMA buffer size.
* o ASF for Fiber nics isn't supported.
* o Bug fix: Workaround added for potential hang with 82544 running in
* PCI-X if send buffer terminates within an evenly-aligned dword.
* o Feature: Add support for ethtool flow control setting.
* o Feature: Add support for ethtool TSO setting.
* o Feature: Increase default Tx Descriptor count to 1024 for >= 82544.
*
* 5.1.13 5/28/03
* o Bug fix: request_irq() failure resulted in freeing resources twice!
......@@ -39,18 +55,11 @@
* o Cleanup: s/int/unsigned int/ for descriptor ring indexes.
*
* 5.1.11 5/6/03
* o Feature: Added support for 82546EB (Quad-port) hardware.
* o Feature: Added support for Diagnostics through Ethtool.
* o Cleanup: Removed /proc support.
* o Cleanup: Removed proprietary IDIAG interface.
* o Bug fix: TSO bug fixes.
*
* 5.0.42 3/5/03
*/
char e1000_driver_name[] = "e1000";
char e1000_driver_string[] = "Intel(R) PRO/1000 Network Driver";
char e1000_driver_version[] = "5.1.13-k2";
char e1000_driver_version[] = "5.2.16-k1";
char e1000_copyright[] = "Copyright (c) 1999-2003 Intel Corporation.";
/* e1000_pci_tbl - PCI Device ID Table
......@@ -2078,6 +2087,7 @@ e1000_intr(int irq, void *data, struct pt_regs *regs)
!e1000_clean_tx_irq(adapter))
break;
#endif
return IRQ_HANDLED;
}
......@@ -2736,7 +2746,7 @@ e1000_notify_reboot(struct notifier_block *nb, unsigned long event, void *p)
case SYS_DOWN:
case SYS_HALT:
case SYS_POWER_OFF:
while ((pdev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, pdev)) != NULL) {
while((pdev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, pdev))) {
if(pci_dev_driver(pdev) == &e1000_driver)
e1000_suspend(pdev, 3);
}
......
drivers/net/e1000/e1000_osdep.h
View file @ bdaad158
......@@ -55,10 +55,13 @@
#define CMD_MEM_WRT_INVALIDATE PCI_COMMAND_INVALIDATE
typedef enum {
#undef FALSE
FALSE = 0,
#undef TRUE
TRUE = 1
} boolean_t;
#undef ASSERT
#define ASSERT(x) if(!(x)) BUG()
#define MSGOUT(S, A, B) printk(KERN_DEBUG S "\n", A, B)
......
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