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Commit bdc4af28 authored by Asmaa Mnebhi's avatar Asmaa Mnebhi Committed by Wolfram Sang
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i2c: mlxbf: add multi slave functionality 

Support the multi slave functionality which enables the BlueField
to be registered at up to 16 i2c slave addresses.
Reviewed-by: default avatarKhalil Blaiech <kblaiech@nvidia.com>
Signed-off-by: default avatarAsmaa Mnebhi <asmaa@nvidia.com>
Signed-off-by: default avatarWolfram Sang <wsa@kernel.org>
parent 86067ccf
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Showing with 149 additions and 171 deletions
drivers/i2c/busses/i2c-mlxbf.c
View file @ bdc4af28
...@@ -298,9 +298,6 @@ static u64 mlxbf_i2c_corepll_frequency; ...@@ -298,9 +298,6 @@ static u64 mlxbf_i2c_corepll_frequency;
#define MLXBF_I2C_SMBUS_SLAVE_ADDR_EN_BIT 7 #define MLXBF_I2C_SMBUS_SLAVE_ADDR_EN_BIT 7
#define MLXBF_I2C_SMBUS_SLAVE_ADDR_MASK GENMASK(6, 0) #define MLXBF_I2C_SMBUS_SLAVE_ADDR_MASK GENMASK(6, 0)
#define MLXBF_I2C_SLAVE_ADDR_ENABLED(addr) \
((addr) & (1 << MLXBF_I2C_SMBUS_SLAVE_ADDR_EN_BIT))
/* /*
* Timeout is given in microsends. Note also that timeout handling is not * Timeout is given in microsends. Note also that timeout handling is not
* exact. * exact.
...@@ -426,7 +423,7 @@ struct mlxbf_i2c_priv { ...@@ -426,7 +423,7 @@ struct mlxbf_i2c_priv {
u64 frequency; /* Core frequency in Hz. */ u64 frequency; /* Core frequency in Hz. */
int bus; /* Physical bus identifier. */ int bus; /* Physical bus identifier. */
int irq; int irq;
struct i2c_client *slave; struct i2c_client *slave[MLXBF_I2C_SMBUS_SLAVE_ADDR_CNT];
}; };
static struct mlxbf_i2c_resource mlxbf_i2c_coalesce_res[] = { static struct mlxbf_i2c_resource mlxbf_i2c_coalesce_res[] = {
...@@ -1543,25 +1540,23 @@ static int mlxbf_i2c_calculate_corepll_freq(struct platform_device *pdev, ...@@ -1543,25 +1540,23 @@ static int mlxbf_i2c_calculate_corepll_freq(struct platform_device *pdev,
return 0; return 0;
} }
static int mlxbf_slave_enable(struct mlxbf_i2c_priv *priv, u8 addr) static int mlxbf_i2c_slave_enable(struct mlxbf_i2c_priv *priv,
struct i2c_client *slave)
{ {
u32 slave_reg, slave_reg_tmp, slave_reg_avail, slave_addr_mask; u8 reg, reg_cnt, byte, addr_tmp;
u8 reg, reg_cnt, byte, addr_tmp, reg_avail, byte_avail; u32 slave_reg, slave_reg_tmp;
bool avail, disabled;
disabled = false;
avail = false;
if (!priv) if (!priv)
return -EPERM; return -EPERM;
reg_cnt = MLXBF_I2C_SMBUS_SLAVE_ADDR_CNT >> 2; reg_cnt = MLXBF_I2C_SMBUS_SLAVE_ADDR_CNT >> 2;
slave_addr_mask = MLXBF_I2C_SMBUS_SLAVE_ADDR_MASK;
/* /*
* Read the slave registers. There are 4 * 32-bit slave registers. * Read the slave registers. There are 4 * 32-bit slave registers.
* Each slave register can hold up to 4 * 8-bit slave configuration * Each slave register can hold up to 4 * 8-bit slave configuration:
* (7-bit address, 1 status bit (1 if enabled, 0 if not)). * 1) A 7-bit address
* 2) And a status bit (1 if enabled, 0 if not).
* Look for the next available slave register slot.
*/ */
for (reg = 0; reg < reg_cnt; reg++) { for (reg = 0; reg < reg_cnt; reg++) {
slave_reg = readl(priv->smbus->io + slave_reg = readl(priv->smbus->io +
...@@ -1576,121 +1571,87 @@ static int mlxbf_slave_enable(struct mlxbf_i2c_priv *priv, u8 addr) ...@@ -1576,121 +1571,87 @@ static int mlxbf_slave_enable(struct mlxbf_i2c_priv *priv, u8 addr)
addr_tmp = slave_reg_tmp & GENMASK(7, 0); addr_tmp = slave_reg_tmp & GENMASK(7, 0);
/* /*
* Mark the first available slave address slot, i.e. its * If an enable bit is not set in the
* enabled bit should be unset. This slot might be used * MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG register, then the
* later on to register our slave. * slave address slot associated with that bit is
*/ * free. So set the enable bit and write the
if (!avail && !MLXBF_I2C_SLAVE_ADDR_ENABLED(addr_tmp)) { * slave address bits.
avail = true; */
reg_avail = reg; if (!(addr_tmp & MLXBF_I2C_SMBUS_SLAVE_ADDR_EN_BIT)) {
byte_avail = byte; slave_reg &= ~(MLXBF_I2C_SMBUS_SLAVE_ADDR_MASK << (byte * 8));
slave_reg_avail = slave_reg; slave_reg |= (slave->addr << (byte * 8));
} slave_reg |= MLXBF_I2C_SMBUS_SLAVE_ADDR_EN_BIT << (byte * 8);
writel(slave_reg, priv->smbus->io +
MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG +
(reg * 0x4));
/* /*
* Parse slave address bytes and check whether the * Set the slave at the corresponding index.
* slave address already exists and it's enabled,
* i.e. most significant bit is set.
*/ */
if ((addr_tmp & slave_addr_mask) == addr) { priv->slave[(reg * 4) + byte] = slave;
if (MLXBF_I2C_SLAVE_ADDR_ENABLED(addr_tmp))
return 0; return 0;
disabled = true;
break;
} }
/* Parse next byte. */ /* Parse next byte. */
slave_reg_tmp >>= 8; slave_reg_tmp >>= 8;
} }
/* Exit the loop if the slave address is found. */
if (disabled)
break;
}
if (!avail && !disabled)
return -EINVAL; /* No room for a new slave address. */
if (avail && !disabled) {
reg = reg_avail;
byte = byte_avail;
/* Set the slave address. */
slave_reg_avail &= ~(slave_addr_mask << (byte * 8));
slave_reg_avail |= addr << (byte * 8);
slave_reg = slave_reg_avail;
} }
/* Enable the slave address and update the register. */ return -EBUSY;
slave_reg |= (1 << MLXBF_I2C_SMBUS_SLAVE_ADDR_EN_BIT) << (byte * 8);
writel(slave_reg, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG +
reg * 0x4);
return 0;
} }
static int mlxbf_slave_disable(struct mlxbf_i2c_priv *priv) static int mlxbf_i2c_slave_disable(struct mlxbf_i2c_priv *priv, u8 addr)
{ {
u32 slave_reg, slave_reg_tmp, slave_addr_mask; u8 addr_tmp, reg, reg_cnt, byte;
u8 addr, addr_tmp, reg, reg_cnt, slave_byte; u32 slave_reg, slave_reg_tmp;
struct i2c_client *client = priv->slave;
bool exist;
exist = false;
addr = client->addr;
reg_cnt = MLXBF_I2C_SMBUS_SLAVE_ADDR_CNT >> 2; reg_cnt = MLXBF_I2C_SMBUS_SLAVE_ADDR_CNT >> 2;
slave_addr_mask = MLXBF_I2C_SMBUS_SLAVE_ADDR_MASK;
/* /*
* Read the slave registers. There are 4 * 32-bit slave registers. * Read the slave registers. There are 4 * 32-bit slave registers.
* Each slave register can hold up to 4 * 8-bit slave configuration * Each slave register can hold up to 4 * 8-bit slave configuration:
* (7-bit address, 1 status bit (1 if enabled, 0 if not)). * 1) A 7-bit address
* 2) And a status bit (1 if enabled, 0 if not).
* Check if addr is present in the registers.
*/ */
for (reg = 0; reg < reg_cnt; reg++) { for (reg = 0; reg < reg_cnt; reg++) {
slave_reg = readl(priv->smbus->io + slave_reg = readl(priv->smbus->io +
MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG + reg * 0x4); MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG + reg * 0x4);
/* Check whether the address slots are empty. */ /* Check whether the address slots are empty. */
if (slave_reg == 0) if (!slave_reg)
continue; continue;
/* /*
* Each register holds 4 slave addresses. So, we have to keep * Check if addr matches any of the 4 slave addresses
* the byte order consistent with the value read in order to * in the register.
* update the register correctly, if needed.
*/ */
slave_reg_tmp = slave_reg; slave_reg_tmp = slave_reg;
slave_byte = 0; for (byte = 0; byte < 4; byte++) {
while (slave_reg_tmp != 0) { addr_tmp = slave_reg_tmp & MLXBF_I2C_SMBUS_SLAVE_ADDR_MASK;
addr_tmp = slave_reg_tmp & slave_addr_mask;
/* /*
* Parse slave address bytes and check whether the * Parse slave address bytes and check whether the
* slave address already exists. * slave address already exists.
*/ */
if (addr_tmp == addr) { if (addr_tmp == addr) {
exist = true; /* Clear the slave address slot. */
break; slave_reg &= ~(GENMASK(7, 0) << (byte * 8));
writel(slave_reg, priv->smbus->io +
MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG +
(reg * 0x4));
/* Free slave at the corresponding index */
priv->slave[(reg * 4) + byte] = NULL;
return 0;
} }
/* Parse next byte. */ /* Parse next byte. */
slave_reg_tmp >>= 8; slave_reg_tmp >>= 8;
slave_byte += 1;
} }
/* Exit the loop if the slave address is found. */
if (exist)
break;
} }
if (!exist) return -ENXIO;
return 0; /* Slave is not registered, nothing to do. */
/* Cleanup the slave address slot. */
slave_reg &= ~(GENMASK(7, 0) << (slave_byte * 8));
writel(slave_reg, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG +
reg * 0x4);
return 0;
} }
static int mlxbf_i2c_init_coalesce(struct platform_device *pdev, static int mlxbf_i2c_init_coalesce(struct platform_device *pdev,
...@@ -1852,72 +1813,81 @@ static bool mlxbf_smbus_slave_wait_for_idle(struct mlxbf_i2c_priv *priv, ...@@ -1852,72 +1813,81 @@ static bool mlxbf_smbus_slave_wait_for_idle(struct mlxbf_i2c_priv *priv,
return false; return false;
} }
/* Send byte to 'external' smbus master. */ static struct i2c_client *mlxbf_i2c_get_slave_from_addr(
static int mlxbf_smbus_irq_send(struct mlxbf_i2c_priv *priv, u8 recv_bytes) struct mlxbf_i2c_priv *priv, u8 addr)
{ {
u8 data_desc[MLXBF_I2C_SLAVE_DATA_DESC_SIZE] = { 0 }; int i;
u8 write_size, pec_en, addr, byte, value, byte_cnt, desc_size;
struct i2c_client *slave = priv->slave;
u32 control32, data32;
int ret;
if (!slave) for (i = 0; i < MLXBF_I2C_SMBUS_SLAVE_ADDR_CNT; i++) {
return -EINVAL; if (!priv->slave[i])
continue;
addr = 0; if (priv->slave[i]->addr == addr)
byte = 0; return priv->slave[i];
desc_size = MLXBF_I2C_SLAVE_DATA_DESC_SIZE; }
return NULL;
}
/*
* Send byte to 'external' smbus master. This function is executed when
* an external smbus master wants to read data from the BlueField.
*/
static int mlxbf_i2c_irq_send(struct mlxbf_i2c_priv *priv, u8 recv_bytes)
{
u8 data_desc[MLXBF_I2C_SLAVE_DATA_DESC_SIZE] = { 0 };
u8 write_size, pec_en, addr, value, byte_cnt;
struct i2c_client *slave;
u32 control32, data32;
int ret = 0;
/* /*
* Read bytes received from the external master. These bytes should * Read the first byte received from the external master to
* be located in the first data descriptor register of the slave GW. * determine the slave address. This byte is located in the
* These bytes are the slave address byte and the internal register * first data descriptor register of the slave GW.
* address, if supplied.
*/ */
if (recv_bytes > 0) {
data32 = ioread32be(priv->smbus->io + data32 = ioread32be(priv->smbus->io +
MLXBF_I2C_SLAVE_DATA_DESC_ADDR); MLXBF_I2C_SLAVE_DATA_DESC_ADDR);
/* Parse the received bytes. */
switch (recv_bytes) {
case 2:
byte = (data32 >> 8) & GENMASK(7, 0);
fallthrough;
case 1:
addr = (data32 & GENMASK(7, 0)) >> 1; addr = (data32 & GENMASK(7, 0)) >> 1;
}
/* Check whether it's our slave address. */ /*
if (slave->addr != addr) * Check if the slave address received in the data descriptor register
return -EINVAL; * matches any of the slave addresses registered. If there is a match,
* set the slave.
*/
slave = mlxbf_i2c_get_slave_from_addr(priv, addr);
if (!slave) {
ret = -ENXIO;
goto clear_csr;
} }
/* /*
* I2C read transactions may start by a WRITE followed by a READ. * An I2C read can consist of a WRITE bit transaction followed by
* Indeed, most slave devices would expect the internal address * a READ bit transaction. Indeed, slave devices often expect
* following the slave address byte. So, write that byte first, * the slave address to be followed by the internal address.
* and then, send the requested data bytes to the master. * So, write the internal address byte first, and then, send the
* requested data to the master.
*/ */
if (recv_bytes > 1) { if (recv_bytes > 1) {
i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value); i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value);
value = byte; value = (data32 >> 8) & GENMASK(7, 0);
ret = i2c_slave_event(slave, I2C_SLAVE_WRITE_RECEIVED, ret = i2c_slave_event(slave, I2C_SLAVE_WRITE_RECEIVED,
&value); &value);
i2c_slave_event(slave, I2C_SLAVE_STOP, &value); i2c_slave_event(slave, I2C_SLAVE_STOP, &value);
if (ret < 0) if (ret < 0)
return ret; goto clear_csr;
} }
/* /*
* Now, send data to the master; currently, the driver supports * Send data to the master. Currently, the driver supports
* READ_BYTE, READ_WORD and BLOCK READ protocols. Note that the * READ_BYTE, READ_WORD and BLOCK READ protocols. The
* hardware can send up to 128 bytes per transfer. That is the * hardware can send up to 128 bytes per transfer which is
* size of its data registers. * the total size of the data registers.
*/ */
i2c_slave_event(slave, I2C_SLAVE_READ_REQUESTED, &value); i2c_slave_event(slave, I2C_SLAVE_READ_REQUESTED, &value);
for (byte_cnt = 0; byte_cnt < desc_size; byte_cnt++) { for (byte_cnt = 0; byte_cnt < MLXBF_I2C_SLAVE_DATA_DESC_SIZE; byte_cnt++) {
data_desc[byte_cnt] = value; data_desc[byte_cnt] = value;
i2c_slave_event(slave, I2C_SLAVE_READ_PROCESSED, &value); i2c_slave_event(slave, I2C_SLAVE_READ_PROCESSED, &value);
} }
...@@ -1925,8 +1895,6 @@ static int mlxbf_smbus_irq_send(struct mlxbf_i2c_priv *priv, u8 recv_bytes) ...@@ -1925,8 +1895,6 @@ static int mlxbf_smbus_irq_send(struct mlxbf_i2c_priv *priv, u8 recv_bytes)
/* Send a stop condition to the backend. */ /* Send a stop condition to the backend. */
i2c_slave_event(slave, I2C_SLAVE_STOP, &value); i2c_slave_event(slave, I2C_SLAVE_STOP, &value);
/* Handle the actual transfer. */
/* Set the number of bytes to write to master. */ /* Set the number of bytes to write to master. */
write_size = (byte_cnt - 1) & 0x7f; write_size = (byte_cnt - 1) & 0x7f;
...@@ -1949,38 +1917,44 @@ static int mlxbf_smbus_irq_send(struct mlxbf_i2c_priv *priv, u8 recv_bytes) ...@@ -1949,38 +1917,44 @@ static int mlxbf_smbus_irq_send(struct mlxbf_i2c_priv *priv, u8 recv_bytes)
*/ */
mlxbf_smbus_slave_wait_for_idle(priv, MLXBF_I2C_SMBUS_TIMEOUT); mlxbf_smbus_slave_wait_for_idle(priv, MLXBF_I2C_SMBUS_TIMEOUT);
clear_csr:
/* Release the Slave GW. */ /* Release the Slave GW. */
writel(0x0, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES); writel(0x0, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES);
writel(0x0, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_PEC); writel(0x0, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_PEC);
writel(0x1, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_READY); writel(0x1, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_READY);
return 0; return ret;
} }
/* Receive bytes from 'external' smbus master. */ /*
static int mlxbf_smbus_irq_recv(struct mlxbf_i2c_priv *priv, u8 recv_bytes) * Receive bytes from 'external' smbus master. This function is executed when
* an external smbus master wants to write data to the BlueField.
*/
static int mlxbf_i2c_irq_recv(struct mlxbf_i2c_priv *priv, u8 recv_bytes)
{ {
u8 data_desc[MLXBF_I2C_SLAVE_DATA_DESC_SIZE] = { 0 }; u8 data_desc[MLXBF_I2C_SLAVE_DATA_DESC_SIZE] = { 0 };
struct i2c_client *slave = priv->slave; struct i2c_client *slave;
u8 value, byte, addr; u8 value, byte, addr;
int ret = 0; int ret = 0;
if (!slave)
return -EINVAL;
/* Read data from Slave GW data descriptor. */ /* Read data from Slave GW data descriptor. */
mlxbf_i2c_smbus_read_data(priv, data_desc, recv_bytes, mlxbf_i2c_smbus_read_data(priv, data_desc, recv_bytes,
MLXBF_I2C_SLAVE_DATA_DESC_ADDR); MLXBF_I2C_SLAVE_DATA_DESC_ADDR);
/* Check whether its our slave address. */
addr = data_desc[0] >> 1; addr = data_desc[0] >> 1;
if (slave->addr != addr)
return -EINVAL;
/* /*
* Notify the slave backend; another I2C master wants to write data * Check if the slave address received in the data descriptor register
* to us. This event is sent once the slave address and the write bit * matches any of the slave addresses registered.
* is detected. */
slave = mlxbf_i2c_get_slave_from_addr(priv, addr);
if (!slave) {
ret = -EINVAL;
goto clear_csr;
}
/*
* Notify the slave backend that an smbus master wants to write data
* to the BlueField.
*/ */
i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value); i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value);
...@@ -1993,9 +1967,13 @@ static int mlxbf_smbus_irq_recv(struct mlxbf_i2c_priv *priv, u8 recv_bytes) ...@@ -1993,9 +1967,13 @@ static int mlxbf_smbus_irq_recv(struct mlxbf_i2c_priv *priv, u8 recv_bytes)
break; break;
} }
/* Send a stop condition to the backend. */ /*
* Send a stop event to the slave backend, to signal
* the end of the write transactions.
*/
i2c_slave_event(slave, I2C_SLAVE_STOP, &value); i2c_slave_event(slave, I2C_SLAVE_STOP, &value);
clear_csr:
/* Release the Slave GW. */ /* Release the Slave GW. */
writel(0x0, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES); writel(0x0, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES);
writel(0x0, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_PEC); writel(0x0, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_PEC);
...@@ -2004,7 +1982,7 @@ static int mlxbf_smbus_irq_recv(struct mlxbf_i2c_priv *priv, u8 recv_bytes) ...@@ -2004,7 +1982,7 @@ static int mlxbf_smbus_irq_recv(struct mlxbf_i2c_priv *priv, u8 recv_bytes)
return ret; return ret;
} }
static irqreturn_t mlxbf_smbus_irq(int irq, void *ptr) static irqreturn_t mlxbf_i2c_irq(int irq, void *ptr)
{ {
struct mlxbf_i2c_priv *priv = ptr; struct mlxbf_i2c_priv *priv = ptr;
bool read, write, irq_is_set; bool read, write, irq_is_set;
...@@ -2052,9 +2030,9 @@ static irqreturn_t mlxbf_smbus_irq(int irq, void *ptr) ...@@ -2052,9 +2030,9 @@ static irqreturn_t mlxbf_smbus_irq(int irq, void *ptr)
MLXBF_I2C_SLAVE_DATA_DESC_SIZE : recv_bytes; MLXBF_I2C_SLAVE_DATA_DESC_SIZE : recv_bytes;
if (read) if (read)
mlxbf_smbus_irq_send(priv, recv_bytes); mlxbf_i2c_irq_send(priv, recv_bytes);
else else
mlxbf_smbus_irq_recv(priv, recv_bytes); mlxbf_i2c_irq_recv(priv, recv_bytes);
return IRQ_HANDLED; return IRQ_HANDLED;
} }
...@@ -2149,23 +2127,21 @@ static s32 mlxbf_i2c_smbus_xfer(struct i2c_adapter *adap, u16 addr, ...@@ -2149,23 +2127,21 @@ static s32 mlxbf_i2c_smbus_xfer(struct i2c_adapter *adap, u16 addr,
static int mlxbf_i2c_reg_slave(struct i2c_client *slave) static int mlxbf_i2c_reg_slave(struct i2c_client *slave)
{ {
struct mlxbf_i2c_priv *priv = i2c_get_adapdata(slave->adapter); struct mlxbf_i2c_priv *priv = i2c_get_adapdata(slave->adapter);
struct device *dev = &slave->dev;
int ret; int ret;
if (priv->slave)
return -EBUSY;
/* /*
* Do not support ten bit chip address and do not use Packet Error * Do not support ten bit chip address and do not use Packet Error
* Checking (PEC). * Checking (PEC).
*/ */
if (slave->flags & (I2C_CLIENT_TEN | I2C_CLIENT_PEC)) if (slave->flags & (I2C_CLIENT_TEN | I2C_CLIENT_PEC)) {
dev_err(dev, "SMBus PEC and 10 bit address not supported\n");
return -EAFNOSUPPORT; return -EAFNOSUPPORT;
}
ret = mlxbf_slave_enable(priv, slave->addr); ret = mlxbf_i2c_slave_enable(priv, slave);
if (ret < 0) if (ret)
return ret; dev_err(dev, "Surpassed max number of registered slaves allowed\n");
priv->slave = slave;
return 0; return 0;
} }
...@@ -2173,18 +2149,19 @@ static int mlxbf_i2c_reg_slave(struct i2c_client *slave) ...@@ -2173,18 +2149,19 @@ static int mlxbf_i2c_reg_slave(struct i2c_client *slave)
static int mlxbf_i2c_unreg_slave(struct i2c_client *slave) static int mlxbf_i2c_unreg_slave(struct i2c_client *slave)
{ {
struct mlxbf_i2c_priv *priv = i2c_get_adapdata(slave->adapter); struct mlxbf_i2c_priv *priv = i2c_get_adapdata(slave->adapter);
struct device *dev = &slave->dev;
int ret; int ret;
WARN_ON(!priv->slave); /*
* Unregister slave by:
* 1) Disabling the slave address in hardware
* 2) Freeing priv->slave at the corresponding index
*/
ret = mlxbf_i2c_slave_disable(priv, slave->addr);
if (ret)
dev_err(dev, "Unable to find slave 0x%x\n", slave->addr);
/* Unregister slave, i.e. disable the slave address in hardware. */
ret = mlxbf_slave_disable(priv);
if (ret < 0)
return ret; return ret;
priv->slave = NULL;
return 0;
} }
static u32 mlxbf_i2c_functionality(struct i2c_adapter *adap) static u32 mlxbf_i2c_functionality(struct i2c_adapter *adap)
...@@ -2392,7 +2369,7 @@ static int mlxbf_i2c_probe(struct platform_device *pdev) ...@@ -2392,7 +2369,7 @@ static int mlxbf_i2c_probe(struct platform_device *pdev)
irq = platform_get_irq(pdev, 0); irq = platform_get_irq(pdev, 0);
if (irq < 0) if (irq < 0)
return irq; return irq;
ret = devm_request_irq(dev, irq, mlxbf_smbus_irq, ret = devm_request_irq(dev, irq, mlxbf_i2c_irq,
IRQF_SHARED | IRQF_PROBE_SHARED, IRQF_SHARED | IRQF_PROBE_SHARED,
dev_name(dev), priv); dev_name(dev), priv);
if (ret < 0) { if (ret < 0) {
...@@ -2487,4 +2464,5 @@ module_exit(mlxbf_i2c_exit); ...@@ -2487,4 +2464,5 @@ module_exit(mlxbf_i2c_exit);
MODULE_DESCRIPTION("Mellanox BlueField I2C bus driver"); MODULE_DESCRIPTION("Mellanox BlueField I2C bus driver");
MODULE_AUTHOR("Khalil Blaiech <kblaiech@nvidia.com>"); MODULE_AUTHOR("Khalil Blaiech <kblaiech@nvidia.com>");
MODULE_AUTHOR("Asmaa Mnebhi <asmaa@nvidia.com>");
MODULE_LICENSE("GPL v2"); MODULE_LICENSE("GPL v2");
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