Commit bea5d143 authored by Florian Fainelli's avatar Florian Fainelli Committed by David S. Miller

net: phy: broadcom: Use bcm54xx_config_clock_delay() for BCM54612E

bcm54612e_config_init() duplicates what bcm54xx_config_clock_delay()
does with respect to configuring RGMII TX/RX delays appropriately.
Signed-off-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent fea7fda7
...@@ -47,26 +47,7 @@ static int bcm54612e_config_init(struct phy_device *phydev) ...@@ -47,26 +47,7 @@ static int bcm54612e_config_init(struct phy_device *phydev)
{ {
int reg; int reg;
/* Clear TX internal delay unless requested. */ bcm54xx_config_clock_delay(phydev);
if ((phydev->interface != PHY_INTERFACE_MODE_RGMII_ID) &&
(phydev->interface != PHY_INTERFACE_MODE_RGMII_TXID)) {
/* Disable TXD to GTXCLK clock delay (default set) */
/* Bit 9 is the only field in shadow register 00011 */
bcm_phy_write_shadow(phydev, 0x03, 0);
}
/* Clear RX internal delay unless requested. */
if ((phydev->interface != PHY_INTERFACE_MODE_RGMII_ID) &&
(phydev->interface != PHY_INTERFACE_MODE_RGMII_RXID)) {
reg = bcm54xx_auxctl_read(phydev,
MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
/* Disable RXD to RXC delay (default set) */
reg &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN;
/* Clear shadow selector field */
reg &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MASK;
bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
MII_BCM54XX_AUXCTL_MISC_WREN | reg);
}
/* Enable CLK125 MUX on LED4 if ref clock is enabled. */ /* Enable CLK125 MUX on LED4 if ref clock is enabled. */
if (!(phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED)) { if (!(phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED)) {
......
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