dt-bindings: display: mediatek: Fix examples on new bindings

To avoid failure of dt_binding_check perform a slight refactoring
of the examples: the main block is kept, but that required fixing
the address and size cells, plus the inclusion of missing dt-bindings
headers, required to parse some of the values assigned to various
properties.

Fixes: 4ed545e7 ("dt-bindings: display: mediatek: disp: split each block to individual yaml")
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Tested-by: jason-jh.lin <jason-jh.lin@medaitek.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220309134702.9942-5-jason-jh.lin@mediatek.com

Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml

@@ -66,6 +66,14 @@ additionalProperties: false
 
 examples:
   - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/clock/mt8173-clk.h>
+    #include <dt-bindings/power/mt8173-power.h>
+    #include <dt-bindings/gce/mt8173-gce.h>
+
+    soc {
+        #address-cells = <2>;
+        #size-cells = <2>;
 
         aal@14015000 {
            compatible = "mediatek,mt8173-disp-aal";
@@ -75,3 +83,4 @@ examples:
            clocks = <&mmsys CLK_MM_DISP_AAL>;
            mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
        };
+    };

Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml

@@ -65,6 +65,14 @@ additionalProperties: false
 
 examples:
   - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/clock/mt8183-clk.h>
+    #include <dt-bindings/power/mt8183-power.h>
+    #include <dt-bindings/gce/mt8183-gce.h>
+
+    soc {
+        #address-cells = <2>;
+        #size-cells = <2>;
 
         ccorr0: ccorr@1400f000 {
             compatible = "mediatek,mt8183-disp-ccorr";
@@ -74,3 +82,4 @@ examples:
             clocks = <&mmsys CLK_MM_DISP_CCORR0>;
             mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
         };
+    };

Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml

@@ -75,6 +75,14 @@ additionalProperties: false
 
 examples:
   - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/clock/mt8173-clk.h>
+    #include <dt-bindings/power/mt8173-power.h>
+    #include <dt-bindings/gce/mt8173-gce.h>
+
+    soc {
+        #address-cells = <2>;
+        #size-cells = <2>;
 
         color0: color@14013000 {
             compatible = "mediatek,mt8173-disp-color";
@@ -84,3 +92,4 @@ examples:
             clocks = <&mmsys CLK_MM_DISP_COLOR0>;
             mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>;
         };
+    };

Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml

@@ -65,6 +65,14 @@ additionalProperties: false
 
 examples:
   - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/clock/mt8183-clk.h>
+    #include <dt-bindings/power/mt8183-power.h>
+    #include <dt-bindings/gce/mt8183-gce.h>
+
+    soc {
+        #address-cells = <2>;
+        #size-cells = <2>;
 
         dither0: dither@14012000 {
             compatible = "mediatek,mt8183-disp-dither";
@@ -74,3 +82,4 @@ examples:
             clocks = <&mmsys CLK_MM_DISP_DITHER0>;
             mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
         };
+    };

Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml

@@ -70,8 +70,7 @@ examples:
   - |
     #include <dt-bindings/interrupt-controller/arm-gic.h>
     #include <dt-bindings/clock/mt8173-clk.h>
-    #include <dt-bindings/interrupt-controller/arm-gic.h>
-    #include <dt-bindings/interrupt-controller/irq.h>
+
     dpi0: dpi@1401d000 {
         compatible = "mediatek,mt8173-dpi";
         reg = <0x1401d000 0x1000>;

Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml

@@ -60,6 +60,14 @@ additionalProperties: false
 
 examples:
   - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/clock/mt8195-clk.h>
+    #include <dt-bindings/power/mt8195-power.h>
+    #include <dt-bindings/gce/mt8195-gce.h>
+
+    soc {
+        #address-cells = <2>;
+        #size-cells = <2>;
 
         dsc0: disp_dsc_wrap@1c009000 {
             compatible = "mediatek,mt8195-disp-dsc";
@@ -69,3 +77,4 @@ examples:
             clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>;
             mediatek,gce-client-reg = <&gce1 SUBSYS_1c00XXXX 0x9000 0x1000>;
         };
+    };

Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml

@@ -66,6 +66,14 @@ additionalProperties: false
 
 examples:
   - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/clock/mt8173-clk.h>
+    #include <dt-bindings/power/mt8173-power.h>
+    #include <dt-bindings/gce/mt8173-gce.h>
+
+    soc {
+        #address-cells = <2>;
+        #size-cells = <2>;
 
         gamma@14016000 {
             compatible = "mediatek,mt8173-disp-gamma";
@@ -75,3 +83,4 @@ examples:
             clocks = <&mmsys CLK_MM_DISP_GAMMA>;
             mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>;
         };
+    };

Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml

@@ -38,16 +38,14 @@ properties:
       Documentation/devicetree/bindings/power/power-domain.yaml for details.
 
   clocks:
+    minItems: 1
     maxItems: 2
-    items:
-      - description: MERGE Clock
-      - description: MERGE Async Clock
-          Controlling the synchronous process between MERGE and other display
-          function blocks cross clock domain.
 
   clock-names:
-    maxItems: 2
-    items:
+    oneOf:
+      - items:
+          - const: merge
+      - items:
           - const: merge
           - const: merge_async
 
@@ -88,23 +86,20 @@ additionalProperties: false
 
 examples:
   - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/clock/mt8173-clk.h>
+    #include <dt-bindings/power/mt8173-power.h>
+
+    soc {
+        #address-cells = <2>;
+        #size-cells = <2>;
 
         merge@14017000 {
             compatible = "mediatek,mt8173-disp-merge";
             reg = <0 0x14017000 0 0x1000>;
             power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
             clocks = <&mmsys CLK_MM_DISP_MERGE>;
+            clock-names = "merge";
         };
-
-    merge5: disp_vpp_merge5@1c110000 {
-        compatible = "mediatek,mt8195-disp-merge";
-        reg = <0 0x1c110000 0 0x1000>;
-        interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH 0>;
-        clocks = <&vdosys1 CLK_VDO1_VPP_MERGE4>,
-                 <&vdosys1 CLK_VDO1_MERGE4_DL_ASYNC>;
-        clock-names = "merge","merge_async";
-        power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
-        mediatek,gce-client-reg = <&gce1 SUBSYS_1c11XXXX 0x0000 0x1000>;
-        mediatek,merge-fifo-en = <1>;
-        resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC>;
     };
+

Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml

@@ -71,6 +71,14 @@ additionalProperties: false
 
 examples:
   - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/clock/mt8173-clk.h>
+    #include <dt-bindings/power/mt8173-power.h>
+    #include <dt-bindings/gce/mt8173-gce.h>
+
+    soc {
+        #address-cells = <2>;
+        #size-cells = <2>;
 
         mutex: mutex@14020000 {
             compatible = "mediatek,mt8173-disp-mutex";
@@ -81,3 +89,4 @@ examples:
             mediatek,gce-events = <CMDQ_EVENT_MUTEX0_STREAM_EOF>,
                                   <CMDQ_EVENT_MUTEX1_STREAM_EOF>;
         };
+    };

Documentation/devicetree/bindings/display/mediatek/mediatek,od.yaml

@@ -45,9 +45,15 @@ additionalProperties: false
 
 examples:
   - |
+    #include <dt-bindings/clock/mt8173-clk.h>
+
+    soc {
+        #address-cells = <2>;
+        #size-cells = <2>;
 
         od@14023000 {
             compatible = "mediatek,mt8173-disp-od";
             reg = <0 0x14023000 0 0x1000>;
             clocks = <&mmsys CLK_MM_DISP_OD>;
         };
+    };

Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml

@@ -66,6 +66,15 @@ additionalProperties: false
 
 examples:
   - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/clock/mt8183-clk.h>
+    #include <dt-bindings/power/mt8183-power.h>
+    #include <dt-bindings/gce/mt8183-gce.h>
+    #include <dt-bindings/memory/mt8183-larb-port.h>
+
+    soc {
+        #address-cells = <2>;
+        #size-cells = <2>;
 
         ovl_2l0: ovl@14009000 {
             compatible = "mediatek,mt8183-disp-ovl-2l";
@@ -76,3 +85,4 @@ examples:
             iommus = <&iommu M4U_PORT_DISP_2L_OVL0_LARB0>;
             mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
         };
+    };

Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml

@@ -81,6 +81,15 @@ additionalProperties: false
 
 examples:
   - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/clock/mt8173-clk.h>
+    #include <dt-bindings/power/mt8173-power.h>
+    #include <dt-bindings/gce/mt8173-gce.h>
+    #include <dt-bindings/memory/mt8173-larb-port.h>
+
+    soc {
+        #address-cells = <2>;
+        #size-cells = <2>;
 
         ovl0: ovl@1400c000 {
             compatible = "mediatek,mt8173-disp-ovl";
@@ -91,3 +100,4 @@ examples:
             iommus = <&iommu M4U_PORT_DISP_OVL0>;
             mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
         };
+    };

Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.yaml

@@ -58,6 +58,14 @@ additionalProperties: false
 
 examples:
   - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/clock/mt8192-clk.h>
+    #include <dt-bindings/power/mt8192-power.h>
+    #include <dt-bindings/gce/mt8192-gce.h>
+
+    soc {
+        #address-cells = <2>;
+        #size-cells = <2>;
 
         postmask0: postmask@1400d000 {
             compatible = "mediatek,mt8192-disp-postmask";
@@ -67,3 +75,4 @@ examples:
             clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
             mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
         };
+    };

Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml

@@ -94,6 +94,15 @@ additionalProperties: false
 
 examples:
   - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/clock/mt8173-clk.h>
+    #include <dt-bindings/power/mt8173-power.h>
+    #include <dt-bindings/gce/mt8173-gce.h>
+    #include <dt-bindings/memory/mt8173-larb-port.h>
+
+    soc {
+        #address-cells = <2>;
+        #size-cells = <2>;
 
         rdma0: rdma@1400e000 {
             compatible = "mediatek,mt8173-disp-rdma";
@@ -102,6 +111,7 @@ examples:
             power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
             clocks = <&mmsys CLK_MM_DISP_RDMA0>;
             iommus = <&iommu M4U_PORT_DISP_RDMA0>;
-        mediatek,rdma-fifosize = <8192>;
+            mediatek,rdma-fifo-size = <8192>;
             mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
         };
+    };

Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml

@@ -49,6 +49,12 @@ additionalProperties: false
 
 examples:
   - |
+    #include <dt-bindings/clock/mt8173-clk.h>
+    #include <dt-bindings/power/mt8173-power.h>
+
+    soc {
+        #address-cells = <2>;
+        #size-cells = <2>;
 
         split0: split@14018000 {
             compatible = "mediatek,mt8173-disp-split";
@@ -56,3 +62,4 @@ examples:
             power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
             clocks = <&mmsys CLK_MM_DISP_SPLIT0>;
         };
+    };

Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml

@@ -51,6 +51,12 @@ additionalProperties: false
 
 examples:
   - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/clock/mt8173-clk.h>
+    #include <dt-bindings/power/mt8173-power.h>
+    soc {
+        #address-cells = <2>;
+        #size-cells = <2>;
 
         ufoe@1401a000 {
             compatible = "mediatek,mt8173-disp-ufoe";
@@ -59,3 +65,4 @@ examples:
             power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
             clocks = <&mmsys CLK_MM_DISP_UFOE>;
         };
+    };

Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml

@@ -64,6 +64,15 @@ additionalProperties: false
 
 examples:
   - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/clock/mt8173-clk.h>
+    #include <dt-bindings/power/mt8173-power.h>
+    #include <dt-bindings/gce/mt8173-gce.h>
+    #include <dt-bindings/memory/mt8173-larb-port.h>
+
+    soc {
+        #address-cells = <2>;
+        #size-cells = <2>;
 
         wdma0: wdma@14011000 {
             compatible = "mediatek,mt8173-disp-wdma";
@@ -74,3 +83,4 @@ examples:
             iommus = <&iommu M4U_PORT_DISP_WDMA0>;
             mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
         };
+    };