Commit c034f2aa authored by Aaron Lewis's avatar Aaron Lewis Committed by Paolo Bonzini

KVM: VMX: Fix conditions for guest IA32_XSS support

Volume 4 of the SDM says that IA32_XSS is supported
if CPUID(EAX=0DH,ECX=1):EAX.XSS[bit 3] is set, so only the
X86_FEATURE_XSAVES check is necessary (X86_FEATURE_XSAVES is the Linux
name for CPUID(EAX=0DH,ECX=1):EAX.XSS[bit 3]).

Fixes: 4d763b16 ("KVM: VMX: check CPUID before allowing read/write of IA32_XSS")
Reviewed-by: default avatarJim Mattson <jmattson@google.com>
Signed-off-by: default avatarAaron Lewis <aaronlewis@google.com>
Change-Id: I9059b9f2e3595e4b09a4cdcf14b933b22ebad419
Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
parent 7204160e
...@@ -1830,10 +1830,8 @@ static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) ...@@ -1830,10 +1830,8 @@ static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
return vmx_get_vmx_msr(&vmx->nested.msrs, msr_info->index, return vmx_get_vmx_msr(&vmx->nested.msrs, msr_info->index,
&msr_info->data); &msr_info->data);
case MSR_IA32_XSS: case MSR_IA32_XSS:
if (!vmx_xsaves_supported() || if (!msr_info->host_initiated &&
(!msr_info->host_initiated && !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
!(guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))))
return 1; return 1;
msr_info->data = vcpu->arch.ia32_xss; msr_info->data = vcpu->arch.ia32_xss;
break; break;
...@@ -2073,10 +2071,8 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) ...@@ -2073,10 +2071,8 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
return 1; return 1;
return vmx_set_vmx_msr(vcpu, msr_index, data); return vmx_set_vmx_msr(vcpu, msr_index, data);
case MSR_IA32_XSS: case MSR_IA32_XSS:
if (!vmx_xsaves_supported() || if (!msr_info->host_initiated &&
(!msr_info->host_initiated && !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
!(guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))))
return 1; return 1;
/* /*
* The only supported bit as of Skylake is bit 8, but * The only supported bit as of Skylake is bit 8, but
...@@ -2085,11 +2081,13 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) ...@@ -2085,11 +2081,13 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
if (data != 0) if (data != 0)
return 1; return 1;
vcpu->arch.ia32_xss = data; vcpu->arch.ia32_xss = data;
if (vcpu->arch.xsaves_enabled) {
if (vcpu->arch.ia32_xss != host_xss) if (vcpu->arch.ia32_xss != host_xss)
add_atomic_switch_msr(vmx, MSR_IA32_XSS, add_atomic_switch_msr(vmx, MSR_IA32_XSS,
vcpu->arch.ia32_xss, host_xss, false); vcpu->arch.ia32_xss, host_xss, false);
else else
clear_atomic_switch_msr(vmx, MSR_IA32_XSS); clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
}
break; break;
case MSR_IA32_RTIT_CTL: case MSR_IA32_RTIT_CTL:
if ((pt_mode != PT_MODE_HOST_GUEST) || if ((pt_mode != PT_MODE_HOST_GUEST) ||
......
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