Commit c1b30e4d authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'pinctrl-v3.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control changes from Linus Walleij:
 "Here is a stash of pin control changes I have collected for the v3.19
  series.  Mainly new hardware support, with Intels new embedded SoC as
  the especially interesting thing standing out, fully using the
  subsystem.

   - Force conversion of the ux500 pin control device trees and parsers
     to use the generic pin control bindings.
   - New driver and device tree bindings for the Qualcomm PMIC MPP pin
     controller and GPIO.
   - Some ACPI infrastructure for pin controllers.
   - New driver for the Intel CherryView/Braswell pin controller, the
     first Intel pin controller to fully take advantage of the pin
     control subsystem.
   - Support the Freescale i.MX VF610 variant.
   - Support the sunxi A80 variant.
   - Support the Samsung Exynos 4415 and Exynos 7 variants.
   - Split out Intel pin controllers to their own subdirectory.
   - A large slew of rockchip pin control updates, including
     suspend/resume support.
   - A large slew of Samsung Exynos pin controller updates.
   - Various minor updates and fixes"

* tag 'pinctrl-v3.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (49 commits)
  pinctrl: at91: enhance (debugfs) at91_gpio_dbg_show
  pinctrl: meson: add device tree bindings documentation
  gpio: tz1090: Fix error handling of irq_of_parse_and_map
  pinctrl: tz1090-pinctrl.txt: Fix typo in binding
  pinctrl: pinconf-generic: Declare dt_params/conf_items const
  pinctrl: exynos: Add support for Exynos4415
  pinctrl: exynos: Add initial driver data for Exynos7
  pinctrl: exynos: Add irq_chip instance for Exynos7 wakeup interrupts
  pinctrl: exynos: Consolidate irq domain callbacks
  pinctrl: exynos: Generalize the eint16_31 demux code
  pinctrl: samsung: Separate per-bank init and runtime data
  pinctrl: samsung: Constify samsung_pin_ctrl struct
  pinctrl: samsung: Constify samsung_pin_bank_type struct
  pinctrl: samsung: Drop unused label field in samsung_pin_ctrl struct
  pinctrl: samsung: Make samsung_pinctrl_get_soc_data use ERR_PTR()
  pinctrl: Add Intel Cherryview/Braswell pin controller support
  gpio / ACPI: Add knowledge about pin controllers to acpi_get_gpiod()
  pinctrl: Fix path error in documentation
  pinctrl: rockchip: save and restore gpio6_c6 pinmux in suspend/resume
  pinctrl: rockchip: add suspend/resume functions
  ...
parents 92a578b0 853b6bf0
......@@ -67,7 +67,7 @@ Valid values for pin and group names are:
They also all support the some form of muxing. Any pins which are contained
in one of the mux groups (see below) can be muxed only to the functions
supported by the mux group. All other pins can be muxed to the "perip"
function which which enables them with their intended peripheral.
function which enables them with their intended peripheral.
Different pins in the same mux group cannot be muxed to different functions,
however it is possible to mux only a subset of the pins in a mux group to a
......
== Amlogic Meson pinmux controller ==
Required properties for the root node:
- compatible: "amlogic,meson8-pinctrl"
- reg: address and size of registers controlling irq functionality
=== GPIO sub-nodes ===
The 2 power domains of the controller (regular and always-on) are
represented as sub-nodes and each of them acts as a GPIO controller.
Required properties for sub-nodes are:
- reg: should contain address and size for mux, pull-enable, pull and
gpio register sets
- reg-names: an array of strings describing the "reg" entries. Must
contain "mux", "pull" and "gpio". "pull-enable" is optional and
when it is missing the "pull" registers are used instead
- gpio-controller: identifies the node as a gpio controller
- #gpio-cells: must be 2
Valid sub-node names are:
- "banks" for the regular domain
- "ao-bank" for the always-on domain
=== Other sub-nodes ===
Child nodes without the "gpio-controller" represent some desired
configuration for a pin or a group. Those nodes can be pinmux nodes or
configuration nodes.
Required properties for pinmux nodes are:
- groups: a list of pinmux groups. The list of all available groups
depends on the SoC and can be found in driver sources.
- function: the name of a function to activate for the specified set
of groups. The list of all available functions depends on the SoC
and can be found in driver sources.
Required properties for configuration nodes:
- pins: a list of pin names
Configuration nodes support the generic properties "bias-disable",
"bias-pull-up" and "bias-pull-down", described in file
pinctrl-bindings.txt
=== Example ===
pinctrl: pinctrl@c1109880 {
compatible = "amlogic,meson8-pinctrl";
reg = <0xc1109880 0x10>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
gpio: banks@c11080b0 {
reg = <0xc11080b0 0x28>,
<0xc11080e8 0x18>,
<0xc1108120 0x18>,
<0xc1108030 0x30>;
reg-names = "mux", "pull", "pull-enable", "gpio";
gpio-controller;
#gpio-cells = <2>;
};
gpio_ao: ao-bank@c1108030 {
reg = <0xc8100014 0x4>,
<0xc810002c 0x4>,
<0xc8100024 0x8>;
reg-names = "mux", "pull", "gpio";
gpio-controller;
#gpio-cells = <2>;
};
nand {
mux {
groups = "nand_io", "nand_io_ce0", "nand_io_ce1",
"nand_io_rb0", "nand_ale", "nand_cle",
"nand_wen_clk", "nand_ren_clk", "nand_dqs",
"nand_ce2", "nand_ce3";
function = "nand";
};
};
uart_ao_a {
mux {
groups = "uart_tx_ao_a", "uart_rx_ao_a",
"uart_cts_ao_a", "uart_rts_ao_a";
function = "uart_ao";
};
conf {
pins = "GPIOAO_0", "GPIOAO_1",
"GPIOAO_2", "GPIOAO_3";
bias-disable;
};
};
};
......@@ -216,4 +216,4 @@ arguments are described below.
or 0 to disable debouncing
More in-depth documentation on these parameters can be found in
<include/linux/pinctrl/pinconfig-generic.h>
<include/linux/pinctrl/pinconf-generic.h>
Qualcomm PMIC GPIO block
This binding describes the GPIO block(s) found in the 8xxx series of
PMIC's from Qualcomm.
- compatible:
Usage: required
Value type: <string>
Definition: must be one of:
"qcom,pm8018-gpio"
"qcom,pm8038-gpio"
"qcom,pm8058-gpio"
"qcom,pm8917-gpio"
"qcom,pm8921-gpio"
"qcom,pm8941-gpio"
"qcom,pma8084-gpio"
- reg:
Usage: required
Value type: <prop-encoded-array>
Definition: Register base of the GPIO block and length.
- interrupts:
Usage: required
Value type: <prop-encoded-array>
Definition: Must contain an array of encoded interrupt specifiers for
each available GPIO
- gpio-controller:
Usage: required
Value type: <none>
Definition: Mark the device node as a GPIO controller
- #gpio-cells:
Usage: required
Value type: <u32>
Definition: Must be 2;
the first cell will be used to define gpio number and the
second denotes the flags for this gpio
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
a general description of GPIO and interrupt bindings.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
The pin configuration nodes act as a container for an arbitrary number of
subnodes. Each of these subnodes represents some desired configuration for a
pin or a list of pins. This configuration can include the
mux function to select on those pin(s), and various pin configuration
parameters, as listed below.
SUBNODES:
The name of each subnode is not important; all subnodes should be enumerated
and processed purely based on their content.
Each subnode only affects those parameters that are explicitly listed. In
other words, a subnode that lists a mux function but no pin configuration
parameters implies no information about any pin configuration parameters.
Similarly, a pin subnode that describes a pullup parameter implies no
information about e.g. the mux function.
The following generic properties as defined in pinctrl-bindings.txt are valid
to specify in a pin configuration subnode:
- pins:
Usage: required
Value type: <string-array>
Definition: List of gpio pins affected by the properties specified in
this subnode. Valid pins are:
gpio1-gpio6 for pm8018
gpio1-gpio12 for pm8038
gpio1-gpio40 for pm8058
gpio1-gpio38 for pm8917
gpio1-gpio44 for pm8921
gpio1-gpio36 for pm8941
gpio1-gpio22 for pma8084
- function:
Usage: required
Value type: <string>
Definition: Specify the alternative function to be configured for the
specified pins. Valid values are:
"normal",
"paired",
"func1",
"func2",
"dtest1",
"dtest2",
"dtest3",
"dtest4"
- bias-disable:
Usage: optional
Value type: <none>
Definition: The specified pins should be configured as no pull.
- bias-pull-down:
Usage: optional
Value type: <none>
Definition: The specified pins should be configured as pull down.
- bias-pull-up:
Usage: optional
Value type: <empty>
Definition: The specified pins should be configured as pull up.
- qcom,pull-up-strength:
Usage: optional
Value type: <u32>
Definition: Specifies the strength to use for pull up, if selected.
Valid values are; as defined in
<dt-bindings/pinctrl/qcom,pmic-gpio.h>:
1: 30uA (PMIC_GPIO_PULL_UP_30)
2: 1.5uA (PMIC_GPIO_PULL_UP_1P5)
3: 31.5uA (PMIC_GPIO_PULL_UP_31P5)
4: 1.5uA + 30uA boost (PMIC_GPIO_PULL_UP_1P5_30)
If this property is ommited 30uA strength will be used if
pull up is selected
- bias-high-impedance:
Usage: optional
Value type: <none>
Definition: The specified pins will put in high-Z mode and disabled.
- input-enable:
Usage: optional
Value type: <none>
Definition: The specified pins are put in input mode.
- output-high:
Usage: optional
Value type: <none>
Definition: The specified pins are configured in output mode, driven
high.
- output-low:
Usage: optional
Value type: <none>
Definition: The specified pins are configured in output mode, driven
low.
- power-source:
Usage: optional
Value type: <u32>
Definition: Selects the power source for the specified pins. Valid
power sources are defined per chip in
<dt-bindings/pinctrl/qcom,pmic-gpio.h>
- qcom,drive-strength:
Usage: optional
Value type: <u32>
Definition: Selects the drive strength for the specified pins. Value
drive strengths are:
0: no (PMIC_GPIO_STRENGTH_NO)
1: high (PMIC_GPIO_STRENGTH_HIGH) 0.9mA @ 1.8V - 1.9mA @ 2.6V
2: medium (PMIC_GPIO_STRENGTH_MED) 0.6mA @ 1.8V - 1.25mA @ 2.6V
3: low (PMIC_GPIO_STRENGTH_LOW) 0.15mA @ 1.8V - 0.3mA @ 2.6V
as defined in <dt-bindings/pinctrl/qcom,pmic-gpio.h>
- drive-push-pull:
Usage: optional
Value type: <none>
Definition: The specified pins are configured in push-pull mode.
- drive-open-drain:
Usage: optional
Value type: <none>
Definition: The specified pins are configured in open-drain mode.
- drive-open-source:
Usage: optional
Value type: <none>
Definition: The specified pins are configured in open-source mode.
Example:
pm8921_gpio: gpio@150 {
compatible = "qcom,pm8921-gpio";
reg = <0x150 0x160>;
interrupts = <192 1>, <193 1>, <194 1>,
<195 1>, <196 1>, <197 1>,
<198 1>, <199 1>, <200 1>,
<201 1>, <202 1>, <203 1>,
<204 1>, <205 1>, <206 1>,
<207 1>, <208 1>, <209 1>,
<210 1>, <211 1>, <212 1>,
<213 1>, <214 1>, <215 1>,
<216 1>, <217 1>, <218 1>,
<219 1>, <220 1>, <221 1>,
<222 1>, <223 1>, <224 1>,
<225 1>, <226 1>, <227 1>,
<228 1>, <229 1>, <230 1>,
<231 1>, <232 1>, <233 1>,
<234 1>, <235 1>;
gpio-controller;
#gpio-cells = <2>;
pm8921_gpio_keys: gpio-keys {
volume-keys {
pins = "gpio20", "gpio21";
function = "normal";
input-enable;
bias-pull-up;
drive-push-pull;
qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
power-source = <PM8921_GPIO_S4>;
};
};
};
Qualcomm PMIC Multi-Purpose Pin (MPP) block
This binding describes the MPP block(s) found in the 8xxx series
of PMIC's from Qualcomm.
- compatible:
Usage: required
Value type: <string>
Definition: Should contain one of:
"qcom,pm8841-mpp",
"qcom,pm8941-mpp",
"qcom,pma8084-mpp",
- reg:
Usage: required
Value type: <prop-encoded-array>
Definition: Register base of the MPP block and length.
- interrupts:
Usage: required
Value type: <prop-encoded-array>
Definition: Must contain an array of encoded interrupt specifiers for
each available MPP
- gpio-controller:
Usage: required
Value type: <none>
Definition: Mark the device node as a GPIO controller
- #gpio-cells:
Usage: required
Value type: <u32>
Definition: Must be 2;
the first cell will be used to define MPP number and the
second denotes the flags for this MPP
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
a general description of GPIO and interrupt bindings.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
The pin configuration nodes act as a container for an arbitrary number of
subnodes. Each of these subnodes represents some desired configuration for a
pin or a list of pins. This configuration can include the
mux function to select on those pin(s), and various pin configuration
parameters, as listed below.
SUBNODES:
The name of each subnode is not important; all subnodes should be enumerated
and processed purely based on their content.
Each subnode only affects those parameters that are explicitly listed. In
other words, a subnode that lists a mux function but no pin configuration
parameters implies no information about any pin configuration parameters.
Similarly, a pin subnode that describes a pullup parameter implies no
information about e.g. the mux function.
The following generic properties as defined in pinctrl-bindings.txt are valid
to specify in a pin configuration subnode:
- pins:
Usage: required
Value type: <string-array>
Definition: List of MPP pins affected by the properties specified in
this subnode. Valid pins are:
mpp1-mpp4 for pm8841
mpp1-mpp8 for pm8941
mpp1-mpp4 for pma8084
- function:
Usage: required
Value type: <string>
Definition: Specify the alternative function to be configured for the
specified pins. Valid values are:
"normal",
"paired",
"dtest1",
"dtest2",
"dtest3",
"dtest4"
- bias-disable:
Usage: optional
Value type: <none>
Definition: The specified pins should be configured as no pull.
- bias-pull-up:
Usage: optional
Value type: <u32>
Definition: The specified pins should be configured as pull up.
Valid values are 600, 10000 and 30000 in bidirectional mode
only, i.e. when operating in qcom,analog-mode and input and
outputs are enabled. The hardware ignores the configuration
when operating in other modes.
- bias-high-impedance:
Usage: optional
Value type: <none>
Definition: The specified pins will put in high-Z mode and disabled.
- input-enable:
Usage: optional
Value type: <none>
Definition: The specified pins are put in input mode, i.e. their input
buffer is enabled
- output-high:
Usage: optional
Value type: <none>
Definition: The specified pins are configured in output mode, driven
high.
- output-low:
Usage: optional
Value type: <none>
Definition: The specified pins are configured in output mode, driven
low.
- power-source:
Usage: optional
Value type: <u32>
Definition: Selects the power source for the specified pins. Valid power
sources are defined in <dt-bindings/pinctrl/qcom,pmic-mpp.h>
- qcom,analog-mode:
Usage: optional
Value type: <none>
Definition: Selects Analog mode of operation: combined with input-enable
and/or output-high, output-low MPP could operate as
Bidirectional Logic, Analog Input, Analog Output.
- qcom,amux-route:
Usage: optional
Value type: <u32>
Definition: Selects the source for analog input. Valid values are
defined in <dt-bindings/pinctrl/qcom,pmic-mpp.h>
PMIC_MPP_AMUX_ROUTE_CH5, PMIC_MPP_AMUX_ROUTE_CH6...
Example:
mpps@a000 {
compatible = "qcom,pm8841-mpp";
reg = <0xa000>;
gpio-controller;
#gpio-cells = <2>;
interrupts = <4 0xa0 0 0>, <4 0xa1 0 0>, <4 0xa2 0 0>, <4 0xa3 0 0>;
pinctrl-names = "default";
pinctrl-0 = <&pm8841_default>;
pm8841_default: default {
gpio {
pins = "mpp1", "mpp2", "mpp3", "mpp4";
function = "normal";
input-enable;
power-source = <PM8841_MPP_S3>;
};
};
};
......@@ -18,6 +18,7 @@ Required Properties:
- "samsung,exynos5250-pinctrl": for Exynos5250 compatible pin-controller.
- "samsung,exynos5260-pinctrl": for Exynos5260 compatible pin-controller.
- "samsung,exynos5420-pinctrl": for Exynos5420 compatible pin-controller.
- "samsung,exynos7-pinctrl": for Exynos7 compatible pin-controller.
- reg: Base address of the pin controller hardware module and length of
the address space it occupies.
......@@ -136,6 +137,8 @@ B. External Wakeup Interrupts: For supporting external wakeup interrupts, a
found on Samsung S3C64xx SoCs,
- samsung,exynos4210-wakeup-eint: represents wakeup interrupt controller
found on Samsung Exynos4210 and S5PC110/S5PV210 SoCs.
- samsung,exynos7-wakeup-eint: represents wakeup interrupt controller
found on Samsung Exynos7 SoC.
- interrupt-parent: phandle of the interrupt parent to which the external
wakeup interrupts are forwarded to.
- interrupts: interrupt used by multiplexed wakeup interrupts.
......
......@@ -7285,7 +7285,13 @@ PIN CONTROLLER - ATMEL AT91
M: Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: drivers/pinctrl/pinctrl-at91.c
F: drivers/pinctrl/pinctrl-at91.*
PIN CONTROLLER - INTEL
M: Mika Westerberg <mika.westerberg@linux.intel.com>
M: Heikki Krogerus <heikki.krogerus@linux.intel.com>
S: Maintained
F: drivers/pinctrl/intel/
PIN CONTROLLER - RENESAS
M: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
......
......@@ -16,31 +16,31 @@ pinctrl {
uart0 {
uart0_default_mux: uart0_mux {
default_mux {
ste,function = "u0";
ste,pins = "u0_a_1";
function = "u0";
groups = "u0_a_1";
};
};
uart0_default_mode: uart0_default {
default_cfg1 {
ste,pins = "GPIO0", "GPIO2";
pins = "GPIO0", "GPIO2";
ste,config = <&in_pu>;
};
default_cfg2 {
ste,pins = "GPIO1", "GPIO3";
pins = "GPIO1", "GPIO3";
ste,config = <&out_hi>;
};
};
uart0_sleep_mode: uart0_sleep {
sleep_cfg1 {
ste,pins = "GPIO0", "GPIO2";
pins = "GPIO0", "GPIO2";
ste,config = <&slpm_in_pu>;
};
sleep_cfg2 {
ste,pins = "GPIO1", "GPIO3";
pins = "GPIO1", "GPIO3";
ste,config = <&slpm_out_hi>;
};
};
......@@ -49,29 +49,29 @@ sleep_cfg2 {
uart2 {
uart2_default_mode: uart2_default {
default_mux {
ste,function = "u2";
ste,pins = "u2txrx_a_1";
function = "u2";
groups = "u2txrx_a_1";
};
default_cfg1 {
ste,pins = "GPIO120";
pins = "GPIO120";
ste,config = <&in_pu>;
};
default_cfg2 {
ste,pins = "GPIO121";
pins = "GPIO121";
ste,config = <&out_hi>;
};
};
uart2_sleep_mode: uart2_sleep {
sleep_cfg1 {
ste,pins = "GPIO120";
pins = "GPIO120";
ste,config = <&slpm_in_pu>;
};
sleep_cfg2 {
ste,pins = "GPIO121";
pins = "GPIO121";
ste,config = <&slpm_out_hi>;
};
};
......@@ -80,21 +80,21 @@ sleep_cfg2 {
i2c0 {
i2c0_default_mux: i2c_mux {
default_mux {
ste,function = "i2c0";
ste,pins = "i2c0_a_1";
function = "i2c0";
groups = "i2c0_a_1";
};
};
i2c0_default_mode: i2c_default {
default_cfg1 {
ste,pins = "GPIO147", "GPIO148";
pins = "GPIO147", "GPIO148";
ste,config = <&in_pu>;
};
};
i2c0_sleep_mode: i2c_sleep {
sleep_cfg1 {
ste,pins = "GPIO147", "GPIO148";
pins = "GPIO147", "GPIO148";
ste,config = <&slpm_in_pu>;
};
};
......@@ -103,21 +103,21 @@ sleep_cfg1 {
i2c1 {
i2c1_default_mux: i2c_mux {
default_mux {
ste,function = "i2c1";
ste,pins = "i2c1_b_2";
function = "i2c1";
groups = "i2c1_b_2";
};
};
i2c1_default_mode: i2c_default {
default_cfg1 {
ste,pins = "GPIO16", "GPIO17";
pins = "GPIO16", "GPIO17";
ste,config = <&in_pu>;
};
};
i2c1_sleep_mode: i2c_sleep {
sleep_cfg1 {
ste,pins = "GPIO16", "GPIO17";
pins = "GPIO16", "GPIO17";
ste,config = <&slpm_in_pu>;
};
};
......@@ -126,21 +126,21 @@ sleep_cfg1 {
i2c2 {
i2c2_default_mux: i2c_mux {
default_mux {
ste,function = "i2c2";
ste,pins = "i2c2_b_2";
function = "i2c2";
groups = "i2c2_b_2";
};
};
i2c2_default_mode: i2c_default {
default_cfg1 {
ste,pins = "GPIO10", "GPIO11";
pins = "GPIO10", "GPIO11";
ste,config = <&in_pu>;
};
};
i2c2_sleep_mode: i2c_sleep {
sleep_cfg1 {
ste,pins = "GPIO11", "GPIO11";
pins = "GPIO11", "GPIO11";
ste,config = <&slpm_in_pu>;
};
};
......@@ -149,21 +149,21 @@ sleep_cfg1 {
i2c4 {
i2c4_default_mux: i2c_mux {
default_mux {
ste,function = "i2c4";
ste,pins = "i2c4_b_2";
function = "i2c4";
groups = "i2c4_b_2";
};
};
i2c4_default_mode: i2c_default {
default_cfg1 {
ste,pins = "GPIO122", "GPIO123";
pins = "GPIO122", "GPIO123";
ste,config = <&in_pu>;
};
};
i2c4_sleep_mode: i2c_sleep {
sleep_cfg1 {
ste,pins = "GPIO122", "GPIO123";
pins = "GPIO122", "GPIO123";
ste,config = <&slpm_in_pu>;
};
};
......@@ -172,21 +172,21 @@ sleep_cfg1 {
i2c5 {
i2c5_default_mux: i2c_mux {
default_mux {
ste,function = "i2c5";
ste,pins = "i2c5_c_2";
function = "i2c5";
groups = "i2c5_c_2";
};
};
i2c5_default_mode: i2c_default {
default_cfg1 {
ste,pins = "GPIO118", "GPIO119";
pins = "GPIO118", "GPIO119";
ste,config = <&in_pu>;
};
};
i2c5_sleep_mode: i2c_sleep {
sleep_cfg1 {
ste,pins = "GPIO118", "GPIO119";
pins = "GPIO118", "GPIO119";
ste,config = <&slpm_in_pu>;
};
};
......
This diff is collapsed.
......@@ -35,11 +35,11 @@ ab8505-gpio {
gpio2 {
gpio2_default_mode: gpio2_default {
default_mux {
ste,function = "gpio";
ste,pins = "gpio2_a_1";
function = "gpio";
groups = "gpio2_a_1";
};
default_cfg {
ste,pins = "GPIO2_R5";
pins = "GPIO2_R5";
input-enable;
bias-pull-down;
};
......@@ -48,11 +48,11 @@ default_cfg {
gpio10 {
gpio10_default_mode: gpio10_default {
default_mux {
ste,function = "gpio";
ste,pins = "gpio10_d_1";
function = "gpio";
groups = "gpio10_d_1";
};
default_cfg {
ste,pins = "GPIO10_B16";
pins = "GPIO10_B16";
input-enable;
bias-pull-down;
};
......@@ -61,11 +61,11 @@ default_cfg {
gpio11 {
gpio11_default_mode: gpio11_default {
default_mux {
ste,function = "gpio";
ste,pins = "gpio11_d_1";
function = "gpio";
groups = "gpio11_d_1";
};
default_cfg {
ste,pins = "GPIO11_B17";
pins = "GPIO11_B17";
input-enable;
bias-pull-down;
};
......@@ -74,11 +74,11 @@ default_cfg {
gpio13 {
gpio13_default_mode: gpio13_default {
default_mux {
ste,function = "gpio";
ste,pins = "gpio13_d_1";
function = "gpio";
groups = "gpio13_d_1";
};
default_cfg {
ste,pins = "GPIO13_D17";
pins = "GPIO13_D17";
input-enable;
bias-disable;
};
......@@ -87,11 +87,11 @@ default_cfg {
gpio34 {
gpio34_default_mode: gpio34_default {
default_mux {
ste,function = "gpio";
ste,pins = "gpio34_a_1";
function = "gpio";
groups = "gpio34_a_1";
};
default_cfg {
ste,pins = "GPIO34_H14";
pins = "GPIO34_H14";
input-enable;
bias-pull-down;
};
......@@ -100,11 +100,11 @@ default_cfg {
gpio50 {
gpio50_default_mode: gpio50_default {
default_mux {
ste,function = "gpio";
ste,pins = "gpio50_d_1";
function = "gpio";
groups = "gpio50_d_1";
};
default_cfg {
ste,pins = "GPIO50_L4";
pins = "GPIO50_L4";
input-enable;
bias-disable;
};
......@@ -114,11 +114,11 @@ default_cfg {
pwm {
pwm_default_mode: pwm_default {
default_mux {
ste,function = "pwmout";
ste,pins = "pwmout1_d_1";
function = "pwmout";
groups = "pwmout1_d_1";
};
default_cfg {
ste,pins = "GPIO14_C16";
pins = "GPIO14_C16";
input-enable;
bias-pull-down;
};
......@@ -128,11 +128,11 @@ default_cfg {
adi2 {
adi2_default_mode: adi2_default {
default_mux {
ste,function = "adi2";
ste,pins = "adi2_d_1";
function = "adi2";
groups = "adi2_d_1";
};
default_cfg {
ste,pins = "GPIO17_P2",
pins = "GPIO17_P2",
"GPIO18_N3",
"GPIO19_T1",
"GPIO20_P3";
......@@ -145,11 +145,11 @@ default_cfg {
modsclsda {
modsclsda_default_mode: modsclsda_default {
default_mux {
ste,function = "modsclsda";
ste,pins = "modsclsda_d_1";
function = "modsclsda";
groups = "modsclsda_d_1";
};
default_cfg {
ste,pins = "GPIO40_J15",
pins = "GPIO40_J15",
"GPIO41_J14";
input-enable;
bias-pull-down;
......@@ -159,11 +159,11 @@ default_cfg {
resethw {
resethw_default_mode: resethw_default {
default_mux {
ste,function = "resethw";
ste,pins = "resethw_d_1";
function = "resethw";
groups = "resethw_d_1";
};
default_cfg {
ste,pins = "GPIO52_D16";
pins = "GPIO52_D16";
input-enable;
bias-pull-down;
};
......@@ -172,11 +172,11 @@ default_cfg {
service {
service_default_mode: service_default {
default_mux {
ste,function = "service";
ste,pins = "service_d_1";
function = "service";
groups = "service_d_1";
};
default_cfg {
ste,pins = "GPIO53_D15";
pins = "GPIO53_D15";
input-enable;
bias-pull-down;
};
......@@ -188,22 +188,22 @@ default_cfg {
sysclkreq2 {
sysclkreq2_default_mode: sysclkreq2_default {
default_mux {
ste,function = "sysclkreq";
ste,pins = "sysclkreq2_d_1";
function = "sysclkreq";
groups = "sysclkreq2_d_1";
};
default_cfg {
ste,pins = "GPIO1_N4";
pins = "GPIO1_N4";
input-enable;
bias-disable;
};
};
sysclkreq2_sleep_mode: sysclkreq2_sleep {
default_mux {
ste,function = "gpio";
ste,pins = "gpio1_a_1";
function = "gpio";
groups = "gpio1_a_1";
};
default_cfg {
ste,pins = "GPIO1_N4";
pins = "GPIO1_N4";
input-enable;
bias-pull-down;
};
......@@ -212,22 +212,22 @@ default_cfg {
sysclkreq4 {
sysclkreq4_default_mode: sysclkreq4_default {
default_mux {
ste,function = "sysclkreq";
ste,pins = "sysclkreq4_d_1";
function = "sysclkreq";
groups = "sysclkreq4_d_1";
};
default_cfg {
ste,pins = "GPIO3_P5";
pins = "GPIO3_P5";
input-enable;
bias-disable;
};
};
sysclkreq4_sleep_mode: sysclkreq4_sleep {
default_mux {
ste,function = "gpio";
ste,pins = "gpio3_a_1";
function = "gpio";
groups = "gpio3_a_1";
};
default_cfg {
ste,pins = "GPIO3_P5";
pins = "GPIO3_P5";
input-enable;
bias-pull-down;
};
......
......@@ -103,7 +103,7 @@ pinctrl {
prox {
prox_stuib_mode: prox_stuib {
stuib_cfg {
ste,pins = "GPIO217_AH12";
pins = "GPIO217_AH12";
ste,config = <&gpio_in_pu>;
};
};
......@@ -111,7 +111,7 @@ stuib_cfg {
hall {
hall_stuib_mode: stuib_tvk {
stuib_cfg {
ste,pins = "GPIO145_C13";
pins = "GPIO145_C13";
ste,config = <&gpio_in_pu>;
};
};
......
......@@ -130,7 +130,7 @@ pinctrl {
tc35893 {
tc35893_tvk_mode: tc35893_tvk {
tvk_cfg {
ste,pins = "GPIO218_AH11";
pins = "GPIO218_AH11";
ste,config = <&gpio_in_pu>;
};
};
......@@ -138,7 +138,7 @@ tvk_cfg {
prox {
prox_tvk_mode: prox_tvk {
tvk_cfg {
ste,pins = "GPIO217_AH12";
pins = "GPIO217_AH12";
ste,config = <&gpio_in_pu>;
};
};
......@@ -146,7 +146,7 @@ tvk_cfg {
hall {
hall_tvk_mode: hall_tvk {
tvk_cfg {
ste,pins = "GPIO145_C13";
pins = "GPIO145_C13";
ste,config = <&gpio_in_pu>;
};
};
......@@ -155,7 +155,7 @@ accelerometer {
accel_tvk_mode: accel_tvk {
/* Accelerometer interrupt lines 1 & 2 */
tvk_cfg {
ste,pins = "GPIO82_C1", "GPIO83_D3";
pins = "GPIO82_C1", "GPIO83_D3";
ste,config = <&gpio_in_pu>;
};
};
......@@ -164,11 +164,11 @@ magnetometer {
magneto_tvk_mode: magneto_tvk {
/* Magnetometer uses GPIO 31 and 32, pull these up/down respectively */
tvk_cfg1 {
ste,pins = "GPIO31_V3";
pins = "GPIO31_V3";
ste,config = <&gpio_in_pu>;
};
tvk_cfg2 {
ste,pins = "GPIO32_V2";
pins = "GPIO32_V2";
ste,config = <&gpio_in_pd>;
};
};
......
......@@ -79,11 +79,11 @@ pinctrl {
ssp0 {
ssp0_hrefprev60_mode: ssp0_hrefprev60_default {
hrefprev60_mux {
ste,function = "ssp0";
ste,pins = "ssp0_a_1";
function = "ssp0";
groups = "ssp0_a_1";
};
hrefprev60_cfg1 {
ste,pins = "GPIO145_C13"; /* RXD */
pins = "GPIO145_C13"; /* RXD */
ste,config = <&in_pd>;
};
......@@ -93,11 +93,11 @@ sdi0 {
/* This additional pin needed on early MOP500 and HREFs previous to v60 */
sdi0_default_mode: sdi0_default {
hrefprev60_mux {
ste,function = "mc0";
ste,pins = "mc0dat31dir_a_1";
function = "mc0";
groups = "mc0dat31dir_a_1";
};
hrefprev60_cfg1 {
ste,pins = "GPIO21_AB3"; /* DAT31DIR */
pins = "GPIO21_AB3"; /* DAT31DIR */
ste,config = <&out_hi>;
};
......@@ -106,7 +106,7 @@ hrefprev60_cfg1 {
tc35892 {
tc35892_hrefprev60_mode: tc35892_hrefprev60 {
hrefprev60_cfg {
ste,pins = "GPIO217_AH12";
pins = "GPIO217_AH12";
ste,config = <&gpio_in_pu>;
};
};
......@@ -114,11 +114,11 @@ hrefprev60_cfg {
ipgpio {
ipgpio_hrefprev60_mode: ipgpio_hrefprev60 {
hrefprev60_mux {
ste,function = "ipgpio";
ste,pins = "ipgpio0_c_1", "ipgpio1_c_1";
function = "ipgpio";
groups = "ipgpio0_c_1", "ipgpio1_c_1";
};
hrefprev60_cfg1 {
ste,pins = "GPIO6_AF6", "GPIO7_AG5";
pins = "GPIO6_AF6", "GPIO7_AG5";
ste,config = <&in_pu>;
};
};
......
......@@ -49,7 +49,7 @@ sdi0 {
/* SD card detect GPIO pin, extend default state */
sdi0_default_mode: sdi0_default {
default_hrefv60_cfg1 {
ste,pins = "GPIO95_E8";
pins = "GPIO95_E8";
ste,config = <&gpio_in_pu>;
};
};
......@@ -64,19 +64,19 @@ ipgpio {
*/
ipgpio_hrefv60_mode: ipgpio_hrefv60 {
hrefv60_mux {
ste,function = "ipgpio";
ste,pins = "ipgpio0_c_1", "ipgpio1_c_1", "ipgpio4_c_1";
function = "ipgpio";
groups = "ipgpio0_c_1", "ipgpio1_c_1", "ipgpio4_c_1";
};
hrefv60_cfg1 {
ste,pins = "GPIO6_AF6", "GPIO7_AG5";
pins = "GPIO6_AF6", "GPIO7_AG5";
ste,config = <&in_pu>;
};
hrefv60_cfg2 {
ste,pins = "GPIO21_AB3";
pins = "GPIO21_AB3";
ste,config = <&gpio_out_lo>;
};
hrefv60_cfg3 {
ste,pins = "GPIO64_F3";
pins = "GPIO64_F3";
ste,config = <&out_lo>;
};
};
......@@ -89,7 +89,7 @@ etm {
*/
etm_hrefv60_mode: etm_hrefv60 {
hrefv60_cfg1 {
ste,pins =
pins =
"GPIO70_G5",
"GPIO71_G4",
"GPIO72_H4",
......@@ -103,11 +103,11 @@ nahj {
nahj_hrefv60_mode: nahj_hrefv60 {
/* NAHJ CTRL on GPIO76 to low, CTRL_INV on GPIO216 to high */
hrefv60_cfg1 {
ste,pins = "GPIO76_J2";
pins = "GPIO76_J2";
ste,config = <&gpio_out_lo>;
};
hrefv60_cfg2 {
ste,pins = "GPIO216_AG12";
pins = "GPIO216_AG12";
ste,config = <&gpio_out_hi>;
};
};
......@@ -116,13 +116,13 @@ nfc {
nfc_hrefv60_mode: nfc_hrefv60 {
/* NFC ENA and RESET to low, pulldown IRQ line */
hrefv60_cfg1 {
ste,pins =
pins =
"GPIO77_H1", /* NFC_ENA */
"GPIO142_C11"; /* NFC_RESET */
ste,config = <&gpio_out_lo>;
};
hrefv60_cfg2 {
ste,pins = "GPIO144_B13"; /* NFC_IRQ */
pins = "GPIO144_B13"; /* NFC_IRQ */
ste,config = <&gpio_in_pd>;
};
};
......@@ -130,11 +130,11 @@ hrefv60_cfg2 {
force {
force_hrefv60_mode: force_hrefv60 {
hrefv60_cfg1 {
ste,pins = "GPIO91_B6"; /* FORCE_SENSING_INT */
pins = "GPIO91_B6"; /* FORCE_SENSING_INT */
ste,config = <&gpio_in_pu>;
};
hrefv60_cfg2 {
ste,pins =
pins =
"GPIO92_D6", /* FORCE_SENSING_RST */
"GPIO97_D9"; /* FORCE_SENSING_WU */
ste,config = <&gpio_out_lo>;
......@@ -144,7 +144,7 @@ hrefv60_cfg2 {
dipro {
dipro_hrefv60_mode: dipro_hrefv60 {
hrefv60_cfg1 {
ste,pins = "GPIO139_C9"; /* DIPRO_INT */
pins = "GPIO139_C9"; /* DIPRO_INT */
ste,config = <&gpio_in_pu>;
};
};
......@@ -153,7 +153,7 @@ vaudio_hf {
vaudio_hf_hrefv60_mode: vaudio_hf_hrefv60 {
/* Audio Amplifier HF enable GPIO */
hrefv60_cfg1 {
ste,pins = "GPIO149_B14"; /* VAUDIO_HF_EN, enable MAX8968 */
pins = "GPIO149_B14"; /* VAUDIO_HF_EN, enable MAX8968 */
ste,config = <&gpio_out_hi>;
};
};
......@@ -165,7 +165,7 @@ gbf_hrefv60_mode: gbf_hrefv60 {
* pull low to reset state
*/
hrefv60_cfg1 {
ste,pins = "GPIO171_D23"; /* GBF_ENA_RESET */
pins = "GPIO171_D23"; /* GBF_ENA_RESET */
ste,config = <&gpio_out_lo>;
};
};
......@@ -174,7 +174,7 @@ hdtv {
hdtv_hrefv60_mode: hdtv_hrefv60 {
/* MSP : HDTV INTERFACE GPIO line */
hrefv60_cfg1 {
ste,pins = "GPIO192_AJ27";
pins = "GPIO192_AJ27";
ste,config = <&gpio_in_pd>;
};
};
......@@ -187,11 +187,11 @@ touch_hrefv60_mode: touch_hrefv60 {
* reset signals low.
*/
hrefv60_cfg1 {
ste,pins = "GPIO143_D12", "GPIO146_D13";
pins = "GPIO143_D12", "GPIO146_D13";
ste,config = <&gpio_out_lo>;
};
hrefv60_cfg2 {
ste,pins = "GPIO67_G2";
pins = "GPIO67_G2";
ste,config = <&gpio_in_pu>;
};
};
......@@ -204,11 +204,11 @@ lcd_hrefv60_mode: lcd_hrefv60 {
* Drive DISP1 reset high (not reset), driver DISP2 reset low (reset)
*/
hrefv60_cfg1 {
ste,pins ="GPIO65_F1";
pins ="GPIO65_F1";
ste,config = <&gpio_out_hi>;
};
hrefv60_cfg2 {
ste,pins ="GPIO66_G3";
pins ="GPIO66_G3";
ste,config = <&gpio_out_lo>;
};
};
......
......@@ -30,12 +30,12 @@ mmcsd-cd {
cd_default_mode: cd_default {
cd_default_cfg1 {
/* CD input GPIO */
ste,pins = "GPIO111_H21";
pins = "GPIO111_H21";
ste,input = <0>;
};
cd_default_cfg2 {
/* CD GPIO biasing */
ste,pins = "GPIO112_J21";
pins = "GPIO112_J21";
ste,output = <0>;
};
};
......@@ -43,7 +43,7 @@ cd_default_cfg2 {
gpioi2c {
gpioi2c_default_mode: gpioi2c_default {
gpioi2c_default_cfg {
ste,pins = "GPIO73_C21", "GPIO74_C20";
pins = "GPIO73_C21", "GPIO74_C20";
ste,input = <0>;
};
};
......@@ -51,7 +51,7 @@ gpioi2c_default_cfg {
user-led {
user_led_default_mode: user_led_default {
user_led_default_cfg {
ste,pins = "GPIO2_C5";
pins = "GPIO2_C5";
ste,output = <1>;
};
};
......@@ -59,7 +59,7 @@ user_led_default_cfg {
user-button {
user_button_default_mode: user_button_default {
user_button_default_cfg {
ste,pins = "GPIO3_A4";
pins = "GPIO3_A4";
ste,input = <0>;
};
};
......
......@@ -100,41 +100,41 @@ pinctrl {
uart0 {
uart0_default_mux: uart0_mux {
u0_default_mux {
ste,function = "u0";
ste,pins = "u0_a_1";
function = "u0";
groups = "u0_a_1";
};
};
};
uart1 {
uart1_default_mux: uart1_mux {
u1_default_mux {
ste,function = "u1";
ste,pins = "u1_a_1";
function = "u1";
groups = "u1_a_1";
};
};
};
mmcsd {
mmcsd_default_mux: mmcsd_mux {
mmcsd_default_mux {
ste,function = "mmcsd";
ste,pins = "mmcsd_a_1", "mmcsd_b_1";
function = "mmcsd";
groups = "mmcsd_a_1", "mmcsd_b_1";
};
};
mmcsd_default_mode: mmcsd_default {
mmcsd_default_cfg1 {
/* MCCLK */
ste,pins = "GPIO8_B10";
pins = "GPIO8_B10";
ste,output = <0>;
};
mmcsd_default_cfg2 {
/* MCCMDDIR, MCDAT0DIR, MCDAT31DIR, MCDATDIR2 */
ste,pins = "GPIO10_C11", "GPIO15_A12",
pins = "GPIO10_C11", "GPIO15_A12",
"GPIO16_C13", "GPIO23_D15";
ste,output = <1>;
};
mmcsd_default_cfg3 {
/* MCCMD, MCDAT3-0, MCMSFBCLK */
ste,pins = "GPIO9_A10", "GPIO11_B11",
pins = "GPIO9_A10", "GPIO11_B11",
"GPIO12_A11", "GPIO13_C12",
"GPIO14_B12", "GPIO24_C15";
ste,input = <1>;
......@@ -144,13 +144,13 @@ mmcsd_default_cfg3 {
i2c0 {
i2c0_default_mux: i2c0_mux {
i2c0_default_mux {
ste,function = "i2c0";
ste,pins = "i2c0_a_1";
function = "i2c0";
groups = "i2c0_a_1";
};
};
i2c0_default_mode: i2c0_default {
i2c0_default_cfg {
ste,pins = "GPIO62_D3", "GPIO63_D2";
pins = "GPIO62_D3", "GPIO63_D2";
ste,input = <0>;
};
};
......@@ -158,13 +158,13 @@ i2c0_default_cfg {
i2c1 {
i2c1_default_mux: i2c1_mux {
i2c1_default_mux {
ste,function = "i2c1";
ste,pins = "i2c1_a_1";
function = "i2c1";
groups = "i2c1_a_1";
};
};
i2c1_default_mode: i2c1_default {
i2c1_default_cfg {
ste,pins = "GPIO53_L4", "GPIO54_L3";
pins = "GPIO53_L4", "GPIO54_L3";
ste,input = <0>;
};
};
......
......@@ -404,17 +404,17 @@ ethernet {
*/
eth_snowball_mode: eth_snowball {
snowball_mux {
ste,function = "sm";
ste,pins = "sm_b_1";
function = "sm";
groups = "sm_b_1";
};
/* LAN IRQ pin */
snowball_cfg1 {
ste,pins = "GPIO140_B11";
pins = "GPIO140_B11";
ste,config = <&in_nopull>;
};
/* LAN reset pin */
snowball_cfg2 {
ste,pins = "GPIO141_C12";
pins = "GPIO141_C12";
ste,config = <&gpio_out_hi>;
};
......@@ -423,11 +423,11 @@ snowball_cfg2 {
sdi0 {
sdi0_default_mode: sdi0_default {
snowball_mux {
ste,function = "mc0";
ste,pins = "mc0dat31dir_a_1";
function = "mc0";
groups = "mc0dat31dir_a_1";
};
snowball_cfg1 {
ste,pins = "GPIO21_AB3"; /* DAT31DIR */
pins = "GPIO21_AB3"; /* DAT31DIR */
ste,config = <&out_hi>;
};
......@@ -436,19 +436,19 @@ snowball_cfg1 {
ssp0 {
ssp0_snowball_mode: ssp0_snowball_default {
snowball_mux {
ste,function = "ssp0";
ste,pins = "ssp0_a_1";
function = "ssp0";
groups = "ssp0_a_1";
};
snowball_cfg1 {
ste,pins = "GPIO144_B13"; /* FRM */
pins = "GPIO144_B13"; /* FRM */
ste,config = <&gpio_out_hi>;
};
snowball_cfg2 {
ste,pins = "GPIO145_C13"; /* RXD */
pins = "GPIO145_C13"; /* RXD */
ste,config = <&in_pd>;
};
snowball_cfg3 {
ste,pins =
pins =
"GPIO146_D13", /* TXD */
"GPIO143_D12"; /* CLK */
ste,config = <&out_lo>;
......@@ -459,7 +459,7 @@ snowball_cfg3 {
gpio_led {
gpioled_snowball_mode: gpioled_default {
snowball_cfg1 {
ste,pins = "GPIO142_C11";
pins = "GPIO142_C11";
ste,config = <&gpio_out_hi>;
};
......@@ -469,7 +469,7 @@ accelerometer {
accel_snowball_mode: accel_snowball {
/* Accelerometer lines */
snowball_cfg1 {
ste,pins =
pins =
"GPIO163_C20", /* ACCEL_IRQ1 */
"GPIO164_B21"; /* ACCEL_IRQ2 */
ste,config = <&gpio_in_pu>;
......@@ -479,7 +479,7 @@ snowball_cfg1 {
magnetometer {
magneto_snowball_mode: magneto_snowball {
snowball_cfg1 {
ste,pins = "GPIO165_C21"; /* MAG_DRDY */
pins = "GPIO165_C21"; /* MAG_DRDY */
ste,config = <&gpio_in_pu>;
};
};
......@@ -491,7 +491,7 @@ gbf_snowball_mode: gbf_snowball {
* pull low to reset state
*/
snowball_cfg1 {
ste,pins = "GPIO171_D23"; /* GBF_ENA_RESET */
pins = "GPIO171_D23"; /* GBF_ENA_RESET */
ste,config = <&gpio_out_lo>;
};
};
......@@ -503,13 +503,13 @@ wlan_snowball_mode: wlan_snowball {
* These are plain GPIO pins used by WLAN
*/
snowball_cfg1 {
ste,pins =
pins =
"GPIO161_D21", /* WLAN_PMU_EN */
"GPIO215_AH13"; /* WLAN_ENA */
ste,config = <&gpio_out_lo>;
};
snowball_cfg2 {
ste,pins = "GPIO216_AG12"; /* WLAN_IRQ */
pins = "GPIO216_AG12"; /* WLAN_IRQ */
ste,config = <&gpio_in_pu>;
};
};
......
......@@ -446,7 +446,7 @@ static int tz1090_gpio_bank_probe(struct tz1090_gpio_bank_info *info)
bank->irq = irq_of_parse_and_map(np, 0);
/* The interrupt is optional (it may be used by another core on chip) */
if (bank->irq < 0) {
if (!bank->irq) {
dev_info(dev, "IRQ not provided for bank %u, IRQs disabled\n",
info->index);
return 0;
......
......@@ -11,12 +11,14 @@
*/
#include <linux/errno.h>
#include <linux/gpio.h>
#include <linux/gpio/consumer.h>
#include <linux/gpio/driver.h>
#include <linux/export.h>
#include <linux/acpi.h>
#include <linux/interrupt.h>
#include <linux/mutex.h>
#include <linux/pinctrl/pinctrl.h>
#include "gpiolib.h"
......@@ -55,6 +57,58 @@ static int acpi_gpiochip_find(struct gpio_chip *gc, void *data)
return ACPI_HANDLE(gc->dev) == data;
}
#ifdef CONFIG_PINCTRL
/**
* acpi_gpiochip_pin_to_gpio_offset() - translates ACPI GPIO to Linux GPIO
* @chip: GPIO chip
* @pin: ACPI GPIO pin number from GpioIo/GpioInt resource
*
* Function takes ACPI GpioIo/GpioInt pin number as a parameter and
* translates it to a corresponding offset suitable to be passed to a
* GPIO controller driver.
*
* Typically the returned offset is same as @pin, but if the GPIO
* controller uses pin controller and the mapping is not contigous the
* offset might be different.
*/
static int acpi_gpiochip_pin_to_gpio_offset(struct gpio_chip *chip, int pin)
{
struct gpio_pin_range *pin_range;
/* If there are no ranges in this chip, use 1:1 mapping */
if (list_empty(&chip->pin_ranges))
return pin;
list_for_each_entry(pin_range, &chip->pin_ranges, node) {
const struct pinctrl_gpio_range *range = &pin_range->range;
int i;
if (range->pins) {
for (i = 0; i < range->npins; i++) {
if (range->pins[i] == pin)
return range->base + i - chip->base;
}
} else {
if (pin >= range->pin_base &&
pin < range->pin_base + range->npins) {
unsigned gpio_base;
gpio_base = range->base - chip->base;
return gpio_base + pin - range->pin_base;
}
}
}
return -EINVAL;
}
#else
static inline int acpi_gpiochip_pin_to_gpio_offset(struct gpio_chip *chip,
int pin)
{
return pin;
}
#endif
/**
* acpi_get_gpiod() - Translate ACPI GPIO pin to GPIO descriptor usable with GPIO API
* @path: ACPI GPIO controller full path name, (e.g. "\\_SB.GPO1")
......@@ -69,6 +123,7 @@ static struct gpio_desc *acpi_get_gpiod(char *path, int pin)
struct gpio_chip *chip;
acpi_handle handle;
acpi_status status;
int offset;
status = acpi_get_handle(NULL, path, &handle);
if (ACPI_FAILURE(status))
......@@ -78,10 +133,11 @@ static struct gpio_desc *acpi_get_gpiod(char *path, int pin)
if (!chip)
return ERR_PTR(-ENODEV);
if (pin < 0 || pin > chip->ngpio)
return ERR_PTR(-EINVAL);
offset = acpi_gpiochip_pin_to_gpio_offset(chip, pin);
if (offset < 0)
return ERR_PTR(offset);
return gpiochip_get_desc(chip, pin);
return gpiochip_get_desc(chip, offset);
}
static irqreturn_t acpi_gpio_irq_handler(int irq, void *data)
......
......@@ -67,18 +67,6 @@ config PINCTRL_AT91
help
Say Y here to enable the at91 pinctrl driver
config PINCTRL_BAYTRAIL
bool "Intel Baytrail GPIO pin control"
depends on GPIOLIB && ACPI && X86
select GPIOLIB_IRQCHIP
help
driver for memory mapped GPIO functionality on Intel Baytrail
platforms. Supports 3 banks with 102, 28 and 44 gpios.
Most pins are usually muxed to some other functionality by firmware,
so only a small amount is available for gpio use.
Requires ACPI device enumeration code to set up a platform device.
config PINCTRL_BCM2835
bool
select PINMUX
......@@ -205,6 +193,7 @@ config PINCTRL_PALMAS
source "drivers/pinctrl/berlin/Kconfig"
source "drivers/pinctrl/freescale/Kconfig"
source "drivers/pinctrl/intel/Kconfig"
source "drivers/pinctrl/mvebu/Kconfig"
source "drivers/pinctrl/nomadik/Kconfig"
source "drivers/pinctrl/qcom/Kconfig"
......
......@@ -15,7 +15,6 @@ obj-$(CONFIG_PINCTRL_BF54x) += pinctrl-adi2-bf54x.o
obj-$(CONFIG_PINCTRL_BF60x) += pinctrl-adi2-bf60x.o
obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o
obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o
obj-$(CONFIG_PINCTRL_BAYTRAIL) += pinctrl-baytrail.o
obj-$(CONFIG_PINCTRL_BCM281XX) += pinctrl-bcm281xx.o
obj-$(CONFIG_PINCTRL_FALCON) += pinctrl-falcon.o
obj-$(CONFIG_PINCTRL_PALMAS) += pinctrl-palmas.o
......@@ -39,6 +38,7 @@ obj-$(CONFIG_PINCTRL_ST) += pinctrl-st.o
obj-$(CONFIG_ARCH_BERLIN) += berlin/
obj-y += freescale/
obj-$(CONFIG_X86) += intel/
obj-$(CONFIG_PLAT_ORION) += mvebu/
obj-y += nomadik/
obj-$(CONFIG_ARCH_QCOM) += qcom/
......
......@@ -294,11 +294,83 @@ static int imx_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
return 0;
}
static int imx_pmx_gpio_request_enable(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range, unsigned offset)
{
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
const struct imx_pinctrl_soc_info *info = ipctl->info;
const struct imx_pin_reg *pin_reg;
struct imx_pin_group *grp;
struct imx_pin *imx_pin;
unsigned int pin, group;
u32 reg;
/* Currently implementation only for shared mux/conf register */
if (!(info->flags & SHARE_MUX_CONF_REG))
return -EINVAL;
pin_reg = &info->pin_regs[offset];
if (pin_reg->mux_reg == -1)
return -EINVAL;
/* Find the pinctrl config with GPIO mux mode for the requested pin */
for (group = 0; group < info->ngroups; group++) {
grp = &info->groups[group];
for (pin = 0; pin < grp->npins; pin++) {
imx_pin = &grp->pins[pin];
if (imx_pin->pin == offset && !imx_pin->mux_mode)
goto mux_pin;
}
}
return -EINVAL;
mux_pin:
reg = readl(ipctl->base + pin_reg->mux_reg);
reg &= ~(0x7 << 20);
reg |= imx_pin->config;
writel(reg, ipctl->base + pin_reg->mux_reg);
return 0;
}
static int imx_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range, unsigned offset, bool input)
{
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
const struct imx_pinctrl_soc_info *info = ipctl->info;
const struct imx_pin_reg *pin_reg;
u32 reg;
/*
* Only Vybrid has the input/output buffer enable flags (IBE/OBE)
* They are part of the shared mux/conf register.
*/
if (!(info->flags & SHARE_MUX_CONF_REG))
return -EINVAL;
pin_reg = &info->pin_regs[offset];
if (pin_reg->mux_reg == -1)
return -EINVAL;
/* IBE always enabled allows us to read the value "on the wire" */
reg = readl(ipctl->base + pin_reg->mux_reg);
if (input)
reg &= ~0x2;
else
reg |= 0x2;
writel(reg, ipctl->base + pin_reg->mux_reg);
return 0;
}
static const struct pinmux_ops imx_pmx_ops = {
.get_functions_count = imx_pmx_get_funcs_count,
.get_function_name = imx_pmx_get_func_name,
.get_function_groups = imx_pmx_get_groups,
.set_mux = imx_pmx_set,
.gpio_request_enable = imx_pmx_gpio_request_enable,
.gpio_set_direction = imx_pmx_gpio_set_direction,
};
static int imx_pinconf_get(struct pinctrl_dev *pctldev,
......
......@@ -445,6 +445,31 @@ static int mxs_pinctrl_probe_dt(struct platform_device *pdev,
if (of_property_read_u32(child, "reg", &val))
continue;
if (strcmp(fn, child->name)) {
struct device_node *child2;
/*
* This reference is dropped by
* of_get_next_child(np, * child)
*/
of_node_get(child);
/*
* The logic parsing the functions from dt currently
* doesn't handle if functions with the same name are
* not grouped together. Only the first contiguous
* cluster is usable for each function name. This is a
* bug that is not trivial to fix, but at least warn
* about it.
*/
for (child2 = of_get_next_child(np, child);
child2 != NULL;
child2 = of_get_next_child(np, child2)) {
if (!strcmp(child2->name, fn))
dev_warn(&pdev->dev,
"function nodes must be grouped by name (failed for: %s)",
fn);
}
f = &soc->functions[idxf++];
f->name = fn = child->name;
}
......
#
# Intel pin control drivers
#
config PINCTRL_BAYTRAIL
bool "Intel Baytrail GPIO pin control"
depends on GPIOLIB && ACPI
select GPIOLIB_IRQCHIP
help
driver for memory mapped GPIO functionality on Intel Baytrail
platforms. Supports 3 banks with 102, 28 and 44 gpios.
Most pins are usually muxed to some other functionality by firmware,
so only a small amount is available for gpio use.
Requires ACPI device enumeration code to set up a platform device.
config PINCTRL_CHERRYVIEW
tristate "Intel Cherryview/Braswell pinctrl and GPIO driver"
depends on ACPI
select PINMUX
select PINCONF
select GENERIC_PINCONF
select GPIOLIB
select GPIOLIB_IRQCHIP
help
Cherryview/Braswell pinctrl driver provides an interface that
allows configuring of SoC pins and using them as GPIOs.
# Intel pin control drivers
obj-$(CONFIG_PINCTRL_BAYTRAIL) += pinctrl-baytrail.o
obj-$(CONFIG_PINCTRL_CHERRYVIEW) += pinctrl-cherryview.o
......@@ -616,5 +616,10 @@ static int __init byt_gpio_init(void)
{
return platform_driver_register(&byt_gpio_driver);
}
subsys_initcall(byt_gpio_init);
static void __exit byt_gpio_exit(void)
{
platform_driver_unregister(&byt_gpio_driver);
}
module_exit(byt_gpio_exit);
This diff is collapsed.
......@@ -891,14 +891,13 @@ static int abx500_dt_subnode_to_map(struct pinctrl_dev *pctldev,
const char *function = NULL;
unsigned long *configs;
unsigned int nconfigs = 0;
bool has_config = 0;
struct property *prop;
const char *group, *gpio_name;
struct device_node *np_config;
ret = of_property_read_string(np, "ste,function", &function);
ret = of_property_read_string(np, "function", &function);
if (ret >= 0) {
ret = of_property_count_strings(np, "ste,pins");
const char *group;
ret = of_property_count_strings(np, "groups");
if (ret < 0)
goto exit;
......@@ -907,7 +906,7 @@ static int abx500_dt_subnode_to_map(struct pinctrl_dev *pctldev,
if (ret < 0)
goto exit;
of_property_for_each_string(np, "ste,pins", prop, group) {
of_property_for_each_string(np, "groups", prop, group) {
ret = abx500_dt_add_map_mux(map, reserved_maps,
num_maps, group, function);
if (ret < 0)
......@@ -916,18 +915,11 @@ static int abx500_dt_subnode_to_map(struct pinctrl_dev *pctldev,
}
ret = pinconf_generic_parse_dt_config(np, &configs, &nconfigs);
if (nconfigs)
has_config = 1;
np_config = of_parse_phandle(np, "ste,config", 0);
if (np_config) {
ret = pinconf_generic_parse_dt_config(np_config, &configs,
&nconfigs);
if (ret)
goto exit;
has_config |= nconfigs;
}
if (has_config) {
ret = of_property_count_strings(np, "ste,pins");
if (nconfigs) {
const char *gpio_name;
const char *pin;
ret = of_property_count_strings(np, "pins");
if (ret < 0)
goto exit;
......@@ -937,8 +929,8 @@ static int abx500_dt_subnode_to_map(struct pinctrl_dev *pctldev,
if (ret < 0)
goto exit;
of_property_for_each_string(np, "ste,pins", prop, group) {
gpio_name = abx500_find_pin_name(pctldev, group);
of_property_for_each_string(np, "pins", prop, pin) {
gpio_name = abx500_find_pin_name(pctldev, pin);
ret = abx500_dt_add_map_configs(map, reserved_maps,
num_maps, gpio_name, configs, 1);
......@@ -1112,6 +1104,7 @@ static int abx500_pin_config_set(struct pinctrl_dev *pctldev,
static const struct pinconf_ops abx500_pinconf_ops = {
.pin_config_get = abx500_pin_config_get,
.pin_config_set = abx500_pin_config_set,
.is_generic = true,
};
static struct pinctrl_desc abx500_pinctrl_desc = {
......
......@@ -291,6 +291,7 @@ static const unsigned u0_a_1_pins[] = { STN8815_PIN_B4, STN8815_PIN_D5,
static const unsigned mmcsd_a_1_pins[] = { STN8815_PIN_B10, STN8815_PIN_A10,
STN8815_PIN_C11, STN8815_PIN_B11, STN8815_PIN_A11, STN8815_PIN_C12,
STN8815_PIN_B12, STN8815_PIN_A12, STN8815_PIN_C13, STN8815_PIN_C15 };
static const unsigned mmcsd_b_1_pins[] = { STN8815_PIN_D15 };
static const unsigned u1_a_1_pins[] = { STN8815_PIN_M2, STN8815_PIN_L1,
STN8815_PIN_F3, STN8815_PIN_F2 };
static const unsigned i2c1_a_1_pins[] = { STN8815_PIN_L4, STN8815_PIN_L3 };
......@@ -305,6 +306,7 @@ static const unsigned i2cusb_b_1_pins[] = { STN8815_PIN_C21, STN8815_PIN_C20 };
static const struct nmk_pingroup nmk_stn8815_groups[] = {
STN8815_PIN_GROUP(u0_a_1, NMK_GPIO_ALT_A),
STN8815_PIN_GROUP(mmcsd_a_1, NMK_GPIO_ALT_A),
STN8815_PIN_GROUP(mmcsd_b_1, NMK_GPIO_ALT_B),
STN8815_PIN_GROUP(u1_a_1, NMK_GPIO_ALT_A),
STN8815_PIN_GROUP(i2c1_a_1, NMK_GPIO_ALT_A),
STN8815_PIN_GROUP(i2c0_a_1, NMK_GPIO_ALT_A),
......@@ -317,7 +319,7 @@ static const struct nmk_pingroup nmk_stn8815_groups[] = {
static const char * const a##_groups[] = { b };
STN8815_FUNC_GROUPS(u0, "u0_a_1");
STN8815_FUNC_GROUPS(mmcsd, "mmcsd_a_1");
STN8815_FUNC_GROUPS(mmcsd, "mmcsd_a_1", "mmcsd_b_1");
STN8815_FUNC_GROUPS(u1, "u1_a_1", "u1_b_1");
STN8815_FUNC_GROUPS(i2c1, "i2c1_a_1");
STN8815_FUNC_GROUPS(i2c0, "i2c0_a_1");
......
......@@ -1520,12 +1520,13 @@ static int nmk_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
unsigned long configs = 0;
bool has_config = 0;
struct property *prop;
const char *group, *gpio_name;
struct device_node *np_config;
ret = of_property_read_string(np, "ste,function", &function);
ret = of_property_read_string(np, "function", &function);
if (ret >= 0) {
ret = of_property_count_strings(np, "ste,pins");
const char *group;
ret = of_property_count_strings(np, "groups");
if (ret < 0)
goto exit;
......@@ -1535,7 +1536,7 @@ static int nmk_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
if (ret < 0)
goto exit;
of_property_for_each_string(np, "ste,pins", prop, group) {
of_property_for_each_string(np, "groups", prop, group) {
ret = nmk_dt_add_map_mux(map, reserved_maps, num_maps,
group, function);
if (ret < 0)
......@@ -1548,7 +1549,10 @@ static int nmk_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
if (np_config)
has_config |= nmk_pinctrl_dt_get_config(np_config, &configs);
if (has_config) {
ret = of_property_count_strings(np, "ste,pins");
const char *gpio_name;
const char *pin;
ret = of_property_count_strings(np, "pins");
if (ret < 0)
goto exit;
ret = pinctrl_utils_reserve_map(pctldev, map,
......@@ -1557,8 +1561,8 @@ static int nmk_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
if (ret < 0)
goto exit;
of_property_for_each_string(np, "ste,pins", prop, group) {
gpio_name = nmk_find_pin_name(pctldev, group);
of_property_for_each_string(np, "pins", prop, pin) {
gpio_name = nmk_find_pin_name(pctldev, pin);
ret = nmk_dt_add_map_configs(map, reserved_maps,
num_maps,
......
......@@ -32,30 +32,32 @@ struct pin_config_item {
const enum pin_config_param param;
const char * const display;
const char * const format;
bool has_arg;
};
#define PCONFDUMP(a, b, c) { .param = a, .display = b, .format = c }
#define PCONFDUMP(a, b, c, d) { .param = a, .display = b, .format = c, \
.has_arg = d }
static struct pin_config_item conf_items[] = {
PCONFDUMP(PIN_CONFIG_BIAS_DISABLE, "input bias disabled", NULL),
PCONFDUMP(PIN_CONFIG_BIAS_HIGH_IMPEDANCE, "input bias high impedance", NULL),
PCONFDUMP(PIN_CONFIG_BIAS_BUS_HOLD, "input bias bus hold", NULL),
PCONFDUMP(PIN_CONFIG_BIAS_PULL_UP, "input bias pull up", NULL),
PCONFDUMP(PIN_CONFIG_BIAS_PULL_DOWN, "input bias pull down", NULL),
static const struct pin_config_item conf_items[] = {
PCONFDUMP(PIN_CONFIG_BIAS_DISABLE, "input bias disabled", NULL, false),
PCONFDUMP(PIN_CONFIG_BIAS_HIGH_IMPEDANCE, "input bias high impedance", NULL, false),
PCONFDUMP(PIN_CONFIG_BIAS_BUS_HOLD, "input bias bus hold", NULL, false),
PCONFDUMP(PIN_CONFIG_BIAS_PULL_UP, "input bias pull up", NULL, false),
PCONFDUMP(PIN_CONFIG_BIAS_PULL_DOWN, "input bias pull down", NULL, false),
PCONFDUMP(PIN_CONFIG_BIAS_PULL_PIN_DEFAULT,
"input bias pull to pin specific state", NULL),
PCONFDUMP(PIN_CONFIG_DRIVE_PUSH_PULL, "output drive push pull", NULL),
PCONFDUMP(PIN_CONFIG_DRIVE_OPEN_DRAIN, "output drive open drain", NULL),
PCONFDUMP(PIN_CONFIG_DRIVE_OPEN_SOURCE, "output drive open source", NULL),
PCONFDUMP(PIN_CONFIG_DRIVE_STRENGTH, "output drive strength", "mA"),
PCONFDUMP(PIN_CONFIG_INPUT_ENABLE, "input enabled", NULL),
PCONFDUMP(PIN_CONFIG_INPUT_SCHMITT_ENABLE, "input schmitt enabled", NULL),
PCONFDUMP(PIN_CONFIG_INPUT_SCHMITT, "input schmitt trigger", NULL),
PCONFDUMP(PIN_CONFIG_INPUT_DEBOUNCE, "input debounce", "usec"),
PCONFDUMP(PIN_CONFIG_POWER_SOURCE, "pin power source", "selector"),
PCONFDUMP(PIN_CONFIG_SLEW_RATE, "slew rate", NULL),
PCONFDUMP(PIN_CONFIG_LOW_POWER_MODE, "pin low power", "mode"),
PCONFDUMP(PIN_CONFIG_OUTPUT, "pin output", "level"),
"input bias pull to pin specific state", NULL, false),
PCONFDUMP(PIN_CONFIG_DRIVE_PUSH_PULL, "output drive push pull", NULL, false),
PCONFDUMP(PIN_CONFIG_DRIVE_OPEN_DRAIN, "output drive open drain", NULL, false),
PCONFDUMP(PIN_CONFIG_DRIVE_OPEN_SOURCE, "output drive open source", NULL, false),
PCONFDUMP(PIN_CONFIG_DRIVE_STRENGTH, "output drive strength", "mA", true),
PCONFDUMP(PIN_CONFIG_INPUT_ENABLE, "input enabled", NULL, false),
PCONFDUMP(PIN_CONFIG_INPUT_SCHMITT_ENABLE, "input schmitt enabled", NULL, false),
PCONFDUMP(PIN_CONFIG_INPUT_SCHMITT, "input schmitt trigger", NULL, false),
PCONFDUMP(PIN_CONFIG_INPUT_DEBOUNCE, "input debounce", "usec", true),
PCONFDUMP(PIN_CONFIG_POWER_SOURCE, "pin power source", "selector", true),
PCONFDUMP(PIN_CONFIG_SLEW_RATE, "slew rate", NULL, true),
PCONFDUMP(PIN_CONFIG_LOW_POWER_MODE, "pin low power", "mode", true),
PCONFDUMP(PIN_CONFIG_OUTPUT, "pin output", "level", true),
};
void pinconf_generic_dump_pin(struct pinctrl_dev *pctldev,
......@@ -85,11 +87,14 @@ void pinconf_generic_dump_pin(struct pinctrl_dev *pctldev,
seq_puts(s, " ");
seq_puts(s, conf_items[i].display);
/* Print unit if available */
if (conf_items[i].format &&
pinconf_to_config_argument(config) != 0)
seq_printf(s, " (%u %s)",
pinconf_to_config_argument(config),
conf_items[i].format);
if (conf_items[i].has_arg) {
seq_printf(s, " (%u",
pinconf_to_config_argument(config));
if (conf_items[i].format)
seq_printf(s, " %s)", conf_items[i].format);
else
seq_puts(s, ")");
}
}
}
......@@ -121,10 +126,14 @@ void pinconf_generic_dump_group(struct pinctrl_dev *pctldev,
seq_puts(s, " ");
seq_puts(s, conf_items[i].display);
/* Print unit if available */
if (conf_items[i].format && config != 0)
seq_printf(s, " (%u %s)",
pinconf_to_config_argument(config),
conf_items[i].format);
if (conf_items[i].has_arg) {
seq_printf(s, " (%u",
pinconf_to_config_argument(config));
if (conf_items[i].format)
seq_printf(s, " %s)", conf_items[i].format);
else
seq_puts(s, ")");
}
}
}
......@@ -150,7 +159,7 @@ struct pinconf_generic_dt_params {
u32 default_value;
};
static struct pinconf_generic_dt_params dt_params[] = {
static const struct pinconf_generic_dt_params dt_params[] = {
{ "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
{ "bias-high-impedance", PIN_CONFIG_BIAS_HIGH_IMPEDANCE, 0 },
{ "bias-bus-hold", PIN_CONFIG_BIAS_BUS_HOLD, 0 },
......@@ -200,7 +209,7 @@ int pinconf_generic_parse_dt_config(struct device_node *np,
return -ENOMEM;
for (i = 0; i < ARRAY_SIZE(dt_params); i++) {
struct pinconf_generic_dt_params *par = &dt_params[i];
const struct pinconf_generic_dt_params *par = &dt_params[i];
ret = of_property_read_u32(np, par->property, &val);
/* property not found */
......
......@@ -25,9 +25,7 @@
/* Since we request GPIOs from ourself */
#include <linux/pinctrl/consumer.h>
#include <mach/hardware.h>
#include <mach/at91_pio.h>
#include "pinctrl-at91.h"
#include "core.h"
#define MAX_GPIO_BANKS 5
......@@ -1344,7 +1342,6 @@ static void at91_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
for (i = 0; i < chip->ngpio; i++) {
unsigned mask = pin_to_mask(i);
const char *gpio_label;
u32 pdsr;
gpio_label = gpiochip_is_requested(chip, i);
if (!gpio_label)
......@@ -1353,10 +1350,12 @@ static void at91_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
seq_printf(s, "[%s] GPIO%s%d: ",
gpio_label, chip->label, i);
if (mode == AT91_MUX_GPIO) {
pdsr = readl_relaxed(pio + PIO_PDSR);
seq_printf(s, "[gpio] %s\n",
pdsr & mask ?
seq_printf(s, "[gpio] ");
seq_printf(s, "%s ",
readl_relaxed(pio + PIO_OSR) & mask ?
"output" : "input");
seq_printf(s, "%s\n",
readl_relaxed(pio + PIO_PDSR) & mask ?
"set" : "clear");
} else {
seq_printf(s, "[periph %c]\n",
......
/*
* Copyright (C) 2005 Ivan Kokshaysky
* Copyright (C) SAN People
*
* Parallel I/O Controller (PIO) - System peripherals registers.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef __PINCTRL_AT91_H
#define __PINCTRL_AT91_H
#define PIO_PER 0x00 /* Enable Register */
#define PIO_PDR 0x04 /* Disable Register */
#define PIO_PSR 0x08 /* Status Register */
#define PIO_OER 0x10 /* Output Enable Register */
#define PIO_ODR 0x14 /* Output Disable Register */
#define PIO_OSR 0x18 /* Output Status Register */
#define PIO_IFER 0x20 /* Glitch Input Filter Enable */
#define PIO_IFDR 0x24 /* Glitch Input Filter Disable */
#define PIO_IFSR 0x28 /* Glitch Input Filter Status */
#define PIO_SODR 0x30 /* Set Output Data Register */
#define PIO_CODR 0x34 /* Clear Output Data Register */
#define PIO_ODSR 0x38 /* Output Data Status Register */
#define PIO_PDSR 0x3c /* Pin Data Status Register */
#define PIO_IER 0x40 /* Interrupt Enable Register */
#define PIO_IDR 0x44 /* Interrupt Disable Register */
#define PIO_IMR 0x48 /* Interrupt Mask Register */
#define PIO_ISR 0x4c /* Interrupt Status Register */
#define PIO_MDER 0x50 /* Multi-driver Enable Register */
#define PIO_MDDR 0x54 /* Multi-driver Disable Register */
#define PIO_MDSR 0x58 /* Multi-driver Status Register */
#define PIO_PUDR 0x60 /* Pull-up Disable Register */
#define PIO_PUER 0x64 /* Pull-up Enable Register */
#define PIO_PUSR 0x68 /* Pull-up Status Register */
#define PIO_ASR 0x70 /* Peripheral A Select Register */
#define PIO_ABCDSR1 0x70 /* Peripheral ABCD Select Register 1 [some sam9 only] */
#define PIO_BSR 0x74 /* Peripheral B Select Register */
#define PIO_ABCDSR2 0x74 /* Peripheral ABCD Select Register 2 [some sam9 only] */
#define PIO_ABSR 0x78 /* AB Status Register */
#define PIO_IFSCDR 0x80 /* Input Filter Slow Clock Disable Register */
#define PIO_IFSCER 0x84 /* Input Filter Slow Clock Enable Register */
#define PIO_IFSCSR 0x88 /* Input Filter Slow Clock Status Register */
#define PIO_SCDR 0x8c /* Slow Clock Divider Debouncing Register */
#define PIO_SCDR_DIV (0x3fff << 0) /* Slow Clock Divider Mask */
#define PIO_PPDDR 0x90 /* Pad Pull-down Disable Register */
#define PIO_PPDER 0x94 /* Pad Pull-down Enable Register */
#define PIO_PPDSR 0x98 /* Pad Pull-down Status Register */
#define PIO_OWER 0xa0 /* Output Write Enable Register */
#define PIO_OWDR 0xa4 /* Output Write Disable Register */
#define PIO_OWSR 0xa8 /* Output Write Status Register */
#define PIO_AIMER 0xb0 /* Additional Interrupt Modes Enable Register */
#define PIO_AIMDR 0xb4 /* Additional Interrupt Modes Disable Register */
#define PIO_AIMMR 0xb8 /* Additional Interrupt Modes Mask Register */
#define PIO_ESR 0xc0 /* Edge Select Register */
#define PIO_LSR 0xc4 /* Level Select Register */
#define PIO_ELSR 0xc8 /* Edge/Level Status Register */
#define PIO_FELLSR 0xd0 /* Falling Edge/Low Level Select Register */
#define PIO_REHLSR 0xd4 /* Rising Edge/ High Level Select Register */
#define PIO_FRLHSR 0xd8 /* Fall/Rise - Low/High Status Register */
#define PIO_SCHMITT 0x100 /* Schmitt Trigger Register */
#define SAMA5D3_PIO_DRIVER1 0x118 /*PIO Driver 1 register offset*/
#define SAMA5D3_PIO_DRIVER2 0x11C /*PIO Driver 2 register offset*/
#define AT91SAM9X5_PIO_DRIVER1 0x114 /*PIO Driver 1 register offset*/
#define AT91SAM9X5_PIO_DRIVER2 0x118 /*PIO Driver 2 register offset*/
#endif
......@@ -1404,11 +1404,6 @@ static int __init bcm281xx_pinctrl_probe(struct platform_device *pdev)
/* So far We can assume there is only 1 bank of registers */
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
dev_err(&pdev->dev, "Missing MEM resource\n");
return -ENODEV;
}
pdata->reg_base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(pdata->reg_base)) {
dev_err(&pdev->dev, "Failed to ioremap MEM resource\n");
......
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......@@ -1512,7 +1512,7 @@ static int st_gpiolib_register_bank(struct st_pinctrl *info,
gpio_irq, st_gpio_irq_handler);
}
if (info->irqmux_base > 0 || gpio_irq > 0) {
if (info->irqmux_base || gpio_irq > 0) {
err = gpiochip_irqchip_add(&bank->gpio_chip, &st_gpio_irqchip,
0, handle_simple_irq,
IRQ_TYPE_LEVEL_LOW);
......
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