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Commit c3d1f174 authored by Linus Torvalds's avatar Linus Torvalds
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Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/upstream-linus 

* 'upstream' of git://git.linux-mips.org/pub/scm/upstream-linus: (150 commits)
  MIPS: PowerTV: Separate PowerTV USB support from non-USB code
  MIPS: strip the un-needed sections of vmlinuz
  MIPS: Clean up the calculation of VMLINUZ_LOAD_ADDRESS
  MIPS: Clean up arch/mips/boot/compressed/decompress.c
  MIPS: Clean up arch/mips/boot/compressed/ld.script
  MIPS: Unify the suffix of compressed vmlinux.bin
  MIPS: PowerTV: Add Gaia platform definitions.
  MIPS: BCM47xx: Fix nvram_getenv return value.
  MIPS: Octeon: Allow more than 3.75GB of memory with PCIe
  MIPS: Clean up notify_die() usage.
  MIPS: Remove unused task_struct.trap_no field.
  Documentation: Mention that KProbes is supported on MIPS
  SAMPLES: kprobe_example: Make it print something on MIPS.
  MIPS: kprobe: Add support.
  MIPS: Add instrunction format for BREAK and SYSCALL
  MIPS: kprobes: Define regs_return_value()
  MIPS: Ritually kill stupid printk.
  MIPS: Octeon: Disallow MSI-X interrupt and fall back to MSI interrupts.
  MIPS: Octeon: Support 256 MSI on PCIe
  MIPS: Decode core number for R2 CPUs.
  ...
parents 66eddbfc 0d365753
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Documentation/kprobes.txt
View file @ c3d1f174
......@@ -285,6 +285,7 @@ architectures:
- sparc64 (Return probes not yet implemented.)
- arm
- ppc
- mips
3. Configuring Kprobes
......
arch/mips/Kbuild 0 → 100644
View file @ c3d1f174
# Fail on warnings - also for files referenced in subdirs
# -Werror can be disabled for specific files using:
# CFLAGS_<file.o> := -Wno-error
subdir-ccflags-y := -Werror
# platform specific definitions
include arch/mips/Kbuild.platforms
obj-y := $(platform-y)
# mips object files
# The object files are linked as core-y files would be linked
obj-y += kernel/
obj-y += mm/
obj-y += math-emu/
arch/mips/Kbuild.platforms 0 → 100644
View file @ c3d1f174
# All platforms listed in alphabetic order
platforms += alchemy
platforms += ar7
platforms += bcm47xx
platforms += bcm63xx
platforms += cavium-octeon
platforms += cobalt
platforms += dec
platforms += emma
platforms += jazz
platforms += jz4740
platforms += lasat
platforms += loongson
platforms += mipssim
platforms += mti-malta
platforms += pmc-sierra
platforms += pnx833x
platforms += pnx8550
platforms += powertv
platforms += rb532
platforms += sgi-ip22
platforms += sgi-ip27
platforms += sgi-ip32
platforms += sibyte
platforms += sni
platforms += txx9
platforms += vr41xx
platforms += wrppmc
# include the platform specific files
include $(patsubst %, $(srctree)/arch/mips/%/Platform, $(platforms))
arch/mips/Kconfig
View file @ c3d1f174
......@@ -10,6 +10,8 @@ config MIPS
select HAVE_DYNAMIC_FTRACE
select HAVE_FTRACE_MCOUNT_RECORD
select HAVE_FUNCTION_GRAPH_TRACER
select HAVE_KPROBES
select HAVE_KRETPROBES
select RTC_LIB if !MACH_LOONGSON
mainmenu "Linux/MIPS Kernel Configuration"
......@@ -23,8 +25,17 @@ choice
prompt "System type"
default SGI_IP22
config MACH_ALCHEMY
config MIPS_ALCHEMY
bool "Alchemy processor based machines"
select 64BIT_PHYS_ADDR
select CEVT_R4K_LIB
select CSRC_R4K_LIB
select IRQ_CPU
select SYS_HAS_CPU_MIPS32_R1
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_APM_EMULATION
select GENERIC_GPIO
select ARCH_WANT_OPTIONAL_GPIOLIB
select SYS_SUPPORTS_ZBOOT
config AR7
......@@ -62,6 +73,7 @@ config BCM47XX
select SSB_DRIVER_MIPS
select SSB_DRIVER_EXTIF
select SSB_EMBEDDED
select SSB_B43_PCI_BRIDGE if PCI
select SSB_PCICORE_HOSTMODE if PCI
select GENERIC_GPIO
select SYS_HAS_EARLY_PRINTK
......@@ -162,6 +174,18 @@ config MACH_JAZZ
Members include the Acer PICA, MIPS Magnum 4000, MIPS Millennium and
Olivetti M700-10 workstations.
config MACH_JZ4740
bool "Ingenic JZ4740 based machines"
select SYS_HAS_CPU_MIPS32_R1
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_LITTLE_ENDIAN
select DMA_NONCOHERENT
select IRQ_CPU
select GENERIC_GPIO
select ARCH_REQUIRE_GPIOLIB
select SYS_HAS_EARLY_PRINTK
select HAVE_PWM
config LASAT
bool "LASAT Networks platforms"
select CEVT_R4K
......@@ -686,6 +710,7 @@ endchoice
source "arch/mips/alchemy/Kconfig"
source "arch/mips/bcm63xx/Kconfig"
source "arch/mips/jazz/Kconfig"
source "arch/mips/jz4740/Kconfig"
source "arch/mips/lasat/Kconfig"
source "arch/mips/pmc-sierra/Kconfig"
source "arch/mips/powertv/Kconfig"
......@@ -892,6 +917,9 @@ config CPU_LITTLE_ENDIAN
endchoice
config EXPORT_UASM
bool
config SYS_SUPPORTS_APM_EMULATION
bool
......
arch/mips/Makefile
View file @ c3d1f174
This diff is collapsed.
arch/mips/alchemy/Kconfig
View file @ c3d1f174
......@@ -11,7 +11,7 @@ config ALCHEMY_GPIO_INDIRECT
choice
prompt "Machine type"
depends on MACH_ALCHEMY
depends on MIPS_ALCHEMY
default MIPS_DB1000
config MIPS_MTX1
......@@ -128,41 +128,33 @@ config MIPS_XXS1500
select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_HAS_EARLY_PRINTK
config MIPS_GPR
bool "Trapeze ITS GPR board"
select SOC_AU1550
select HW_HAS_PCI
select DMA_NONCOHERENT
select MIPS_DISABLE_OBSOLETE_IDE
select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_HAS_EARLY_PRINTK
endchoice
config SOC_AU1000
bool
select SOC_AU1X00
select ALCHEMY_GPIOINT_AU1000
config SOC_AU1100
bool
select SOC_AU1X00
select ALCHEMY_GPIOINT_AU1000
config SOC_AU1500
bool
select SOC_AU1X00
select ALCHEMY_GPIOINT_AU1000
config SOC_AU1550
bool
select SOC_AU1X00
select ALCHEMY_GPIOINT_AU1000
config SOC_AU1200
bool
select SOC_AU1X00
select ALCHEMY_GPIOINT_AU1000
config SOC_AU1X00
bool
select 64BIT_PHYS_ADDR
select CEVT_R4K_LIB
select CSRC_R4K_LIB
select IRQ_CPU
select SYS_HAS_CPU_MIPS32_R1
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_APM_EMULATION
select GENERIC_GPIO
select ARCH_WANT_OPTIONAL_GPIOLIB
arch/mips/alchemy/Platform 0 → 100644
View file @ c3d1f174
#
# Core Alchemy code
#
platform-$(CONFIG_MIPS_ALCHEMY) += alchemy/common/
#
# AMD Alchemy Pb1000 eval board
#
platform-$(CONFIG_MIPS_PB1000) += alchemy/devboards/
cflags-$(CONFIG_MIPS_PB1000) += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
load-$(CONFIG_MIPS_PB1000) += 0xffffffff80100000
#
# AMD Alchemy Pb1100 eval board
#
platform-$(CONFIG_MIPS_PB1100) += alchemy/devboards/
cflags-$(CONFIG_MIPS_PB1100) += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
load-$(CONFIG_MIPS_PB1100) += 0xffffffff80100000
#
# AMD Alchemy Pb1500 eval board
#
platform-$(CONFIG_MIPS_PB1500) += alchemy/devboards/
cflags-$(CONFIG_MIPS_PB1500) += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
load-$(CONFIG_MIPS_PB1500) += 0xffffffff80100000
#
# AMD Alchemy Pb1550 eval board
#
platform-$(CONFIG_MIPS_PB1550) += alchemy/devboards/
cflags-$(CONFIG_MIPS_PB1550) += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
load-$(CONFIG_MIPS_PB1550) += 0xffffffff80100000
#
# AMD Alchemy Pb1200 eval board
#
platform-$(CONFIG_MIPS_PB1200) += alchemy/devboards/
cflags-$(CONFIG_MIPS_PB1200) += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
load-$(CONFIG_MIPS_PB1200) += 0xffffffff80100000
#
# AMD Alchemy Db1000 eval board
#
platform-$(CONFIG_MIPS_DB1000) += alchemy/devboards/
cflags-$(CONFIG_MIPS_DB1000) += -I$(srctree)/arch/mips/include/asm/mach-db1x00
load-$(CONFIG_MIPS_DB1000) += 0xffffffff80100000
#
# AMD Alchemy Db1100 eval board
#
platform-$(CONFIG_MIPS_DB1100) += alchemy/devboards/
cflags-$(CONFIG_MIPS_DB1100) += -I$(srctree)/arch/mips/include/asm/mach-db1x00
load-$(CONFIG_MIPS_DB1100) += 0xffffffff80100000
#
# AMD Alchemy Db1500 eval board
#
platform-$(CONFIG_MIPS_DB1500) += alchemy/devboards/
cflags-$(CONFIG_MIPS_DB1500) += -I$(srctree)/arch/mips/include/asm/mach-db1x00
load-$(CONFIG_MIPS_DB1500) += 0xffffffff80100000
#
# AMD Alchemy Db1550 eval board
#
platform-$(CONFIG_MIPS_DB1550) += alchemy/devboards/
cflags-$(CONFIG_MIPS_DB1550) += -I$(srctree)/arch/mips/include/asm/mach-db1x00
load-$(CONFIG_MIPS_DB1550) += 0xffffffff80100000
#
# AMD Alchemy Db1200 eval board
#
platform-$(CONFIG_MIPS_DB1200) += alchemy/devboards/
cflags-$(CONFIG_MIPS_DB1200) += -I$(srctree)/arch/mips/include/asm/mach-db1x00
load-$(CONFIG_MIPS_DB1200) += 0xffffffff80100000
#
# AMD Alchemy Bosporus eval board
#
platform-$(CONFIG_MIPS_BOSPORUS) += alchemy/devboards/
cflags-$(CONFIG_MIPS_BOSPORUS) += -I$(srctree)/arch/mips/include/asm/mach-db1x00
load-$(CONFIG_MIPS_BOSPORUS) += 0xffffffff80100000
#
# AMD Alchemy Mirage eval board
#
platform-$(CONFIG_MIPS_MIRAGE) += alchemy/devboards/
cflags-$(CONFIG_MIPS_MIRAGE) += -I$(srctree)/arch/mips/include/asm/mach-db1x00
load-$(CONFIG_MIPS_MIRAGE) += 0xffffffff80100000
#
# 4G-Systems eval board
#
platform-$(CONFIG_MIPS_MTX1) += alchemy/mtx-1/
load-$(CONFIG_MIPS_MTX1) += 0xffffffff80100000
#
# MyCable eval board
#
platform-$(CONFIG_MIPS_XXS1500) += alchemy/xxs1500/
load-$(CONFIG_MIPS_XXS1500) += 0xffffffff80100000
#
# Trapeze ITS GRP board
#
platform-$(CONFIG_MIPS_GPR) += alchemy/gpr/
load-$(CONFIG_MIPS_GPR) += 0xffffffff80100000
# boards can specify their own <gpio.h> in one of their include dirs.
# If they do, placing this line here at the end will make sure the
# compiler picks the board one. If they don't, it will make sure
# the alchemy generic gpio header is picked up.
cflags-$(CONFIG_MIPS_ALCHEMY) += -I$(srctree)/arch/mips/include/asm/mach-au1x00
arch/mips/alchemy/common/Makefile
View file @ c3d1f174
......@@ -18,5 +18,3 @@ ifeq ($(CONFIG_ALCHEMY_GPIO_INDIRECT),)
endif
obj-$(CONFIG_PCI) += pci.o
EXTRA_CFLAGS += -Werror
arch/mips/alchemy/common/clocks.c
View file @ c3d1f174
......@@ -89,11 +89,7 @@ unsigned long au1xxx_calc_clock(void)
* over backwards trying to determine the frequency.
*/
if (au1xxx_cpu_has_pll_wo())
#ifdef CONFIG_SOC_AU1000_FREQUENCY
cpu_speed = CONFIG_SOC_AU1000_FREQUENCY;
#else
cpu_speed = 396000000;
#endif
else
cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) * AU1000_SRC_CLK;
......
arch/mips/alchemy/common/platform.c
View file @ c3d1f174
......@@ -12,6 +12,7 @@
*/
#include <linux/dma-mapping.h>
#include <linux/etherdevice.h>
#include <linux/platform_device.h>
#include <linux/serial_8250.h>
#include <linux/init.h>
......@@ -21,6 +22,8 @@
#include <asm/mach-au1x00/au1100_mmc.h>
#include <asm/mach-au1x00/au1xxx_eth.h>
#include <prom.h>
#define PORT(_base, _irq) \
{ \
.mapbase = _base, \
......@@ -33,7 +36,6 @@
}
static struct plat_serial8250_port au1x00_uart_data[] = {
#if defined(CONFIG_SERIAL_8250_AU1X00)
#if defined(CONFIG_SOC_AU1000)
PORT(UART0_PHYS_ADDR, AU1000_UART0_INT),
PORT(UART1_PHYS_ADDR, AU1000_UART1_INT),
......@@ -54,7 +56,6 @@ static struct plat_serial8250_port au1x00_uart_data[] = {
PORT(UART0_PHYS_ADDR, AU1200_UART0_INT),
PORT(UART1_PHYS_ADDR, AU1200_UART1_INT),
#endif
#endif /* CONFIG_SERIAL_8250_AU1X00 */
{ },
};
......@@ -436,17 +437,27 @@ static int __init au1xxx_platform_init(void)
{
unsigned int uartclk = get_au1x00_uart_baud_base() * 16;
int err, i;
unsigned char ethaddr[6];
/* Fill up uartclk. */
for (i = 0; au1x00_uart_data[i].flags; i++)
au1x00_uart_data[i].uartclk = uartclk;
/* use firmware-provided mac addr if available and necessary */
i = prom_get_ethernet_addr(ethaddr);
if (!i && !is_valid_ether_addr(au1xxx_eth0_platform_data.mac))
memcpy(au1xxx_eth0_platform_data.mac, ethaddr, 6);
err = platform_add_devices(au1xxx_platform_devices,
ARRAY_SIZE(au1xxx_platform_devices));
#ifndef CONFIG_SOC_AU1100
ethaddr[5] += 1; /* next addr for 2nd MAC */
if (!i && !is_valid_ether_addr(au1xxx_eth1_platform_data.mac))
memcpy(au1xxx_eth1_platform_data.mac, ethaddr, 6);
/* Register second MAC if enabled in pinfunc */
if (!err && !(au_readl(SYS_PINFUNC) & (u32)SYS_PF_NI2))
platform_device_register(&au1xxx_eth1_device);
err = platform_device_register(&au1xxx_eth1_device);
#endif
return err;
......
arch/mips/alchemy/devboards/Makefile
View file @ c3d1f174
......@@ -16,5 +16,3 @@ obj-$(CONFIG_MIPS_DB1500) += db1x00/
obj-$(CONFIG_MIPS_DB1550) += db1x00/
obj-$(CONFIG_MIPS_BOSPORUS) += db1x00/
obj-$(CONFIG_MIPS_MIRAGE) += db1x00/
EXTRA_CFLAGS += -Werror
arch/mips/alchemy/devboards/db1200/platform.c
View file @ c3d1f174
......@@ -216,14 +216,14 @@ static struct resource db1200_ide_res[] = {
}
};
static u64 ide_dmamask = DMA_32BIT_MASK;
static u64 ide_dmamask = DMA_BIT_MASK(32);
static struct platform_device db1200_ide_dev = {
.name = "au1200-ide",
.id = 0,
.dev = {
.dma_mask = &ide_dmamask,
.coherent_dma_mask = DMA_32BIT_MASK,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
.num_resources = ARRAY_SIZE(db1200_ide_res),
.resource = db1200_ide_res,
......@@ -385,12 +385,12 @@ static struct au1550_spi_info db1200_spi_platdata = {
.activate_cs = db1200_spi_cs_en,
};
static u64 spi_dmamask = DMA_32BIT_MASK;
static u64 spi_dmamask = DMA_BIT_MASK(32);
static struct platform_device db1200_spi_dev = {
.dev = {
.dma_mask = &spi_dmamask,
.coherent_dma_mask = DMA_32BIT_MASK,
.coherent_dma_mask = DMA_BIT_MASK(32),
.platform_data = &db1200_spi_platdata,
},
.name = "au1550-spi",
......
arch/mips/alchemy/devboards/db1x00/board_setup.c
View file @ c3d1f174
......@@ -79,7 +79,6 @@ static struct au1000_eth_platform_data eth0_pdata = {
static void bosporus_power_off(void)
{
printk(KERN_INFO "It's now safe to turn off power\n");
while (1)
asm volatile (".set mips3 ; wait ; .set mips0");
}
......
arch/mips/alchemy/devboards/pb1000/board_setup.c
View file @ c3d1f174
......@@ -47,9 +47,11 @@ static void board_reset(char *c)
static void board_power_off(void)
{
printk(KERN_ALERT "It's now safe to remove power\n");
while (1)
asm volatile (".set mips3 ; wait ; .set mips1");
asm volatile (
" .set mips32 \n"
" wait \n"
" .set mips0 \n");
}
void __init board_setup(void)
......
arch/mips/alchemy/devboards/pb1200/Makefile
View file @ c3d1f174
......@@ -3,5 +3,3 @@
#
obj-y := board_setup.o platform.o
EXTRA_CFLAGS += -Werror
arch/mips/alchemy/gpr/Makefile 0 → 100644
View file @ c3d1f174
#
# Copyright 2003 MontaVista Software Inc.
# Author: MontaVista Software, Inc. <source@mvista.com>
#
# Makefile for Trapeze ITS GPR board.
#
obj-y += board_setup.o init.o platform.o
arch/mips/alchemy/gpr/board_setup.c 0 → 100644
View file @ c3d1f174
/*
* Copyright 2010 Wolfgang Grandegger <wg@denx.de>
*
* Copyright 2000-2003, 2008 MontaVista Software Inc.
* Author: MontaVista Software, Inc. <source@mvista.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/gpio.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <asm/reboot.h>
#include <asm/mach-au1x00/au1000.h>
#include <prom.h>
#define UART1_ADDR KSEG1ADDR(UART1_PHYS_ADDR)
#define UART3_ADDR KSEG1ADDR(UART3_PHYS_ADDR)
char irq_tab_alchemy[][5] __initdata = {
[0] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff },
};
static void gpr_reset(char *c)
{
/* switch System-LED to orange (red# and green# on) */
alchemy_gpio_direction_output(4, 0);
alchemy_gpio_direction_output(5, 0);
/* trigger watchdog to reset board in 200ms */
printk(KERN_EMERG "Triggering watchdog soft reset...\n");
raw_local_irq_disable();
alchemy_gpio_direction_output(1, 0);
udelay(1);
alchemy_gpio_set_value(1, 1);
while (1)
cpu_wait();
}
static void gpr_power_off(void)
{
while (1)
cpu_wait();
}
void __init board_setup(void)
{
printk(KERN_INFO "Tarpeze ITS GPR board\n");
pm_power_off = gpr_power_off;
_machine_halt = gpr_power_off;
_machine_restart = gpr_reset;
/* Enable UART3 */
au_writel(0x1, UART3_ADDR + UART_MOD_CNTRL);/* clock enable (CE) */
au_writel(0x3, UART3_ADDR + UART_MOD_CNTRL); /* CE and "enable" */
/* Enable UART1 */
au_writel(0x1, UART1_ADDR + UART_MOD_CNTRL); /* clock enable (CE) */
au_writel(0x3, UART1_ADDR + UART_MOD_CNTRL); /* CE and "enable" */
/* Take away Reset of UMTS-card */
alchemy_gpio_direction_output(215, 1);
#ifdef CONFIG_PCI
#if defined(__MIPSEB__)
au_writel(0xf | (2 << 6) | (1 << 4), Au1500_PCI_CFG);
#else
au_writel(0xf, Au1500_PCI_CFG);
#endif
#endif
}
arch/mips/alchemy/gpr/init.c 0 → 100644
View file @ c3d1f174
/*
* Copyright 2010 Wolfgang Grandegger <wg@denx.de>
*
* Copyright 2003, 2008 MontaVista Software Inc.
* Author: MontaVista Software, Inc. <source@mvista.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <asm/bootinfo.h>
#include <asm/mach-au1x00/au1000.h>
#include <prom.h>
const char *get_system_type(void)
{
return "GPR";
}
void __init prom_init(void)
{
unsigned char *memsize_str;
unsigned long memsize;
prom_argc = fw_arg0;
prom_argv = (char **)fw_arg1;
prom_envp = (char **)fw_arg2;
prom_init_cmdline();
memsize_str = prom_getenv("memsize");
if (!memsize_str)
memsize = 0x04000000;
else
strict_strtoul(memsize_str, 0, &memsize);
add_memory_region(0, memsize, BOOT_MEM_RAM);
}
void prom_putchar(unsigned char c)
{
alchemy_uart_putchar(UART0_PHYS_ADDR, c);
}
arch/mips/alchemy/gpr/platform.c 0 → 100644
View file @ c3d1f174
/*
* GPR board platform device registration
*
* Copyright (C) 2010 Wolfgang Grandegger <wg@denx.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/physmap.h>
#include <linux/leds.h>
#include <linux/gpio.h>
#include <linux/i2c.h>
#include <linux/i2c-gpio.h>
#include <asm/mach-au1x00/au1000.h>
/*
* Watchdog
*/
static struct resource gpr_wdt_resource[] = {
[0] = {
.start = 1,
.end = 1,
.name = "gpr-adm6320-wdt",
.flags = IORESOURCE_IRQ,
}
};
static struct platform_device gpr_wdt_device = {
.name = "adm6320-wdt",
.id = 0,
.num_resources = ARRAY_SIZE(gpr_wdt_resource),
.resource = gpr_wdt_resource,
};
/*
* FLASH
*
* 0x00000000-0x00200000 : "kernel"
* 0x00200000-0x00a00000 : "rootfs"
* 0x01d00000-0x01f00000 : "config"
* 0x01c00000-0x01d00000 : "yamon"
* 0x01d00000-0x01d40000 : "yamon env vars"
* 0x00000000-0x00a00000 : "kernel+rootfs"
*/
static struct mtd_partition gpr_mtd_partitions[] = {
{
.name = "kernel",
.size = 0x00200000,
.offset = 0,
},
{
.name = "rootfs",
.size = 0x00800000,
.offset = MTDPART_OFS_APPEND,
.mask_flags = MTD_WRITEABLE,
},
{
.name = "config",
.size = 0x00200000,
.offset = 0x01d00000,
},
{
.name = "yamon",
.size = 0x00100000,
.offset = 0x01c00000,
},
{
.name = "yamon env vars",
.size = 0x00040000,
.offset = MTDPART_OFS_APPEND,
},
{
.name = "kernel+rootfs",
.size = 0x00a00000,
.offset = 0,
},
};
static struct physmap_flash_data gpr_flash_data = {
.width = 4,
.nr_parts = ARRAY_SIZE(gpr_mtd_partitions),
.parts = gpr_mtd_partitions,
};
static struct resource gpr_mtd_resource = {
.start = 0x1e000000,
.end = 0x1fffffff,
.flags = IORESOURCE_MEM,
};
static struct platform_device gpr_mtd_device = {
.name = "physmap-flash",
.dev = {
.platform_data = &gpr_flash_data,
},
.num_resources = 1,
.resource = &gpr_mtd_resource,
};
/*
* LEDs
*/
static struct gpio_led gpr_gpio_leds[] = {
{ /* green */
.name = "gpr:green",
.gpio = 4,
.active_low = 1,
},
{ /* red */
.name = "gpr:red",
.gpio = 5,
.active_low = 1,
}
};
static struct gpio_led_platform_data gpr_led_data = {
.num_leds = ARRAY_SIZE(gpr_gpio_leds),
.leds = gpr_gpio_leds,
};
static struct platform_device gpr_led_devices = {
.name = "leds-gpio",
.id = -1,
.dev = {
.platform_data = &gpr_led_data,
}
};
/*
* I2C
*/
static struct i2c_gpio_platform_data gpr_i2c_data = {
.sda_pin = 209,
.sda_is_open_drain = 1,
.scl_pin = 210,
.scl_is_open_drain = 1,
.udelay = 2, /* ~100 kHz */
.timeout = HZ,
};
static struct platform_device gpr_i2c_device = {
.name = "i2c-gpio",
.id = -1,
.dev.platform_data = &gpr_i2c_data,
};
static struct i2c_board_info gpr_i2c_info[] __initdata = {
{
I2C_BOARD_INFO("lm83", 0x18),
.type = "lm83"
}
};
static struct platform_device *gpr_devices[] __initdata = {
&gpr_wdt_device,
&gpr_mtd_device,
&gpr_i2c_device,
&gpr_led_devices,
};
static int __init gpr_dev_init(void)
{
i2c_register_board_info(0, gpr_i2c_info, ARRAY_SIZE(gpr_i2c_info));
return platform_add_devices(gpr_devices, ARRAY_SIZE(gpr_devices));
}
device_initcall(gpr_dev_init);
arch/mips/alchemy/mtx-1/Makefile
View file @ c3d1f174
......@@ -6,7 +6,4 @@
# Makefile for 4G Systems MTX-1 board.
#
lib-y := init.o board_setup.o
obj-y := platform.o
EXTRA_CFLAGS += -Werror
obj-y += init.o board_setup.o platform.o
arch/mips/alchemy/mtx-1/board_setup.c
View file @ c3d1f174
......@@ -60,9 +60,11 @@ static void mtx1_reset(char *c)
static void mtx1_power_off(void)
{
printk(KERN_ALERT "It's now safe to remove power\n");
while (1)
asm volatile (".set mips3 ; wait ; .set mips1");
asm volatile (
" .set mips32 \n"
" wait \n"
" .set mips0 \n");
}
void __init board_setup(void)
......@@ -105,14 +107,10 @@ void __init board_setup(void)
int
mtx1_pci_idsel(unsigned int devsel, int assert)
{
#define MTX_IDSEL_ONLY_0_AND_3 0
#if MTX_IDSEL_ONLY_0_AND_3
if (devsel != 0 && devsel != 3) {
printk(KERN_ERR "*** not 0 or 3\n");
return 0;
}
#endif
/* This function is only necessary to support a proprietary Cardbus
* adapter on the mtx-1 "singleboard" variant. It triggers a custom
* logic chip connected to EXT_IO3 (GPIO1) to suppress IDSEL signals.
*/
if (assert && devsel != 0)
/* Suppress signal to Cardbus */
alchemy_gpio_set_value(1, 0); /* set EXT_IO3 OFF */
......
arch/mips/alchemy/xxs1500/Makefile
View file @ c3d1f174
......@@ -5,6 +5,4 @@
# Makefile for MyCable XXS1500 board.
#
lib-y := init.o board_setup.o platform.o
EXTRA_CFLAGS += -Werror
obj-y += init.o board_setup.o platform.o
arch/mips/alchemy/xxs1500/board_setup.c
View file @ c3d1f174
......@@ -42,9 +42,11 @@ static void xxs1500_reset(char *c)
static void xxs1500_power_off(void)
{
printk(KERN_ALERT "It's now safe to remove power\n");
while (1)
asm volatile (".set mips3 ; wait ; .set mips1");
asm volatile (
" .set mips32 \n"
" wait \n"
" .set mips0 \n");
}
void __init board_setup(void)
......
arch/mips/ar7/Makefile
View file @ c3d1f174
......@@ -8,4 +8,3 @@ obj-y := \
platform.o \
gpio.o \
clock.o
EXTRA_CFLAGS += -Werror
arch/mips/ar7/Platform 0 → 100644
View file @ c3d1f174
#
# Texas Instruments AR7
#
platform-$(CONFIG_AR7) += ar7/
cflags-$(CONFIG_AR7) += -I$(srctree)/arch/mips/include/asm/mach-ar7
load-$(CONFIG_AR7) += 0xffffffff94100000
arch/mips/ar7/platform.c
View file @ c3d1f174
......@@ -292,40 +292,28 @@ static struct platform_device cpmac_high = {
.num_resources = ARRAY_SIZE(cpmac_high_res),
};
static inline unsigned char char2hex(char h)
static void __init cpmac_get_mac(int instance, unsigned char *dev_addr)
{
switch (h) {
case '0': case '1': case '2': case '3': case '4':
case '5': case '6': case '7': case '8': case '9':
return h - '0';
case 'A': case 'B': case 'C': case 'D': case 'E': case 'F':
return h - 'A' + 10;
case 'a': case 'b': case 'c': case 'd': case 'e': case 'f':
return h - 'a' + 10;
default:
return 0;
}
}
char name[5], *mac;
static void cpmac_get_mac(int instance, unsigned char *dev_addr)
{
int i;
char name[5], default_mac[ETH_ALEN], *mac;
mac = NULL;
sprintf(name, "mac%c", 'a' + instance);
mac = prom_getenv(name);
if (!mac) {
if (!mac && instance) {
sprintf(name, "mac%c", 'a');
mac = prom_getenv(name);
}
if (!mac) {
random_ether_addr(default_mac);
mac = default_mac;
if (mac) {
if (sscanf(mac, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx",
&dev_addr[0], &dev_addr[1],
&dev_addr[2], &dev_addr[3],
&dev_addr[4], &dev_addr[5]) != 6) {
pr_warning("cannot parse mac address, "
"using random address\n");
random_ether_addr(dev_addr);
}
for (i = 0; i < 6; i++)
dev_addr[i] = (char2hex(mac[i * 3]) << 4) +
char2hex(mac[i * 3 + 1]);
} else
random_ether_addr(dev_addr);
}
/*****************************************************************************
......
arch/mips/bcm47xx/Platform 0 → 100644
View file @ c3d1f174
#
# Broadcom BCM47XX boards
#
platform-$(CONFIG_BCM47XX) += bcm47xx/
cflags-$(CONFIG_BCM47XX) += \
-I$(srctree)/arch/mips/include/asm/mach-bcm47xx
load-$(CONFIG_BCM47XX) := 0xffffffff80001000
arch/mips/bcm47xx/nvram.c
View file @ c3d1f174
......@@ -69,7 +69,7 @@ int nvram_getenv(char *name, char *val, size_t val_len)
char *var, *value, *end, *eq;
if (!name)
return 1;
return NVRAM_ERR_INV_PARAM;
if (!nvram_buf[0])
early_nvram_init();
......@@ -89,6 +89,6 @@ int nvram_getenv(char *name, char *val, size_t val_len)
return 0;
}
}
return 1;
return NVRAM_ERR_ENVNOTFOUND;
}
EXPORT_SYMBOL(nvram_getenv);
arch/mips/bcm47xx/prom.c
View file @ c3d1f174
......@@ -126,6 +126,7 @@ static __init void prom_init_cmdline(void)
static __init void prom_init_mem(void)
{
unsigned long mem;
unsigned long max;
/* Figure out memory size by finding aliases.
*
......@@ -134,21 +135,26 @@ static __init void prom_init_mem(void)
* want to reuse the memory used by CFE (around 4MB). That means cfe_*
* functions stop to work at some point during the boot, we should only
* call them at the beginning of the boot.
*
* BCM47XX uses 128MB for addressing the ram, if the system contains
* less that that amount of ram it remaps the ram more often into the
* available space.
* Accessing memory after 128MB will cause an exception.
* max contains the biggest possible address supported by the platform.
* If the method wants to try something above we assume 128MB ram.
*/
max = ((unsigned long)(prom_init) | ((128 << 20) - 1));
for (mem = (1 << 20); mem < (128 << 20); mem += (1 << 20)) {
if (((unsigned long)(prom_init) + mem) > max) {
mem = (128 << 20);
printk(KERN_DEBUG "assume 128MB RAM\n");
break;
}
if (*(unsigned long *)((unsigned long)(prom_init) + mem) ==
*(unsigned long *)(prom_init))
break;
}
/* Ignoring the last page when ddr size is 128M. Cached
* accesses to last page is causing the processor to prefetch
* using address above 128M stepping out of the ddr address
* space.
*/
if (mem == 0x8000000)
mem -= 0x1000;
add_memory_region(0, mem, BOOT_MEM_RAM);
}
......
arch/mips/bcm63xx/Makefile
View file @ c3d1f174
......@@ -3,5 +3,3 @@ obj-y += clk.o cpu.o cs.o gpio.o irq.o prom.o setup.o timer.o \
obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
obj-y += boards/
EXTRA_CFLAGS += -Werror
arch/mips/bcm63xx/Platform 0 → 100644
View file @ c3d1f174
#
# Broadcom BCM63XX boards
#
platform-$(CONFIG_BCM63XX) += bcm63xx/
cflags-$(CONFIG_BCM63XX) += \
-I$(srctree)/arch/mips/include/asm/mach-bcm63xx/
load-$(CONFIG_BCM63XX) := 0xffffffff80010000
arch/mips/boot/.gitignore
View file @ c3d1f174
......@@ -3,3 +3,4 @@ elf2ecoff
vmlinux.*
zImage
zImage.tmp
calc_vmlinuz_load_addr
arch/mips/boot/Makefile
View file @ c3d1f174
......@@ -11,35 +11,32 @@
# Some DECstations need all possible sections of an ECOFF executable
#
ifdef CONFIG_MACH_DECSTATION
E2EFLAGS = -a
else
E2EFLAGS =
e2eflag := -a
endif
#
# Drop some uninteresting sections in the kernel.
# This is only relevant for ELF kernels but doesn't hurt a.out
#
drop-sections = .reginfo .mdebug .comment .note .pdr .options .MIPS.options
strip-flags = $(addprefix --remove-section=,$(drop-sections))
VMLINUX = vmlinux
all: vmlinux.ecoff vmlinux.srec
vmlinux.ecoff: $(obj)/elf2ecoff $(VMLINUX)
$(obj)/elf2ecoff $(VMLINUX) $(obj)/vmlinux.ecoff $(E2EFLAGS)
$(obj)/elf2ecoff: $(obj)/elf2ecoff.c
$(HOSTCC) -o $@ $^
vmlinux.bin: $(VMLINUX)
$(OBJCOPY) -O binary $(strip-flags) $(VMLINUX) $(obj)/vmlinux.bin
vmlinux.srec: $(VMLINUX)
$(OBJCOPY) -S -O srec $(strip-flags) $(VMLINUX) $(obj)/vmlinux.srec
clean-files += elf2ecoff \
vmlinux.bin \
vmlinux.ecoff \
vmlinux.srec
drop-sections := .reginfo .mdebug .comment .note .pdr .options .MIPS.options
strip-flags := $(addprefix --remove-section=,$(drop-sections))
hostprogs-y := elf2ecoff
targets := vmlinux.ecoff
quiet_cmd_ecoff = ECOFF $@
cmd_ecoff = $(obj)/elf2ecoff $(VMLINUX) $@ $(e2eflag)
$(obj)/vmlinux.ecoff: $(obj)/elf2ecoff $(VMLINUX) FORCE
$(call if_changed,ecoff)
targets += vmlinux.bin
quiet_cmd_bin = OBJCOPY $@
cmd_bin = $(OBJCOPY) -O binary $(strip-flags) $(VMLINUX) $@
$(obj)/vmlinux.bin: $(VMLINUX) FORCE
$(call if_changed,bin)
targets += vmlinux.srec
quiet_cmd_srec = OBJCOPY $@
cmd_srec = $(OBJCOPY) -S -O srec $(strip-flags) $(VMLINUX) $@
$(obj)/vmlinux.srec: $(VMLINUX) FORCE
$(call if_changed,srec)
arch/mips/boot/compressed/Makefile
View file @ c3d1f174
......@@ -12,14 +12,6 @@
# Author: Wu Zhangjin <wuzhangjin@gmail.com>
#
# compressed kernel load addr: VMLINUZ_LOAD_ADDRESS > VMLINUX_LOAD_ADDRESS + VMLINUX_SIZE
VMLINUX_SIZE := $(shell wc -c $(objtree)/$(KBUILD_IMAGE) 2>/dev/null | cut -d' ' -f1)
VMLINUX_SIZE := $(shell [ -n "$(VMLINUX_SIZE)" ] && echo -n $$(($(VMLINUX_SIZE) + (65536 - $(VMLINUX_SIZE) % 65536))))
# VMLINUZ_LOAD_ADDRESS = concat "high32 of VMLINUX_LOAD_ADDRESS" and "(low32 of VMLINUX_LOAD_ADDRESS) + VMLINUX_SIZE"
HIGH32 := $(shell A=$(VMLINUX_LOAD_ADDRESS); [ $${\#A} -gt 10 ] && expr substr "$(VMLINUX_LOAD_ADDRESS)" 3 $$(($${\#A} - 10)))
LOW32 := $(shell [ -n "$(HIGH32)" ] && A=11 || A=3; expr substr "$(VMLINUX_LOAD_ADDRESS)" $${A} 8)
VMLINUZ_LOAD_ADDRESS := 0x$(shell [ -n "$(VMLINUX_SIZE)" -a -n "$(LOW32)" ] && printf "$(HIGH32)%08x" $$(($(VMLINUX_SIZE) + 0x$(LOW32))))
# set the default size of the mallocing area for decompressing
BOOT_HEAP_SIZE := 0x400000
......@@ -33,49 +25,61 @@ KBUILD_AFLAGS := $(LINUXINCLUDE) $(KBUILD_AFLAGS) -D__ASSEMBLY__ \
-DBOOT_HEAP_SIZE=$(BOOT_HEAP_SIZE) \
-DKERNEL_ENTRY=0x$(shell $(NM) $(objtree)/$(KBUILD_IMAGE) 2>/dev/null | grep " kernel_entry" | cut -f1 -d \ )
obj-y := $(obj)/head.o $(obj)/decompress.o $(obj)/dbg.o
targets := head.o decompress.o dbg.o uart-16550.o uart-alchemy.o
# decompressor objects (linked with vmlinuz)
vmlinuzobjs-y := $(obj)/head.o $(obj)/decompress.o $(obj)/dbg.o
ifdef CONFIG_DEBUG_ZBOOT
obj-$(CONFIG_SYS_SUPPORTS_ZBOOT_UART16550) += $(obj)/uart-16550.o
obj-$(CONFIG_MACH_ALCHEMY) += $(obj)/uart-alchemy.o
vmlinuzobjs-$(CONFIG_SYS_SUPPORTS_ZBOOT_UART16550) += $(obj)/uart-16550.o
vmlinuzobjs-$(CONFIG_MIPS_ALCHEMY) += $(obj)/uart-alchemy.o
endif
targets += vmlinux.bin
OBJCOPYFLAGS_vmlinux.bin := $(OBJCOPYFLAGS) -O binary -R .comment -S
$(obj)/vmlinux.bin: $(KBUILD_IMAGE)
$(obj)/vmlinux.bin: $(KBUILD_IMAGE) FORCE
$(call if_changed,objcopy)
suffix_$(CONFIG_KERNEL_GZIP) = gz
suffix_$(CONFIG_KERNEL_BZIP2) = bz2
suffix_$(CONFIG_KERNEL_LZMA) = lzma
suffix_$(CONFIG_KERNEL_LZO) = lzo
tool_$(CONFIG_KERNEL_GZIP) = gzip
tool_$(CONFIG_KERNEL_BZIP2) = bzip2
tool_$(CONFIG_KERNEL_LZMA) = lzma
tool_$(CONFIG_KERNEL_LZO) = lzo
$(obj)/vmlinux.$(suffix_y): $(obj)/vmlinux.bin
targets += vmlinux.bin.z
$(obj)/vmlinux.bin.z: $(obj)/vmlinux.bin FORCE
$(call if_changed,$(tool_y))
$(obj)/piggy.o: $(obj)/vmlinux.$(suffix_y) $(obj)/dummy.o
$(Q)$(OBJCOPY) $(OBJCOPYFLAGS) \
--add-section=.image=$< \
--set-section-flags=.image=contents,alloc,load,readonly,data \
$(obj)/dummy.o $@
targets += piggy.o
OBJCOPYFLAGS_piggy.o := --add-section=.image=$(obj)/vmlinux.bin.z \
--set-section-flags=.image=contents,alloc,load,readonly,data
$(obj)/piggy.o: $(obj)/dummy.o $(obj)/vmlinux.bin.z FORCE
$(call if_changed,objcopy)
# Calculate the load address of the compressed kernel image
hostprogs-y := calc_vmlinuz_load_addr
VMLINUZ_LOAD_ADDRESS = $(shell $(obj)/calc_vmlinuz_load_addr \
$(objtree)/$(KBUILD_IMAGE) $(VMLINUX_LOAD_ADDRESS))
LDFLAGS_vmlinuz := $(LDFLAGS) -Ttext $(VMLINUZ_LOAD_ADDRESS) -T
vmlinuz: $(src)/ld.script $(obj-y) $(obj)/piggy.o
$(call if_changed,ld)
$(Q)$(OBJCOPY) $(OBJCOPYFLAGS) $@
vmlinuzobjs-y += $(obj)/piggy.o
quiet_cmd_zld = LD $@
cmd_zld = $(LD) $(LDFLAGS) -Ttext $(VMLINUZ_LOAD_ADDRESS) -T $< $(vmlinuzobjs-y) -o $@
quiet_cmd_strip = STRIP $@
cmd_strip = $(STRIP) -s $@
vmlinuz: $(src)/ld.script $(vmlinuzobjs-y) $(obj)/calc_vmlinuz_load_addr
$(call cmd,zld)
$(call cmd,strip)
#
# Some DECstations need all possible sections of an ECOFF executable
#
ifdef CONFIG_MACH_DECSTATION
E2EFLAGS = -a
else
E2EFLAGS =
e2eflag := -a
endif
# elf2ecoff can only handle 32bit image
hostprogs-y += ../elf2ecoff
ifdef CONFIG_32BIT
VMLINUZ = vmlinuz
......@@ -83,23 +87,22 @@ else
VMLINUZ = vmlinuz.32
endif
quiet_cmd_32 = OBJCOPY $@
cmd_32 = $(OBJCOPY) -O $(32bit-bfd) $(OBJCOPYFLAGS) $< $@
vmlinuz.32: vmlinuz
$(Q)$(OBJCOPY) -O $(32bit-bfd) $(OBJCOPYFLAGS) $< $@
$(call cmd,32)
quiet_cmd_ecoff = ECOFF $@
cmd_ecoff = $< $(VMLINUZ) $@ $(e2eflag)
vmlinuz.ecoff: $(obj)/../elf2ecoff $(VMLINUZ)
$(Q)$(obj)/../elf2ecoff $(VMLINUZ) vmlinuz.ecoff $(E2EFLAGS)
$(obj)/../elf2ecoff: $(src)/../elf2ecoff.c
$(Q)$(HOSTCC) -o $@ $^
$(call cmd,ecoff)
OBJCOPYFLAGS_vmlinuz.bin := $(OBJCOPYFLAGS) -O binary
vmlinuz.bin: vmlinuz
$(call if_changed,objcopy)
$(call cmd,objcopy)
OBJCOPYFLAGS_vmlinuz.srec := $(OBJCOPYFLAGS) -S -O srec
vmlinuz.srec: vmlinuz
$(call if_changed,objcopy)
$(call cmd,objcopy)
clean:
clean-files += *.o \
vmlinu*
clean-files := $(objtree)/vmlinuz.*
arch/mips/boot/compressed/calc_vmlinuz_load_addr.c 0 → 100644
View file @ c3d1f174
/*
* Copyright (C) 2010 "Wu Zhangjin" <wuzhangjin@gmail.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <sys/types.h>
#include <sys/stat.h>
#include <errno.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
int main(int argc, char *argv[])
{
struct stat sb;
uint64_t vmlinux_size, vmlinux_load_addr, vmlinuz_load_addr;
if (argc != 3) {
fprintf(stderr, "Usage: %s <pathname> <vmlinux_load_addr>\n",
argv[0]);
return EXIT_FAILURE;
}
if (stat(argv[1], &sb) == -1) {
perror("stat");
return EXIT_FAILURE;
}
/* Convert hex characters to dec number */
errno = 0;
if (sscanf(argv[2], "%llx", &vmlinux_load_addr) != 1) {
if (errno != 0)
perror("sscanf");
else
fprintf(stderr, "No matching characters\n");
return EXIT_FAILURE;
}
vmlinux_size = (uint64_t)sb.st_size;
vmlinuz_load_addr = vmlinux_load_addr + vmlinux_size;
/*
* Align with 16 bytes: "greater than that used for any standard data
* types by a MIPS compiler." -- See MIPS Run Linux (Second Edition).
*/
vmlinuz_load_addr += (16 - vmlinux_size % 16);
printf("0x%llx\n", vmlinuz_load_addr);
return EXIT_SUCCESS;
}
arch/mips/boot/compressed/decompress.c
View file @ c3d1f174
/*
* Misc. bootloader code for many machines.
*
* Copyright 2001 MontaVista Software Inc.
* Author: Matt Porter <mporter@mvista.com> Derived from
* arch/ppc/boot/prep/misc.c
* Author: Matt Porter <mporter@mvista.com>
*
* Copyright (C) 2009 Lemote, Inc.
* Author: Wu Zhangjin <wuzhangjin@gmail.com>
......@@ -19,12 +16,12 @@
#include <asm/addrspace.h>
/* These two variables specify the free mem region
/*
* These two variables specify the free mem region
* that can be used for temporary malloc area
*/
unsigned long free_mem_ptr;
unsigned long free_mem_end_ptr;
char *zimage_start;
/* The linker tells us where the image is. */
extern unsigned char __image_begin, __image_end;
......@@ -83,38 +80,31 @@ void *memset(void *s, int c, size_t n)
void decompress_kernel(unsigned long boot_heap_start)
{
int zimage_size;
unsigned long zimage_start, zimage_size;
/*
* We link ourself to an arbitrary low address. When we run, we
* relocate outself to that address. __image_beign points to
* the part of the image where the zImage is. -- Tom
*/
zimage_start = (char *)(unsigned long)(&__image_begin);
zimage_start = (unsigned long)(&__image_begin);
zimage_size = (unsigned long)(&__image_end) -
(unsigned long)(&__image_begin);
/*
* The zImage and initrd will be between start and _end, so they've
* already been moved once. We're good to go now. -- Tom
*/
puts("zimage at: ");
puthex((unsigned long)zimage_start);
puthex(zimage_start);
puts(" ");
puthex((unsigned long)(zimage_size + zimage_start));
puthex(zimage_size + zimage_start);
puts("\n");
/* this area are prepared for mallocing when decompressing */
/* This area are prepared for mallocing when decompressing */
free_mem_ptr = boot_heap_start;
free_mem_end_ptr = boot_heap_start + BOOT_HEAP_SIZE;
/* Display standard Linux/MIPS boot prompt for kernel args */
/* Display standard Linux/MIPS boot prompt */
puts("Uncompressing Linux at load address ");
puthex(VMLINUX_LOAD_ADDRESS_ULL);
puts("\n");
/* Decompress the kernel with according algorithm */
decompress(zimage_start, zimage_size, 0, 0,
decompress((char *)zimage_start, zimage_size, 0, 0,
(void *)VMLINUX_LOAD_ADDRESS_ULL, 0, error);
/* FIXME: is there a need to flush cache here? */
/* FIXME: should we flush cache here? */
puts("Now, booting the kernel...\n");
}
arch/mips/boot/compressed/ld.script
View file @ c3d1f174
......@@ -2,58 +2,41 @@
* ld.script for compressed kernel support of MIPS
*
* Copyright (C) 2009 Lemote Inc.
* Author: Wu Zhangjin <wuzj@lemote.com>
* Author: Wu Zhangjin <wuzhanjing@gmail.com>
* Copyright (C) 2010 "Wu Zhangjin" <wuzhanjing@gmail.com>
*/
OUTPUT_ARCH(mips)
ENTRY(start)
SECTIONS
{
/* . = VMLINUZ_LOAD_ADDRESS */
/* read-only */
_text = .; /* Text and read-only data */
/* Text and read-only data */
/* . = VMLINUZ_LOAD_ADDRESS; */
.text : {
_ftext = . ;
*(.text)
*(.rodata)
} = 0
_etext = .; /* End of text section */
}
/* End of text section */
/* writable */
.data : { /* Data */
_fdata = . ;
/* Writable data */
.data : {
*(.data)
/* Put the compressed image here, so bss is on the end. */
/* Put the compressed image here */
__image_begin = .;
*(.image)
__image_end = .;
CONSTRUCTORS
}
.sdata : { *(.sdata) }
. = ALIGN(4);
_edata = .; /* End of data section */
. = ALIGN(16);
_edata = .;
/* End of data section */
/* BSS */
__bss_start = .;
_fbss = .;
.sbss : { *(.sbss) *(.scommon) }
.bss : {
*(.dynbss)
*(.bss)
*(COMMON)
}
. = ALIGN(4);
_end = . ;
/* These are needed for ELF backends which have not yet been converted
* to the new style linker. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
/* These must appear regardless of . */
.gptab.sdata : { *(.gptab.data) *(.gptab.sdata) }
.gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) }
. = ALIGN(16);
_end = .;
/* Sections to be discarded */
/DISCARD/ : {
......
arch/mips/cavium-octeon/Makefile
View file @ c3d1f174
......@@ -12,7 +12,6 @@
obj-y := cpu.o setup.o serial.o octeon-platform.o octeon-irq.o csrc-octeon.o
obj-y += dma-octeon.o flash_setup.o
obj-y += octeon-memcpy.o
obj-y += executive/
obj-$(CONFIG_SMP) += smp.o
EXTRA_CFLAGS += -Werror
arch/mips/cavium-octeon/Platform 0 → 100644
View file @ c3d1f174
#
# Cavium Octeon
#
platform-$(CONFIG_CPU_CAVIUM_OCTEON) += cavium-octeon/
cflags-$(CONFIG_CPU_CAVIUM_OCTEON) += \
-I$(srctree)/arch/mips/include/asm/mach-cavium-octeon
ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL
load-$(CONFIG_CPU_CAVIUM_OCTEON) += 0xffffffff84100000
else
load-$(CONFIG_CPU_CAVIUM_OCTEON) += 0xffffffff81100000
endif
arch/mips/cavium-octeon/cpu.c
View file @ c3d1f174
......@@ -41,12 +41,8 @@ static int cnmips_cu2_call(struct notifier_block *nfb, unsigned long action,
return NOTIFY_OK; /* Let default notifier send signals */
}
static struct notifier_block cnmips_cu2_notifier = {
.notifier_call = cnmips_cu2_call,
};
static int cnmips_cu2_setup(void)
{
return register_cu2_notifier(&cnmips_cu2_notifier);
return cu2_notifier(cnmips_cu2_call, 0);
}
early_initcall(cnmips_cu2_setup);
arch/mips/cavium-octeon/csrc-octeon.c
View file @ c3d1f174
......@@ -53,7 +53,6 @@ static struct clocksource clocksource_mips = {
unsigned long long notrace sched_clock(void)
{
/* 64-bit arithmatic can overflow, so use 128-bit. */
#if (__GNUC__ < 4) || ((__GNUC__ == 4) && (__GNUC_MINOR__ <= 3))
u64 t1, t2, t3;
unsigned long long rv;
u64 mult = clocksource_mips.mult;
......@@ -73,13 +72,6 @@ unsigned long long notrace sched_clock(void)
: [cnt] "r" (cnt), [mult] "r" (mult), [shift] "r" (shift)
: "hi", "lo");
return rv;
#else
/* GCC > 4.3 do it the easy way. */
unsigned int __attribute__((mode(TI))) t;
t = read_c0_cvmcount();
t = t * clocksource_mips.mult;
return (unsigned long long)(t >> clocksource_mips.shift);
#endif
}
void __init plat_time_init(void)
......@@ -88,3 +80,58 @@ void __init plat_time_init(void)
clocksource_set_clock(&clocksource_mips, mips_hpt_frequency);
clocksource_register(&clocksource_mips);
}
static u64 octeon_udelay_factor;
static u64 octeon_ndelay_factor;
void __init octeon_setup_delays(void)
{
octeon_udelay_factor = octeon_get_clock_rate() / 1000000;
/*
* For __ndelay we divide by 2^16, so the factor is multiplied
* by the same amount.
*/
octeon_ndelay_factor = (octeon_udelay_factor * 0x10000ull) / 1000ull;
preset_lpj = octeon_get_clock_rate() / HZ;
}
void __udelay(unsigned long us)
{
u64 cur, end, inc;
cur = read_c0_cvmcount();
inc = us * octeon_udelay_factor;
end = cur + inc;
while (end > cur)
cur = read_c0_cvmcount();
}
EXPORT_SYMBOL(__udelay);
void __ndelay(unsigned long ns)
{
u64 cur, end, inc;
cur = read_c0_cvmcount();
inc = ((ns * octeon_ndelay_factor) >> 16);
end = cur + inc;
while (end > cur)
cur = read_c0_cvmcount();
}
EXPORT_SYMBOL(__ndelay);
void __delay(unsigned long loops)
{
u64 cur, end;
cur = read_c0_cvmcount();
end = cur + loops;
while (end > cur)
cur = read_c0_cvmcount();
}
EXPORT_SYMBOL(__delay);
arch/mips/cavium-octeon/dma-octeon.c
View file @ c3d1f174
......@@ -99,13 +99,16 @@ dma_addr_t octeon_map_dma_mem(struct device *dev, void *ptr, size_t size)
panic("dma_map_single: "
"Attempt to map illegal memory address 0x%llx\n",
physical);
else if ((physical + size >=
(4ull<<30) - (OCTEON_PCI_BAR1_HOLE_SIZE<<20))
&& physical < (4ull<<30))
pr_warning("dma_map_single: Warning: "
"Mapping memory address that might "
"conflict with devices 0x%llx-0x%llx\n",
physical, physical+size-1);
else if (physical >= CVMX_PCIE_BAR1_PHYS_BASE &&
physical + size < (CVMX_PCIE_BAR1_PHYS_BASE + CVMX_PCIE_BAR1_PHYS_SIZE)) {
result = physical - CVMX_PCIE_BAR1_PHYS_BASE + CVMX_PCIE_BAR1_RC_BASE;
if (((result+size-1) & dma_mask) != result+size-1)
panic("dma_map_single: Attempt to map address 0x%llx-0x%llx, which can't be accessed according to the dma mask 0x%llx\n",
physical, physical+size-1, dma_mask);
goto done;
}
/* The 2nd 256MB is mapped at 256<<20 instead of 0x410000000 */
if ((physical >= 0x410000000ull) && physical < 0x420000000ull)
result = physical - 0x400000000ull;
......
arch/mips/cavium-octeon/octeon-irq.c
View file @ c3d1f174
This diff is collapsed.
arch/mips/cavium-octeon/octeon_boot.h
View file @ c3d1f174
......@@ -23,14 +23,16 @@
#include <linux/types.h>
struct boot_init_vector {
uint32_t stack_addr;
uint32_t code_addr;
/* First stage address - in ram instead of flash */
uint64_t code_addr;
/* Setup code for application, NOT application entry point */
uint32_t app_start_func_addr;
/* k0 is used for global data - needs to be passed to other cores */
uint32_t k0_val;
uint32_t flags;
uint32_t boot_info_addr;
/* Address of boot info block structure */
uint64_t boot_info_addr;
uint32_t flags; /* flags */
uint32_t pad;
uint32_t pad2;
};
/* similar to bootloader's linux_app_boot_info but without global data */
......@@ -40,7 +42,7 @@ struct linux_app_boot_info {
uint32_t avail_coremask;
uint32_t pci_console_active;
uint32_t icache_prefetch_disable;
uint32_t InitTLBStart_addr;
uint64_t InitTLBStart_addr;
uint32_t start_app_addr;
uint32_t cur_exception_base;
uint32_t no_mark_private_data;
......@@ -58,7 +60,7 @@ struct linux_app_boot_info {
#define LINUX_APP_BOOT_BLOCK_NAME "linux-app-boot"
#define LABI_SIGNATURE 0xAABBCCDD
#define LABI_SIGNATURE 0xAABBCC01
/* from uboot-headers/octeon_mem_map.h */
#define EXCEPTION_BASE_INCR (4 * 1024)
......
arch/mips/cavium-octeon/serial.c
View file @ c3d1f174
......@@ -18,11 +18,7 @@
#include <asm/octeon/octeon.h>
#ifdef CONFIG_GDB_CONSOLE
#define DEBUG_UART 0
#else
#define DEBUG_UART 1
#endif
unsigned int octeon_serial_in(struct uart_port *up, int offset)
{
......
arch/mips/cavium-octeon/setup.c
View file @ c3d1f174
......@@ -32,6 +32,7 @@
#include <asm/time.h>
#include <asm/octeon/octeon.h>
#include <asm/octeon/pci-octeon.h>
#ifdef CONFIG_CAVIUM_DECODE_RSL
extern void cvmx_interrupt_rsl_decode(void);
......@@ -578,9 +579,6 @@ void __init prom_init(void)
}
if (strstr(arcs_cmdline, "console=") == NULL) {
#ifdef CONFIG_GDB_CONSOLE
strcat(arcs_cmdline, " console=gdb");
#else
#ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL
strcat(arcs_cmdline, " console=ttyS0,115200");
#else
......@@ -588,7 +586,6 @@ void __init prom_init(void)
strcat(arcs_cmdline, " console=ttyS1,115200");
else
strcat(arcs_cmdline, " console=ttyS0,115200");
#endif
#endif
}
......@@ -598,13 +595,13 @@ void __init prom_init(void)
* the filesystem. Also specify the calibration delay
* to avoid calculating it every time.
*/
strcat(arcs_cmdline, " rw root=1f00"
" lpj=60176 slram=root,0x40000000,+1073741824");
strcat(arcs_cmdline, " rw root=1f00 slram=root,0x40000000,+1073741824");
}
mips_hpt_frequency = octeon_get_clock_rate();
octeon_init_cvmcount();
octeon_setup_delays();
_machine_restart = octeon_restart;
_machine_halt = octeon_halt;
......@@ -613,6 +610,22 @@ void __init prom_init(void)
register_smp_ops(&octeon_smp_ops);
}
/* Exclude a single page from the regions obtained in plat_mem_setup. */
static __init void memory_exclude_page(u64 addr, u64 *mem, u64 *size)
{
if (addr > *mem && addr < *mem + *size) {
u64 inc = addr - *mem;
add_memory_region(*mem, inc, BOOT_MEM_RAM);
*mem += inc;
*size -= inc;
}
if (addr == *mem && *size > PAGE_SIZE) {
*mem += PAGE_SIZE;
*size -= PAGE_SIZE;
}
}
void __init plat_mem_setup(void)
{
uint64_t mem_alloc_size;
......@@ -663,12 +676,27 @@ void __init plat_mem_setup(void)
CVMX_BOOTMEM_FLAG_NO_LOCKING);
#endif
if (memory >= 0) {
u64 size = mem_alloc_size;
/*
* exclude a page at the beginning and end of
* the 256MB PCIe 'hole' so the kernel will not
* try to allocate multi-page buffers that
* span the discontinuity.
*/
memory_exclude_page(CVMX_PCIE_BAR1_PHYS_BASE,
&memory, &size);
memory_exclude_page(CVMX_PCIE_BAR1_PHYS_BASE +
CVMX_PCIE_BAR1_PHYS_SIZE,
&memory, &size);
/*
* This function automatically merges address
* regions next to each other if they are
* received in incrementing order.
*/
add_memory_region(memory, mem_alloc_size, BOOT_MEM_RAM);
if (size)
add_memory_region(memory, size, BOOT_MEM_RAM);
total += mem_alloc_size;
} else {
break;
......@@ -691,7 +719,10 @@ void __init plat_mem_setup(void)
"cvmx_bootmem_phy_alloc\n");
}
/*
* Emit one character to the boot UART. Exported for use by the
* watchdog timer.
*/
int prom_putchar(char c)
{
uint64_t lsrval;
......@@ -705,6 +736,7 @@ int prom_putchar(char c)
cvmx_write_csr(CVMX_MIO_UARTX_THR(octeon_uart), c & 0xffull);
return 1;
}
EXPORT_SYMBOL(prom_putchar);
void prom_free_prom_memory(void)
{
......
arch/mips/cavium-octeon/smp.c
View file @ c3d1f174
......@@ -3,7 +3,7 @@
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2004-2008 Cavium Networks
* Copyright (C) 2004-2008, 2009, 2010 Cavium Networks
*/
#include <linux/cpu.h>
#include <linux/init.h>
......@@ -27,7 +27,8 @@ volatile unsigned long octeon_processor_sp;
volatile unsigned long octeon_processor_gp;
#ifdef CONFIG_HOTPLUG_CPU
static unsigned int InitTLBStart_addr;
uint64_t octeon_bootloader_entry_addr;
EXPORT_SYMBOL(octeon_bootloader_entry_addr);
#endif
static irqreturn_t mailbox_interrupt(int irq, void *dev_id)
......@@ -80,20 +81,13 @@ static inline void octeon_send_ipi_mask(const struct cpumask *mask,
static void octeon_smp_hotplug_setup(void)
{
#ifdef CONFIG_HOTPLUG_CPU
uint32_t labi_signature;
labi_signature =
cvmx_read64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
LABI_ADDR_IN_BOOTLOADER +
offsetof(struct linux_app_boot_info,
labi_signature)));
if (labi_signature != LABI_SIGNATURE)
pr_err("The bootloader version on this board is incorrect\n");
InitTLBStart_addr =
cvmx_read64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
LABI_ADDR_IN_BOOTLOADER +
offsetof(struct linux_app_boot_info,
InitTLBStart_addr)));
struct linux_app_boot_info *labi;
labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
if (labi->labi_signature != LABI_SIGNATURE)
panic("The bootloader version on this board is incorrect.");
octeon_bootloader_entry_addr = labi->InitTLBStart_addr;
#endif
}
......@@ -102,24 +96,47 @@ static void octeon_smp_setup(void)
const int coreid = cvmx_get_core_num();
int cpus;
int id;
int core_mask = octeon_get_boot_coremask();
#ifdef CONFIG_HOTPLUG_CPU
unsigned int num_cores = cvmx_octeon_num_cores();
#endif
/* The present CPUs are initially just the boot cpu (CPU 0). */
for (id = 0; id < NR_CPUS; id++) {
set_cpu_possible(id, id == 0);
set_cpu_present(id, id == 0);
}
cpus_clear(cpu_possible_map);
__cpu_number_map[coreid] = 0;
__cpu_logical_map[0] = coreid;
cpu_set(0, cpu_possible_map);
/* The present CPUs get the lowest CPU numbers. */
cpus = 1;
for (id = 0; id < 16; id++) {
for (id = 0; id < NR_CPUS; id++) {
if ((id != coreid) && (core_mask & (1 << id))) {
cpu_set(cpus, cpu_possible_map);
set_cpu_possible(cpus, true);
set_cpu_present(cpus, true);
__cpu_number_map[id] = cpus;
__cpu_logical_map[cpus] = id;
cpus++;
}
}
cpu_present_map = cpu_possible_map;
#ifdef CONFIG_HOTPLUG_CPU
/*
* The possible CPUs are all those present on the chip. We
* will assign CPU numbers for possible cores as well. Cores
* are always consecutively numberd from 0.
*/
for (id = 0; id < num_cores && id < NR_CPUS; id++) {
if (!(core_mask & (1 << id))) {
set_cpu_possible(cpus, true);
__cpu_number_map[id] = cpus;
__cpu_logical_map[cpus] = id;
cpus++;
}
}
#endif
octeon_smp_hotplug_setup();
}
......@@ -158,18 +175,21 @@ static void octeon_init_secondary(void)
{
const int coreid = cvmx_get_core_num();
union cvmx_ciu_intx_sum0 interrupt_enable;
unsigned int sr;
#ifdef CONFIG_HOTPLUG_CPU
unsigned int cur_exception_base;
cur_exception_base = cvmx_read64_uint32(
CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
LABI_ADDR_IN_BOOTLOADER +
offsetof(struct linux_app_boot_info,
cur_exception_base)));
/* cur_exception_base is incremented in bootloader after setting */
write_c0_ebase((unsigned int)(cur_exception_base - EXCEPTION_BASE_INCR));
struct linux_app_boot_info *labi;
labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
if (labi->labi_signature != LABI_SIGNATURE)
panic("The bootloader version on this board is incorrect.");
#endif
sr = set_c0_status(ST0_BEV);
write_c0_ebase((u32)ebase);
write_c0_status(sr);
octeon_check_cpu_bist();
octeon_init_cvmcount();
/*
......@@ -276,8 +296,8 @@ static int octeon_cpu_disable(void)
static void octeon_cpu_die(unsigned int cpu)
{
int coreid = cpu_logical_map(cpu);
uint32_t avail_coremask;
struct cvmx_bootmem_named_block_desc *block_desc;
uint32_t mask, new_mask;
const struct cvmx_bootmem_named_block_desc *block_desc;
while (per_cpu(cpu_state, cpu) != CPU_DEAD)
cpu_relax();
......@@ -286,52 +306,40 @@ static void octeon_cpu_die(unsigned int cpu)
* This is a bit complicated strategics of getting/settig available
* cores mask, copied from bootloader
*/
mask = 1 << coreid;
/* LINUX_APP_BOOT_BLOCK is initialized in bootoct binary */
block_desc = cvmx_bootmem_find_named_block(LINUX_APP_BOOT_BLOCK_NAME);
if (!block_desc) {
avail_coremask =
cvmx_read64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
LABI_ADDR_IN_BOOTLOADER +
offsetof
(struct linux_app_boot_info,
avail_coremask)));
} else { /* alternative, already initialized */
avail_coremask =
cvmx_read64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
block_desc->base_addr +
AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK));
}
struct linux_app_boot_info *labi;
avail_coremask |= 1 << coreid;
labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
/* Setting avail_coremask for bootoct binary */
if (!block_desc) {
cvmx_write64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
LABI_ADDR_IN_BOOTLOADER +
offsetof(struct linux_app_boot_info,
avail_coremask)),
avail_coremask);
} else {
cvmx_write64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
block_desc->base_addr +
AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK),
avail_coremask);
labi->avail_coremask |= mask;
new_mask = labi->avail_coremask;
} else { /* alternative, already initialized */
uint32_t *p = (uint32_t *)PHYS_TO_XKSEG_CACHED(block_desc->base_addr +
AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK);
*p |= mask;
new_mask = *p;
}
pr_info("Reset core %d. Available Coremask = %x\n", coreid,
avail_coremask);
pr_info("Reset core %d. Available Coremask = 0x%x \n", coreid, new_mask);
mb();
cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid);
cvmx_write_csr(CVMX_CIU_PP_RST, 0);
}
void play_dead(void)
{
int coreid = cvmx_get_core_num();
int cpu = cpu_number_map(cvmx_get_core_num());
idle_task_exit();
octeon_processor_boot = 0xff;
per_cpu(cpu_state, coreid) = CPU_DEAD;
per_cpu(cpu_state, cpu) = CPU_DEAD;
mb();
while (1) /* core will be reset here */
;
......@@ -344,29 +352,27 @@ static void start_after_reset(void)
kernel_entry(0, 0, 0); /* set a2 = 0 for secondary core */
}
int octeon_update_boot_vector(unsigned int cpu)
static int octeon_update_boot_vector(unsigned int cpu)
{
int coreid = cpu_logical_map(cpu);
unsigned int avail_coremask;
struct cvmx_bootmem_named_block_desc *block_desc;
uint32_t avail_coremask;
const struct cvmx_bootmem_named_block_desc *block_desc;
struct boot_init_vector *boot_vect =
(struct boot_init_vector *) cvmx_phys_to_ptr(0x0 +
BOOTLOADER_BOOT_VECTOR);
(struct boot_init_vector *)PHYS_TO_XKSEG_CACHED(BOOTLOADER_BOOT_VECTOR);
block_desc = cvmx_bootmem_find_named_block(LINUX_APP_BOOT_BLOCK_NAME);
if (!block_desc) {
avail_coremask =
cvmx_read64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
LABI_ADDR_IN_BOOTLOADER +
offsetof(struct linux_app_boot_info,
avail_coremask)));
struct linux_app_boot_info *labi;
labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
avail_coremask = labi->avail_coremask;
labi->avail_coremask &= ~(1 << coreid);
} else { /* alternative, already initialized */
avail_coremask =
cvmx_read64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
block_desc->base_addr +
AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK));
avail_coremask = *(uint32_t *)PHYS_TO_XKSEG_CACHED(
block_desc->base_addr + AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK);
}
if (!(avail_coremask & (1 << coreid))) {
......@@ -377,9 +383,9 @@ int octeon_update_boot_vector(unsigned int cpu)
boot_vect[coreid].app_start_func_addr =
(uint32_t) (unsigned long) start_after_reset;
boot_vect[coreid].code_addr = InitTLBStart_addr;
boot_vect[coreid].code_addr = octeon_bootloader_entry_addr;
CVMX_SYNC;
mb();
cvmx_write_csr(CVMX_CIU_NMI, (1 << coreid) & avail_coremask);
......@@ -405,17 +411,11 @@ static int __cpuinit octeon_cpu_callback(struct notifier_block *nfb,
return NOTIFY_OK;
}
static struct notifier_block __cpuinitdata octeon_cpu_notifier = {
.notifier_call = octeon_cpu_callback,
};
static int __cpuinit register_cavium_notifier(void)
{
register_hotcpu_notifier(&octeon_cpu_notifier);
hotcpu_notifier(octeon_cpu_callback, 0);
return 0;
}
late_initcall(register_cavium_notifier);
#endif /* CONFIG_HOTPLUG_CPU */
......
arch/mips/cobalt/Makefile
View file @ c3d1f174
......@@ -7,5 +7,3 @@ obj-y := buttons.o irq.o lcd.o led.o reset.o rtc.o serial.o setup.o time.o
obj-$(CONFIG_PCI) += pci.o
obj-$(CONFIG_EARLY_PRINTK) += console.o
obj-$(CONFIG_MTD_PHYSMAP) += mtd.o
EXTRA_CFLAGS += -Werror
arch/mips/cobalt/Platform 0 → 100644
View file @ c3d1f174
#
# Cobalt Server
#
platform-$(CONFIG_MIPS_COBALT) += cobalt/
cflags-$(CONFIG_MIPS_COBALT) += -I$(srctree)/arch/mips/include/asm/mach-cobalt
load-$(CONFIG_MIPS_COBALT) += 0xffffffff80080000
arch/mips/configs/db1000_defconfig
View file @ c3d1f174
......@@ -8,7 +8,7 @@ CONFIG_MIPS=y
#
# Machine selection
#
CONFIG_MACH_ALCHEMY=y
CONFIG_MIPS_ALCHEMY=y
# CONFIG_AR7 is not set
# CONFIG_BCM47XX is not set
# CONFIG_BCM63XX is not set
......@@ -64,7 +64,6 @@ CONFIG_MIPS_DB1000=y
# CONFIG_MIPS_PB1550 is not set
# CONFIG_MIPS_XXS1500 is not set
CONFIG_SOC_AU1000=y
CONFIG_SOC_AU1X00=y
CONFIG_LOONGSON_UART_BASE=y
CONFIG_RWSEM_GENERIC_SPINLOCK=y
# CONFIG_ARCH_HAS_ILOG2_U32 is not set
......
arch/mips/configs/db1100_defconfig
View file @ c3d1f174
......@@ -8,7 +8,7 @@ CONFIG_MIPS=y
#
# Machine selection
#
CONFIG_MACH_ALCHEMY=y
CONFIG_MIPS_ALCHEMY=y
# CONFIG_AR7 is not set
# CONFIG_BCM47XX is not set
# CONFIG_BCM63XX is not set
......@@ -64,7 +64,6 @@ CONFIG_MIPS_DB1100=y
# CONFIG_MIPS_PB1550 is not set
# CONFIG_MIPS_XXS1500 is not set
CONFIG_SOC_AU1100=y
CONFIG_SOC_AU1X00=y
CONFIG_LOONGSON_UART_BASE=y
CONFIG_RWSEM_GENERIC_SPINLOCK=y
# CONFIG_ARCH_HAS_ILOG2_U32 is not set
......
arch/mips/configs/db1200_defconfig
View file @ c3d1f174
......@@ -8,7 +8,7 @@ CONFIG_MIPS=y
#
# Machine selection
#
CONFIG_MACH_ALCHEMY=y
CONFIG_MIPS_ALCHEMY=y
# CONFIG_AR7 is not set
# CONFIG_BCM47XX is not set
# CONFIG_BCM63XX is not set
......@@ -64,7 +64,6 @@ CONFIG_MIPS_DB1200=y
# CONFIG_MIPS_PB1550 is not set
# CONFIG_MIPS_XXS1500 is not set
CONFIG_SOC_AU1200=y
CONFIG_SOC_AU1X00=y
CONFIG_LOONGSON_UART_BASE=y
CONFIG_RWSEM_GENERIC_SPINLOCK=y
# CONFIG_ARCH_HAS_ILOG2_U32 is not set
......
arch/mips/configs/db1500_defconfig
View file @ c3d1f174
......@@ -8,7 +8,7 @@ CONFIG_MIPS=y
#
# Machine selection
#
CONFIG_MACH_ALCHEMY=y
CONFIG_MIPS_ALCHEMY=y
# CONFIG_AR7 is not set
# CONFIG_BCM47XX is not set
# CONFIG_BCM63XX is not set
......@@ -64,7 +64,6 @@ CONFIG_MIPS_DB1500=y
# CONFIG_MIPS_PB1550 is not set
# CONFIG_MIPS_XXS1500 is not set
CONFIG_SOC_AU1500=y
CONFIG_SOC_AU1X00=y
CONFIG_LOONGSON_UART_BASE=y
CONFIG_RWSEM_GENERIC_SPINLOCK=y
# CONFIG_ARCH_HAS_ILOG2_U32 is not set
......
arch/mips/configs/db1550_defconfig
View file @ c3d1f174
......@@ -8,7 +8,7 @@ CONFIG_MIPS=y
#
# Machine selection
#
CONFIG_MACH_ALCHEMY=y
CONFIG_MIPS_ALCHEMY=y
# CONFIG_AR7 is not set
# CONFIG_BCM47XX is not set
# CONFIG_BCM63XX is not set
......@@ -64,7 +64,6 @@ CONFIG_MIPS_DB1550=y
# CONFIG_MIPS_PB1550 is not set
# CONFIG_MIPS_XXS1500 is not set
CONFIG_SOC_AU1550=y
CONFIG_SOC_AU1X00=y
CONFIG_LOONGSON_UART_BASE=y
CONFIG_RWSEM_GENERIC_SPINLOCK=y
# CONFIG_ARCH_HAS_ILOG2_U32 is not set
......
arch/mips/configs/gpr_defconfig 0 → 100644
View file @ c3d1f174
This diff is collapsed.
arch/mips/configs/mtx1_defconfig
View file @ c3d1f174
......@@ -8,7 +8,7 @@ CONFIG_MIPS=y
#
# Machine selection
#
CONFIG_MACH_ALCHEMY=y
CONFIG_MIPS_ALCHEMY=y
# CONFIG_AR7 is not set
# CONFIG_BCM47XX is not set
# CONFIG_BCM63XX is not set
......@@ -64,7 +64,6 @@ CONFIG_MIPS_MTX1=y
# CONFIG_MIPS_PB1550 is not set
# CONFIG_MIPS_XXS1500 is not set
CONFIG_SOC_AU1500=y
CONFIG_SOC_AU1X00=y
CONFIG_LOONGSON_UART_BASE=y
CONFIG_RWSEM_GENERIC_SPINLOCK=y
# CONFIG_ARCH_HAS_ILOG2_U32 is not set
......
arch/mips/configs/pb1100_defconfig
View file @ c3d1f174
......@@ -8,7 +8,7 @@ CONFIG_MIPS=y
#
# Machine selection
#
CONFIG_MACH_ALCHEMY=y
CONFIG_MIPS_ALCHEMY=y
# CONFIG_AR7 is not set
# CONFIG_BCM47XX is not set
# CONFIG_BCM63XX is not set
......@@ -64,7 +64,6 @@ CONFIG_MIPS_PB1100=y
# CONFIG_MIPS_PB1550 is not set
# CONFIG_MIPS_XXS1500 is not set
CONFIG_SOC_AU1100=y
CONFIG_SOC_AU1X00=y
CONFIG_LOONGSON_UART_BASE=y
CONFIG_RWSEM_GENERIC_SPINLOCK=y
# CONFIG_ARCH_HAS_ILOG2_U32 is not set
......
arch/mips/configs/pb1200_defconfig
View file @ c3d1f174
......@@ -8,7 +8,7 @@ CONFIG_MIPS=y
#
# Machine selection
#
CONFIG_MACH_ALCHEMY=y
CONFIG_MIPS_ALCHEMY=y
# CONFIG_AR7 is not set
# CONFIG_BCM47XX is not set
# CONFIG_BCM63XX is not set
......@@ -64,7 +64,6 @@ CONFIG_MIPS_PB1200=y
# CONFIG_MIPS_PB1550 is not set
# CONFIG_MIPS_XXS1500 is not set
CONFIG_SOC_AU1200=y
CONFIG_SOC_AU1X00=y
CONFIG_LOONGSON_UART_BASE=y
CONFIG_RWSEM_GENERIC_SPINLOCK=y
# CONFIG_ARCH_HAS_ILOG2_U32 is not set
......
arch/mips/configs/pb1500_defconfig
View file @ c3d1f174
......@@ -8,7 +8,7 @@ CONFIG_MIPS=y
#
# Machine selection
#
CONFIG_MACH_ALCHEMY=y
CONFIG_MIPS_ALCHEMY=y
# CONFIG_AR7 is not set
# CONFIG_BCM47XX is not set
# CONFIG_BCM63XX is not set
......@@ -64,7 +64,6 @@ CONFIG_MIPS_PB1500=y
# CONFIG_MIPS_PB1550 is not set
# CONFIG_MIPS_XXS1500 is not set
CONFIG_SOC_AU1500=y
CONFIG_SOC_AU1X00=y
CONFIG_LOONGSON_UART_BASE=y
CONFIG_RWSEM_GENERIC_SPINLOCK=y
# CONFIG_ARCH_HAS_ILOG2_U32 is not set
......
arch/mips/configs/pb1550_defconfig
View file @ c3d1f174
......@@ -8,7 +8,7 @@ CONFIG_MIPS=y
#
# Machine selection
#
CONFIG_MACH_ALCHEMY=y
CONFIG_MIPS_ALCHEMY=y
# CONFIG_AR7 is not set
# CONFIG_BCM47XX is not set
# CONFIG_BCM63XX is not set
......@@ -64,7 +64,6 @@ CONFIG_ALCHEMY_GPIOINT_AU1000=y
CONFIG_MIPS_PB1550=y
# CONFIG_MIPS_XXS1500 is not set
CONFIG_SOC_AU1550=y
CONFIG_SOC_AU1X00=y
CONFIG_LOONGSON_UART_BASE=y
CONFIG_RWSEM_GENERIC_SPINLOCK=y
# CONFIG_ARCH_HAS_ILOG2_U32 is not set
......
arch/mips/configs/powertv_defconfig
View file @ c3d1f174
This diff is collapsed.
arch/mips/dec/Makefile
View file @ c3d1f174
......@@ -8,5 +8,3 @@ obj-y := ecc-berr.o int-handler.o ioasic-irq.o kn01-berr.o \
obj-$(CONFIG_PROM_CONSOLE) += promcon.o
obj-$(CONFIG_TC) += tc.o
obj-$(CONFIG_CPU_HAS_WB) += wbflush.o
EXTRA_CFLAGS += -Werror
arch/mips/dec/Platform 0 → 100644
View file @ c3d1f174
#
# DECstation family
#
platform-$(CONFIG_MACH_DECSTATION) = dec/
cflags-$(CONFIG_MACH_DECSTATION) += \
-I$(srctree)/arch/mips/include/asm/mach-dec
libs-$(CONFIG_MACH_DECSTATION) += arch/mips/dec/prom/
load-$(CONFIG_MACH_DECSTATION) += 0xffffffff80040000
arch/mips/dec/promcon.c
View file @ c3d1f174
......@@ -33,8 +33,7 @@ static int __init prom_console_setup(struct console *co, char *options)
return 0;
}
static struct console sercons =
{
static struct console sercons = {
.name = "ttyS",
.write = prom_console_write,
.setup = prom_console_setup,
......
arch/mips/emma/Makefile 0 → 100644
View file @ c3d1f174
obj-$(CONFIG_SOC_EMMA2RH) += common/
#
# NEC EMMA2RH Mark-eins
#
obj-$(CONFIG_NEC_MARKEINS) += markeins/
arch/mips/emma/Platform 0 → 100644
View file @ c3d1f174
platform-$(CONFIG_SOC_EMMA2RH) += emma/
cflags-$(CONFIG_SOC_EMMA2RH) += \
-I$(srctree)/arch/mips/include/asm/mach-emma2rh
load-$(CONFIG_NEC_MARKEINS) += 0xffffffff88100000
arch/mips/emma/markeins/irq.c
View file @ c3d1f174
......@@ -301,7 +301,7 @@ void __init arch_init_irq(void)
/* setup cascade interrupts */
setup_irq(EMMA2RH_IRQ_BASE + EMMA2RH_SW_CASCADE, &irq_cascade);
setup_irq(EMMA2RH_IRQ_BASE + EMMA2RH_GPIO_CASCADE, &irq_cascade);
setup_irq(CPU_IRQ_BASE + CPU_EMMA2RH_CASCADE, &irq_cascade);
setup_irq(MIPS_CPU_IRQ_BASE + 2, &irq_cascade);
}
asmlinkage void plat_irq_dispatch(void)
......@@ -309,13 +309,13 @@ asmlinkage void plat_irq_dispatch(void)
unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
if (pending & STATUSF_IP7)
do_IRQ(CPU_IRQ_BASE + 7);
do_IRQ(MIPS_CPU_IRQ_BASE + 7);
else if (pending & STATUSF_IP2)
emma2rh_irq_dispatch();
else if (pending & STATUSF_IP1)
do_IRQ(CPU_IRQ_BASE + 1);
do_IRQ(MIPS_CPU_IRQ_BASE + 1);
else if (pending & STATUSF_IP0)
do_IRQ(CPU_IRQ_BASE + 0);
do_IRQ(MIPS_CPU_IRQ_BASE + 0);
else
spurious_interrupt();
}
arch/mips/emma/markeins/setup.c
View file @ c3d1f174
......@@ -52,7 +52,6 @@ static void markeins_machine_halt(void)
static void markeins_machine_power_off(void)
{
printk("EMMA2RH Mark-eins halted. Please turn off the power.\n");
markeins_led("poweroff.");
while (1) ;
}
......
arch/mips/include/asm/arch_hweight.h 0 → 100644
View file @ c3d1f174
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
*/
#ifndef _ASM_ARCH_HWEIGHT_H
#define _ASM_ARCH_HWEIGHT_H
#ifdef ARCH_HAS_USABLE_BUILTIN_POPCOUNT
#include <asm/types.h>
static inline unsigned int __arch_hweight32(unsigned int w)
{
return __builtin_popcount(w);
}
static inline unsigned int __arch_hweight16(unsigned int w)
{
return __builtin_popcount(w & 0xffff);
}
static inline unsigned int __arch_hweight8(unsigned int w)
{
return __builtin_popcount(w & 0xff);
}
static inline unsigned long __arch_hweight64(__u64 w)
{
return __builtin_popcountll(w);
}
#else
#include <asm-generic/bitops/arch_hweight.h>
#endif
#endif /* _ASM_ARCH_HWEIGHT_H */
arch/mips/include/asm/bitops.h
View file @ c3d1f174
......@@ -700,7 +700,10 @@ static inline int ffs(int word)
#ifdef __KERNEL__
#include <asm-generic/bitops/sched.h>
#include <asm-generic/bitops/hweight.h>
#include <asm/arch_hweight.h>
#include <asm-generic/bitops/const_hweight.h>
#include <asm-generic/bitops/ext2-non-atomic.h>
#include <asm-generic/bitops/ext2-atomic.h>
#include <asm-generic/bitops/minix.h>
......
arch/mips/include/asm/bootinfo.h
View file @ c3d1f174
......@@ -71,6 +71,12 @@
#define MACH_LEMOTE_LL2F 7
#define MACH_LOONGSON_END 8
/*
* Valid machtype for group INGENIC
*/
#define MACH_INGENIC_JZ4730 0 /* JZ4730 SOC */
#define MACH_INGENIC_JZ4740 1 /* JZ4740 SOC */
extern char *system_type;
const char *get_system_type(void);
......
arch/mips/include/asm/break.h
View file @ c3d1f174
......@@ -30,6 +30,8 @@
#define BRK_BUG 512 /* Used by BUG() */
#define BRK_KDB 513 /* Used in KDB_ENTER() */
#define BRK_MEMU 514 /* Used by FPU emulator */
#define BRK_KPROBE_BP 515 /* Kprobe break */
#define BRK_KPROBE_SSTEPBP 516 /* Kprobe single step software implementation */
#define BRK_MULOVF 1023 /* Multiply overflow */
#endif /* __ASM_BREAK_H */
arch/mips/include/asm/cacheops.h
View file @ c3d1f174
......@@ -62,6 +62,8 @@
* RM7000-specific cacheops
*/
#define Page_Invalidate_T 0x16
#define Index_Store_Tag_T 0x0a
#define Index_Load_Tag_T 0x06
/*
* R10000-specific cacheops
......
arch/mips/include/asm/cop2.h
View file @ c3d1f174
......@@ -9,6 +9,8 @@
#ifndef __ASM_COP2_H
#define __ASM_COP2_H
#include <linux/notifier.h>
enum cu2_ops {
CU2_EXCEPTION,
CU2_LWC2_OP,
......@@ -20,4 +22,14 @@ enum cu2_ops {
extern int register_cu2_notifier(struct notifier_block *nb);
extern int cu2_notifier_call_chain(unsigned long val, void *v);
#define cu2_notifier(fn, pri) \
({ \
static struct notifier_block fn##_nb __cpuinitdata = { \
.notifier_call = fn, \
.priority = pri \
}; \
\
register_cu2_notifier(&fn##_nb); \
})
#endif /* __ASM_COP2_H */
arch/mips/include/asm/cpu-features.h
View file @ c3d1f174
......@@ -159,7 +159,8 @@
/*
* MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other
* pre-MIPS32/MIPS53 processors have CLO, CLZ. For 64-bit kernels
* pre-MIPS32/MIPS53 processors have CLO, CLZ. The IDT RC64574 is 64-bit and
* has CLO and CLZ but not DCLO nor DCLZ. For 64-bit kernels
* cpu_has_clo_clz also indicates the availability of DCLO and DCLZ.
*/
# ifndef cpu_has_clo_clz
......
arch/mips/include/asm/cpu.h
View file @ c3d1f174
......@@ -34,7 +34,7 @@
#define PRID_COMP_LSI 0x080000
#define PRID_COMP_LEXRA 0x0b0000
#define PRID_COMP_CAVIUM 0x0d0000
#define PRID_COMP_INGENIC 0xd00000
/*
* Assigned values for the product ID register. In order to detect a
......@@ -132,6 +132,12 @@
#define PRID_IMP_CAVIUM_CN50XX 0x0600
#define PRID_IMP_CAVIUM_CN52XX 0x0700
/*
* These are the PRID's for when 23:16 == PRID_COMP_INGENIC
*/
#define PRID_IMP_JZRISC 0x0200
/*
* Definitions for 7:0 on legacy processors
*/
......@@ -219,6 +225,7 @@ enum cpu_type_enum {
CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,
CPU_ALCHEMY, CPU_PR4450, CPU_BCM3302, CPU_BCM4710,
CPU_BCM6338, CPU_BCM6345, CPU_BCM6348, CPU_BCM6358,
CPU_JZRISC,
/*
* MIPS64 class processors
......
arch/mips/include/asm/elf.h
View file @ c3d1f174
......@@ -372,4 +372,9 @@ extern const char *__elf_platform;
struct linux_binprm;
extern int arch_setup_additional_pages(struct linux_binprm *bprm,
int uses_interp);
struct mm_struct;
extern unsigned long arch_randomize_brk(struct mm_struct *mm);
#define arch_randomize_brk arch_randomize_brk
#endif /* _ASM_ELF_H */
arch/mips/include/asm/emma/emma2rh.h
View file @ c3d1f174
......@@ -99,88 +99,22 @@
#define EMMA2RH_PCI_CONFIG_BASE EMMA2RH_PCI_IO_BASE
#define EMMA2RH_PCI_CONFIG_SIZE EMMA2RH_PCI_IO_SIZE
#define NUM_CPU_IRQ 8
#define NUM_EMMA2RH_IRQ 96
#define CPU_EMMA2RH_CASCADE 2
#define CPU_IRQ_BASE MIPS_CPU_IRQ_BASE
#define EMMA2RH_IRQ_BASE (CPU_IRQ_BASE + NUM_CPU_IRQ)
#define EMMA2RH_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8)
/*
* emma2rh irq defs
*/
#define EMMA2RH_IRQ_INT0 (0 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT1 (1 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT2 (2 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT3 (3 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT4 (4 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT5 (5 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT6 (6 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT7 (7 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT8 (8 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT9 (9 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT10 (10 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT11 (11 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT12 (12 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT13 (13 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT14 (14 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT15 (15 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT16 (16 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT17 (17 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT18 (18 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT19 (19 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT20 (20 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT21 (21 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT22 (22 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT23 (23 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT24 (24 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT25 (25 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT26 (26 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT27 (27 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT28 (28 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT29 (29 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT30 (30 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT31 (31 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT32 (32 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT33 (33 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT34 (34 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT35 (35 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT36 (36 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT37 (37 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT38 (38 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT39 (39 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT40 (40 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT41 (41 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT42 (42 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT43 (43 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT44 (44 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT45 (45 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT46 (46 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT47 (47 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT48 (48 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT49 (49 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT50 (50 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT51 (51 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT52 (52 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT53 (53 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT54 (54 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT55 (55 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT56 (56 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT57 (57 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT58 (58 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT59 (59 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT60 (60 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT61 (61 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT62 (62 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT63 (63 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_PFUR0 EMMA2RH_IRQ_INT49
#define EMMA2RH_IRQ_PFUR1 EMMA2RH_IRQ_INT50
#define EMMA2RH_IRQ_PFUR2 EMMA2RH_IRQ_INT51
#define EMMA2RH_IRQ_PIIC0 EMMA2RH_IRQ_INT56
#define EMMA2RH_IRQ_PIIC1 EMMA2RH_IRQ_INT57
#define EMMA2RH_IRQ_PIIC2 EMMA2RH_IRQ_INT58
#define EMMA2RH_IRQ_INT(n) (EMMA2RH_IRQ_BASE + (n))
#define EMMA2RH_IRQ_PFUR0 EMMA2RH_IRQ_INT(49)
#define EMMA2RH_IRQ_PFUR1 EMMA2RH_IRQ_INT(50)
#define EMMA2RH_IRQ_PFUR2 EMMA2RH_IRQ_INT(51)
#define EMMA2RH_IRQ_PIIC0 EMMA2RH_IRQ_INT(56)
#define EMMA2RH_IRQ_PIIC1 EMMA2RH_IRQ_INT(57)
#define EMMA2RH_IRQ_PIIC2 EMMA2RH_IRQ_INT(58)
/*
* EMMA2RH Register Access
......
arch/mips/include/asm/emma/markeins.h
View file @ c3d1f174
......@@ -25,44 +25,13 @@
#define NUM_EMMA2RH_IRQ_SW 32
#define NUM_EMMA2RH_IRQ_GPIO 32
#define EMMA2RH_SW_CASCADE (EMMA2RH_IRQ_INT7 - EMMA2RH_IRQ_INT0)
#define EMMA2RH_GPIO_CASCADE (EMMA2RH_IRQ_INT46 - EMMA2RH_IRQ_INT0)
#define EMMA2RH_SW_CASCADE (EMMA2RH_IRQ_INT(7) - EMMA2RH_IRQ_INT(0))
#define EMMA2RH_GPIO_CASCADE (EMMA2RH_IRQ_INT(46) - EMMA2RH_IRQ_INT(0))
#define EMMA2RH_SW_IRQ_BASE (EMMA2RH_IRQ_BASE + NUM_EMMA2RH_IRQ)
#define EMMA2RH_GPIO_IRQ_BASE (EMMA2RH_SW_IRQ_BASE + NUM_EMMA2RH_IRQ_SW)
#define EMMA2RH_SW_IRQ_INT0 (0+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT1 (1+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT2 (2+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT3 (3+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT4 (4+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT5 (5+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT6 (6+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT7 (7+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT8 (8+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT9 (9+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT10 (10+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT11 (11+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT12 (12+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT13 (13+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT14 (14+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT15 (15+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT16 (16+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT17 (17+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT18 (18+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT19 (19+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT20 (20+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT21 (21+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT22 (22+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT23 (23+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT24 (24+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT25 (25+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT26 (26+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT27 (27+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT28 (28+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT29 (29+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT30 (30+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT31 (31+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT(n) (EMMA2RH_SW_IRQ_BASE + (n))
#define MARKEINS_PCI_IRQ_INTA EMMA2RH_GPIO_IRQ_BASE+15
#define MARKEINS_PCI_IRQ_INTB EMMA2RH_GPIO_IRQ_BASE+16
......
arch/mips/include/asm/hazards.h
View file @ c3d1f174
......@@ -87,7 +87,7 @@ do { \
: "=r" (tmp)); \
} while (0)
#elif defined(CONFIG_CPU_MIPSR1) && !defined(CONFIG_MACH_ALCHEMY)
#elif defined(CONFIG_CPU_MIPSR1) && !defined(CONFIG_MIPS_ALCHEMY)
/*
* These are slightly complicated by the fact that we guarantee R1 kernels to
......@@ -138,7 +138,7 @@ do { \
__instruction_hazard(); \
} while (0)
#elif defined(CONFIG_MACH_ALCHEMY) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \
#elif defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \
defined(CONFIG_CPU_LOONGSON2) || defined(CONFIG_CPU_R10000) || \
defined(CONFIG_CPU_R5500)
......
arch/mips/include/asm/inst.h
View file @ c3d1f174
......@@ -247,6 +247,12 @@ struct ma_format { /* FPU multipy and add format (MIPS IV) */
unsigned int fmt : 2;
};
struct b_format { /* BREAK and SYSCALL */
unsigned int opcode:6;
unsigned int code:20;
unsigned int func:6;
};
#elif defined(__MIPSEL__)
struct j_format { /* Jump format */
......@@ -314,6 +320,12 @@ struct ma_format { /* FPU multipy and add format (MIPS IV) */
unsigned int opcode : 6;
};
struct b_format { /* BREAK and SYSCALL */
unsigned int func:6;
unsigned int code:20;
unsigned int opcode:6;
};
#else /* !defined (__MIPSEB__) && !defined (__MIPSEL__) */
#error "MIPS but neither __MIPSEL__ nor __MIPSEB__?"
#endif
......@@ -329,6 +341,7 @@ union mips_instruction {
struct r_format r_format;
struct f_format f_format;
struct ma_format ma_format;
struct b_format b_format;
};
/* HACHACHAHCAHC ... */
......
arch/mips/include/asm/kdebug.h
View file @ c3d1f174
......@@ -8,6 +8,9 @@ enum die_val {
DIE_FP,
DIE_TRAP,
DIE_RI,
DIE_PAGE_FAULT,
DIE_BREAK,
DIE_SSTEPBP
};
#endif /* _ASM_MIPS_KDEBUG_H */
arch/mips/include/asm/kprobes.h 0 → 100644
View file @ c3d1f174
/*
* Kernel Probes (KProbes)
* include/asm-mips/kprobes.h
*
* Copyright 2006 Sony Corp.
* Copyright 2010 Cavium Networks
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef _ASM_KPROBES_H
#define _ASM_KPROBES_H
#include <linux/ptrace.h>
#include <linux/types.h>
#include <asm/cacheflush.h>
#include <asm/kdebug.h>
#include <asm/inst.h>
#define __ARCH_WANT_KPROBES_INSN_SLOT
struct kprobe;
struct pt_regs;
typedef union mips_instruction kprobe_opcode_t;
#define MAX_INSN_SIZE 2
#define flush_insn_slot(p) \
do { \
flush_icache_range((unsigned long)p->addr, \
(unsigned long)p->addr + \
(MAX_INSN_SIZE * sizeof(kprobe_opcode_t))); \
} while (0)
#define kretprobe_blacklist_size 0
void arch_remove_kprobe(struct kprobe *p);
/* Architecture specific copy of original instruction*/
struct arch_specific_insn {
/* copy of the original instruction */
kprobe_opcode_t *insn;
};
struct prev_kprobe {
struct kprobe *kp;
unsigned long status;
unsigned long old_SR;
unsigned long saved_SR;
unsigned long saved_epc;
};
#define MAX_JPROBES_STACK_SIZE 128
#define MAX_JPROBES_STACK_ADDR \
(((unsigned long)current_thread_info()) + THREAD_SIZE - 32 - sizeof(struct pt_regs))
#define MIN_JPROBES_STACK_SIZE(ADDR) \
((((ADDR) + MAX_JPROBES_STACK_SIZE) > MAX_JPROBES_STACK_ADDR) \
? MAX_JPROBES_STACK_ADDR - (ADDR) \
: MAX_JPROBES_STACK_SIZE)
/* per-cpu kprobe control block */
struct kprobe_ctlblk {
unsigned long kprobe_status;
unsigned long kprobe_old_SR;
unsigned long kprobe_saved_SR;
unsigned long kprobe_saved_epc;
unsigned long jprobe_saved_sp;
struct pt_regs jprobe_saved_regs;
u8 jprobes_stack[MAX_JPROBES_STACK_SIZE];
struct prev_kprobe prev_kprobe;
};
extern int kprobe_exceptions_notify(struct notifier_block *self,
unsigned long val, void *data);
#endif /* _ASM_KPROBES_H */
arch/mips/include/asm/mach-au1x00/au1xxx_eth.h
View file @ c3d1f174
......@@ -9,6 +9,7 @@ struct au1000_eth_platform_data {
int phy_addr;
int phy_busid;
int phy_irq;
char mac[6];
};
void __init au1xxx_override_eth_cfg(unsigned port,
......
arch/mips/include/asm/mach-bcm47xx/nvram.h
View file @ c3d1f174
......@@ -31,6 +31,9 @@ struct nvram_header {
#define NVRAM_MAX_VALUE_LEN 255
#define NVRAM_MAX_PARAM_LEN 64
#define NVRAM_ERR_INV_PARAM -8
#define NVRAM_ERR_ENVNOTFOUND -9
extern int nvram_getenv(char *name, char *val, size_t val_len);
#endif
arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
View file @ c3d1f174
......@@ -61,21 +61,18 @@
#define kernel_uses_smartmips_rixi (cpu_data[0].cputype == CPU_CAVIUM_OCTEON_PLUS)
#define ARCH_HAS_READ_CURRENT_TIMER 1
#define ARCH_HAS_IRQ_PER_CPU 1
#define ARCH_HAS_SPINLOCK_PREFETCH 1
#define spin_lock_prefetch(x) prefetch(x)
#define PREFETCH_STRIDE 128
static inline int read_current_timer(unsigned long *result)
{
asm volatile ("rdhwr %0,$31\n"
#ifndef CONFIG_64BIT
"\tsll %0, 0"
#ifdef __OCTEON__
/*
* All gcc versions that have OCTEON support define __OCTEON__ and have the
* __builtin_popcount support.
*/
#define ARCH_HAS_USABLE_BUILTIN_POPCOUNT 1
#endif
: "=r" (*result));
return 0;
}
static inline int octeon_has_saa(void)
{
......
arch/mips/include/asm/mach-cavium-octeon/irq.h
View file @ c3d1f174
......@@ -172,71 +172,9 @@
#ifdef CONFIG_PCI_MSI
/* 152 - 215 represent the MSI interrupts 0-63 */
#define OCTEON_IRQ_MSI_BIT0 152
#define OCTEON_IRQ_MSI_BIT1 153
#define OCTEON_IRQ_MSI_BIT2 154
#define OCTEON_IRQ_MSI_BIT3 155
#define OCTEON_IRQ_MSI_BIT4 156
#define OCTEON_IRQ_MSI_BIT5 157
#define OCTEON_IRQ_MSI_BIT6 158
#define OCTEON_IRQ_MSI_BIT7 159
#define OCTEON_IRQ_MSI_BIT8 160
#define OCTEON_IRQ_MSI_BIT9 161
#define OCTEON_IRQ_MSI_BIT10 162
#define OCTEON_IRQ_MSI_BIT11 163
#define OCTEON_IRQ_MSI_BIT12 164
#define OCTEON_IRQ_MSI_BIT13 165
#define OCTEON_IRQ_MSI_BIT14 166
#define OCTEON_IRQ_MSI_BIT15 167
#define OCTEON_IRQ_MSI_BIT16 168
#define OCTEON_IRQ_MSI_BIT17 169
#define OCTEON_IRQ_MSI_BIT18 170
#define OCTEON_IRQ_MSI_BIT19 171
#define OCTEON_IRQ_MSI_BIT20 172
#define OCTEON_IRQ_MSI_BIT21 173
#define OCTEON_IRQ_MSI_BIT22 174
#define OCTEON_IRQ_MSI_BIT23 175
#define OCTEON_IRQ_MSI_BIT24 176
#define OCTEON_IRQ_MSI_BIT25 177
#define OCTEON_IRQ_MSI_BIT26 178
#define OCTEON_IRQ_MSI_BIT27 179
#define OCTEON_IRQ_MSI_BIT28 180
#define OCTEON_IRQ_MSI_BIT29 181
#define OCTEON_IRQ_MSI_BIT30 182
#define OCTEON_IRQ_MSI_BIT31 183
#define OCTEON_IRQ_MSI_BIT32 184
#define OCTEON_IRQ_MSI_BIT33 185
#define OCTEON_IRQ_MSI_BIT34 186
#define OCTEON_IRQ_MSI_BIT35 187
#define OCTEON_IRQ_MSI_BIT36 188
#define OCTEON_IRQ_MSI_BIT37 189
#define OCTEON_IRQ_MSI_BIT38 190
#define OCTEON_IRQ_MSI_BIT39 191
#define OCTEON_IRQ_MSI_BIT40 192
#define OCTEON_IRQ_MSI_BIT41 193
#define OCTEON_IRQ_MSI_BIT42 194
#define OCTEON_IRQ_MSI_BIT43 195
#define OCTEON_IRQ_MSI_BIT44 196
#define OCTEON_IRQ_MSI_BIT45 197
#define OCTEON_IRQ_MSI_BIT46 198
#define OCTEON_IRQ_MSI_BIT47 199
#define OCTEON_IRQ_MSI_BIT48 200
#define OCTEON_IRQ_MSI_BIT49 201
#define OCTEON_IRQ_MSI_BIT50 202
#define OCTEON_IRQ_MSI_BIT51 203
#define OCTEON_IRQ_MSI_BIT52 204
#define OCTEON_IRQ_MSI_BIT53 205
#define OCTEON_IRQ_MSI_BIT54 206
#define OCTEON_IRQ_MSI_BIT55 207
#define OCTEON_IRQ_MSI_BIT56 208
#define OCTEON_IRQ_MSI_BIT57 209
#define OCTEON_IRQ_MSI_BIT58 210
#define OCTEON_IRQ_MSI_BIT59 211
#define OCTEON_IRQ_MSI_BIT60 212
#define OCTEON_IRQ_MSI_BIT61 213
#define OCTEON_IRQ_MSI_BIT62 214
#define OCTEON_IRQ_MSI_BIT63 215
#define OCTEON_IRQ_MSI_LAST (OCTEON_IRQ_MSI_BIT0 + 255)
#define OCTEON_IRQ_LAST 216
#define OCTEON_IRQ_LAST (OCTEON_IRQ_MSI_LAST + 1)
#else
#define OCTEON_IRQ_LAST 152
#endif
......
arch/mips/include/asm/mach-jz4740/base.h 0 → 100644
View file @ c3d1f174
#ifndef __ASM_MACH_JZ4740_BASE_H__
#define __ASM_MACH_JZ4740_BASE_H__
#define JZ4740_CPM_BASE_ADDR 0x10000000
#define JZ4740_INTC_BASE_ADDR 0x10001000
#define JZ4740_WDT_BASE_ADDR 0x10002000
#define JZ4740_TCU_BASE_ADDR 0x10002010
#define JZ4740_RTC_BASE_ADDR 0x10003000
#define JZ4740_GPIO_BASE_ADDR 0x10010000
#define JZ4740_AIC_BASE_ADDR 0x10020000
#define JZ4740_MSC_BASE_ADDR 0x10021000
#define JZ4740_UART0_BASE_ADDR 0x10030000
#define JZ4740_UART1_BASE_ADDR 0x10031000
#define JZ4740_I2C_BASE_ADDR 0x10042000
#define JZ4740_SSI_BASE_ADDR 0x10043000
#define JZ4740_SADC_BASE_ADDR 0x10070000
#define JZ4740_EMC_BASE_ADDR 0x13010000
#define JZ4740_DMAC_BASE_ADDR 0x13020000
#define JZ4740_UHC_BASE_ADDR 0x13030000
#define JZ4740_UDC_BASE_ADDR 0x13040000
#define JZ4740_LCD_BASE_ADDR 0x13050000
#define JZ4740_SLCD_BASE_ADDR 0x13050000
#define JZ4740_CIM_BASE_ADDR 0x13060000
#define JZ4740_IPU_BASE_ADDR 0x13080000
#endif
arch/mips/include/asm/mach-jz4740/clock.h 0 → 100644
View file @ c3d1f174
/*
* Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
*/
#ifndef __ASM_JZ4740_CLOCK_H__
#define __ASM_JZ4740_CLOCK_H__
enum jz4740_wait_mode {
JZ4740_WAIT_MODE_IDLE,
JZ4740_WAIT_MODE_SLEEP,
};
void jz4740_clock_set_wait_mode(enum jz4740_wait_mode mode);
void jz4740_clock_udc_enable_auto_suspend(void);
void jz4740_clock_udc_disable_auto_suspend(void);
#endif
arch/mips/include/asm/mach-jz4740/cpu-feature-overrides.h 0 → 100644
View file @ c3d1f174
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
*/
#ifndef __ASM_MACH_JZ4740_CPU_FEATURE_OVERRIDES_H
#define __ASM_MACH_JZ4740_CPU_FEATURE_OVERRIDES_H
#define cpu_has_tlb 1
#define cpu_has_4kex 1
#define cpu_has_3k_cache 0
#define cpu_has_4k_cache 1
#define cpu_has_tx39_cache 0
#define cpu_has_fpu 0
#define cpu_has_32fpr 0
#define cpu_has_counter 0
#define cpu_has_watch 1
#define cpu_has_divec 1
#define cpu_has_vce 0
#define cpu_has_cache_cdex_p 0
#define cpu_has_cache_cdex_s 0
#define cpu_has_prefetch 1
#define cpu_has_mcheck 1
#define cpu_has_ejtag 1
#define cpu_has_llsc 1
#define cpu_has_mips16 0
#define cpu_has_mdmx 0
#define cpu_has_mips3d 0
#define cpu_has_smartmips 0
#define kernel_uses_llsc 1
#define cpu_has_vtag_icache 1
#define cpu_has_dc_aliases 0
#define cpu_has_ic_fills_f_dc 0
#define cpu_has_pindexed_dcache 0
#define cpu_has_mips32r1 1
#define cpu_has_mips32r2 0
#define cpu_has_mips64r1 0
#define cpu_has_mips64r2 0
#define cpu_has_dsp 0
#define cpu_has_mipsmt 0
#define cpu_has_userlocal 0
#define cpu_has_nofpuex 0
#define cpu_has_64bits 0
#define cpu_has_64bit_zero_reg 0
#define cpu_has_inclusive_pcaches 0
#define cpu_dcache_line_size() 32
#define cpu_icache_line_size() 32
#endif
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arch/mips/include/asm/mach-jz4740/jz4740_mmc.h 0 → 100644
View file @ c3d1f174
#ifndef __LINUX_MMC_JZ4740_MMC
#define __LINUX_MMC_JZ4740_MMC
struct jz4740_mmc_platform_data {
int gpio_power;
int gpio_card_detect;
int gpio_read_only;
unsigned card_detect_active_low:1;
unsigned read_only_active_low:1;
unsigned power_active_low:1;
unsigned data_1bit:1;
};
#endif
arch/mips/include/asm/mach-jz4740/jz4740_nand.h 0 → 100644
View file @ c3d1f174
/*
* Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
* JZ4740 SoC NAND controller driver
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
*/
#ifndef __ASM_MACH_JZ4740_JZ4740_NAND_H__
#define __ASM_MACH_JZ4740_JZ4740_NAND_H__
#include <linux/mtd/nand.h>
#include <linux/mtd/partitions.h>
struct jz_nand_platform_data {
int num_partitions;
struct mtd_partition *partitions;
struct nand_ecclayout *ecc_layout;
unsigned int busy_gpio;
void (*ident_callback)(struct platform_device *, struct nand_chip *,
struct mtd_partition **, int *num_partitions);
};
#endif
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arch/mips/include/asm/mach-tx49xx/kmalloc.h
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