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Commit c4256885 authored by Rex Zhu's avatar Rex Zhu Committed by Alex Deucher
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drm/amd/pp: Replace rv_* with smu10_* 

Powerplay is for the hw ip smu, for RV, smu10 is used,
so use smu10 as the prefix of the files name/function name.
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarRex Zhu <Rex.Zhu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 567cc73a
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Showing with 371 additions and 371 deletions
drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
View file @ c4256885
...@@ -30,7 +30,7 @@ HARDWARE_MGR = hwmgr.o processpptables.o \ ...@@ -30,7 +30,7 @@ HARDWARE_MGR = hwmgr.o processpptables.o \
smu7_hwmgr.o smu7_powertune.o smu7_thermal.o \ smu7_hwmgr.o smu7_powertune.o smu7_thermal.o \
smu7_clockpowergating.o \ smu7_clockpowergating.o \
vega10_processpptables.o vega10_hwmgr.o vega10_powertune.o \ vega10_processpptables.o vega10_hwmgr.o vega10_powertune.o \
vega10_thermal.o rv_hwmgr.o pp_psm.o\ vega10_thermal.o smu10_hwmgr.o pp_psm.o\
pp_overdriver.o pp_overdriver.o
AMD_PP_HWMGR = $(addprefix $(AMD_PP_PATH)/hwmgr/,$(HARDWARE_MGR)) AMD_PP_HWMGR = $(addprefix $(AMD_PP_PATH)/hwmgr/,$(HARDWARE_MGR))
......
drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
View file @ c4256885
...@@ -43,7 +43,7 @@ extern const struct pp_smumgr_func tonga_smu_funcs; ...@@ -43,7 +43,7 @@ extern const struct pp_smumgr_func tonga_smu_funcs;
extern const struct pp_smumgr_func fiji_smu_funcs; extern const struct pp_smumgr_func fiji_smu_funcs;
extern const struct pp_smumgr_func polaris10_smu_funcs; extern const struct pp_smumgr_func polaris10_smu_funcs;
extern const struct pp_smumgr_func vega10_smu_funcs; extern const struct pp_smumgr_func vega10_smu_funcs;
extern const struct pp_smumgr_func rv_smu_funcs; extern const struct pp_smumgr_func smu10_smu_funcs;
extern int cz_init_function_pointers(struct pp_hwmgr *hwmgr); extern int cz_init_function_pointers(struct pp_hwmgr *hwmgr);
static int polaris_set_asic_special_caps(struct pp_hwmgr *hwmgr); static int polaris_set_asic_special_caps(struct pp_hwmgr *hwmgr);
...@@ -230,8 +230,8 @@ int hwmgr_early_init(struct pp_instance *handle) ...@@ -230,8 +230,8 @@ int hwmgr_early_init(struct pp_instance *handle)
switch (hwmgr->chip_id) { switch (hwmgr->chip_id) {
case CHIP_RAVEN: case CHIP_RAVEN:
hwmgr->od_enabled = false; hwmgr->od_enabled = false;
hwmgr->smumgr_funcs = &rv_smu_funcs; hwmgr->smumgr_funcs = &smu10_smu_funcs;
rv_init_function_pointers(hwmgr); smu10_init_function_pointers(hwmgr);
break; break;
default: default:
return -EINVAL; return -EINVAL;
......
drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h → drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h
View file @ c4256885
...@@ -21,17 +21,17 @@ ...@@ -21,17 +21,17 @@
* *
*/ */
#ifndef RAVEN_HWMGR_H #ifndef SMU10_HWMGR_H
#define RAVEN_HWMGR_H #define SMU10_HWMGR_H
#include "hwmgr.h" #include "hwmgr.h"
#include "rv_inc.h" #include "smu10_inc.h"
#include "smu10_driver_if.h" #include "smu10_driver_if.h"
#include "rv_ppsmc.h" #include "rv_ppsmc.h"
#define RAVEN_MAX_HARDWARE_POWERLEVELS 8 #define SMU10_MAX_HARDWARE_POWERLEVELS 8
#define PHMRAVEN_DYNCLK_NUMBER_OF_TREND_COEFFICIENTS 15 #define SMU10_DYNCLK_NUMBER_OF_TREND_COEFFICIENTS 15
#define DPMFlags_SCLK_Enabled 0x00000001 #define DPMFlags_SCLK_Enabled 0x00000001
#define DPMFlags_UVD_Enabled 0x00000002 #define DPMFlags_UVD_Enabled 0x00000002
...@@ -47,10 +47,10 @@ ...@@ -47,10 +47,10 @@
#define SMU_PHYID_SHIFT 8 #define SMU_PHYID_SHIFT 8
#define RAVEN_PCIE_POWERGATING_TARGET_GFX 0 #define SMU10_PCIE_POWERGATING_TARGET_GFX 0
#define RAVEN_PCIE_POWERGATING_TARGET_DDI 1 #define SMU10_PCIE_POWERGATING_TARGET_DDI 1
#define RAVEN_PCIE_POWERGATING_TARGET_PLLCASCADE 2 #define SMU10_PCIE_POWERGATING_TARGET_PLLCASCADE 2
#define RAVEN_PCIE_POWERGATING_TARGET_PHY 3 #define SMU10_PCIE_POWERGATING_TARGET_PHY 3
enum VQ_TYPE { enum VQ_TYPE {
CLOCK_TYPE_DCLK = 0L, CLOCK_TYPE_DCLK = 0L,
...@@ -65,14 +65,14 @@ enum VQ_TYPE { ...@@ -65,14 +65,14 @@ enum VQ_TYPE {
#define SUSTAINABLE_CU_MASK 0xff000000 #define SUSTAINABLE_CU_MASK 0xff000000
#define SUSTAINABLE_CU_SHIFT 24 #define SUSTAINABLE_CU_SHIFT 24
struct rv_dpm_entry { struct smu10_dpm_entry {
uint32_t soft_min_clk; uint32_t soft_min_clk;
uint32_t hard_min_clk; uint32_t hard_min_clk;
uint32_t soft_max_clk; uint32_t soft_max_clk;
uint32_t hard_max_clk; uint32_t hard_max_clk;
}; };
struct rv_power_level { struct smu10_power_level {
uint32_t engine_clock; uint32_t engine_clock;
uint8_t vddc_index; uint8_t vddc_index;
uint8_t ds_divider_index; uint8_t ds_divider_index;
...@@ -86,14 +86,14 @@ struct rv_power_level { ...@@ -86,14 +86,14 @@ struct rv_power_level {
uint8_t rsv[3]; uint8_t rsv[3];
}; };
/*used for the nbpsFlags field in rv_power state*/ /*used for the nbpsFlags field in smu10_power state*/
#define RAVEN_POWERSTATE_FLAGS_NBPS_FORCEHIGH (1<<0) #define SMU10_POWERSTATE_FLAGS_NBPS_FORCEHIGH (1<<0)
#define RAVEN_POWERSTATE_FLAGS_NBPS_LOCKTOHIGH (1<<1) #define SMU10_POWERSTATE_FLAGS_NBPS_LOCKTOHIGH (1<<1)
#define RAVEN_POWERSTATE_FLAGS_NBPS_LOCKTOLOW (1<<2) #define SMU10_POWERSTATE_FLAGS_NBPS_LOCKTOLOW (1<<2)
#define RAVEN_POWERSTATE_FLAGS_BAPM_DISABLE (1<<0) #define SMU10_POWERSTATE_FLAGS_BAPM_DISABLE (1<<0)
struct rv_uvd_clocks { struct smu10_uvd_clocks {
uint32_t vclk; uint32_t vclk;
uint32_t dclk; uint32_t dclk;
uint32_t vclk_low_divider; uint32_t vclk_low_divider;
...@@ -118,16 +118,16 @@ struct pp_disable_nbpslo_flags { ...@@ -118,16 +118,16 @@ struct pp_disable_nbpslo_flags {
}; };
enum rv_pstate_previous_action { enum smu10_pstate_previous_action {
DO_NOTHING = 1, DO_NOTHING = 1,
FORCE_HIGH, FORCE_HIGH,
CANCEL_FORCE_HIGH CANCEL_FORCE_HIGH
}; };
struct rv_power_state { struct smu10_power_state {
unsigned int magic; unsigned int magic;
uint32_t level; uint32_t level;
struct rv_uvd_clocks uvd_clocks; struct smu10_uvd_clocks uvd_clocks;
uint32_t evclk; uint32_t evclk;
uint32_t ecclk; uint32_t ecclk;
uint32_t samclk; uint32_t samclk;
...@@ -141,79 +141,79 @@ struct rv_power_state { ...@@ -141,79 +141,79 @@ struct rv_power_state {
uint8_t dpm_x_nbps_low; uint8_t dpm_x_nbps_low;
uint8_t dpm_x_nbps_high; uint8_t dpm_x_nbps_high;
enum rv_pstate_previous_action action; enum smu10_pstate_previous_action action;
struct rv_power_level levels[RAVEN_MAX_HARDWARE_POWERLEVELS]; struct smu10_power_level levels[SMU10_MAX_HARDWARE_POWERLEVELS];
struct pp_disable_nbpslo_flags nbpslo_flags; struct pp_disable_nbpslo_flags nbpslo_flags;
}; };
#define RAVEN_NUM_NBPSTATES 4 #define SMU10_NUM_NBPSTATES 4
#define RAVEN_NUM_NBPMEMORYCLOCK 2 #define SMU10_NUM_NBPMEMORYCLOCK 2
struct rv_display_phy_info_entry { struct smu10_display_phy_info_entry {
uint8_t phy_present; uint8_t phy_present;
uint8_t active_lane_mapping; uint8_t active_lane_mapping;
uint8_t display_config_type; uint8_t display_config_type;
uint8_t active_num_of_lanes; uint8_t active_num_of_lanes;
}; };
#define RAVEN_MAX_DISPLAYPHY_IDS 10 #define SMU10_MAX_DISPLAYPHY_IDS 10
struct rv_display_phy_info { struct smu10_display_phy_info {
bool display_phy_access_initialized; bool display_phy_access_initialized;
struct rv_display_phy_info_entry entries[RAVEN_MAX_DISPLAYPHY_IDS]; struct smu10_display_phy_info_entry entries[SMU10_MAX_DISPLAYPHY_IDS];
}; };
#define MAX_DISPLAY_CLOCK_LEVEL 8 #define MAX_DISPLAY_CLOCK_LEVEL 8
struct rv_system_info{ struct smu10_system_info{
uint8_t htc_tmp_lmt; uint8_t htc_tmp_lmt;
uint8_t htc_hyst_lmt; uint8_t htc_hyst_lmt;
}; };
#define MAX_REGULAR_DPM_NUMBER 8 #define MAX_REGULAR_DPM_NUMBER 8
struct rv_mclk_latency_entries { struct smu10_mclk_latency_entries {
uint32_t frequency; uint32_t frequency;
uint32_t latency; uint32_t latency;
}; };
struct rv_mclk_latency_table { struct smu10_mclk_latency_table {
uint32_t count; uint32_t count;
struct rv_mclk_latency_entries entries[MAX_REGULAR_DPM_NUMBER]; struct smu10_mclk_latency_entries entries[MAX_REGULAR_DPM_NUMBER];
}; };
struct rv_clock_voltage_dependency_record { struct smu10_clock_voltage_dependency_record {
uint32_t clk; uint32_t clk;
uint32_t vol; uint32_t vol;
}; };
struct rv_voltage_dependency_table { struct smu10_voltage_dependency_table {
uint32_t count; uint32_t count;
struct rv_clock_voltage_dependency_record entries[1]; struct smu10_clock_voltage_dependency_record entries[1];
}; };
struct rv_clock_voltage_information { struct smu10_clock_voltage_information {
struct rv_voltage_dependency_table *vdd_dep_on_dcefclk; struct smu10_voltage_dependency_table *vdd_dep_on_dcefclk;
struct rv_voltage_dependency_table *vdd_dep_on_socclk; struct smu10_voltage_dependency_table *vdd_dep_on_socclk;
struct rv_voltage_dependency_table *vdd_dep_on_fclk; struct smu10_voltage_dependency_table *vdd_dep_on_fclk;
struct rv_voltage_dependency_table *vdd_dep_on_mclk; struct smu10_voltage_dependency_table *vdd_dep_on_mclk;
struct rv_voltage_dependency_table *vdd_dep_on_dispclk; struct smu10_voltage_dependency_table *vdd_dep_on_dispclk;
struct rv_voltage_dependency_table *vdd_dep_on_dppclk; struct smu10_voltage_dependency_table *vdd_dep_on_dppclk;
struct rv_voltage_dependency_table *vdd_dep_on_phyclk; struct smu10_voltage_dependency_table *vdd_dep_on_phyclk;
}; };
struct rv_hwmgr { struct smu10_hwmgr {
uint32_t disable_driver_thermal_policy; uint32_t disable_driver_thermal_policy;
uint32_t thermal_auto_throttling_treshold; uint32_t thermal_auto_throttling_treshold;
struct rv_system_info sys_info; struct smu10_system_info sys_info;
struct rv_mclk_latency_table mclk_latency_table; struct smu10_mclk_latency_table mclk_latency_table;
uint32_t ddi_power_gating_disabled; uint32_t ddi_power_gating_disabled;
struct rv_display_phy_info_entry display_phy_info; struct smu10_display_phy_info_entry display_phy_info;
uint32_t dce_slow_sclk_threshold; uint32_t dce_slow_sclk_threshold;
bool disp_clk_bypass; bool disp_clk_bypass;
...@@ -255,10 +255,10 @@ struct rv_hwmgr { ...@@ -255,10 +255,10 @@ struct rv_hwmgr {
uint32_t fps_low_threshold; uint32_t fps_low_threshold;
uint32_t dpm_flags; uint32_t dpm_flags;
struct rv_dpm_entry sclk_dpm; struct smu10_dpm_entry sclk_dpm;
struct rv_dpm_entry uvd_dpm; struct smu10_dpm_entry uvd_dpm;
struct rv_dpm_entry vce_dpm; struct smu10_dpm_entry vce_dpm;
struct rv_dpm_entry acp_dpm; struct smu10_dpm_entry acp_dpm;
bool acp_power_up_no_dsp; bool acp_power_up_no_dsp;
uint32_t max_sclk_level; uint32_t max_sclk_level;
...@@ -291,7 +291,7 @@ struct rv_hwmgr { ...@@ -291,7 +291,7 @@ struct rv_hwmgr {
bool gfx_off_controled_by_driver; bool gfx_off_controled_by_driver;
Watermarks_t water_marks_table; Watermarks_t water_marks_table;
struct rv_clock_voltage_information clock_vol_info; struct smu10_clock_voltage_information clock_vol_info;
DpmClocks_t clock_table; DpmClocks_t clock_table;
uint32_t active_process_mask; uint32_t active_process_mask;
...@@ -302,21 +302,21 @@ struct rv_hwmgr { ...@@ -302,21 +302,21 @@ struct rv_hwmgr {
struct pp_hwmgr; struct pp_hwmgr;
int rv_init_function_pointers(struct pp_hwmgr *hwmgr); int smu10_init_function_pointers(struct pp_hwmgr *hwmgr);
/* UMD PState Raven Msg Parameters in MHz */ /* UMD PState SMU10 Msg Parameters in MHz */
#define RAVEN_UMD_PSTATE_GFXCLK 700 #define SMU10_UMD_PSTATE_GFXCLK 700
#define RAVEN_UMD_PSTATE_SOCCLK 626 #define SMU10_UMD_PSTATE_SOCCLK 626
#define RAVEN_UMD_PSTATE_FCLK 933 #define SMU10_UMD_PSTATE_FCLK 933
#define RAVEN_UMD_PSTATE_VCE 0x03C00320 #define SMU10_UMD_PSTATE_VCE 0x03C00320
#define RAVEN_UMD_PSTATE_PEAK_GFXCLK 1100 #define SMU10_UMD_PSTATE_PEAK_GFXCLK 1100
#define RAVEN_UMD_PSTATE_PEAK_SOCCLK 757 #define SMU10_UMD_PSTATE_PEAK_SOCCLK 757
#define RAVEN_UMD_PSTATE_PEAK_FCLK 1200 #define SMU10_UMD_PSTATE_PEAK_FCLK 1200
#define RAVEN_UMD_PSTATE_MIN_GFXCLK 200 #define SMU10_UMD_PSTATE_MIN_GFXCLK 200
#define RAVEN_UMD_PSTATE_MIN_FCLK 400 #define SMU10_UMD_PSTATE_MIN_FCLK 400
#define RAVEN_UMD_PSTATE_MIN_SOCCLK 200 #define SMU10_UMD_PSTATE_MIN_SOCCLK 200
#define RAVEN_UMD_PSTATE_MIN_VCE 0x0190012C #define SMU10_UMD_PSTATE_MIN_VCE 0x0190012C
#endif #endif
drivers/gpu/drm/amd/powerplay/hwmgr/rv_inc.h → drivers/gpu/drm/amd/powerplay/hwmgr/smu10_inc.h
View file @ c4256885
...@@ -21,8 +21,8 @@ ...@@ -21,8 +21,8 @@
* *
*/ */
#ifndef RAVEN_INC_H #ifndef SMU10_INC_H
#define RAVEN_INC_H #define SMU10_INC_H
#include "asic_reg/mp/mp_10_0_default.h" #include "asic_reg/mp/mp_10_0_default.h"
......
drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
View file @ c4256885
...@@ -820,7 +820,7 @@ extern void phm_apply_dal_min_voltage_request(struct pp_hwmgr *hwmgr); ...@@ -820,7 +820,7 @@ extern void phm_apply_dal_min_voltage_request(struct pp_hwmgr *hwmgr);
extern int smu7_init_function_pointers(struct pp_hwmgr *hwmgr); extern int smu7_init_function_pointers(struct pp_hwmgr *hwmgr);
extern int vega10_hwmgr_init(struct pp_hwmgr *hwmgr); extern int vega10_hwmgr_init(struct pp_hwmgr *hwmgr);
extern int rv_init_function_pointers(struct pp_hwmgr *hwmgr); extern int smu10_init_function_pointers(struct pp_hwmgr *hwmgr);
extern int phm_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type, extern int phm_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
uint32_t sclk, uint16_t id, uint16_t *voltage); uint32_t sclk, uint16_t id, uint16_t *voltage);
......
drivers/gpu/drm/amd/powerplay/smumgr/Makefile
View file @ c4256885
...@@ -25,7 +25,7 @@ ...@@ -25,7 +25,7 @@
SMU_MGR = smumgr.o cz_smumgr.o tonga_smumgr.o fiji_smumgr.o \ SMU_MGR = smumgr.o cz_smumgr.o tonga_smumgr.o fiji_smumgr.o \
polaris10_smumgr.o iceland_smumgr.o \ polaris10_smumgr.o iceland_smumgr.o \
smu7_smumgr.o vega10_smumgr.o rv_smumgr.o ci_smumgr.o smu7_smumgr.o vega10_smumgr.o smu10_smumgr.o ci_smumgr.o
AMD_PP_SMUMGR = $(addprefix $(AMD_PP_PATH)/smumgr/,$(SMU_MGR)) AMD_PP_SMUMGR = $(addprefix $(AMD_PP_PATH)/smumgr/,$(SMU_MGR))
......
drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c → drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c
View file @ c4256885
...@@ -22,9 +22,9 @@ ...@@ -22,9 +22,9 @@
*/ */
#include "smumgr.h" #include "smumgr.h"
#include "rv_inc.h" #include "smu10_inc.h"
#include "pp_soc15.h" #include "pp_soc15.h"
#include "rv_smumgr.h" #include "smu10_smumgr.h"
#include "ppatomctrl.h" #include "ppatomctrl.h"
#include "rv_ppsmc.h" #include "rv_ppsmc.h"
#include "smu10_driver_if.h" #include "smu10_driver_if.h"
...@@ -47,7 +47,7 @@ ...@@ -47,7 +47,7 @@
#define smnMP1_FIRMWARE_FLAGS 0x3010028 #define smnMP1_FIRMWARE_FLAGS 0x3010028
static uint32_t rv_wait_for_response(struct pp_hwmgr *hwmgr) static uint32_t smu10_wait_for_response(struct pp_hwmgr *hwmgr)
{ {
uint32_t reg; uint32_t reg;
...@@ -60,7 +60,7 @@ static uint32_t rv_wait_for_response(struct pp_hwmgr *hwmgr) ...@@ -60,7 +60,7 @@ static uint32_t rv_wait_for_response(struct pp_hwmgr *hwmgr)
return cgs_read_register(hwmgr->device, reg); return cgs_read_register(hwmgr->device, reg);
} }
static int rv_send_msg_to_smc_without_waiting(struct pp_hwmgr *hwmgr, static int smu10_send_msg_to_smc_without_waiting(struct pp_hwmgr *hwmgr,
uint16_t msg) uint16_t msg)
{ {
uint32_t reg; uint32_t reg;
...@@ -72,7 +72,7 @@ static int rv_send_msg_to_smc_without_waiting(struct pp_hwmgr *hwmgr, ...@@ -72,7 +72,7 @@ static int rv_send_msg_to_smc_without_waiting(struct pp_hwmgr *hwmgr,
return 0; return 0;
} }
static int rv_read_arg_from_smc(struct pp_hwmgr *hwmgr) static int smu10_read_arg_from_smc(struct pp_hwmgr *hwmgr)
{ {
uint32_t reg; uint32_t reg;
...@@ -82,31 +82,31 @@ static int rv_read_arg_from_smc(struct pp_hwmgr *hwmgr) ...@@ -82,31 +82,31 @@ static int rv_read_arg_from_smc(struct pp_hwmgr *hwmgr)
return cgs_read_register(hwmgr->device, reg); return cgs_read_register(hwmgr->device, reg);
} }
static int rv_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg) static int smu10_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg)
{ {
uint32_t reg; uint32_t reg;
rv_wait_for_response(hwmgr); smu10_wait_for_response(hwmgr);
reg = soc15_get_register_offset(MP1_HWID, 0, reg = soc15_get_register_offset(MP1_HWID, 0,
mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90); mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90);
cgs_write_register(hwmgr->device, reg, 0); cgs_write_register(hwmgr->device, reg, 0);
rv_send_msg_to_smc_without_waiting(hwmgr, msg); smu10_send_msg_to_smc_without_waiting(hwmgr, msg);
if (rv_wait_for_response(hwmgr) == 0) if (smu10_wait_for_response(hwmgr) == 0)
printk("Failed to send Message %x.\n", msg); printk("Failed to send Message %x.\n", msg);
return 0; return 0;
} }
static int rv_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr, static int smu10_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr,
uint16_t msg, uint32_t parameter) uint16_t msg, uint32_t parameter)
{ {
uint32_t reg; uint32_t reg;
rv_wait_for_response(hwmgr); smu10_wait_for_response(hwmgr);
reg = soc15_get_register_offset(MP1_HWID, 0, reg = soc15_get_register_offset(MP1_HWID, 0,
mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90); mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90);
...@@ -116,20 +116,20 @@ static int rv_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr, ...@@ -116,20 +116,20 @@ static int rv_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr,
mmMP1_SMN_C2PMSG_82_BASE_IDX, mmMP1_SMN_C2PMSG_82); mmMP1_SMN_C2PMSG_82_BASE_IDX, mmMP1_SMN_C2PMSG_82);
cgs_write_register(hwmgr->device, reg, parameter); cgs_write_register(hwmgr->device, reg, parameter);
rv_send_msg_to_smc_without_waiting(hwmgr, msg); smu10_send_msg_to_smc_without_waiting(hwmgr, msg);
if (rv_wait_for_response(hwmgr) == 0) if (smu10_wait_for_response(hwmgr) == 0)
printk("Failed to send Message %x.\n", msg); printk("Failed to send Message %x.\n", msg);
return 0; return 0;
} }
static int rv_copy_table_from_smc(struct pp_hwmgr *hwmgr, static int smu10_copy_table_from_smc(struct pp_hwmgr *hwmgr,
uint8_t *table, int16_t table_id) uint8_t *table, int16_t table_id)
{ {
struct rv_smumgr *priv = struct smu10_smumgr *priv =
(struct rv_smumgr *)(hwmgr->smu_backend); (struct smu10_smumgr *)(hwmgr->smu_backend);
PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE, PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE,
"Invalid SMU Table ID!", return -EINVAL;); "Invalid SMU Table ID!", return -EINVAL;);
...@@ -137,13 +137,13 @@ static int rv_copy_table_from_smc(struct pp_hwmgr *hwmgr, ...@@ -137,13 +137,13 @@ static int rv_copy_table_from_smc(struct pp_hwmgr *hwmgr,
"Invalid SMU Table version!", return -EINVAL;); "Invalid SMU Table version!", return -EINVAL;);
PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0, PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0,
"Invalid SMU Table Length!", return -EINVAL;); "Invalid SMU Table Length!", return -EINVAL;);
rv_send_msg_to_smc_with_parameter(hwmgr, smu10_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh,
upper_32_bits(priv->smu_tables.entry[table_id].mc_addr)); upper_32_bits(priv->smu_tables.entry[table_id].mc_addr));
rv_send_msg_to_smc_with_parameter(hwmgr, smu10_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow,
lower_32_bits(priv->smu_tables.entry[table_id].mc_addr)); lower_32_bits(priv->smu_tables.entry[table_id].mc_addr));
rv_send_msg_to_smc_with_parameter(hwmgr, smu10_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram,
priv->smu_tables.entry[table_id].table_id); priv->smu_tables.entry[table_id].table_id);
...@@ -153,11 +153,11 @@ static int rv_copy_table_from_smc(struct pp_hwmgr *hwmgr, ...@@ -153,11 +153,11 @@ static int rv_copy_table_from_smc(struct pp_hwmgr *hwmgr,
return 0; return 0;
} }
static int rv_copy_table_to_smc(struct pp_hwmgr *hwmgr, static int smu10_copy_table_to_smc(struct pp_hwmgr *hwmgr,
uint8_t *table, int16_t table_id) uint8_t *table, int16_t table_id)
{ {
struct rv_smumgr *priv = struct smu10_smumgr *priv =
(struct rv_smumgr *)(hwmgr->smu_backend); (struct smu10_smumgr *)(hwmgr->smu_backend);
PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE, PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE,
"Invalid SMU Table ID!", return -EINVAL;); "Invalid SMU Table ID!", return -EINVAL;);
...@@ -169,26 +169,26 @@ static int rv_copy_table_to_smc(struct pp_hwmgr *hwmgr, ...@@ -169,26 +169,26 @@ static int rv_copy_table_to_smc(struct pp_hwmgr *hwmgr,
memcpy(priv->smu_tables.entry[table_id].table, table, memcpy(priv->smu_tables.entry[table_id].table, table,
priv->smu_tables.entry[table_id].size); priv->smu_tables.entry[table_id].size);
rv_send_msg_to_smc_with_parameter(hwmgr, smu10_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh,
upper_32_bits(priv->smu_tables.entry[table_id].mc_addr)); upper_32_bits(priv->smu_tables.entry[table_id].mc_addr));
rv_send_msg_to_smc_with_parameter(hwmgr, smu10_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow,
lower_32_bits(priv->smu_tables.entry[table_id].mc_addr)); lower_32_bits(priv->smu_tables.entry[table_id].mc_addr));
rv_send_msg_to_smc_with_parameter(hwmgr, smu10_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu,
priv->smu_tables.entry[table_id].table_id); priv->smu_tables.entry[table_id].table_id);
return 0; return 0;
} }
static int rv_verify_smc_interface(struct pp_hwmgr *hwmgr) static int smu10_verify_smc_interface(struct pp_hwmgr *hwmgr)
{ {
uint32_t smc_driver_if_version; uint32_t smc_driver_if_version;
rv_send_msg_to_smc(hwmgr, smu10_send_msg_to_smc(hwmgr,
PPSMC_MSG_GetDriverIfVersion); PPSMC_MSG_GetDriverIfVersion);
smc_driver_if_version = rv_read_arg_from_smc(hwmgr); smc_driver_if_version = smu10_read_arg_from_smc(hwmgr);
if (smc_driver_if_version != SMU10_DRIVER_IF_VERSION) { if (smc_driver_if_version != SMU10_DRIVER_IF_VERSION) {
pr_err("Attempt to read SMC IF Version Number Failed!\n"); pr_err("Attempt to read SMC IF Version Number Failed!\n");
...@@ -199,39 +199,39 @@ static int rv_verify_smc_interface(struct pp_hwmgr *hwmgr) ...@@ -199,39 +199,39 @@ static int rv_verify_smc_interface(struct pp_hwmgr *hwmgr)
} }
/* sdma is disabled by default in vbios, need to re-enable in driver */ /* sdma is disabled by default in vbios, need to re-enable in driver */
static void rv_smc_enable_sdma(struct pp_hwmgr *hwmgr) static void smu10_smc_enable_sdma(struct pp_hwmgr *hwmgr)
{ {
rv_send_msg_to_smc(hwmgr, smu10_send_msg_to_smc(hwmgr,
PPSMC_MSG_PowerUpSdma); PPSMC_MSG_PowerUpSdma);
} }
static void rv_smc_disable_sdma(struct pp_hwmgr *hwmgr) static void smu10_smc_disable_sdma(struct pp_hwmgr *hwmgr)
{ {
rv_send_msg_to_smc(hwmgr, smu10_send_msg_to_smc(hwmgr,
PPSMC_MSG_PowerDownSdma); PPSMC_MSG_PowerDownSdma);
} }
/* vcn is disabled by default in vbios, need to re-enable in driver */ /* vcn is disabled by default in vbios, need to re-enable in driver */
static void rv_smc_enable_vcn(struct pp_hwmgr *hwmgr) static void smu10_smc_enable_vcn(struct pp_hwmgr *hwmgr)
{ {
rv_send_msg_to_smc_with_parameter(hwmgr, smu10_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_PowerUpVcn, 0); PPSMC_MSG_PowerUpVcn, 0);
} }
static void rv_smc_disable_vcn(struct pp_hwmgr *hwmgr) static void smu10_smc_disable_vcn(struct pp_hwmgr *hwmgr)
{ {
rv_send_msg_to_smc_with_parameter(hwmgr, smu10_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_PowerDownVcn, 0); PPSMC_MSG_PowerDownVcn, 0);
} }
static int rv_smu_fini(struct pp_hwmgr *hwmgr) static int smu10_smu_fini(struct pp_hwmgr *hwmgr)
{ {
struct rv_smumgr *priv = struct smu10_smumgr *priv =
(struct rv_smumgr *)(hwmgr->smu_backend); (struct smu10_smumgr *)(hwmgr->smu_backend);
if (priv) { if (priv) {
rv_smc_disable_sdma(hwmgr); smu10_smc_disable_sdma(hwmgr);
rv_smc_disable_vcn(hwmgr); smu10_smc_disable_vcn(hwmgr);
amdgpu_bo_free_kernel(&priv->smu_tables.entry[SMU10_WMTABLE].handle, amdgpu_bo_free_kernel(&priv->smu_tables.entry[SMU10_WMTABLE].handle,
&priv->smu_tables.entry[SMU10_WMTABLE].mc_addr, &priv->smu_tables.entry[SMU10_WMTABLE].mc_addr,
&priv->smu_tables.entry[SMU10_WMTABLE].table); &priv->smu_tables.entry[SMU10_WMTABLE].table);
...@@ -245,29 +245,29 @@ static int rv_smu_fini(struct pp_hwmgr *hwmgr) ...@@ -245,29 +245,29 @@ static int rv_smu_fini(struct pp_hwmgr *hwmgr)
return 0; return 0;
} }
static int rv_start_smu(struct pp_hwmgr *hwmgr) static int smu10_start_smu(struct pp_hwmgr *hwmgr)
{ {
struct cgs_firmware_info info = {0}; struct cgs_firmware_info info = {0};
smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetSmuVersion); smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetSmuVersion);
hwmgr->smu_version = rv_read_arg_from_smc(hwmgr); hwmgr->smu_version = smu10_read_arg_from_smc(hwmgr);
info.version = hwmgr->smu_version >> 8; info.version = hwmgr->smu_version >> 8;
cgs_get_firmware_info(hwmgr->device, CGS_UCODE_ID_SMU, &info); cgs_get_firmware_info(hwmgr->device, CGS_UCODE_ID_SMU, &info);
if (rv_verify_smc_interface(hwmgr)) if (smu10_verify_smc_interface(hwmgr))
return -EINVAL; return -EINVAL;
rv_smc_enable_sdma(hwmgr); smu10_smc_enable_sdma(hwmgr);
rv_smc_enable_vcn(hwmgr); smu10_smc_enable_vcn(hwmgr);
return 0; return 0;
} }
static int rv_smu_init(struct pp_hwmgr *hwmgr) static int smu10_smu_init(struct pp_hwmgr *hwmgr)
{ {
struct rv_smumgr *priv; struct smu10_smumgr *priv;
int r; int r;
priv = kzalloc(sizeof(struct rv_smumgr), GFP_KERNEL); priv = kzalloc(sizeof(struct smu10_smumgr), GFP_KERNEL);
if (!priv) if (!priv)
return -ENOMEM; return -ENOMEM;
...@@ -317,30 +317,30 @@ static int rv_smu_init(struct pp_hwmgr *hwmgr) ...@@ -317,30 +317,30 @@ static int rv_smu_init(struct pp_hwmgr *hwmgr)
return -EINVAL; return -EINVAL;
} }
static int rv_smc_table_manager(struct pp_hwmgr *hwmgr, uint8_t *table, uint16_t table_id, bool rw) static int smu10_smc_table_manager(struct pp_hwmgr *hwmgr, uint8_t *table, uint16_t table_id, bool rw)
{ {
int ret; int ret;
if (rw) if (rw)
ret = rv_copy_table_from_smc(hwmgr, table, table_id); ret = smu10_copy_table_from_smc(hwmgr, table, table_id);
else else
ret = rv_copy_table_to_smc(hwmgr, table, table_id); ret = smu10_copy_table_to_smc(hwmgr, table, table_id);
return ret; return ret;
} }
const struct pp_smumgr_func rv_smu_funcs = { const struct pp_smumgr_func smu10_smu_funcs = {
.smu_init = &rv_smu_init, .smu_init = &smu10_smu_init,
.smu_fini = &rv_smu_fini, .smu_fini = &smu10_smu_fini,
.start_smu = &rv_start_smu, .start_smu = &smu10_start_smu,
.request_smu_load_specific_fw = NULL, .request_smu_load_specific_fw = NULL,
.send_msg_to_smc = &rv_send_msg_to_smc, .send_msg_to_smc = &smu10_send_msg_to_smc,
.send_msg_to_smc_with_parameter = &rv_send_msg_to_smc_with_parameter, .send_msg_to_smc_with_parameter = &smu10_send_msg_to_smc_with_parameter,
.download_pptable_settings = NULL, .download_pptable_settings = NULL,
.upload_pptable_settings = NULL, .upload_pptable_settings = NULL,
.get_argument = rv_read_arg_from_smc, .get_argument = smu10_read_arg_from_smc,
.smc_table_manager = rv_smc_table_manager, .smc_table_manager = smu10_smc_table_manager,
}; };
drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.h → drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.h
View file @ c4256885
...@@ -21,8 +21,8 @@ ...@@ -21,8 +21,8 @@
* *
*/ */
#ifndef PP_RAVEN_SMUMANAGER_H #ifndef PP_SMU10_SMUMANAGER_H
#define PP_RAVEN_SMUMANAGER_H #define PP_SMU10_SMUMANAGER_H
#include "rv_ppsmc.h" #include "rv_ppsmc.h"
#include "smu10_driver_if.h" #include "smu10_driver_if.h"
...@@ -42,7 +42,7 @@ struct smu_table_array { ...@@ -42,7 +42,7 @@ struct smu_table_array {
struct smu_table_entry entry[MAX_SMU_TABLE]; struct smu_table_entry entry[MAX_SMU_TABLE];
}; };
struct rv_smumgr { struct smu10_smumgr {
struct smu_table_array smu_tables; struct smu_table_array smu_tables;
}; };
......
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