drm/i915: Settle on "adl-x" in WA comments

Most of the places are using this format so lets consolidate it.

v2:
- split patch in two: display and non-display because of conflicts
between drm-intel-gt-next x drm-intel-next
Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Signed-off-by: default avatarJosé Roberto de Souza <jose.souza@intel.com>
Signed-off-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210713003854.143197-2-jose.souza@intel.com
parent 78d2ad7e
...@@ -1078,7 +1078,7 @@ gen12_gt_workarounds_init(struct drm_i915_private *i915, ...@@ -1078,7 +1078,7 @@ gen12_gt_workarounds_init(struct drm_i915_private *i915,
{ {
icl_wa_init_mcr(i915, wal); icl_wa_init_mcr(i915, wal);
/* Wa_14011060649:tgl,rkl,dg1,adls,adl-p */ /* Wa_14011060649:tgl,rkl,dg1,adl-s,adl-p */
wa_14011060649(i915, wal); wa_14011060649(i915, wal);
} }
......
...@@ -7351,7 +7351,7 @@ static void icl_init_clock_gating(struct drm_i915_private *dev_priv) ...@@ -7351,7 +7351,7 @@ static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
static void gen12lp_init_clock_gating(struct drm_i915_private *dev_priv) static void gen12lp_init_clock_gating(struct drm_i915_private *dev_priv)
{ {
/* Wa_1409120013:tgl,rkl,adl_s,dg1 */ /* Wa_1409120013:tgl,rkl,adl-s,dg1 */
if (IS_TIGERLAKE(dev_priv) || IS_ROCKETLAKE(dev_priv) || if (IS_TIGERLAKE(dev_priv) || IS_ROCKETLAKE(dev_priv) ||
IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv)) IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv))
intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN,
...@@ -7362,7 +7362,7 @@ static void gen12lp_init_clock_gating(struct drm_i915_private *dev_priv) ...@@ -7362,7 +7362,7 @@ static void gen12lp_init_clock_gating(struct drm_i915_private *dev_priv)
intel_uncore_write(&dev_priv->uncore, GEN9_CLKGATE_DIS_3, intel_uncore_read(&dev_priv->uncore, GEN9_CLKGATE_DIS_3) | intel_uncore_write(&dev_priv->uncore, GEN9_CLKGATE_DIS_3, intel_uncore_read(&dev_priv->uncore, GEN9_CLKGATE_DIS_3) |
TGL_VRH_GATING_DIS); TGL_VRH_GATING_DIS);
/* Wa_14011059788:tgl,rkl,adl_s,dg1,adl-p */ /* Wa_14011059788:tgl,rkl,adl-s,dg1,adl-p */
intel_uncore_rmw(&dev_priv->uncore, GEN10_DFR_RATIO_EN_AND_CHICKEN, intel_uncore_rmw(&dev_priv->uncore, GEN10_DFR_RATIO_EN_AND_CHICKEN,
0, DFR_DISABLE); 0, DFR_DISABLE);
......
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