Commit c52e167b authored by Thierry Reding's avatar Thierry Reding

drm/tegra: Use proper IOVA address for cursor image

The IOVA address for the cursor is the result of mapping the buffer
object for the given display controller. Make sure to use the proper
IOVA address as stored in the cursor's plane state.
Reviewed-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 49f82191
...@@ -837,16 +837,15 @@ static int tegra_cursor_atomic_check(struct drm_plane *plane, ...@@ -837,16 +837,15 @@ static int tegra_cursor_atomic_check(struct drm_plane *plane,
static void tegra_cursor_atomic_update(struct drm_plane *plane, static void tegra_cursor_atomic_update(struct drm_plane *plane,
struct drm_plane_state *old_state) struct drm_plane_state *old_state)
{ {
struct tegra_bo *bo = tegra_fb_get_plane(plane->state->fb, 0); struct tegra_plane_state *state = to_tegra_plane_state(plane->state);
struct tegra_dc *dc = to_tegra_dc(plane->state->crtc); struct tegra_dc *dc = to_tegra_dc(plane->state->crtc);
struct drm_plane_state *state = plane->state;
u32 value = CURSOR_CLIP_DISPLAY; u32 value = CURSOR_CLIP_DISPLAY;
/* rien ne va plus */ /* rien ne va plus */
if (!plane->state->crtc || !plane->state->fb) if (!plane->state->crtc || !plane->state->fb)
return; return;
switch (state->crtc_w) { switch (plane->state->crtc_w) {
case 32: case 32:
value |= CURSOR_SIZE_32x32; value |= CURSOR_SIZE_32x32;
break; break;
...@@ -864,16 +863,16 @@ static void tegra_cursor_atomic_update(struct drm_plane *plane, ...@@ -864,16 +863,16 @@ static void tegra_cursor_atomic_update(struct drm_plane *plane,
break; break;
default: default:
WARN(1, "cursor size %ux%u not supported\n", state->crtc_w, WARN(1, "cursor size %ux%u not supported\n",
state->crtc_h); plane->state->crtc_w, plane->state->crtc_h);
return; return;
} }
value |= (bo->iova >> 10) & 0x3fffff; value |= (state->iova[0] >> 10) & 0x3fffff;
tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR); tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR);
#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
value = (bo->iova >> 32) & 0x3; value = (state->iova[0] >> 32) & 0x3;
tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI); tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI);
#endif #endif
...@@ -892,7 +891,8 @@ static void tegra_cursor_atomic_update(struct drm_plane *plane, ...@@ -892,7 +891,8 @@ static void tegra_cursor_atomic_update(struct drm_plane *plane,
tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL); tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL);
/* position the cursor */ /* position the cursor */
value = (state->crtc_y & 0x3fff) << 16 | (state->crtc_x & 0x3fff); value = (plane->state->crtc_y & 0x3fff) << 16 |
(plane->state->crtc_x & 0x3fff);
tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION); tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION);
} }
......
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