Commit c5d67a0e authored by Lang Yu's avatar Lang Yu Committed by Alex Deucher

drm/amdgpu: add PSP loading support for VPE

Add PSP loading support for Video Processing Engine.
Signed-off-by: default avatarLang Yu <Lang.Yu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 9d4346bd
...@@ -749,6 +749,7 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev, ...@@ -749,6 +749,7 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev,
const struct mes_firmware_header_v1_0 *mes_hdr = NULL; const struct mes_firmware_header_v1_0 *mes_hdr = NULL;
const struct sdma_firmware_header_v2_0 *sdma_hdr = NULL; const struct sdma_firmware_header_v2_0 *sdma_hdr = NULL;
const struct imu_firmware_header_v1_0 *imu_hdr = NULL; const struct imu_firmware_header_v1_0 *imu_hdr = NULL;
const struct vpe_firmware_header_v1_0 *vpe_hdr = NULL;
u8 *ucode_addr; u8 *ucode_addr;
if (!ucode->fw) if (!ucode->fw)
...@@ -768,6 +769,7 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev, ...@@ -768,6 +769,7 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev,
mes_hdr = (const struct mes_firmware_header_v1_0 *)ucode->fw->data; mes_hdr = (const struct mes_firmware_header_v1_0 *)ucode->fw->data;
sdma_hdr = (const struct sdma_firmware_header_v2_0 *)ucode->fw->data; sdma_hdr = (const struct sdma_firmware_header_v2_0 *)ucode->fw->data;
imu_hdr = (const struct imu_firmware_header_v1_0 *)ucode->fw->data; imu_hdr = (const struct imu_firmware_header_v1_0 *)ucode->fw->data;
vpe_hdr = (const struct vpe_firmware_header_v1_0 *)ucode->fw->data;
if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
switch (ucode->ucode_id) { switch (ucode->ucode_id) {
...@@ -950,6 +952,16 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev, ...@@ -950,6 +952,16 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev,
ucode_addr = (u8 *)ucode->fw->data + ucode_addr = (u8 *)ucode->fw->data +
le32_to_cpu(cpv2_hdr->data_offset_bytes); le32_to_cpu(cpv2_hdr->data_offset_bytes);
break; break;
case AMDGPU_UCODE_ID_VPE_CTX:
ucode->ucode_size = le32_to_cpu(vpe_hdr->ctx_ucode_size_bytes);
ucode_addr = (u8 *)ucode->fw->data +
le32_to_cpu(vpe_hdr->header.ucode_array_offset_bytes);
break;
case AMDGPU_UCODE_ID_VPE_CTL:
ucode->ucode_size = le32_to_cpu(vpe_hdr->ctl_ucode_size_bytes);
ucode_addr = (u8 *)ucode->fw->data +
le32_to_cpu(vpe_hdr->ctl_ucode_offset);
break;
default: default:
ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes); ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes);
ucode_addr = (u8 *)ucode->fw->data + ucode_addr = (u8 *)ucode->fw->data +
......
...@@ -56,6 +56,22 @@ int amdgpu_vpe_init_microcode(struct amdgpu_vpe *vpe) ...@@ -56,6 +56,22 @@ int amdgpu_vpe_init_microcode(struct amdgpu_vpe *vpe)
adev->vpe.fw_version = le32_to_cpu(vpe_hdr->header.ucode_version); adev->vpe.fw_version = le32_to_cpu(vpe_hdr->header.ucode_version);
adev->vpe.feature_version = le32_to_cpu(vpe_hdr->ucode_feature_version); adev->vpe.feature_version = le32_to_cpu(vpe_hdr->ucode_feature_version);
if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
struct amdgpu_firmware_info *info;
info = &adev->firmware.ucode[AMDGPU_UCODE_ID_VPE_CTX];
info->ucode_id = AMDGPU_UCODE_ID_VPE_CTX;
info->fw = adev->vpe.fw;
adev->firmware.fw_size +=
ALIGN(le32_to_cpu(vpe_hdr->ctx_ucode_size_bytes), PAGE_SIZE);
info = &adev->firmware.ucode[AMDGPU_UCODE_ID_VPE_CTL];
info->ucode_id = AMDGPU_UCODE_ID_VPE_CTL;
info->fw = adev->vpe.fw;
adev->firmware.fw_size +=
ALIGN(le32_to_cpu(vpe_hdr->ctl_ucode_size_bytes), PAGE_SIZE);
}
return 0; return 0;
out: out:
dev_err(adev->dev, "fail to initialize vpe microcode\n"); dev_err(adev->dev, "fail to initialize vpe microcode\n");
......
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