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Commit c6e2e454 authored by Arnd Bergmann's avatar Arnd Bergmann
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Merge tag 'qcom-arm64-for-5.9' of... 

Merge tag 'qcom-arm64-for-5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/dt

Qualcomm ARM64 DT updates for v5.9

For SM8250 this adds the main pinctrl/gpio block (TLMM), I2C and SPI
controllers, the CPU subsytem watchdog, inter-processor signalling
controller (IPCC), always-on power/clock controller (AOSS),
inter-processor state machine (SMP2P), defines remoteproc controls
for audio, compute and sensor processors and base definition for the
PM8009 PMIC. It also does fix up a few minor issues from the initial
merge of the platform support.

SC7180 and SDM845 gains interconnect paths and performance tables
defined for display, QUP, QSPI, SDHC and CPUs.

SC7180 gains WiFi support and some cleanups related to the modem
remoteproc.

SDM845 gains inline crypto engine support for UFS, LAB/IBB
regulators for powering display panels, remoteproc relocation debug
support

SM8150 gains USB controller support and the two related PHYs, as well as
thermal zones and throttling support.

IPQ8074 gains USB and SDHCI support.

MSM8916 is being cleaned up, gains interconnect providers and Samsung
A2015 gains accelerometer and magnetometer support.

MSM8994 gains PSCI, SDHCI, SPMI support, I2C, SPI, UART gains DMA
support and the DTS files are cleaned up.

The SDM630 platform DTS is at last merged and initial support for Sony
Xperia 10, 10 Plus, XA2, XA2 Plus and XA2 Ultra is added.

* tag 'qcom-arm64-for-5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (66 commits)
  arm64: dts: qcom: pmi8998: Add nodes for LAB and IBB regulators
  arm64: dts: sc7180: Add DSI and MDP OPP tables and power-domains
  arm64: dts: sdm845: Add DSI and MDP OPP tables and power-domains
  arm64: dts: qcom: sc7180: Move the fixed-perm property to SoC dtsi
  arm64: dts: qcom: msm8916-samsung-a2015: Add accelerometer/magnetometer
  arm64: dts: qcom: msm8916: Use higher I2C drive-strength only on DB410c
  arm64: dts: qcom: msm8916: Simplify pinctrl configuration
  arm64: dts: msm8916-samsung/longcheer: Move pinctrl/regulators to end of file
  arm64: dts: qcom: sm8250: Drop tcsr_mutex syscon
  arm64: dts: qcom: sc7180: Add missing properties for Wifi node
  arm64: dts: qcom: Fix WiFi supplies on sc7180-idp
  arm64: dts: sdm845: add Inline Crypto Engine registers and clock
  arm64: dts: sc7180: Add sdhc opps and power-domains
  arm64: dts: sdm845: Add sdhc opps and power-domains
  arm64: dts: sc7180: Add OPP table for all qup devices
  arm64: dts: sdm845: Add OPP table for all qup devices
  arm64: dts: sc7180: Add qspi opps and power-domains
  arm64: dts: sdm845: Add qspi opps and power-domains
  arm64: dts: qcom: sdm845: Add cpu OPP tables
  arm64: dts: qcom: sc7180: Drop the unused non-MSA SID
  ...

Link: https://lore.kernel.org/r/20200721044934.3430084-1-bjorn.andersson@linaro.orgSigned-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 01407153 208921ba
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Documentation/devicetree/bindings/thermal/qcom-tsens.yaml
View file @ c6e2e454
......@@ -40,6 +40,8 @@ properties:
- qcom,msm8998-tsens
- qcom,sc7180-tsens
- qcom,sdm845-tsens
- qcom,sm8150-tsens
- qcom,sm8250-tsens
- const: qcom,tsens-v2
reg:
......
arch/arm64/boot/dts/qcom/Makefile
View file @ c6e2e454
......@@ -16,6 +16,11 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8998-hp-envy-x2.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8998-lenovo-miix-630.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8998-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-idp.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-ganges-kirin.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-discovery.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-pioneer.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-voyager.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm636-sony-xperia-ganges-mermaid.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm660-xiaomi-lavender.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r1.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r2.dtb
......
arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
View file @ c6e2e454
......@@ -466,9 +466,10 @@ sound: sound {
qcom,audio-routing =
"AMIC2", "MIC BIAS Internal2",
"AMIC3", "MIC BIAS External1";
external-dai-link@0 {
link-name = "ADV7533";
cpu { /* QUAT */
cpu {
sound-dai = <&lpass MI2S_QUATERNARY>;
};
codec {
......@@ -476,9 +477,9 @@ codec {
};
};
internal-codec-playback-dai-link@0 { /* I2S - Internal codec */
internal-codec-playback-dai-link@0 {
link-name = "WCD";
cpu { /* PRIMARY */
cpu {
sound-dai = <&lpass MI2S_PRIMARY>;
};
codec {
......@@ -486,9 +487,9 @@ codec {
};
};
internal-codec-capture-dai-link@0 { /* I2S - Internal codec */
internal-codec-capture-dai-link@0 {
link-name = "WCD-Capture";
cpu { /* PRIMARY */
cpu {
sound-dai = <&lpass MI2S_TERTIARY>;
};
codec {
......@@ -778,136 +779,121 @@ l18 {
};
};
/*
* 2mA drive strength is not enough when connecting multiple
* I2C devices with different pull up resistors.
*/
&i2c2_default {
drive-strength = <16>;
};
&i2c4_default {
drive-strength = <16>;
};
&i2c6_default {
drive-strength = <16>;
};
&msmgpio {
msmgpio_leds: msmgpio-leds {
pinconf {
pins = "gpio21", "gpio120";
function = "gpio";
output-low;
};
};
usb_id_default: usb-id-default {
pinmux {
function = "gpio";
pins = "gpio121";
};
function = "gpio";
pinconf {
pins = "gpio121";
drive-strength = <8>;
input-enable;
bias-pull-up;
};
};
adv7533_int_active: adv533-int-active {
pinmux {
function = "gpio";
pins = "gpio31";
};
pinconf {
pins = "gpio31";
function = "gpio";
drive-strength = <16>;
bias-disable;
};
};
adv7533_int_suspend: adv7533-int-suspend {
pinmux {
function = "gpio";
pins = "gpio31";
};
pinconf {
pins = "gpio31";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
};
adv7533_switch_active: adv7533-switch-active {
pinmux {
function = "gpio";
pins = "gpio32";
};
pinconf {
pins = "gpio32";
function = "gpio";
drive-strength = <16>;
bias-disable;
};
};
adv7533_switch_suspend: adv7533-switch-suspend {
pinmux {
function = "gpio";
pins = "gpio32";
};
pinconf {
pins = "gpio32";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
};
msm_key_volp_n_default: msm-key-volp-n-default {
pinmux {
function = "gpio";
pins = "gpio107";
};
pinconf {
pins = "gpio107";
function = "gpio";
drive-strength = <8>;
input-enable;
bias-pull-up;
};
};
};
&pm8916_gpios {
usb_hub_reset_pm: usb-hub-reset-pm {
pinconf {
pins = "gpio3";
function = PMIC_GPIO_FUNC_NORMAL;
input-disable;
output-high;
};
};
usb_hub_reset_pm_device: usb-hub-reset-pm-device {
pinconf {
pins = "gpio3";
function = PMIC_GPIO_FUNC_NORMAL;
output-low;
};
};
usb_sw_sel_pm: usb-sw-sel-pm {
pinconf {
pins = "gpio4";
function = PMIC_GPIO_FUNC_NORMAL;
power-source = <PM8916_GPIO_VPH>;
input-disable;
output-high;
};
};
usb_sw_sel_pm_device: usb-sw-sel-pm-device {
pinconf {
pins = "gpio4";
function = PMIC_GPIO_FUNC_NORMAL;
power-source = <PM8916_GPIO_VPH>;
input-disable;
output-low;
};
};
pm8916_gpios_leds: pm8916-gpios-leds {
pinconf {
pins = "gpio1", "gpio2";
function = PMIC_GPIO_FUNC_NORMAL;
output-low;
};
};
};
&pm8916_mpps {
......@@ -915,19 +901,17 @@ &pm8916_mpps {
pinctrl-0 = <&ls_exp_gpio_f>;
ls_exp_gpio_f: pm8916-mpp4 {
pinconf {
pins = "mpp4";
function = "digital";
output-low;
power-source = <PM8916_MPP_L5>; // 1.8V
};
};
pm8916_mpps_leds: pm8916-mpps-leds {
pinconf {
pins = "mpp2", "mpp3";
function = "digital";
output-low;
};
};
};
arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
View file @ c6e2e454
......@@ -82,3 +82,31 @@ nand@0 {
nand-bus-width = <8>;
};
};
&sdhc_1 {
status = "ok";
};
&qusb_phy_0 {
status = "ok";
};
&qusb_phy_1 {
status = "ok";
};
&ssphy_0 {
status = "ok";
};
&ssphy_1 {
status = "ok";
};
&usb_0 {
status = "ok";
};
&usb_1 {
status = "ok";
};
arch/arm64/boot/dts/qcom/ipq8074.dtsi
View file @ c6e2e454
......@@ -82,6 +82,91 @@ soc: soc {
ranges = <0 0 0 0xffffffff>;
compatible = "simple-bus";
ssphy_1: phy@58000 {
compatible = "qcom,ipq8074-qmp-usb3-phy";
reg = <0x00058000 0x1c4>;
#clock-cells = <1>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
clocks = <&gcc GCC_USB1_AUX_CLK>,
<&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
<&xo>;
clock-names = "aux", "cfg_ahb", "ref";
resets = <&gcc GCC_USB1_PHY_BCR>,
<&gcc GCC_USB3PHY_1_PHY_BCR>;
reset-names = "phy","common";
status = "disabled";
usb1_ssphy: lane@58200 {
reg = <0x00058200 0x130>, /* Tx */
<0x00058400 0x200>, /* Rx */
<0x00058800 0x1f8>, /* PCS */
<0x00058600 0x044>; /* PCS misc*/
#phy-cells = <0>;
clocks = <&gcc GCC_USB1_PIPE_CLK>;
clock-names = "pipe0";
clock-output-names = "gcc_usb1_pipe_clk_src";
};
};
qusb_phy_1: phy@59000 {
compatible = "qcom,ipq8074-qusb2-phy";
reg = <0x00059000 0x180>;
#phy-cells = <0>;
clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
<&xo>;
clock-names = "cfg_ahb", "ref";
resets = <&gcc GCC_QUSB2_1_PHY_BCR>;
status = "disabled";
};
ssphy_0: phy@78000 {
compatible = "qcom,ipq8074-qmp-usb3-phy";
reg = <0x00078000 0x1c4>;
#clock-cells = <1>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
clocks = <&gcc GCC_USB0_AUX_CLK>,
<&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
<&xo>;
clock-names = "aux", "cfg_ahb", "ref";
resets = <&gcc GCC_USB0_PHY_BCR>,
<&gcc GCC_USB3PHY_0_PHY_BCR>;
reset-names = "phy","common";
status = "disabled";
usb0_ssphy: lane@78200 {
reg = <0x00078200 0x130>, /* Tx */
<0x00078400 0x200>, /* Rx */
<0x00078800 0x1f8>, /* PCS */
<0x00078600 0x044>; /* PCS misc*/
#phy-cells = <0>;
clocks = <&gcc GCC_USB0_PIPE_CLK>;
clock-names = "pipe0";
clock-output-names = "gcc_usb0_pipe_clk_src";
};
};
qusb_phy_0: phy@79000 {
compatible = "qcom,ipq8074-qusb2-phy";
reg = <0x00079000 0x180>;
#phy-cells = <0>;
clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
<&xo>;
clock-names = "cfg_ahb", "ref";
resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
};
pcie_phy0: phy@86000 {
compatible = "qcom,ipq8074-qmp-pcie-phy";
reg = <0x00086000 0x1000>;
......@@ -169,6 +254,28 @@ gcc: gcc@1800000 {
#reset-cells = <0x1>;
};
sdhc_1: sdhci@7824900 {
compatible = "qcom,sdhci-msm-v4";
reg = <0x7824900 0x500>, <0x7824000 0x800>;
reg-names = "hc_mem", "core_mem";
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
clocks = <&xo>,
<&gcc GCC_SDCC1_AHB_CLK>,
<&gcc GCC_SDCC1_APPS_CLK>;
clock-names = "xo", "iface", "core";
max-frequency = <384000000>;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
bus-width = <8>;
status = "disabled";
};
blsp_dma: dma@7884000 {
compatible = "qcom,bam-v1.7.0";
reg = <0x07884000 0x2b000>;
......@@ -294,6 +401,88 @@ qpic_nand: nand@79b0000 {
status = "disabled";
};
usb_0: usb@8af8800 {
compatible = "qcom,dwc3";
reg = <0x08af8800 0x400>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
<&gcc GCC_USB0_MASTER_CLK>,
<&gcc GCC_USB0_SLEEP_CLK>,
<&gcc GCC_USB0_MOCK_UTMI_CLK>;
clock-names = "sys_noc_axi",
"master",
"sleep",
"mock_utmi";
assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
<&gcc GCC_USB0_MASTER_CLK>,
<&gcc GCC_USB0_MOCK_UTMI_CLK>;
assigned-clock-rates = <133330000>,
<133330000>,
<19200000>;
resets = <&gcc GCC_USB0_BCR>;
status = "disabled";
dwc_0: dwc3@8a00000 {
compatible = "snps,dwc3";
reg = <0x8a00000 0xcd00>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
phys = <&qusb_phy_0>, <&usb0_ssphy>;
phy-names = "usb2-phy", "usb3-phy";
tx-fifo-resize;
snps,is-utmi-l1-suspend;
snps,hird-threshold = /bits/ 8 <0x0>;
snps,dis_u2_susphy_quirk;
snps,dis_u3_susphy_quirk;
dr_mode = "host";
};
};
usb_1: usb@8cf8800 {
compatible = "qcom,dwc3";
reg = <0x08cf8800 0x400>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>,
<&gcc GCC_USB1_MASTER_CLK>,
<&gcc GCC_USB1_SLEEP_CLK>,
<&gcc GCC_USB1_MOCK_UTMI_CLK>;
clock-names = "sys_noc_axi",
"master",
"sleep",
"mock_utmi";
assigned-clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>,
<&gcc GCC_USB1_MASTER_CLK>,
<&gcc GCC_USB1_MOCK_UTMI_CLK>;
assigned-clock-rates = <133330000>,
<133330000>,
<19200000>;
resets = <&gcc GCC_USB1_BCR>;
status = "disabled";
dwc_1: dwc3@8c00000 {
compatible = "snps,dwc3";
reg = <0x8c00000 0xcd00>;
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
phys = <&qusb_phy_1>, <&usb1_ssphy>;
phy-names = "usb2-phy", "usb3-phy";
tx-fifo-resize;
snps,is-utmi-l1-suspend;
snps,hird-threshold = /bits/ 8 <0x0>;
snps,dis_u2_susphy_quirk;
snps,dis_u3_susphy_quirk;
dr_mode = "host";
};
};
intc: interrupt-controller@b000000 {
compatible = "qcom,msm-qgic2";
interrupt-controller;
......
arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts
View file @ c6e2e454
......@@ -108,31 +108,6 @@ volume-up {
};
};
&msmgpio {
gpio_keys_default: gpio-keys-default {
pinmux {
function = "gpio";
pins = "gpio107";
};
pinconf {
pins = "gpio107";
drive-strength = <2>;
bias-pull-up;
};
};
usb_vbus_default: usb-vbus-default {
pinmux {
function = "gpio";
pins = "gpio62";
};
pinconf {
pins = "gpio62";
bias-pull-up;
};
};
};
&spmi_bus {
pm8916@0 {
pon@800 {
......@@ -258,3 +233,20 @@ l18 {
regulator-max-microvolt = <2700000>;
};
};
&msmgpio {
gpio_keys_default: gpio-keys-default {
pins = "gpio107";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
usb_vbus_default: usb-vbus-default {
pins = "gpio62";
function = "gpio";
bias-pull-up;
};
};
arch/arm64/boot/dts/qcom/msm8916-pins.dtsi
View file @ c6e2e454
......@@ -6,74 +6,49 @@
&msmgpio {
blsp1_uart1_default: blsp1-uart1-default {
pinmux {
function = "blsp_uart1";
// TX, RX, CTS_N, RTS_N
pins = "gpio0", "gpio1",
"gpio2", "gpio3";
};
pinconf {
pins = "gpio0", "gpio1",
"gpio2", "gpio3";
pins = "gpio0", "gpio1", "gpio2", "gpio3";
function = "blsp_uart1";
drive-strength = <16>;
bias-disable;
};
};
blsp1_uart1_sleep: blsp1-uart1-sleep {
pinmux {
pins = "gpio0", "gpio1", "gpio2", "gpio3";
function = "gpio";
pins = "gpio0", "gpio1",
"gpio2", "gpio3";
};
pinconf {
pins = "gpio0", "gpio1",
"gpio2", "gpio3";
drive-strength = <2>;
bias-pull-down;
};
};
blsp1_uart2_default: blsp1-uart2-default {
pinmux {
function = "blsp_uart2";
pins = "gpio4", "gpio5";
};
pinconf {
pins = "gpio4", "gpio5";
function = "blsp_uart2";
drive-strength = <16>;
bias-disable;
};
};
blsp1_uart2_sleep: blsp1-uart2-sleep {
pinmux {
function = "gpio";
pins = "gpio4", "gpio5";
};
pinconf {
pins = "gpio4", "gpio5";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
};
spi1_default: spi1-default {
pinmux {
function = "blsp_spi1";
pins = "gpio0", "gpio1", "gpio3";
};
pinmux-cs {
function = "gpio";
pins = "gpio2";
};
pinconf {
pins = "gpio0", "gpio1", "gpio3";
function = "blsp_spi1";
drive-strength = <12>;
bias-disable;
};
pinconf-cs {
cs {
pins = "gpio2";
function = "gpio";
drive-strength = <16>;
bias-disable;
output-high;
......@@ -81,33 +56,24 @@ pinconf-cs {
};
spi1_sleep: spi1-sleep {
pinmux {
function = "gpio";
pins = "gpio0", "gpio1", "gpio2", "gpio3";
};
pinconf {
pins = "gpio0", "gpio1", "gpio2", "gpio3";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
};
spi2_default: spi2-default {
pinmux {
function = "blsp_spi2";
pins = "gpio4", "gpio5", "gpio7";
};
pinmux-cs {
function = "gpio";
pins = "gpio6";
};
pinconf {
pins = "gpio4", "gpio5", "gpio7";
function = "blsp_spi2";
drive-strength = <12>;
bias-disable;
};
pinconf-cs {
cs {
pins = "gpio6";
function = "gpio";
drive-strength = <16>;
bias-disable;
output-high;
......@@ -115,33 +81,24 @@ pinconf-cs {
};
spi2_sleep: spi2-sleep {
pinmux {
function = "gpio";
pins = "gpio4", "gpio5", "gpio6", "gpio7";
};
pinconf {
pins = "gpio4", "gpio5", "gpio6", "gpio7";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
};
spi3_default: spi3-default {
pinmux {
function = "blsp_spi3";
pins = "gpio8", "gpio9", "gpio11";
};
pinmux-cs {
function = "gpio";
pins = "gpio10";
};
pinconf {
pins = "gpio8", "gpio9", "gpio11";
function = "blsp_spi3";
drive-strength = <12>;
bias-disable;
};
pinconf-cs {
cs {
pins = "gpio10";
function = "gpio";
drive-strength = <16>;
bias-disable;
output-high;
......@@ -149,33 +106,24 @@ pinconf-cs {
};
spi3_sleep: spi3-sleep {
pinmux {
function = "gpio";
pins = "gpio8", "gpio9", "gpio10", "gpio11";
};
pinconf {
pins = "gpio8", "gpio9", "gpio10", "gpio11";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
};
spi4_default: spi4-default {
pinmux {
function = "blsp_spi4";
pins = "gpio12", "gpio13", "gpio15";
};
pinmux-cs {
function = "gpio";
pins = "gpio14";
};
pinconf {
pins = "gpio12", "gpio13", "gpio15";
function = "blsp_spi4";
drive-strength = <12>;
bias-disable;
};
pinconf-cs {
cs {
pins = "gpio14";
function = "gpio";
drive-strength = <16>;
bias-disable;
output-high;
......@@ -183,33 +131,24 @@ pinconf-cs {
};
spi4_sleep: spi4-sleep {
pinmux {
function = "gpio";
pins = "gpio12", "gpio13", "gpio14", "gpio15";
};
pinconf {
pins = "gpio12", "gpio13", "gpio14", "gpio15";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
};
spi5_default: spi5-default {
pinmux {
function = "blsp_spi5";
pins = "gpio16", "gpio17", "gpio19";
};
pinmux-cs {
function = "gpio";
pins = "gpio18";
};
pinconf {
pins = "gpio16", "gpio17", "gpio19";
function = "blsp_spi5";
drive-strength = <12>;
bias-disable;
};
pinconf-cs {
cs {
pins = "gpio18";
function = "gpio";
drive-strength = <16>;
bias-disable;
output-high;
......@@ -217,33 +156,24 @@ pinconf-cs {
};
spi5_sleep: spi5-sleep {
pinmux {
function = "gpio";
pins = "gpio16", "gpio17", "gpio18", "gpio19";
};
pinconf {
pins = "gpio16", "gpio17", "gpio18", "gpio19";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
};
spi6_default: spi6-default {
pinmux {
function = "blsp_spi6";
pins = "gpio20", "gpio21", "gpio23";
};
pinmux-cs {
function = "gpio";
pins = "gpio22";
};
pinconf {
pins = "gpio20", "gpio21", "gpio23";
function = "blsp_spi6";
drive-strength = <12>;
bias-disable;
};
pinconf-cs {
cs {
pins = "gpio22";
function = "gpio";
drive-strength = <16>;
bias-disable;
output-high;
......@@ -251,466 +181,315 @@ pinconf-cs {
};
spi6_sleep: spi6-sleep {
pinmux {
function = "gpio";
pins = "gpio20", "gpio21", "gpio22", "gpio23";
};
pinconf {
pins = "gpio20", "gpio21", "gpio22", "gpio23";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
};
i2c1_default: i2c1-default {
pinmux {
function = "blsp_i2c1";
pins = "gpio2", "gpio3";
};
pinconf {
pins = "gpio2", "gpio3";
function = "blsp_i2c1";
drive-strength = <2>;
bias-disable;
};
};
i2c1_sleep: i2c1-sleep {
pinmux {
function = "gpio";
pins = "gpio2", "gpio3";
};
pinconf {
pins = "gpio2", "gpio3";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
};
i2c2_default: i2c2-default {
pinmux {
function = "blsp_i2c2";
pins = "gpio6", "gpio7";
};
pinconf {
pins = "gpio6", "gpio7";
drive-strength = <16>;
function = "blsp_i2c2";
drive-strength = <2>;
bias-disable;
};
};
i2c2_sleep: i2c2-sleep {
pinmux {
function = "gpio";
pins = "gpio6", "gpio7";
};
pinconf {
pins = "gpio6", "gpio7";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
};
i2c4_default: i2c4-default {
pinmux {
function = "blsp_i2c4";
pins = "gpio14", "gpio15";
};
pinconf {
pins = "gpio14", "gpio15";
drive-strength = <16>;
function = "blsp_i2c4";
drive-strength = <2>;
bias-disable;
};
};
i2c4_sleep: i2c4-sleep {
pinmux {
function = "gpio";
pins = "gpio14", "gpio15";
};
pinconf {
pins = "gpio14", "gpio15";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
};
i2c5_default: i2c5-default {
pinmux {
function = "blsp_i2c5";
pins = "gpio18", "gpio19";
};
pinconf {
pins = "gpio18", "gpio19";
function = "blsp_i2c5";
drive-strength = <2>;
bias-disable;
};
};
i2c5_sleep: i2c5-sleep {
pinmux {
function = "gpio";
pins = "gpio18", "gpio19";
};
pinconf {
pins = "gpio18", "gpio19";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
};
i2c6_default: i2c6-default {
pinmux {
function = "blsp_i2c6";
pins = "gpio22", "gpio23";
};
pinconf {
pins = "gpio22", "gpio23";
drive-strength = <16>;
function = "blsp_i2c6";
drive-strength = <2>;
bias-disable;
};
};
i2c6_sleep: i2c6-sleep {
pinmux {
function = "gpio";
pins = "gpio22", "gpio23";
};
pinconf {
pins = "gpio22", "gpio23";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
};
pmx-sdc1-clk {
sdc1_clk_on: clk-on {
pinmux {
pins = "sdc1_clk";
};
pinconf {
pins = "sdc1_clk";
bias-disable;
drive-strength = <16>;
};
};
sdc1_clk_off: clk-off {
pinmux {
pins = "sdc1_clk";
};
pinconf {
pins = "sdc1_clk";
bias-disable;
drive-strength = <2>;
};
};
};
pmx-sdc1-cmd {
sdc1_cmd_on: cmd-on {
pinmux {
pins = "sdc1_cmd";
};
pinconf {
pins = "sdc1_cmd";
bias-pull-up;
drive-strength = <10>;
};
};
sdc1_cmd_off: cmd-off {
pinmux {
pins = "sdc1_cmd";
};
pinconf {
pins = "sdc1_cmd";
bias-pull-up;
drive-strength = <2>;
};
};
};
pmx-sdc1-data {
sdc1_data_on: data-on {
pinmux {
pins = "sdc1_data";
};
pinconf {
pins = "sdc1_data";
bias-pull-up;
drive-strength = <10>;
};
};
sdc1_data_off: data-off {
pinmux {
pins = "sdc1_data";
};
pinconf {
pins = "sdc1_data";
bias-pull-up;
drive-strength = <2>;
};
};
};
pmx-sdc2-clk {
sdc2_clk_on: clk-on {
pinmux {
pins = "sdc2_clk";
};
pinconf {
pins = "sdc2_clk";
bias-disable;
drive-strength = <16>;
};
};
sdc2_clk_off: clk-off {
pinmux {
pins = "sdc2_clk";
};
pinconf {
pins = "sdc2_clk";
bias-disable;
drive-strength = <2>;
};
};
};
pmx-sdc2-cmd {
sdc2_cmd_on: cmd-on {
pinmux {
pins = "sdc2_cmd";
};
pinconf {
pins = "sdc2_cmd";
bias-pull-up;
drive-strength = <10>;
};
};
sdc2_cmd_off: cmd-off {
pinmux {
pins = "sdc2_cmd";
};
pinconf {
pins = "sdc2_cmd";
bias-pull-up;
drive-strength = <2>;
};
};
};
pmx-sdc2-data {
sdc2_data_on: data-on {
pinmux {
pins = "sdc2_data";
};
pinconf {
pins = "sdc2_data";
bias-pull-up;
drive-strength = <10>;
};
};
sdc2_data_off: data-off {
pinmux {
pins = "sdc2_data";
};
pinconf {
pins = "sdc2_data";
bias-pull-up;
drive-strength = <2>;
};
};
};
pmx-sdc2-cd-pin {
sdc2_cd_on: cd-on {
pinmux {
function = "gpio";
pins = "gpio38";
};
pinconf {
pins = "gpio38";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
sdc2_cd_off: cd-off {
pinmux {
function = "gpio";
pins = "gpio38";
};
pinconf {
pins = "gpio38";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
};
};
cdc-pdm-lines {
cdc_pdm_lines_act: pdm-lines-on {
pinmux {
function = "cdc_pdm0";
pins = "gpio63", "gpio64", "gpio65", "gpio66",
"gpio67", "gpio68";
};
pinconf {
pins = "gpio63", "gpio64", "gpio65", "gpio66",
"gpio67", "gpio68";
function = "cdc_pdm0";
drive-strength = <8>;
bias-pull-none;
};
bias-disable;
};
cdc_pdm_lines_sus: pdm-lines-off {
pinmux {
function = "cdc_pdm0";
pins = "gpio63", "gpio64", "gpio65", "gpio66",
"gpio67", "gpio68";
};
pinconf {
pins = "gpio63", "gpio64", "gpio65", "gpio66",
"gpio67", "gpio68";
function = "cdc_pdm0";
drive-strength = <2>;
bias-disable;
};
bias-pull-down;
};
};
ext-pri-tlmm-lines {
ext_pri_tlmm_lines_act: ext-pa-on {
pinmux {
pins = "gpio113", "gpio114", "gpio115", "gpio116";
function = "pri_mi2s";
pins = "gpio113", "gpio114", "gpio115",
"gpio116";
};
pinconf {
pins = "gpio113", "gpio114", "gpio115",
"gpio116";
drive-strength = <8>;
bias-pull-none;
};
bias-disable;
};
ext_pri_tlmm_lines_sus: ext-pa-off {
pinmux {
pins = "gpio113", "gpio114", "gpio115", "gpio116";
function = "pri_mi2s";
pins = "gpio113", "gpio114", "gpio115",
"gpio116";
};
pinconf {
pins = "gpio113", "gpio114", "gpio115",
"gpio116";
drive-strength = <2>;
bias-disable;
};
};
};
ext-pri-ws-line {
ext_pri_ws_act: ext-pa-on {
pinmux {
function = "pri_mi2s_ws";
pins = "gpio110";
};
pinconf {
pins = "gpio110";
function = "pri_mi2s_ws";
drive-strength = <8>;
bias-pull-none;
};
bias-disable;
};
ext_pri_ws_sus: ext-pa-off {
pinmux {
function = "pri_mi2s_ws";
pins = "gpio110";
};
pinconf {
pins = "gpio110";
function = "pri_mi2s_ws";
drive-strength = <2>;
bias-disable;
};
};
};
ext-mclk-tlmm-lines {
ext_mclk_tlmm_lines_act: mclk-lines-on {
pinmux {
function = "pri_mi2s";
pins = "gpio116";
};
pinconf {
pins = "gpio116";
function = "pri_mi2s";
drive-strength = <8>;
bias-pull-none;
};
bias-disable;
};
ext_mclk_tlmm_lines_sus: mclk-lines-off {
pinmux {
function = "pri_mi2s";
pins = "gpio116";
};
pinconf {
pins = "gpio116";
function = "pri_mi2s";
drive-strength = <2>;
bias-disable;
};
};
};
/* secondary Mi2S */
ext-sec-tlmm-lines {
ext_sec_tlmm_lines_act: tlmm-lines-on {
pinmux {
pins = "gpio112", "gpio117", "gpio118", "gpio119";
function = "sec_mi2s";
pins = "gpio112", "gpio117", "gpio118",
"gpio119";
};
pinconf {
pins = "gpio112", "gpio117", "gpio118",
"gpio119";
drive-strength = <8>;
bias-pull-none;
};
bias-disable;
};
ext_sec_tlmm_lines_sus: tlmm-lines-off {
pinmux {
pins = "gpio112", "gpio117", "gpio118", "gpio119";
function = "sec_mi2s";
pins = "gpio112", "gpio117", "gpio118",
"gpio119";
};
pinconf {
pins = "gpio112", "gpio117", "gpio118",
"gpio119";
drive-strength = <2>;
bias-disable;
};
};
};
cdc-dmic-lines {
cdc_dmic_lines_act: dmic-lines-on {
pinmux-dmic0-clk {
function = "dmic0_clk";
clk {
pins = "gpio0";
function = "dmic0_clk";
drive-strength = <8>;
};
pinmux-dmic0-data {
function = "dmic0_data";
data {
pins = "gpio1";
};
pinconf {
pins = "gpio0", "gpio1";
function = "dmic0_data";
drive-strength = <8>;
};
};
cdc_dmic_lines_sus: dmic-lines-off {
pinmux-dmic0-clk {
function = "dmic0_clk";
clk {
pins = "gpio0";
function = "dmic0_clk";
drive-strength = <2>;
bias-disable;
};
pinmux-dmic0-data {
function = "dmic0_data";
data {
pins = "gpio1";
};
pinconf {
pins = "gpio0", "gpio1";
function = "dmic0_data";
drive-strength = <2>;
bias-disable;
};
......@@ -718,88 +497,64 @@ pinconf {
};
wcnss_pin_a: wcnss-active {
pinmux {
pins = "gpio40", "gpio41", "gpio42", "gpio43", "gpio44";
function = "wcss_wlan";
};
pinconf {
pins = "gpio40", "gpio41", "gpio42", "gpio43", "gpio44";
drive-strength = <6>;
bias-pull-up;
};
};
cci0_default: cci0-default {
pinmux {
function = "cci_i2c";
pins = "gpio29", "gpio30";
};
pinconf {
pins = "gpio29", "gpio30";
function = "cci_i2c";
drive-strength = <16>;
bias-disable;
};
};
camera_front_default: camera-front-default {
pinmux-pwdn {
function = "gpio";
pins = "gpio33";
};
pinconf-pwdn {
pwdn {
pins = "gpio33";
function = "gpio";
drive-strength = <16>;
bias-disable;
};
pinmux-rst {
function = "gpio";
pins = "gpio28";
};
pinconf-rst {
rst {
pins = "gpio28";
function = "gpio";
drive-strength = <16>;
bias-disable;
};
pinmux-mclk1 {
function = "cam_mclk1";
pins = "gpio27";
};
pinconf-mclk1 {
mclk1 {
pins = "gpio27";
function = "cam_mclk1";
drive-strength = <16>;
bias-disable;
};
};
camera_rear_default: camera-rear-default {
pinmux-pwdn {
function = "gpio";
pins = "gpio34";
};
pinconf-pwdn {
pwdn {
pins = "gpio34";
function = "gpio";
drive-strength = <16>;
bias-disable;
};
pinmux-rst {
function = "gpio";
pins = "gpio35";
};
pinconf-rst {
rst {
pins = "gpio35";
function = "gpio";
drive-strength = <16>;
bias-disable;
};
pinmux-mclk0 {
function = "cam_mclk0";
pins = "gpio26";
};
pinconf-mclk0 {
mclk0 {
pins = "gpio26";
function = "cam_mclk0";
drive-strength = <16>;
bias-disable;
};
......
arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi
View file @ c6e2e454
......@@ -167,77 +167,33 @@ muic: sm5502@25 {
};
};
&msmgpio {
gpio_keys_default: gpio-keys-default {
pinmux {
function = "gpio";
pins = "gpio107", "gpio109";
};
pinconf {
pins = "gpio107", "gpio109";
drive-strength = <2>;
bias-pull-up;
};
};
gpio_hall_sensor_default: gpio-hall-sensor-default {
pinmux {
function = "gpio";
pins = "gpio52";
};
pinconf {
pins = "gpio52";
drive-strength = <2>;
bias-disable;
};
};
&blsp_i2c2 {
status = "okay";
muic_int_default: muic-int-default {
pinmux {
function = "gpio";
pins = "gpio12";
};
pinconf {
pins = "gpio12";
drive-strength = <2>;
bias-disable;
};
};
accelerometer: accelerometer@10 {
compatible = "bosch,bmc150_accel";
reg = <0x10>;
interrupt-parent = <&msmgpio>;
interrupts = <115 IRQ_TYPE_EDGE_RISING>;
tsp_en_default: tsp-en-default {
pinmux {
function = "gpio";
pins = "gpio73";
};
pinconf {
pins = "gpio73";
drive-strength = <2>;
bias-disable;
};
pinctrl-names = "default";
pinctrl-0 = <&accel_int_default>;
};
pmx-mdss {
mdss_default: mdss-default {
pinmux {
function = "gpio";
pins = "gpio25";
};
pinconf {
pins = "gpio25";
drive-strength = <8>;
bias-disable;
};
magnetometer@12 {
compatible = "bosch,bmc150_magn";
reg = <0x12>;
};
};
mdss_sleep: mdss-sleep {
pinmux {
function = "gpio";
pins = "gpio25";
};
pinconf {
pins = "gpio25";
drive-strength = <2>;
bias-pull-down;
&spmi_bus {
pm8916@0 {
pon@800 {
volume-down {
compatible = "qcom,pm8941-resin";
interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
bias-pull-up;
linux,code = <KEY_VOLUMEDOWN>;
};
};
};
......@@ -356,15 +312,61 @@ l18 {
};
};
&spmi_bus {
pm8916@0 {
pon@800 {
volume-down {
compatible = "qcom,pm8941-resin";
interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
&msmgpio {
accel_int_default: accel-int-default {
pins = "gpio115";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
gpio_keys_default: gpio-keys-default {
pins = "gpio107", "gpio109";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
linux,code = <KEY_VOLUMEDOWN>;
};
gpio_hall_sensor_default: gpio-hall-sensor-default {
pins = "gpio52";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
mdss {
mdss_default: mdss-default {
pins = "gpio25";
function = "gpio";
drive-strength = <8>;
bias-disable;
};
mdss_sleep: mdss-sleep {
pins = "gpio25";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
};
muic_int_default: muic-int-default {
pins = "gpio12";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
tsp_en_default: tsp-en-default {
pins = "gpio73";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
};
arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts
View file @ c6e2e454
......@@ -22,6 +22,12 @@ reg_panel_vdd3: regulator-panel-vdd3 {
};
};
&accelerometer {
mount-matrix = "0", "1", "0",
"1", "0", "0",
"0", "0", "1";
};
&dsi0 {
panel@0 {
reg = <0>;
......@@ -51,14 +57,10 @@ dsi0_out: endpoint {
&msmgpio {
panel_vdd3_default: panel-vdd3-default {
pinmux {
function = "gpio";
pins = "gpio9";
};
pinconf {
pins = "gpio9";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
};
};
arch/arm64/boot/dts/qcom/msm8916-samsung-a5u-eur.dts
View file @ c6e2e454
......@@ -9,6 +9,12 @@ / {
compatible = "samsung,a5u-eur", "qcom,msm8916";
};
&accelerometer {
mount-matrix = "-1", "0", "0",
"0", "1", "0",
"0", "0", "1";
};
&blsp_i2c5 {
status = "okay";
......@@ -38,14 +44,10 @@ iris {
&msmgpio {
ts_int_default: ts-int-default {
pinmux {
function = "gpio";
pins = "gpio13";
};
pinconf {
pins = "gpio13";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
};
};
arch/arm64/boot/dts/qcom/msm8916.dtsi
View file @ c6e2e454
......@@ -4,6 +4,7 @@
*/
#include <dt-bindings/arm/coresight-cti-dt.h>
#include <dt-bindings/interconnect/qcom,msm8916.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-msm8916.h>
#include <dt-bindings/reset/qcom,gcc-msm8916.h>
......@@ -406,11 +407,38 @@ soc: soc {
ranges = <0 0 0 0xffffffff>;
compatible = "simple-bus";
bimc: interconnect@400000 {
compatible = "qcom,msm8916-bimc";
reg = <0x00400000 0x62000>;
#interconnect-cells = <1>;
clock-names = "bus", "bus_a";
clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
<&rpmcc RPM_SMD_BIMC_A_CLK>;
};
restart@4ab000 {
compatible = "qcom,pshold";
reg = <0x4ab000 0x4>;
};
pcnoc: interconnect@500000 {
compatible = "qcom,msm8916-pcnoc";
reg = <0x00500000 0x11000>;
#interconnect-cells = <1>;
clock-names = "bus", "bus_a";
clocks = <&rpmcc RPM_SMD_PCNOC_CLK>,
<&rpmcc RPM_SMD_PCNOC_A_CLK>;
};
snoc: interconnect@580000 {
compatible = "qcom,msm8916-snoc";
reg = <0x00580000 0x14000>;
#interconnect-cells = <1>;
clock-names = "bus", "bus_a";
clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
<&rpmcc RPM_SMD_SNOC_A_CLK>;
};
msmgpio: pinctrl@1000000 {
compatible = "qcom,msm8916-pinctrl";
reg = <0x1000000 0x300000>;
......@@ -700,6 +728,9 @@ lpass: lpass@7708000 {
interrupt-names = "lpass-irq-lpaif";
reg = <0x07708000 0x10000>;
reg-names = "lpass-lpaif";
#address-cells = <1>;
#size-cells = <0>;
};
lpass_codec: codec{
......
arch/arm64/boot/dts/qcom/msm8994-angler-rev-101.dts
View file @ c6e2e454
......@@ -11,6 +11,8 @@ / {
model = "Huawei Nexus 6P";
compatible = "huawei,angler", "qcom,msm8994";
/* required for bootloader to select correct board */
qcom,msm-id = <207 0x20000>;
qcom,pmic-id = <0x10009 0x1000A 0x0 0x0>;
qcom,board-id = <8026 0>;
aliases {
......
arch/arm64/boot/dts/qcom/msm8994-pins.dtsi deleted 100644 → 0
View file @ 01407153
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
*/
&msmgpio {
blsp1_uart2_default: blsp1_uart2_default {
pinmux {
function = "blsp_uart2";
pins = "gpio4", "gpio5";
};
pinconf {
pins = "gpio4", "gpio5";
drive-strength = <16>;
bias-disable;
};
};
blsp1_uart2_sleep: blsp1_uart2_sleep {
pinmux {
function = "gpio";
pins = "gpio4", "gpio5";
};
pinconf {
pins = "gpio4", "gpio5";
drive-strength = <2>;
bias-pull-down;
};
};
};
arch/arm64/boot/dts/qcom/msm8994.dtsi
View file @ c6e2e454
......@@ -6,12 +6,6 @@
#include <dt-bindings/clock/qcom,gcc-msm8994.h>
/ {
model = "Qualcomm Technologies, Inc. MSM 8994";
compatible = "qcom,msm8994";
// msm-id and pmic-id are required by bootloader for
// proper selection of dt blob
qcom,msm-id = <207 0x20000>;
qcom,pmic-id = <0x10009 0x1000A 0x0 0x0>;
interrupt-parent = <&intc>;
#address-cells = <2>;
......@@ -19,35 +13,166 @@ / {
chosen { };
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
clocks {
xo_board: xo_board {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <19200000>;
};
sleep_clk: sleep_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
};
};
cpus {
#address-cells = <2>;
#size-cells = <0>;
CPU0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0>;
reg = <0x0 0x0>;
enable-method = "psci";
next-level-cache = <&L2_0>;
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
};
};
CPU1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x1>;
enable-method = "psci";
next-level-cache = <&L2_0>;
};
timer {
compatible = "arm,armv8-timer";
interrupts = <1 2 0xff08>,
<1 3 0xff08>,
<1 4 0xff08>,
<1 1 0xff08>;
CPU2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x2>;
enable-method = "psci";
next-level-cache = <&L2_0>;
};
CPU3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x3>;
enable-method = "psci";
next-level-cache = <&L2_0>;
};
CPU4: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x100>;
enable-method = "psci";
next-level-cache = <&L2_1>;
L2_1: l2-cache {
compatible = "cache";
cache-level = <2>;
};
};
CPU5: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x101>;
enable-method = "psci";
next-level-cache = <&L2_1>;
};
CPU6: cpu@102 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x101>;
enable-method = "psci";
next-level-cache = <&L2_1>;
};
CPU7: cpu@103 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x101>;
enable-method = "psci";
next-level-cache = <&L2_1>;
};
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
};
core1 {
cpu = <&CPU1>;
};
core2 {
cpu = <&CPU2>;
};
core3 {
cpu = <&CPU3>;
};
};
cluster1 {
core0 {
cpu = <&CPU4>;
};
core1 {
cpu = <&CPU5>;
};
core2 {
cpu = <&CPU6>;
};
core3 {
cpu = <&CPU7>;
};
};
};
};
memory {
device_type = "memory";
/* We expect the bootloader to fill in the reg */
reg = <0 0 0 0>;
};
pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4)| IRQ_TYPE_LEVEL_HIGH)>;
};
psci {
compatible = "arm,psci-0.2";
method = "hvc";
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
smem_mem: smem_region@6a00000 {
reg = <0x0 0x6a00000 0x0 0x200000>;
no-map;
};
};
smem {
compatible = "qcom,smem";
memory-region = <&smem_mem>;
hwlocks = <&tcsr_mutex 3>;
};
soc: soc {
......@@ -123,72 +248,402 @@ frame@f9028000 {
};
};
restart@fc4ab000 {
compatible = "qcom,pshold";
reg = <0xfc4ab000 0x4>;
sdhc1: sdhci@f9824900 {
compatible = "qcom,sdhci-msm-v4";
reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>;
reg-names = "hc_mem", "core_mem";
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
clocks = <&gcc GCC_SDCC1_APPS_CLK>,
<&gcc GCC_SDCC1_AHB_CLK>,
<&xo_board>;
clock-names = "core", "iface", "xo";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>;
pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>;
bus-width = <8>;
non-removable;
status = "disabled";
};
msmgpio: pinctrl@fd510000 {
compatible = "qcom,msm8994-pinctrl";
reg = <0xfd510000 0x4000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
gpio-ranges = <&msmgpio 0 0 146>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
blsp1_dma: dma@f9904000 {
compatible = "qcom,bam-v1.7.0";
reg = <0xf9904000 0x19000>;
interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "bam_clk";
#dma-cells = <1>;
qcom,ee = <0>;
qcom,controlled-remotely;
num-channels = <18>;
qcom,num-ees = <4>;
};
blsp1_uart2: serial@f991e000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0xf991e000 0x1000>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "core", "iface";
clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp1_uart2_default>;
pinctrl-1 = <&blsp1_uart2_sleep>;
status = "disabled";
};
blsp_i2c1: i2c@f9923000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0xf9923000 0x500>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
clock-names = "iface", "core";
clock-frequency = <400000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c1_default>;
pinctrl-1 = <&i2c1_sleep>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
blsp_spi0: spi@f9923000 {
compatible = "qcom,spi-qup-v2.2.1";
reg = <0xf9923000 0x500>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
clocks = <&clock_gcc GCC_BLSP1_UART2_APPS_CLK>,
<&clock_gcc GCC_BLSP1_AHB_CLK>;
spi-max-frequency = <19200000>;
dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp1_spi0_default>;
pinctrl-1 = <&blsp1_spi0_sleep>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
tcsr_mutex_regs: syscon@fd484000 {
compatible = "syscon";
reg = <0xfd484000 0x2000>;
blsp_i2c2: i2c@f9924000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0xf9924000 0x500>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
clock-names = "iface", "core";
clock-frequency = <355000>;
dmas = <&blsp1_dma 14>, <&blsp1_dma 15>;
dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c2_default>;
pinctrl-1 = <&i2c2_sleep>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
/* I2C3 doesn't exist */
blsp_i2c4: i2c@f9926000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0xf9926000 0x500>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
clock-names = "iface", "core";
clock-frequency = <355000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c4_default>;
pinctrl-1 = <&i2c4_sleep>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
blsp2_dma: dma@f9944000 {
compatible = "qcom,bam-v1.7.0";
reg = <0xf9944000 0x19000>;
interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP2_AHB_CLK>;
clock-names = "bam_clk";
#dma-cells = <1>;
qcom,ee = <0>;
qcom,controlled-remotely;
num-channels = <18>;
qcom,num-ees = <4>;
};
clock_gcc: clock-controller@fc400000 {
/* According to downstream kernels, i2c6
* comes before i2c5 address-wise...
*/
blsp_i2c6: i2c@f9928000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0xf9928000 0x500>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
clock-names = "iface", "core";
clock-frequency = <355000>;
dmas = <&blsp1_dma 22>, <&blsp1_dma 23>;
dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c6_default>;
pinctrl-1 = <&i2c6_sleep>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
blsp2_uart2: serial@f995e000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0xf995e000 0x1000>;
interrupts = <GIC_SPI 146 IRQ_TYPE_EDGE_FALLING>;
clock-names = "core", "iface";
clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
<&gcc GCC_BLSP2_AHB_CLK>;
dmas = <&blsp2_dma 2>, <&blsp2_dma 3>;
dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp2_uart2_default>;
pinctrl-1 = <&blsp2_uart2_sleep>;
status = "disabled";
};
blsp_i2c5: i2c@f9967000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0xf9967000 0x500>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP2_AHB_CLK>,
<&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>;
clock-names = "iface", "core";
clock-frequency = <355000>;
dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c5_default>;
pinctrl-1 = <&i2c5_sleep>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
gcc: clock-controller@fc400000 {
compatible = "qcom,gcc-msm8994";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
reg = <0xfc400000 0x2000>;
};
restart@fc4ab000 {
compatible = "qcom,pshold";
reg = <0xfc4ab000 0x4>;
};
memory {
device_type = "memory";
// We expect the bootloader to fill in the reg
reg = <0 0 0 0>;
spmi_bus: spmi@fc4c0000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0xfc4cf000 0x1000>,
<0xfc4cb000 0x1000>,
<0xfc4ca000 0x1000>;
reg-names = "core", "intr", "cnfg";
interrupt-names = "periph_irq";
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
qcom,ee = <0>;
qcom,channel = <0>;
#address-cells = <2>;
#size-cells = <0>;
interrupt-controller;
#interrupt-cells = <4>;
};
xo_board: xo_board {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <19200000>;
tcsr_mutex_regs: syscon@fd484000 {
compatible = "syscon";
reg = <0xfd484000 0x2000>;
};
sleep_clk: sleep_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
tlmm: pinctrl@fd510000 {
compatible = "qcom,msm8994-pinctrl";
reg = <0xfd510000 0x4000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
gpio-ranges = <&tlmm 0 0 146>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
blsp1_uart2_default: blsp1-uart2-default {
function = "blsp_uart2";
pins = "gpio4", "gpio5";
drive-strength = <16>;
bias-disable;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
blsp1_uart2_sleep: blsp1-uart2-sleep {
function = "gpio";
pins = "gpio4", "gpio5";
drive-strength = <2>;
bias-pull-down;
};
smem_mem: smem_region@6a00000 {
reg = <0x0 0x6a00000 0x0 0x200000>;
no-map;
blsp2_uart2_default: blsp2-uart2-default {
function = "blsp_uart8";
pins = "gpio45", "gpio46";
drive-strength = <2>;
bias-disable;
};
blsp2_uart2_sleep: blsp2-uart2-sleep {
function = "gpio";
pins = "gpio45", "gpio46";
drive-strength = <2>;
bias-pull-down;
};
i2c1_default: i2c1-default {
function = "blsp_i2c1";
pins = "gpio2", "gpio3";
drive-strength = <2>;
bias-disable;
};
i2c1_sleep: i2c1-sleep {
function = "gpio";
pins = "gpio2", "gpio3";
drive-strength = <2>;
bias-disable;
};
i2c2_default: i2c2-default {
function = "blsp_i2c2";
pins = "gpio6", "gpio7";
drive-strength = <2>;
bias-disable;
};
i2c2_sleep: i2c2-sleep {
function = "gpio";
pins = "gpio6", "gpio7";
drive-strength = <2>;
bias-disable;
};
i2c4_default: i2c4-default {
function = "blsp_i2c4";
pins = "gpio19", "gpio20";
drive-strength = <2>;
bias-disable;
};
i2c4_sleep: i2c4-sleep {
function = "gpio";
pins = "gpio19", "gpio20";
drive-strength = <2>;
bias-pull-down;
input-enable;
};
i2c5_default: i2c5-default {
function = "blsp_i2c5";
pins = "gpio23", "gpio24";
drive-strength = <2>;
bias-disable;
};
i2c5_sleep: i2c5-sleep {
function = "gpio";
pins = "gpio23", "gpio24";
drive-strength = <2>;
bias-disable;
};
i2c6_default: i2c6-default {
function = "blsp_i2c6";
pins = "gpio28", "gpio27";
drive-strength = <2>;
bias-disable;
};
i2c6_sleep: i2c6-sleep {
function = "gpio";
pins = "gpio28", "gpio27";
drive-strength = <2>;
bias-disable;
};
blsp1_spi0_default: blsp1-spi0-default {
default {
function = "blsp_spi1";
pins = "gpio0", "gpio1", "gpio3";
drive-strength = <10>;
bias-pull-down;
};
cs {
function = "gpio";
pins = "gpio8";
drive-strength = <2>;
bias-disable;
};
};
blsp1_spi0_sleep: blsp1-spi0-sleep {
pins = "gpio0", "gpio1", "gpio3";
drive-strength = <2>;
bias-disable;
};
sdc1_clk_on: clk-on {
pins = "sdc1_clk";
bias-disable;
drive-strength = <16>;
};
sdc1_clk_off: clk-off {
pins = "sdc1_clk";
bias-disable;
drive-strength = <2>;
};
sdc1_cmd_on: cmd-on {
pins = "sdc1_cmd";
bias-pull-up;
drive-strength = <8>;
};
sdc1_cmd_off: cmd-off {
pins = "sdc1_cmd";
bias-pull-up;
drive-strength = <2>;
};
sdc1_data_on: data-on {
pins = "sdc1_data";
bias-pull-up;
drive-strength = <8>;
};
sdc1_data_off: data-off {
pins = "sdc1_data";
bias-pull-up;
drive-strength = <2>;
};
sdc1_rclk_on: rclk-on {
pins = "sdc1_rclk";
bias-pull-down;
};
sdc1_rclk_off: rclk-off {
pins = "sdc1_rclk";
bias-pull-down;
};
};
};
......@@ -198,12 +653,12 @@ tcsr_mutex: hwlock {
#hwlock-cells = <1>;
};
qcom,smem@6a00000 {
compatible = "qcom,smem";
memory-region = <&smem_mem>;
hwlocks = <&tcsr_mutex 3>;
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 2 0xff08>,
<GIC_PPI 3 0xff08>,
<GIC_PPI 4 0xff08>,
<GIC_PPI 1 0xff08>;
};
};
#include "msm8994-pins.dtsi"
arch/arm64/boot/dts/qcom/msm8998-clamshell.dtsi
View file @ c6e2e454
......@@ -202,7 +202,7 @@ vreg_l14a_1p88: l14 {
regulator-min-microvolt = <1880000>;
regulator-max-microvolt = <1880000>;
};
vreg_15a_1p8: l15 {
vreg_l15a_1p8: l15 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
......
arch/arm64/boot/dts/qcom/msm8998-lenovo-miix-630.dts
View file @ c6e2e454
......@@ -25,6 +25,11 @@ keyboard@3a {
};
};
&remoteproc_mss {
firmware-name = "qcom/LENOVO/81F1/qcdsp1v28998.mbn",
"qcom/LENOVO/81F1/qcdsp28998.mbn";
};
&sdhc2 {
cd-gpios = <&tlmm 95 GPIO_ACTIVE_HIGH>;
};
arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi
View file @ c6e2e454
......@@ -235,7 +235,7 @@ vreg_l14a_1p88: l14 {
regulator-min-microvolt = <1880000>;
regulator-max-microvolt = <1880000>;
};
vreg_15a_1p8: l15 {
vreg_l15a_1p8: l15 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
......
arch/arm64/boot/dts/qcom/pm660.dtsi 0 → 100644
View file @ c6e2e454
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2020, Konrad Dybcio
*/
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
&spmi_bus {
pmic@0 {
compatible = "qcom,pm660", "qcom,spmi-pmic";
reg = <0x0 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
rtc@6000 {
compatible = "qcom,pm8941-rtc";
reg = <0x6000>, <0x6100>;
reg-names = "rtc", "alarm";
interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>;
};
pon: pon@800 {
compatible = "qcom,pm8916-pon";
reg = <0x800>;
pwrkey {
compatible = "qcom,pm8941-pwrkey";
interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
debounce = <15625>;
bias-pull-up;
linux,code = <KEY_POWER>;
};
};
pm660_gpios: gpios@c000 {
compatible = "qcom,pm660-gpio";
reg = <0xc000>;
gpio-controller;
gpio-ranges = <&pm660_gpios 0 0 13>;
#gpio-cells = <2>;
interrupt-controller;
interrupt-cells =<2>;
};
};
};
arch/arm64/boot/dts/qcom/pm660l.dtsi 0 → 100644
View file @ c6e2e454
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2020, Konrad Dybcio
*/
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
&spmi_bus {
pmic@2 {
compatible = "qcom,pm660l", "qcom,spmi-pmic";
reg = <0x2 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pm660l_gpios: gpios@c000 {
compatible = "qcom,pm660l-gpio", "qcom,spmi-gpio";
reg = <0xc000>;
gpio-controller;
gpio-ranges = <&pm660l_gpios 0 0 12>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
pmic@3 {
compatible = "qcom,pm660l", "qcom,spmi-pmic";
reg = <0x3 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
};
};
arch/arm64/boot/dts/qcom/pm8009.dtsi 0 → 100644
View file @ c6e2e454
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
* Copyright (c) 2020, Linaro Limited
*/
#include <dt-bindings/spmi/spmi.h>
&spmi_bus {
pmic@a {
compatible = "qcom,pm8009", "qcom,spmi-pmic";
reg = <0xa SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pm8009_pon: pon@800 {
compatible = "qcom,pm8916-pon";
reg = <0x0800>;
};
pm8009_gpios: gpio@c000 {
compatible = "qcom,pm8005-gpio";
reg = <0xc000>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
pmic@b {
compatible = "qcom,pm8009", "qcom,spmi-pmic";
reg = <0xb SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
};
};
arch/arm64/boot/dts/qcom/pm8150.dtsi
View file @ c6e2e454
......@@ -9,6 +9,37 @@
#include <dt-bindings/spmi/spmi.h>
#include <dt-bindings/iio/qcom,spmi-vadc.h>
/ {
thermal-zones {
pm8150 {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-sensors = <&pm8150_temp>;
trips {
trip0 {
temperature = <95000>;
hysteresis = <0>;
type = "passive";
};
trip1 {
temperature = <115000>;
hysteresis = <0>;
type = "hot";
};
trip2 {
temperature = <145000>;
hysteresis = <0>;
type = "critical";
};
};
};
};
};
&spmi_bus {
pm8150_0: pmic@0 {
compatible = "qcom,pm8150", "qcom,spmi-pmic";
......@@ -30,6 +61,15 @@ pwrkey {
};
};
pm8150_temp: temp-alarm@2400 {
compatible = "qcom,spmi-temp-alarm";
reg = <0x2400>;
interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_BOTH>;
io-channels = <&pm8150_adc ADC5_DIE_TEMP>;
io-channel-names = "thermal";
#thermal-sensor-cells = <0>;
};
pm8150_adc: adc@3100 {
compatible = "qcom,spmi-adc5";
reg = <0x3100>;
......@@ -38,8 +78,6 @@ pm8150_adc: adc@3100 {
#io-channel-cells = <1>;
interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
ref-gnd@0 {
reg = <ADC5_REF_GND>;
qcom,pre-scaling = <1 1>;
......
arch/arm64/boot/dts/qcom/pm8150b.dtsi
View file @ c6e2e454
......@@ -8,6 +8,37 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
/ {
thermal-zones {
pm8150b {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-sensors = <&pm8150b_temp>;
trips {
trip0 {
temperature = <95000>;
hysteresis = <0>;
type = "passive";
};
trip1 {
temperature = <115000>;
hysteresis = <0>;
type = "hot";
};
trip2 {
temperature = <145000>;
hysteresis = <0>;
type = "critical";
};
};
};
};
};
&spmi_bus {
pmic@2 {
compatible = "qcom,pm8150b", "qcom,spmi-pmic";
......@@ -22,7 +53,16 @@ power-on@800 {
status = "disabled";
};
adc@3100 {
pm8150b_temp: temp-alarm@2400 {
compatible = "qcom,spmi-temp-alarm";
reg = <0x2400>;
interrupts = <0x2 0x24 0x0 IRQ_TYPE_EDGE_BOTH>;
io-channels = <&pm8150b_adc ADC5_DIE_TEMP>;
io-channel-names = "thermal";
#thermal-sensor-cells = <0>;
};
pm8150b_adc: adc@3100 {
compatible = "qcom,spmi-adc5";
reg = <0x3100>;
#address-cells = <1>;
......@@ -30,8 +70,6 @@ adc@3100 {
#io-channel-cells = <1>;
interrupts = <0x2 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
ref-gnd@0 {
reg = <ADC5_REF_GND>;
qcom,pre-scaling = <1 1>;
......
arch/arm64/boot/dts/qcom/pm8150l.dtsi
View file @ c6e2e454
......@@ -8,6 +8,37 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
/ {
thermal-zones {
pm8150l {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-sensors = <&pm8150l_temp>;
trips {
trip0 {
temperature = <95000>;
hysteresis = <0>;
type = "passive";
};
trip1 {
temperature = <115000>;
hysteresis = <0>;
type = "hot";
};
trip2 {
temperature = <145000>;
hysteresis = <0>;
type = "critical";
};
};
};
};
};
&spmi_bus {
pmic@4 {
compatible = "qcom,pm8150l", "qcom,spmi-pmic";
......@@ -22,7 +53,16 @@ power-on@800 {
status = "disabled";
};
adc@3100 {
pm8150l_temp: temp-alarm@2400 {
compatible = "qcom,spmi-temp-alarm";
reg = <0x2400>;
interrupts = <0x4 0x24 0x0 IRQ_TYPE_EDGE_BOTH>;
io-channels = <&pm8150l_adc ADC5_DIE_TEMP>;
io-channel-names = "thermal";
#thermal-sensor-cells = <0>;
};
pm8150l_adc: adc@3100 {
compatible = "qcom,spmi-adc5";
reg = <0x3100>;
#address-cells = <1>;
......@@ -30,8 +70,6 @@ adc@3100 {
#io-channel-cells = <1>;
interrupts = <0x4 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
ref-gnd@0 {
reg = <ADC5_REF_GND>;
qcom,pre-scaling = <1 1>;
......
arch/arm64/boot/dts/qcom/pmi8998.dtsi
View file @ c6e2e454
......@@ -25,5 +25,17 @@ pmi8998_lsid1: pmic@3 {
reg = <0x3 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
labibb {
compatible = "qcom,pmi8998-lab-ibb";
ibb: ibb {
interrupts = <0x3 0xdc 0x2 IRQ_TYPE_EDGE_RISING>;
};
lab: lab {
interrupts = <0x3 0xde 0x0 IRQ_TYPE_EDGE_RISING>;
};
};
};
};
arch/arm64/boot/dts/qcom/qcs404.dtsi
View file @ c6e2e454
......@@ -1097,6 +1097,21 @@ blsp2_spi0: spi@7af5000 {
status = "disabled";
};
imem@8600000 {
compatible = "simple-mfd";
reg = <0x08600000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x08600000 0x1000>;
pil-reloc@94c {
compatible = "qcom,pil-reloc-info";
reg = <0x94c 0xc8>;
};
};
intc: interrupt-controller@b000000 {
compatible = "qcom,msm-qgic2";
interrupt-controller;
......
arch/arm64/boot/dts/qcom/sc7180-idp.dts
View file @ c6e2e454
......@@ -21,6 +21,7 @@ aliases {
bluetooth0 = &bluetooth;
hsuart0 = &uart3;
serial0 = &uart8;
wifi0 = &wifi;
};
chosen {
......@@ -312,7 +313,7 @@ &qupv3_id_1 {
&remoteproc_mpss {
status = "okay";
compatible = "qcom,sc7180-mss-pil";
iommus = <&apps_smmu 0x460 0x1>, <&apps_smmu 0x444 0x3>;
iommus = <&apps_smmu 0x461 0x0>, <&apps_smmu 0x444 0x3>;
memory-region = <&mba_mem &mpss_mem>;
};
......@@ -389,6 +390,18 @@ video-firmware {
};
};
&wifi {
status = "okay";
vdd-0.8-cx-mx-supply = <&vreg_l9a_0p6>;
vdd-1.8-xo-supply = <&vreg_l1c_1p8>;
vdd-1.3-rfa-supply = <&vreg_l2c_1p3>;
vdd-3.3-ch0-supply = <&vreg_l10c_3p3>;
vdd-3.3-ch1-supply = <&vreg_l11c_3p3>;
wifi-firmware {
iommus = <&apps_smmu 0xc2 0x1>;
};
};
/* PINCTRL - additions to nodes defined in sc7180.dtsi */
&qspi_clk {
......
arch/arm64/boot/dts/qcom/sc7180.dtsi
View file @ c6e2e454
......@@ -10,6 +10,7 @@
#include <dt-bindings/clock/qcom,gpucc-sc7180.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,videocc-sc7180.h>
#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/interconnect/qcom,sc7180.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/phy/phy-qcom-qusb2.h>
......@@ -130,6 +131,9 @@ &LITTLE_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_APPSS_PROC &mc_virt SLAVE_EBI1>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
next-level-cache = <&L2_0>;
#cooling-cells = <2>;
qcom,freq-domain = <&cpufreq_hw 0>;
......@@ -153,6 +157,9 @@ &LITTLE_CPU_SLEEP_1
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_100>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_APPSS_PROC &mc_virt SLAVE_EBI1>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
qcom,freq-domain = <&cpufreq_hw 0>;
L2_100: l2-cache {
......@@ -172,6 +179,9 @@ &LITTLE_CPU_SLEEP_1
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_200>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_APPSS_PROC &mc_virt SLAVE_EBI1>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
qcom,freq-domain = <&cpufreq_hw 0>;
L2_200: l2-cache {
......@@ -191,6 +201,9 @@ &LITTLE_CPU_SLEEP_1
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_300>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_APPSS_PROC &mc_virt SLAVE_EBI1>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
qcom,freq-domain = <&cpufreq_hw 0>;
L2_300: l2-cache {
......@@ -210,6 +223,9 @@ &LITTLE_CPU_SLEEP_1
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_400>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_APPSS_PROC &mc_virt SLAVE_EBI1>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
qcom,freq-domain = <&cpufreq_hw 0>;
L2_400: l2-cache {
......@@ -229,6 +245,9 @@ &LITTLE_CPU_SLEEP_1
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_500>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_APPSS_PROC &mc_virt SLAVE_EBI1>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
qcom,freq-domain = <&cpufreq_hw 0>;
L2_500: l2-cache {
......@@ -248,6 +267,9 @@ &BIG_CPU_SLEEP_1
capacity-dmips-mhz = <1740>;
dynamic-power-coefficient = <405>;
next-level-cache = <&L2_600>;
operating-points-v2 = <&cpu6_opp_table>;
interconnects = <&gem_noc MASTER_APPSS_PROC &mc_virt SLAVE_EBI1>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
qcom,freq-domain = <&cpufreq_hw 1>;
L2_600: l2-cache {
......@@ -267,6 +289,9 @@ &BIG_CPU_SLEEP_1
capacity-dmips-mhz = <1740>;
dynamic-power-coefficient = <405>;
next-level-cache = <&L2_700>;
operating-points-v2 = <&cpu6_opp_table>;
interconnects = <&gem_noc MASTER_APPSS_PROC &mc_virt SLAVE_EBI1>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
qcom,freq-domain = <&cpufreq_hw 1>;
L2_700: l2-cache {
......@@ -366,6 +391,141 @@ CLUSTER_SLEEP_0: cluster-sleep-0 {
};
};
cpu0_opp_table: cpu0_opp_table {
compatible = "operating-points-v2";
opp-shared;
cpu0_opp1: opp-300000000 {
opp-hz = /bits/ 64 <300000000>;
opp-peak-kBps = <1200000 4800000>;
};
cpu0_opp2: opp-576000000 {
opp-hz = /bits/ 64 <576000000>;
opp-peak-kBps = <1200000 4800000>;
};
cpu0_opp3: opp-768000000 {
opp-hz = /bits/ 64 <768000000>;
opp-peak-kBps = <1200000 4800000>;
};
cpu0_opp4: opp-1017600000 {
opp-hz = /bits/ 64 <1017600000>;
opp-peak-kBps = <1804000 8908800>;
};
cpu0_opp5: opp-1248000000 {
opp-hz = /bits/ 64 <1248000000>;
opp-peak-kBps = <2188000 12902400>;
};
cpu0_opp6: opp-1324800000 {
opp-hz = /bits/ 64 <1324800000>;
opp-peak-kBps = <2188000 12902400>;
};
cpu0_opp7: opp-1516800000 {
opp-hz = /bits/ 64 <1516800000>;
opp-peak-kBps = <3072000 15052800>;
};
cpu0_opp8: opp-1612800000 {
opp-hz = /bits/ 64 <1612800000>;
opp-peak-kBps = <3072000 15052800>;
};
cpu0_opp9: opp-1708800000 {
opp-hz = /bits/ 64 <1708800000>;
opp-peak-kBps = <3072000 15052800>;
};
cpu0_opp10: opp-1804800000 {
opp-hz = /bits/ 64 <1804800000>;
opp-peak-kBps = <4068000 22425600>;
};
};
cpu6_opp_table: cpu6_opp_table {
compatible = "operating-points-v2";
opp-shared;
cpu6_opp1: opp-300000000 {
opp-hz = /bits/ 64 <300000000>;
opp-peak-kBps = <2188000 8908800>;
};
cpu6_opp2: opp-652800000 {
opp-hz = /bits/ 64 <652800000>;
opp-peak-kBps = <2188000 8908800>;
};
cpu6_opp3: opp-825600000 {
opp-hz = /bits/ 64 <825600000>;
opp-peak-kBps = <2188000 8908800>;
};
cpu6_opp4: opp-979200000 {
opp-hz = /bits/ 64 <979200000>;
opp-peak-kBps = <2188000 8908800>;
};
cpu6_opp5: opp-1113600000 {
opp-hz = /bits/ 64 <1113600000>;
opp-peak-kBps = <2188000 8908800>;
};
cpu6_opp6: opp-1267200000 {
opp-hz = /bits/ 64 <1267200000>;
opp-peak-kBps = <4068000 12902400>;
};
cpu6_opp7: opp-1555200000 {
opp-hz = /bits/ 64 <1555200000>;
opp-peak-kBps = <4068000 15052800>;
};
cpu6_opp8: opp-1708800000 {
opp-hz = /bits/ 64 <1708800000>;
opp-peak-kBps = <6220000 19353600>;
};
cpu6_opp9: opp-1843200000 {
opp-hz = /bits/ 64 <1843200000>;
opp-peak-kBps = <6220000 19353600>;
};
cpu6_opp10: opp-1900800000 {
opp-hz = /bits/ 64 <1900800000>;
opp-peak-kBps = <6220000 22425600>;
};
cpu6_opp11: opp-1996800000 {
opp-hz = /bits/ 64 <1996800000>;
opp-peak-kBps = <6220000 22425600>;
};
cpu6_opp12: opp-2112000000 {
opp-hz = /bits/ 64 <2112000000>;
opp-peak-kBps = <6220000 22425600>;
};
cpu6_opp13: opp-2208000000 {
opp-hz = /bits/ 64 <2208000000>;
opp-peak-kBps = <7216000 22425600>;
};
cpu6_opp14: opp-2323200000 {
opp-hz = /bits/ 64 <2323200000>;
opp-peak-kBps = <7216000 22425600>;
};
cpu6_opp15: opp-2400000000 {
opp-hz = /bits/ 64 <2400000000>;
opp-peak-kBps = <8532000 23347200>;
};
};
memory@80000000 {
device_type = "memory";
/* We expect the bootloader to fill in the size */
......@@ -524,6 +684,8 @@ sdhc_1: sdhci@7c4000 {
clocks = <&gcc GCC_SDCC1_APPS_CLK>,
<&gcc GCC_SDCC1_AHB_CLK>;
clock-names = "core", "iface";
power-domains = <&rpmhpd SC7180_CX>;
operating-points-v2 = <&sdhc1_opp_table>;
bus-width = <8>;
non-removable;
......@@ -535,6 +697,39 @@ sdhc_1: sdhci@7c4000 {
mmc-hs400-enhanced-strobe;
status = "disabled";
sdhc1_opp_table: sdhc1-opp-table {
compatible = "operating-points-v2";
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
required-opps = <&rpmhpd_opp_low_svs>;
};
opp-384000000 {
opp-hz = /bits/ 64 <384000000>;
required-opps = <&rpmhpd_opp_svs_l1>;
};
};
};
qup_opp_table: qup-opp-table {
compatible = "operating-points-v2";
opp-75000000 {
opp-hz = /bits/ 64 <75000000>;
required-opps = <&rpmhpd_opp_low_svs>;
};
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
required-opps = <&rpmhpd_opp_svs>;
};
opp-128000000 {
opp-hz = /bits/ 64 <128000000>;
required-opps = <&rpmhpd_opp_nom>;
};
};
qupv3_id_0: geniqup@8c0000 {
......@@ -547,6 +742,8 @@ qupv3_id_0: geniqup@8c0000 {
#size-cells = <2>;
ranges;
iommus = <&apps_smmu 0x43 0x0>;
interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>;
interconnect-names = "qup-core";
status = "disabled";
i2c0: i2c@880000 {
......@@ -559,6 +756,11 @@ i2c0: i2c@880000 {
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>,
<&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
status = "disabled";
};
......@@ -572,6 +774,11 @@ spi0: spi@880000 {
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&rpmhpd SC7180_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>;
interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
......@@ -583,6 +790,11 @@ uart0: serial@880000 {
pinctrl-names = "default";
pinctrl-0 = <&qup_uart0_default>;
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd SC7180_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>;
interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
......@@ -596,6 +808,11 @@ i2c1: i2c@884000 {
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>,
<&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
status = "disabled";
};
......@@ -609,6 +826,11 @@ spi1: spi@884000 {
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&rpmhpd SC7180_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>;
interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
......@@ -620,6 +842,11 @@ uart1: serial@884000 {
pinctrl-names = "default";
pinctrl-0 = <&qup_uart1_default>;
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd SC7180_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>;
interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
......@@ -633,6 +860,11 @@ i2c2: i2c@888000 {
interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>,
<&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
status = "disabled";
};
......@@ -644,6 +876,11 @@ uart2: serial@888000 {
pinctrl-names = "default";
pinctrl-0 = <&qup_uart2_default>;
interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd SC7180_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>;
interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
......@@ -657,6 +894,11 @@ i2c3: i2c@88c000 {
interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>,
<&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
status = "disabled";
};
......@@ -670,6 +912,11 @@ spi3: spi@88c000 {
interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&rpmhpd SC7180_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>;
interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
......@@ -681,6 +928,11 @@ uart3: serial@88c000 {
pinctrl-names = "default";
pinctrl-0 = <&qup_uart3_default>;
interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd SC7180_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>;
interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
......@@ -694,6 +946,11 @@ i2c4: i2c@890000 {
interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>,
<&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
status = "disabled";
};
......@@ -705,6 +962,11 @@ uart4: serial@890000 {
pinctrl-names = "default";
pinctrl-0 = <&qup_uart4_default>;
interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd SC7180_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>;
interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
......@@ -718,6 +980,11 @@ i2c5: i2c@894000 {
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>,
<&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
status = "disabled";
};
......@@ -731,6 +998,11 @@ spi5: spi@894000 {
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&rpmhpd SC7180_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>;
interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
......@@ -742,6 +1014,11 @@ uart5: serial@894000 {
pinctrl-names = "default";
pinctrl-0 = <&qup_uart5_default>;
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd SC7180_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>;
interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
};
......@@ -756,6 +1033,8 @@ qupv3_id_1: geniqup@ac0000 {
#size-cells = <2>;
ranges;
iommus = <&apps_smmu 0x4c3 0x0>;
interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>;
interconnect-names = "qup-core";
status = "disabled";
i2c6: i2c@a80000 {
......@@ -768,6 +1047,11 @@ i2c6: i2c@a80000 {
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
status = "disabled";
};
......@@ -781,6 +1065,11 @@ spi6: spi@a80000 {
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&rpmhpd SC7180_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>;
interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
......@@ -792,6 +1081,11 @@ uart6: serial@a80000 {
pinctrl-names = "default";
pinctrl-0 = <&qup_uart6_default>;
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd SC7180_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>;
interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
......@@ -805,6 +1099,11 @@ i2c7: i2c@a84000 {
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
status = "disabled";
};
......@@ -816,6 +1115,11 @@ uart7: serial@a84000 {
pinctrl-names = "default";
pinctrl-0 = <&qup_uart7_default>;
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd SC7180_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>;
interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
......@@ -829,6 +1133,11 @@ i2c8: i2c@a88000 {
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
status = "disabled";
};
......@@ -842,6 +1151,11 @@ spi8: spi@a88000 {
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&rpmhpd SC7180_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>;
interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
......@@ -853,6 +1167,11 @@ uart8: serial@a88000 {
pinctrl-names = "default";
pinctrl-0 = <&qup_uart8_default>;
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd SC7180_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>;
interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
......@@ -866,6 +1185,11 @@ i2c9: i2c@a8c000 {
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
status = "disabled";
};
......@@ -877,6 +1201,11 @@ uart9: serial@a8c000 {
pinctrl-names = "default";
pinctrl-0 = <&qup_uart9_default>;
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd SC7180_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>;
interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
......@@ -890,6 +1219,11 @@ i2c10: i2c@a90000 {
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
status = "disabled";
};
......@@ -903,6 +1237,11 @@ spi10: spi@a90000 {
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&rpmhpd SC7180_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>;
interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
......@@ -914,6 +1253,11 @@ uart10: serial@a90000 {
pinctrl-names = "default";
pinctrl-0 = <&qup_uart10_default>;
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd SC7180_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>;
interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
......@@ -927,6 +1271,11 @@ i2c11: i2c@a94000 {
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
status = "disabled";
};
......@@ -940,6 +1289,11 @@ spi11: spi@a94000 {
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&rpmhpd SC7180_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>;
interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
......@@ -951,6 +1305,11 @@ uart11: serial@a94000 {
pinctrl-names = "default";
pinctrl-0 = <&qup_uart11_default>;
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd SC7180_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>;
interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
};
......@@ -1459,6 +1818,57 @@ pinconf-sd-cd {
};
};
remoteproc_mpss: remoteproc@4080000 {
compatible = "qcom,sc7180-mpss-pas";
reg = <0 0x04080000 0 0x4040>, <0 0x04180000 0 0x48>;
reg-names = "qdsp6", "rmb";
interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
<&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
<&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
<&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
<&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
<&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog", "fatal", "ready", "handover",
"stop-ack", "shutdown-ack";
clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
<&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>,
<&gcc GCC_MSS_NAV_AXI_CLK>,
<&gcc GCC_MSS_SNOC_AXI_CLK>,
<&gcc GCC_MSS_MFAB_AXIS_CLK>,
<&rpmhcc RPMH_CXO_CLK>;
clock-names = "iface", "bus", "nav", "snoc_axi",
"mnoc_axi", "xo";
power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>,
<&rpmhpd SC7180_CX>,
<&rpmhpd SC7180_MX>,
<&rpmhpd SC7180_MSS>;
power-domain-names = "load_state", "cx", "mx", "mss";
memory-region = <&mpss_mem>;
qcom,smem-states = <&modem_smp2p_out 0>;
qcom,smem-state-names = "stop";
resets = <&aoss_reset AOSS_CC_MSS_RESTART>,
<&pdc_reset PDC_MODEM_SYNC_RESET>;
reset-names = "mss_restart", "pdc_reset";
qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;
qcom,spare-regs = <&tcsr_regs 0xb3e4>;
status = "disabled";
glink-edge {
interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
label = "modem";
qcom,remote-pid = <1>;
mboxes = <&apss_shared 12>;
};
};
gpu: gpu@5000000 {
compatible = "qcom,adreno-618.0", "qcom,adreno";
#stream-id-cells = <16>;
......@@ -2054,57 +2464,6 @@ apss_merge_funnel_in: endpoint {
};
};
remoteproc_mpss: remoteproc@4080000 {
compatible = "qcom,sc7180-mpss-pas";
reg = <0 0x04080000 0 0x4040>, <0 0x04180000 0 0x48>;
reg-names = "qdsp6", "rmb";
interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
<&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
<&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
<&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
<&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
<&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog", "fatal", "ready", "handover",
"stop-ack", "shutdown-ack";
clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
<&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>,
<&gcc GCC_MSS_NAV_AXI_CLK>,
<&gcc GCC_MSS_SNOC_AXI_CLK>,
<&gcc GCC_MSS_MFAB_AXIS_CLK>,
<&rpmhcc RPMH_CXO_CLK>;
clock-names = "iface", "bus", "nav", "snoc_axi",
"mnoc_axi", "xo";
power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>,
<&rpmhpd SC7180_CX>,
<&rpmhpd SC7180_MX>,
<&rpmhpd SC7180_MSS>;
power-domain-names = "load_state", "cx", "mx", "mss";
memory-region = <&mpss_mem>;
qcom,smem-states = <&modem_smp2p_out 0>;
qcom,smem-state-names = "stop";
resets = <&aoss_reset AOSS_CC_MSS_RESTART>,
<&pdc_reset PDC_MODEM_SYNC_RESET>;
reset-names = "mss_restart", "pdc_reset";
qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;
qcom,spare-regs = <&tcsr_regs 0xb3e4>;
status = "disabled";
glink-edge {
interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
label = "modem";
qcom,remote-pid = <1>;
mboxes = <&apss_shared 12>;
};
};
sdhc_2: sdhci@8804000 {
compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
reg = <0 0x08804000 0 0x1000>;
......@@ -2117,10 +2476,45 @@ sdhc_2: sdhci@8804000 {
clocks = <&gcc GCC_SDCC2_APPS_CLK>,
<&gcc GCC_SDCC2_AHB_CLK>;
clock-names = "core", "iface";
power-domains = <&rpmhpd SC7180_CX>;
operating-points-v2 = <&sdhc2_opp_table>;
bus-width = <4>;
status = "disabled";
sdhc2_opp_table: sdhc2-opp-table {
compatible = "operating-points-v2";
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
required-opps = <&rpmhpd_opp_low_svs>;
};
opp-202000000 {
opp-hz = /bits/ 64 <202000000>;
required-opps = <&rpmhpd_opp_svs_l1>;
};
};
};
qspi_opp_table: qspi-opp-table {
compatible = "operating-points-v2";
opp-75000000 {
opp-hz = /bits/ 64 <75000000>;
required-opps = <&rpmhpd_opp_low_svs>;
};
opp-150000000 {
opp-hz = /bits/ 64 <150000000>;
required-opps = <&rpmhpd_opp_svs>;
};
opp-300000000 {
opp-hz = /bits/ 64 <300000000>;
required-opps = <&rpmhpd_opp_nom>;
};
};
qspi: spi@88dc000 {
......@@ -2132,6 +2526,11 @@ qspi: spi@88dc000 {
clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
<&gcc GCC_QSPI_CORE_CLK>;
clock-names = "iface", "core";
interconnects = <&gem_noc MASTER_APPSS_PROC
&config_noc SLAVE_QSPI_0>;
interconnect-names = "qspi-config";
power-domains = <&rpmhpd SC7180_CX>;
operating-points-v2 = <&qspi_opp_table>;
status = "disabled";
};
......@@ -2355,6 +2754,8 @@ mdp: mdp@ae01000 {
<19200000>,
<19200000>,
<19200000>;
operating-points-v2 = <&mdp_opp_table>;
power-domains = <&rpmhpd SC7180_CX>;
interrupt-parent = <&mdss>;
interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
......@@ -2372,6 +2773,31 @@ dpu_intf1_out: endpoint {
};
};
};
mdp_opp_table: mdp-opp-table {
compatible = "operating-points-v2";
opp-200000000 {
opp-hz = /bits/ 64 <200000000>;
required-opps = <&rpmhpd_opp_low_svs>;
};
opp-300000000 {
opp-hz = /bits/ 64 <300000000>;
required-opps = <&rpmhpd_opp_svs>;
};
opp-345000000 {
opp-hz = /bits/ 64 <345000000>;
required-opps = <&rpmhpd_opp_svs_l1>;
};
opp-460000000 {
opp-hz = /bits/ 64 <460000000>;
required-opps = <&rpmhpd_opp_nom>;
};
};
};
dsi0: dsi@ae94000 {
......@@ -2395,6 +2821,9 @@ dsi0: dsi@ae94000 {
"iface",
"bus";
operating-points-v2 = <&dsi_opp_table>;
power-domains = <&rpmhpd SC7180_CX>;
phys = <&dsi_phy>;
phy-names = "dsi";
......@@ -2420,6 +2849,25 @@ dsi0_out: endpoint {
};
};
};
dsi_opp_table: dsi-opp-table {
compatible = "operating-points-v2";
opp-187500000 {
opp-hz = /bits/ 64 <187500000>;
required-opps = <&rpmhpd_opp_low_svs>;
};
opp-300000000 {
opp-hz = /bits/ 64 <300000000>;
required-opps = <&rpmhpd_opp_svs>;
};
opp-358000000 {
opp-hz = /bits/ 64 <358000000>;
required-opps = <&rpmhpd_opp_svs_l1>;
};
};
};
dsi_phy: dsi-phy@ae94400 {
......@@ -2814,6 +3262,29 @@ cpufreq_hw: cpufreq@18323000 {
#freq-domain-cells = <1>;
};
wifi: wifi@18800000 {
compatible = "qcom,wcn3990-wifi";
reg = <0 0x18800000 0 0x800000>;
reg-names = "membase";
iommus = <&apps_smmu 0xc0 0x1>;
interrupts =
<GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH /* CE0 */ >,
<GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH /* CE1 */ >,
<GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH /* CE2 */ >,
<GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH /* CE3 */ >,
<GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH /* CE4 */ >,
<GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH /* CE5 */ >,
<GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH /* CE6 */ >,
<GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH /* CE7 */ >,
<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH /* CE8 */ >,
<GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH /* CE9 */ >,
<GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH /* CE10 */>,
<GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH /* CE11 */>;
memory-region = <&wlan_mem>;
qcom,msa-fixed-perm;
status = "disabled";
};
};
thermal-zones {
......
arch/arm64/boot/dts/qcom/sdm630-sony-xperia-ganges-kirin.dts 0 → 100644
View file @ c6e2e454
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2020, Martin Botka
*/
/dts-v1/;
#include "sdm630-sony-xperia-ganges.dtsi"
/ {
model = "Sony Xperia 10";
compatible = "sony,kirin-row", "qcom,sdm630";
};
arch/arm64/boot/dts/qcom/sdm630-sony-xperia-ganges.dtsi 0 → 100644
View file @ c6e2e454
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2020, Martin Botka
*/
/dts-v1/;
/* Ganges is very similar to Nile, but
* there are some differences that will need
* to be addresed when more peripherals are
* enabled upstream. Hence the separate DTSI.
*/
#include "sdm630-sony-xperia-nile.dtsi"
/ {
chosen {
framebuffer@9d400000 {
reg = <0 0x9d400000 0 (2520 * 1080 * 4)>;
height = <2520>;
};
};
/* Yes, this is intentional.
* Ganges devices only use gpio-keys for
* Volume Down, but currently there's an
* issue with it that has to be resolved.
* Until then, let's not make the kernel panic
*/
/delete-node/ gpio-keys;
soc {
i2c@c175000 {
status = "okay";
/* Novatek touchscreen */
};
};
};
arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile-discovery.dts 0 → 100644
View file @ c6e2e454
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2020, Konrad Dybcio
*/
/dts-v1/;
#include "sdm630-sony-xperia-nile.dtsi"
/ {
model = "Sony Xperia XA2 Ultra";
compatible = "sony,discovery-row", "qcom,sdm630";
};
arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile-pioneer.dts 0 → 100644
View file @ c6e2e454
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2020, Konrad Dybcio
*/
/dts-v1/;
#include "sdm630-sony-xperia-nile.dtsi"
/ {
model = "Sony Xperia XA2";
compatible = "sony,pioneer-row", "qcom,sdm630";
};
arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile-voyager.dts 0 → 100644
View file @ c6e2e454
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2020, Konrad Dybcio
*/
/dts-v1/;
#include "sdm630-sony-xperia-nile.dtsi"
/ {
model = "Sony Xperia XA2 Plus";
compatible = "sony,voyager-row", "qcom,sdm630";
chosen {
framebuffer@9d400000 {
reg = <0 0x9d400000 0 (2160 * 1080 * 4)>;
height = <2160>;
};
};
};
arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi 0 → 100644
View file @ c6e2e454
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2020, Konrad Dybcio
*/
/dts-v1/;
#include "sdm630.dtsi"
#include "pm660.dtsi"
#include "pm660l.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/input/gpio-keys.h>
/ {
/* required for bootloader to select correct board */
qcom,msm-id = <318 0>;
qcom,board-id = <8 1>;
qcom,pmic-id = <0x1001b 0x101011a 0x00 0x00 0x1001b 0x201011a 0x00 0x00>;
/* This part enables graphical output via bootloader-enabled display */
chosen {
bootargs = "earlycon=tty0 console=tty0";
#address-cells = <2>;
#size-cells = <2>;
ranges;
stdout-path = "framebuffer0";
framebuffer0: framebuffer@9d400000 {
compatible = "simple-framebuffer";
reg = <0 0x9d400000 0 (1920 * 1080 * 4)>;
width = <1080>;
height = <1920>;
stride = <(1080 * 4)>;
format = "a8r8g8b8";
status= "okay";
};
};
gpio_keys {
status = "okay";
compatible = "gpio-keys";
input-name = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
autorepeat;
camera_focus {
label = "Camera Focus";
gpios = <&tlmm 64 GPIO_ACTIVE_LOW>;
linux,input-type = <1>;
linux,code = <KEY_CAMERA_FOCUS>;
debounce-interval = <15>;
};
camera_snapshot {
label = "Camera Snapshot";
gpios = <&tlmm 113 GPIO_ACTIVE_LOW>;
linux,input-type = <1>;
linux,code = <KEY_CAMERA>;
debounce-interval = <15>;
};
vol_down {
label = "Volume Down";
gpios = <&pm660l_gpios 7 GPIO_ACTIVE_LOW>;
linux,input-type = <1>;
linux,code = <KEY_VOLUMEDOWN>;
gpio-key,wakeup;
debounce-interval = <15>;
};
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
ramoops@ffc00000 {
compatible = "ramoops";
reg = <0x0 0xffc00000 0x0 0x100000>;
record-size = <0x10000>;
console-size = <0x60000>;
ftrace-size = <0x10000>;
pmsg-size = <0x20000>;
ecc-size = <16>;
status = "okay";
};
debug_region@ffb00000 {
reg = <0x00 0xffb00000 0x00 0x100000>;
no-map;
};
removed_region@85800000 {
reg = <0x00 0x85800000 0x00 0x3700000>;
no-map;
};
};
soc {
sdhci@c0c4000 {
status = "okay";
mmc-ddr-1_8v;
/* SoMC Nile platform's eMMC doesn't support HS200 mode */
mmc-hs400-1_8v;
};
i2c@c175000 {
status = "okay";
/* Synaptics touchscreen */
};
i2c@c176000 {
status = "okay";
/* SMB1351 charger */
};
serial@c1af000 {
status = "okay";
};
/* I2C3, 4, 5, 7 and 8 are disabled on this board. */
i2c@c1b6000 {
status = "okay";
/* NXP NFC */
};
};
};
arch/arm64/boot/dts/qcom/sdm630.dtsi 0 → 100644
View file @ c6e2e454
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2020, Konrad Dybcio
*/
#include <dt-bindings/clock/qcom,gcc-sdm660.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
interrupt-parent = <&intc>;
#address-cells = <2>;
#size-cells = <2>;
chosen { };
clocks {
xo_board: xo_board {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <19200000>;
clock-output-names = "xo_board";
};
sleep_clk: sleep_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32764>;
clock-output-names = "sleep_clk";
};
};
cpus {
#address-cells = <2>;
#size-cells = <0>;
CPU0: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x100>;
enable-method = "psci";
cpu-idle-states = <&PERF_CPU_SLEEP_0
&PERF_CPU_SLEEP_1
&PERF_CLUSTER_SLEEP_0
&PERF_CLUSTER_SLEEP_1
&PERF_CLUSTER_SLEEP_2>;
capacity-dmips-mhz = <1126>;
#cooling-cells = <2>;
next-level-cache = <&L2_1>;
L2_1: l2-cache {
compatible = "cache";
cache-level = <2>;
};
};
CPU1: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x101>;
enable-method = "psci";
cpu-idle-states = <&PERF_CPU_SLEEP_0
&PERF_CPU_SLEEP_1
&PERF_CLUSTER_SLEEP_0
&PERF_CLUSTER_SLEEP_1
&PERF_CLUSTER_SLEEP_2>;
capacity-dmips-mhz = <1126>;
#cooling-cells = <2>;
next-level-cache = <&L2_1>;
};
CPU2: cpu@102 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x102>;
enable-method = "psci";
cpu-idle-states = <&PERF_CPU_SLEEP_0
&PERF_CPU_SLEEP_1
&PERF_CLUSTER_SLEEP_0
&PERF_CLUSTER_SLEEP_1
&PERF_CLUSTER_SLEEP_2>;
capacity-dmips-mhz = <1126>;
#cooling-cells = <2>;
next-level-cache = <&L2_1>;
};
CPU3: cpu@103 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x103>;
enable-method = "psci";
cpu-idle-states = <&PERF_CPU_SLEEP_0
&PERF_CPU_SLEEP_1
&PERF_CLUSTER_SLEEP_0
&PERF_CLUSTER_SLEEP_1
&PERF_CLUSTER_SLEEP_2>;
capacity-dmips-mhz = <1126>;
#cooling-cells = <2>;
next-level-cache = <&L2_1>;
};
CPU4: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x0>;
enable-method = "psci";
cpu-idle-states = <&PWR_CPU_SLEEP_0
&PWR_CPU_SLEEP_1
&PWR_CLUSTER_SLEEP_0
&PWR_CLUSTER_SLEEP_1
&PWR_CLUSTER_SLEEP_2>;
capacity-dmips-mhz = <1024>;
#cooling-cells = <2>;
next-level-cache = <&L2_0>;
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
};
};
CPU5: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x1>;
enable-method = "psci";
cpu-idle-states = <&PWR_CPU_SLEEP_0
&PWR_CPU_SLEEP_1
&PWR_CLUSTER_SLEEP_0
&PWR_CLUSTER_SLEEP_1
&PWR_CLUSTER_SLEEP_2>;
capacity-dmips-mhz = <1024>;
#cooling-cells = <2>;
next-level-cache = <&L2_0>;
};
CPU6: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x2>;
enable-method = "psci";
cpu-idle-states = <&PWR_CPU_SLEEP_0
&PWR_CPU_SLEEP_1
&PWR_CLUSTER_SLEEP_0
&PWR_CLUSTER_SLEEP_1
&PWR_CLUSTER_SLEEP_2>;
capacity-dmips-mhz = <1024>;
#cooling-cells = <2>;
next-level-cache = <&L2_0>;
};
CPU7: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x3>;
enable-method = "psci";
cpu-idle-states = <&PWR_CPU_SLEEP_0
&PWR_CPU_SLEEP_1
&PWR_CLUSTER_SLEEP_0
&PWR_CLUSTER_SLEEP_1
&PWR_CLUSTER_SLEEP_2>;
capacity-dmips-mhz = <1024>;
#cooling-cells = <2>;
next-level-cache = <&L2_0>;
};
cpu-map {
cluster0 {
core0 {
cpu = <&CPU4>;
};
core1 {
cpu = <&CPU5>;
};
core2 {
cpu = <&CPU6>;
};
core3 {
cpu = <&CPU7>;
};
};
cluster1 {
core0 {
cpu = <&CPU0>;
};
core1 {
cpu = <&CPU1>;
};
core2 {
cpu = <&CPU2>;
};
core3 {
cpu = <&CPU3>;
};
};
};
idle-states {
entry-method = "psci";
PWR_CPU_SLEEP_0: cpu-sleep-0-0 {
compatible = "arm,idle-state";
idle-state-name = "pwr-retention";
arm,psci-suspend-param = <0x40000002>;
entry-latency-us = <338>;
exit-latency-us = <423>;
min-residency-us = <200>;
};
PWR_CPU_SLEEP_1: cpu-sleep-0-1 {
compatible = "arm,idle-state";
idle-state-name = "pwr-power-collapse";
arm,psci-suspend-param = <0x40000003>;
entry-latency-us = <515>;
exit-latency-us = <1821>;
min-residency-us = <1000>;
local-timer-stop;
};
PERF_CPU_SLEEP_0: cpu-sleep-1-0 {
compatible = "arm,idle-state";
idle-state-name = "perf-retention";
arm,psci-suspend-param = <0x40000002>;
entry-latency-us = <154>;
exit-latency-us = <87>;
min-residency-us = <200>;
};
PERF_CPU_SLEEP_1: cpu-sleep-1-1 {
compatible = "arm,idle-state";
idle-state-name = "perf-power-collapse";
arm,psci-suspend-param = <0x40000003>;
entry-latency-us = <262>;
exit-latency-us = <301>;
min-residency-us = <1000>;
local-timer-stop;
};
PWR_CLUSTER_SLEEP_0: cluster-sleep-0-0 {
compatible = "arm,idle-state";
idle-state-name = "pwr-cluster-dynamic-retention";
arm,psci-suspend-param = <0x400000F2>;
entry-latency-us = <284>;
exit-latency-us = <384>;
min-residency-us = <9987>;
local-timer-stop;
};
PWR_CLUSTER_SLEEP_1: cluster-sleep-0-1 {
compatible = "arm,idle-state";
idle-state-name = "pwr-cluster-retention";
arm,psci-suspend-param = <0x400000F3>;
entry-latency-us = <338>;
exit-latency-us = <423>;
min-residency-us = <9987>;
local-timer-stop;
};
PWR_CLUSTER_SLEEP_2: cluster-sleep-0-2 {
compatible = "arm,idle-state";
idle-state-name = "pwr-cluster-retention";
arm,psci-suspend-param = <0x400000F4>;
entry-latency-us = <515>;
exit-latency-us = <1821>;
min-residency-us = <9987>;
local-timer-stop;
};
PERF_CLUSTER_SLEEP_0: cluster-sleep-1-0 {
compatible = "arm,idle-state";
idle-state-name = "perf-cluster-dynamic-retention";
arm,psci-suspend-param = <0x400000F2>;
entry-latency-us = <272>;
exit-latency-us = <329>;
min-residency-us = <9987>;
local-timer-stop;
};
PERF_CLUSTER_SLEEP_1: cluster-sleep-1-1 {
compatible = "arm,idle-state";
idle-state-name = "perf-cluster-retention";
arm,psci-suspend-param = <0x400000F3>;
entry-latency-us = <332>;
exit-latency-us = <368>;
min-residency-us = <9987>;
local-timer-stop;
};
PERF_CLUSTER_SLEEP_2: cluster-sleep-1-2 {
compatible = "arm,idle-state";
idle-state-name = "perf-cluster-retention";
arm,psci-suspend-param = <0x400000F4>;
entry-latency-us = <545>;
exit-latency-us = <1609>;
min-residency-us = <9987>;
local-timer-stop;
};
};
};
firmware {
scm {
compatible = "qcom,scm-msm8998", "qcom,scm";
};
};
memory {
device_type = "memory";
/* We expect the bootloader to fill in the reg */
reg = <0 0 0 0>;
};
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>;
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
wlan_msa_guard: wlan-msa-guard@85600000 {
reg = <0x0 0x85600000 0x0 0x100000>;
no-map;
};
wlan_msa_mem: wlan-msa-mem@85700000 {
reg = <0x0 0x85700000 0x0 0x100000>;
no-map;
};
qhee_code: qhee-code@85800000 {
reg = <0x0 0x85800000 0x0 0x3700000>;
no-map;
};
smem_region: smem-mem@86000000 {
reg = <0 0x86000000 0 0x200000>;
no-map;
};
tz_mem: memory@86200000 {
reg = <0x0 0x86200000 0x0 0x3300000>;
no-map;
};
modem_fw_mem: modem-fw-region@8ac00000 {
reg = <0x0 0x8ac00000 0x0 0x7e00000>;
no-map;
};
adsp_fw_mem: adsp-fw-region@92a00000 {
reg = <0x0 0x92a00000 0x0 0x1e00000>;
no-map;
};
pil_mba_mem: pil-mba-region@94800000 {
reg = <0x0 0x94800000 0x0 0x200000>;
no-map;
};
buffer_mem: buffer-region@94a00000 {
reg = <0x0 0x94a00000 0x0 0x100000>;
no-map;
};
venus_fw_mem: venus-fw-region@9f800000 {
reg = <0x0 0x9f800000 0x0 0x800000>;
no-map;
};
secure_region2: secure-region2@f7c00000 {
reg = <0x0 0xf7c00000 0x0 0x5c00000>;
no-map;
};
adsp_mem: adsp-region@f6000000 {
reg = <0x0 0xf6000000 0x0 0x800000>;
no-map;
};
qseecom_ta_mem: qseecom-ta-region@fec00000 {
reg = <0x0 0xfec00000 0x0 0x1000000>;
no-map;
};
qseecom_mem: qseecom-region@f6800000 {
reg = <0x0 0xf6800000 0x0 0x1400000>;
no-map;
};
secure_display_memory: secure-region@f5c00000 {
reg = <0x0 0xf5c00000 0x0 0x5c00000>;
no-map;
};
cont_splash_mem: cont-splash-region@9d400000 {
reg = <0x0 0x9d400000 0x0 0x23ff000>;
no-map;
};
};
rpm-glink {
compatible = "qcom,glink-rpm";
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
qcom,rpm-msg-ram = <&rpm_msg_ram>;
mboxes = <&apcs_glb 0>;
rpm_requests: rpm-requests {
compatible = "qcom,rpm-sdm660";
qcom,glink-channels = "rpm_requests";
rpmcc: clock-controller {
compatible = "qcom,rpmcc-sdm660", "qcom,rpmcc";
#clock-cells = <1>;
};
};
};
smem: smem {
compatible = "qcom,smem";
memory-region = <&smem_region>;
hwlocks = <&tcsr_mutex 3>;
};
soc {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0 0xffffffff>;
compatible = "simple-bus";
gcc: clock-controller@100000 {
compatible = "qcom,gcc-sdm630";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
reg = <0x00100000 0x94000>;
clock-names = "xo", "sleep_clk";
clocks = <&xo_board>,
<&sleep_clk>;
};
rpm_msg_ram: memory@778000 {
compatible = "qcom,rpm-msg-ram";
reg = <0x00778000 0x7000>;
};
qfprom: qfprom@780000 {
compatible = "qcom,qfprom";
reg = <0x00780000 0x621c>;
#address-cells = <1>;
#size-cells = <1>;
};
rng: rng@793000 {
compatible = "qcom,prng-ee";
reg = <0x00793000 0x1000>;
clocks = <&gcc GCC_PRNG_AHB_CLK>;
clock-names = "core";
};
restart@10ac000 {
compatible = "qcom,pshold";
reg = <0x010ac000 0x4>;
};
anoc2_smmu: iommu@16c0000 {
compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2";
reg = <0x016c0000 0x40000>;
#iommu-cells = <1>;
#global-interrupts = <2>;
interrupts =
<GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 374 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 375 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 376 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 377 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 378 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
};
tcsr_mutex_regs: syscon@1f40000 {
compatible = "syscon";
reg = <0x01f40000 0x20000>;
};
tlmm: pinctrl@3000000 {
compatible = "qcom,sdm630-pinctrl";
reg = <0x03000000 0xc00000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <0x2>;
interrupt-controller;
#interrupt-cells = <0x2>;
blsp1_uart1_default: blsp1-uart1-default {
pins = "gpio0", "gpio1", "gpio2", "gpio3";
drive-strength = <2>;
bias-disable;
};
blsp1_uart1_sleep: blsp1-uart1-sleep {
pins = "gpio0", "gpio1", "gpio2", "gpio3";
drive-strength = <2>;
bias-disable;
};
blsp1_uart2_default: blsp1-uart2-default {
pins = "gpio4", "gpio5";
drive-strength = <2>;
bias-disable;
};
blsp2_uart1_tx_active: blsp2-uart1-tx-active {
pins = "gpio16";
drive-strength = <2>;
bias-disable;
};
blsp2_uart1_tx_sleep: blsp2-uart1-tx-sleep {
pins = "gpio16";
drive-strength = <2>;
bias-pull-up;
};
blsp2_uart1_rxcts_active: blsp2-uart1-rxcts-active {
pins = "gpio17", "gpio18";
drive-strength = <2>;
bias-disable;
};
blsp2_uart1_rxcts_sleep: blsp2-uart1-rxcts-sleep {
pins = "gpio17", "gpio18";
drive-strength = <2>;
bias-no-pull;
};
blsp2_uart1_rfr_active: blsp2-uart1-rfr-active {
pins = "gpio19";
drive-strength = <2>;
bias-disable;
};
blsp2_uart1_rfr_sleep: blsp2-uart1-rfr-sleep {
pins = "gpio19";
drive-strength = <2>;
bias-no-pull;
};
i2c1_default: i2c1-default {
pins = "gpio2", "gpio3";
drive-strength = <2>;
bias-disable;
};
i2c1_sleep: i2c1-sleep {
pins = "gpio2", "gpio3";
drive-strength = <2>;
bias-pull-up;
};
i2c2_default: i2c2-default {
pins = "gpio6", "gpio7";
drive-strength = <2>;
bias-disable;
};
i2c2_sleep: i2c2-sleep {
pins = "gpio6", "gpio7";
drive-strength = <2>;
bias-pull-up;
};
i2c3_default: i2c3-default {
pins = "gpio10", "gpio11";
drive-strength = <2>;
bias-disable;
};
i2c3_sleep: i2c3-sleep {
pins = "gpio10", "gpio11";
drive-strength = <2>;
bias-pull-up;
};
i2c4_default: i2c4-default {
pins = "gpio14", "gpio15";
drive-strength = <2>;
bias-disable;
};
i2c4_sleep: i2c4-sleep {
pins = "gpio14", "gpio15";
drive-strength = <2>;
bias-pull-up;
};
i2c5_default: i2c5-default {
pins = "gpio18", "gpio19";
drive-strength = <2>;
bias-disable;
};
i2c5_sleep: i2c5-sleep {
pins = "gpio18", "gpio19";
drive-strength = <2>;
bias-pull-up;
};
i2c6_default: i2c6-default {
pins = "gpio22", "gpio23";
drive-strength = <2>;
bias-disable;
};
i2c6_sleep: i2c6-sleep {
pins = "gpio22", "gpio23";
drive-strength = <2>;
bias-pull-up;
};
i2c7_default: i2c7-default {
pins = "gpio26", "gpio27";
drive-strength = <2>;
bias-disable;
};
i2c7_sleep: i2c7-sleep {
pins = "gpio26", "gpio27";
drive-strength = <2>;
bias-pull-up;
};
i2c8_default: i2c8-default {
pins = "gpio30", "gpio31";
drive-strength = <2>;
bias-disable;
};
i2c8_sleep: i2c8-sleep {
pins = "gpio30", "gpio31";
drive-strength = <2>;
bias-pull-up;
};
sdc1_clk_on: sdc1-clk-on {
pins = "sdc1_clk";
bias-disable;
drive-strength = <16>;
};
sdc1_clk_off: sdc1-clk-off {
pins = "sdc1_clk";
bias-disable;
drive-strength = <2>;
};
sdc1_cmd_on: sdc1-cmd-on {
pins = "sdc1_cmd";
bias-pull-up;
drive-strength = <10>;
};
sdc1_cmd_off: sdc1-cmd-off {
pins = "sdc1_cmd";
bias-pull-up;
drive-strength = <2>;
};
sdc1_data_on: sdc1-data-on {
pins = "sdc1_data";
bias-pull-up;
drive-strength = <8>;
};
sdc1_data_off: sdc1-data-off {
pins = "sdc1_data";
bias-pull-up;
drive-strength = <2>;
};
sdc1_rclk_on: sdc1-rclk-on {
pins = "sdc1_rclk";
bias-pull-down;
};
sdc1_rclk_off: sdc1-rclk-off {
pins = "sdc1_rclk";
bias-pull-down;
};
};
kgsl_smmu: iommu@5040000 {
compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2";
reg = <0x05040000 0x10000>;
#iommu-cells = <1>;
#global-interrupts = <2>;
interrupts =
<GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>;
};
lpass_smmu: iommu@5100000 {
compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2";
reg = <0x05100000 0x40000>;
#iommu-cells = <1>;
#global-interrupts = <2>;
interrupts =
<GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
};
spmi_bus: spmi@800f000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0x0800f000 0x1000>,
<0x08400000 0x1000000>,
<0x09400000 0x1000000>,
<0x0a400000 0x220000>,
<0x0800a000 0x3000>;
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
interrupt-names = "periph_irq";
interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
qcom,ee = <0>;
qcom,channel = <0>;
#address-cells = <2>;
#size-cells = <0>;
interrupt-controller;
#interrupt-cells = <4>;
cell-index = <0>;
};
sdhc_1: sdhci@c0c4000 {
compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5";
reg = <0x0c0c4000 0x1000>,
<0x0c0c5000 0x1000>;
reg-names = "hc", "cqhci";
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
clocks = <&gcc GCC_SDCC1_APPS_CLK>,
<&gcc GCC_SDCC1_AHB_CLK>,
<&xo_board>;
clock-names = "core", "iface", "xo";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>;
pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>;
bus-width = <8>;
non-removable;
status = "disabled";
};
blsp1_dma: dma@c144000 {
compatible = "qcom,bam-v1.7.0";
reg = <0x0c144000 0x1f000>;
interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "bam_clk";
#dma-cells = <1>;
qcom,ee = <0>;
qcom,controlled-remotely;
num-channels = <18>;
qcom,num-ees = <4>;
};
blsp1_uart1: serial@c16f000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x0c16f000 0x200>;
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
dmas = <&blsp1_dma 0>, <&blsp1_dma 1>;
dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp1_uart1_default>;
pinctrl-1 = <&blsp1_uart1_sleep>;
status = "disabled";
};
blsp1_uart2: serial@c170000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x0c170000 0x1000>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
dmas = <&blsp1_dma 2>, <&blsp1_dma 3>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&blsp1_uart2_default>;
status = "disabled";
};
blsp_i2c1: i2c@c175000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x0c175000 0x600>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
clock-frequency = <400000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c1_default>;
pinctrl-1 = <&i2c1_sleep>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
blsp_i2c2: i2c@c176000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x0c176000 0x600>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
clock-frequency = <400000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c2_default>;
pinctrl-1 = <&i2c2_sleep>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
blsp_i2c3: i2c@c177000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x0c177000 0x600>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
clock-frequency = <400000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c3_default>;
pinctrl-1 = <&i2c3_sleep>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
blsp_i2c4: i2c@c178000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x0c178000 0x600>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
clock-frequency = <400000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c4_default>;
pinctrl-1 = <&i2c4_sleep>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
blsp2_dma: dma@c184000 {
compatible = "qcom,bam-v1.7.0";
reg = <0x0c184000 0x1f000>;
interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP2_AHB_CLK>;
clock-names = "bam_clk";
#dma-cells = <1>;
qcom,ee = <0>;
qcom,controlled-remotely;
num-channels = <18>;
qcom,num-ees = <4>;
};
blsp2_uart1: serial@c1af000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x0c1af000 0x200>;
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>,
<&gcc GCC_BLSP2_AHB_CLK>;
clock-names = "core", "iface";
dmas = <&blsp2_dma 0>, <&blsp2_dma 1>;
dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp2_uart1_tx_active &blsp2_uart1_rxcts_active
&blsp2_uart1_rfr_active>;
pinctrl-1 = <&blsp2_uart1_tx_sleep &blsp2_uart1_rxcts_sleep
&blsp2_uart1_rfr_sleep>;
status = "disabled";
};
blsp_i2c5: i2c@c1b5000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x0c1b5000 0x600>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
<&gcc GCC_BLSP2_AHB_CLK>;
clock-names = "core", "iface";
clock-frequency = <400000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c5_default>;
pinctrl-1 = <&i2c5_sleep>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
blsp_i2c6: i2c@c1b6000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x0c1b6000 0x600>;
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
<&gcc GCC_BLSP2_AHB_CLK>;
clock-names = "core", "iface";
clock-frequency = <400000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c6_default>;
pinctrl-1 = <&i2c6_sleep>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
blsp_i2c7: i2c@c1b7000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x0c1b7000 0x600>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
<&gcc GCC_BLSP2_AHB_CLK>;
clock-names = "core", "iface";
clock-frequency = <400000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c7_default>;
pinctrl-1 = <&i2c7_sleep>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
blsp_i2c8: i2c@c1b8000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x0c1b8000 0x600>;
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>,
<&gcc GCC_BLSP2_AHB_CLK>;
clock-names = "core", "iface";
clock-frequency = <400000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c8_default>;
pinctrl-1 = <&i2c8_sleep>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
mmss_smmu: iommu@cd00000 {
compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2";
reg = <0x0cd00000 0x40000>;
#iommu-cells = <1>;
#global-interrupts = <2>;
interrupts =
<GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>;
};
apcs_glb: mailbox@17911000 {
compatible = "qcom,sdm660-apcs-hmss-global";
reg = <0x17911000 0x1000>;
#mbox-cells = <1>;
};
timer@17920000 {
#address-cells = <1>;
#size-cells = <1>;
ranges;
compatible = "arm,armv7-timer-mem";
reg = <0x17920000 0x1000>;
clock-frequency = <19200000>;
frame@17921000 {
frame-number = <0>;
interrupts = <0 8 0x4>,
<0 7 0x4>;
reg = <0x17921000 0x1000>,
<0x17922000 0x1000>;
};
frame@17923000 {
frame-number = <1>;
interrupts = <0 9 0x4>;
reg = <0x17923000 0x1000>;
status = "disabled";
};
frame@17924000 {
frame-number = <2>;
interrupts = <0 10 0x4>;
reg = <0x17924000 0x1000>;
status = "disabled";
};
frame@17925000 {
frame-number = <3>;
interrupts = <0 11 0x4>;
reg = <0x17925000 0x1000>;
status = "disabled";
};
frame@17926000 {
frame-number = <4>;
interrupts = <0 12 0x4>;
reg = <0x17926000 0x1000>;
status = "disabled";
};
frame@17927000 {
frame-number = <5>;
interrupts = <0 13 0x4>;
reg = <0x17927000 0x1000>;
status = "disabled";
};
frame@17928000 {
frame-number = <6>;
interrupts = <0 14 0x4>;
reg = <0x17928000 0x1000>;
status = "disabled";
};
};
intc: interrupt-controller@17a00000 {
compatible = "arm,gic-v3";
reg = <0x17a00000 0x10000>, /* GICD */
<0x17b00000 0x100000>; /* GICR * 8 */
#interrupt-cells = <3>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
interrupt-controller;
#redistributor-regions = <1>;
redistributor-stride = <0x0 0x20000>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
};
tcsr_mutex: hwlock {
compatible = "qcom,tcsr-mutex";
syscon = <&tcsr_mutex_regs 0 0x1000>;
#hwlock-cells = <1>;
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 1 0xf08>,
<GIC_PPI 2 0xf08>,
<GIC_PPI 3 0xf08>,
<GIC_PPI 0 0xf08>;
};
};
arch/arm64/boot/dts/qcom/sdm636-sony-xperia-ganges-mermaid.dts 0 → 100644
View file @ c6e2e454
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2020, Martin Botka
*/
/dts-v1/;
/* Mermaid uses sdm636, but it's different ever so slightly
* that we can ignore it for the time being. Sony also commonizes
* the Ganges platform as a whole in downstream kernels.
*/
#include "sdm630-sony-xperia-ganges.dtsi"
/ {
model = "Sony Xperia 10 Plus";
compatible = "sony,mermaid-row", "qcom,sdm636";
qcom,msm-id = <345 0>;
qcom,pmic-id = <0x1001b 0x101011a 0x00 0x00 0x1001b 0x201011a 0x00 0x00 0x1001b 0x102001a 0x00 0x00>;
};
arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi
View file @ c6e2e454
......@@ -634,7 +634,7 @@ &mdss_mdp {
};
&mss_pil {
iommus = <&apps_smmu 0x780 0x1>,
iommus = <&apps_smmu 0x781 0x0>,
<&apps_smmu 0x724 0x3>;
};
......
arch/arm64/boot/dts/qcom/sdm845.dtsi
View file @ c6e2e454
......@@ -12,6 +12,7 @@
#include <dt-bindings/clock/qcom,lpass-sdm845.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,videocc-sdm845.h>
#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/interconnect/qcom,sdm845.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/phy/phy-qcom-qusb2.h>
......@@ -198,6 +199,9 @@ &LITTLE_CPU_SLEEP_1
capacity-dmips-mhz = <607>;
dynamic-power-coefficient = <100>;
qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gladiator_noc MASTER_APPSS_PROC &mem_noc SLAVE_EBI1>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
next-level-cache = <&L2_0>;
L2_0: l2-cache {
......@@ -220,6 +224,9 @@ &LITTLE_CPU_SLEEP_1
capacity-dmips-mhz = <607>;
dynamic-power-coefficient = <100>;
qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gladiator_noc MASTER_APPSS_PROC &mem_noc SLAVE_EBI1>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
next-level-cache = <&L2_100>;
L2_100: l2-cache {
......@@ -239,6 +246,9 @@ &LITTLE_CPU_SLEEP_1
capacity-dmips-mhz = <607>;
dynamic-power-coefficient = <100>;
qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gladiator_noc MASTER_APPSS_PROC &mem_noc SLAVE_EBI1>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
next-level-cache = <&L2_200>;
L2_200: l2-cache {
......@@ -258,6 +268,9 @@ &LITTLE_CPU_SLEEP_1
capacity-dmips-mhz = <607>;
dynamic-power-coefficient = <100>;
qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gladiator_noc MASTER_APPSS_PROC &mem_noc SLAVE_EBI1>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
next-level-cache = <&L2_300>;
L2_300: l2-cache {
......@@ -277,6 +290,9 @@ &BIG_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
dynamic-power-coefficient = <396>;
qcom,freq-domain = <&cpufreq_hw 1>;
operating-points-v2 = <&cpu4_opp_table>;
interconnects = <&gladiator_noc MASTER_APPSS_PROC &mem_noc SLAVE_EBI1>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
next-level-cache = <&L2_400>;
L2_400: l2-cache {
......@@ -296,6 +312,9 @@ &BIG_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
dynamic-power-coefficient = <396>;
qcom,freq-domain = <&cpufreq_hw 1>;
operating-points-v2 = <&cpu4_opp_table>;
interconnects = <&gladiator_noc MASTER_APPSS_PROC &mem_noc SLAVE_EBI1>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
next-level-cache = <&L2_500>;
L2_500: l2-cache {
......@@ -315,6 +334,9 @@ &BIG_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
dynamic-power-coefficient = <396>;
qcom,freq-domain = <&cpufreq_hw 1>;
operating-points-v2 = <&cpu4_opp_table>;
interconnects = <&gladiator_noc MASTER_APPSS_PROC &mem_noc SLAVE_EBI1>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
next-level-cache = <&L2_600>;
L2_600: l2-cache {
......@@ -334,6 +356,9 @@ &BIG_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
dynamic-power-coefficient = <396>;
qcom,freq-domain = <&cpufreq_hw 1>;
operating-points-v2 = <&cpu4_opp_table>;
interconnects = <&gladiator_noc MASTER_APPSS_PROC &mem_noc SLAVE_EBI1>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
next-level-cache = <&L2_700>;
L2_700: l2-cache {
......@@ -433,6 +458,266 @@ CLUSTER_SLEEP_0: cluster-sleep-0 {
};
};
cpu0_opp_table: cpu0_opp_table {
compatible = "operating-points-v2";
opp-shared;
cpu0_opp1: opp-300000000 {
opp-hz = /bits/ 64 <300000000>;
opp-peak-kBps = <800000 4800000>;
};
cpu0_opp2: opp-403200000 {
opp-hz = /bits/ 64 <403200000>;
opp-peak-kBps = <800000 4800000>;
};
cpu0_opp3: opp-480000000 {
opp-hz = /bits/ 64 <480000000>;
opp-peak-kBps = <800000 6451200>;
};
cpu0_opp4: opp-576000000 {
opp-hz = /bits/ 64 <576000000>;
opp-peak-kBps = <800000 6451200>;
};
cpu0_opp5: opp-652800000 {
opp-hz = /bits/ 64 <652800000>;
opp-peak-kBps = <800000 7680000>;
};
cpu0_opp6: opp-748800000 {
opp-hz = /bits/ 64 <748800000>;
opp-peak-kBps = <1804000 9216000>;
};
cpu0_opp7: opp-825600000 {
opp-hz = /bits/ 64 <825600000>;
opp-peak-kBps = <1804000 9216000>;
};
cpu0_opp8: opp-902400000 {
opp-hz = /bits/ 64 <902400000>;
opp-peak-kBps = <1804000 10444800>;
};
cpu0_opp9: opp-979200000 {
opp-hz = /bits/ 64 <979200000>;
opp-peak-kBps = <1804000 11980800>;
};
cpu0_opp10: opp-1056000000 {
opp-hz = /bits/ 64 <1056000000>;
opp-peak-kBps = <1804000 11980800>;
};
cpu0_opp11: opp-1132800000 {
opp-hz = /bits/ 64 <1132800000>;
opp-peak-kBps = <2188000 13516800>;
};
cpu0_opp12: opp-1228800000 {
opp-hz = /bits/ 64 <1228800000>;
opp-peak-kBps = <2188000 15052800>;
};
cpu0_opp13: opp-1324800000 {
opp-hz = /bits/ 64 <1324800000>;
opp-peak-kBps = <2188000 16588800>;
};
cpu0_opp14: opp-1420800000 {
opp-hz = /bits/ 64 <1420800000>;
opp-peak-kBps = <3072000 18124800>;
};
cpu0_opp15: opp-1516800000 {
opp-hz = /bits/ 64 <1516800000>;
opp-peak-kBps = <3072000 19353600>;
};
cpu0_opp16: opp-1612800000 {
opp-hz = /bits/ 64 <1612800000>;
opp-peak-kBps = <4068000 19353600>;
};
cpu0_opp17: opp-1689600000 {
opp-hz = /bits/ 64 <1689600000>;
opp-peak-kBps = <4068000 20889600>;
};
cpu0_opp18: opp-1766400000 {
opp-hz = /bits/ 64 <1766400000>;
opp-peak-kBps = <4068000 22425600>;
};
};
cpu4_opp_table: cpu4_opp_table {
compatible = "operating-points-v2";
opp-shared;
cpu4_opp1: opp-300000000 {
opp-hz = /bits/ 64 <300000000>;
opp-peak-kBps = <800000 4800000>;
};
cpu4_opp2: opp-403200000 {
opp-hz = /bits/ 64 <403200000>;
opp-peak-kBps = <800000 4800000>;
};
cpu4_opp3: opp-480000000 {
opp-hz = /bits/ 64 <480000000>;
opp-peak-kBps = <1804000 4800000>;
};
cpu4_opp4: opp-576000000 {
opp-hz = /bits/ 64 <576000000>;
opp-peak-kBps = <1804000 4800000>;
};
cpu4_opp5: opp-652800000 {
opp-hz = /bits/ 64 <652800000>;
opp-peak-kBps = <1804000 4800000>;
};
cpu4_opp6: opp-748800000 {
opp-hz = /bits/ 64 <748800000>;
opp-peak-kBps = <1804000 4800000>;
};
cpu4_opp7: opp-825600000 {
opp-hz = /bits/ 64 <825600000>;
opp-peak-kBps = <2188000 9216000>;
};
cpu4_opp8: opp-902400000 {
opp-hz = /bits/ 64 <902400000>;
opp-peak-kBps = <2188000 9216000>;
};
cpu4_opp9: opp-979200000 {
opp-hz = /bits/ 64 <979200000>;
opp-peak-kBps = <2188000 9216000>;
};
cpu4_opp10: opp-1056000000 {
opp-hz = /bits/ 64 <1056000000>;
opp-peak-kBps = <3072000 9216000>;
};
cpu4_opp11: opp-1132800000 {
opp-hz = /bits/ 64 <1132800000>;
opp-peak-kBps = <3072000 11980800>;
};
cpu4_opp12: opp-1209600000 {
opp-hz = /bits/ 64 <1209600000>;
opp-peak-kBps = <4068000 11980800>;
};
cpu4_opp13: opp-1286400000 {
opp-hz = /bits/ 64 <1286400000>;
opp-peak-kBps = <4068000 11980800>;
};
cpu4_opp14: opp-1363200000 {
opp-hz = /bits/ 64 <1363200000>;
opp-peak-kBps = <4068000 15052800>;
};
cpu4_opp15: opp-1459200000 {
opp-hz = /bits/ 64 <1459200000>;
opp-peak-kBps = <4068000 15052800>;
};
cpu4_opp16: opp-1536000000 {
opp-hz = /bits/ 64 <1536000000>;
opp-peak-kBps = <5412000 15052800>;
};
cpu4_opp17: opp-1612800000 {
opp-hz = /bits/ 64 <1612800000>;
opp-peak-kBps = <5412000 15052800>;
};
cpu4_opp18: opp-1689600000 {
opp-hz = /bits/ 64 <1689600000>;
opp-peak-kBps = <5412000 19353600>;
};
cpu4_opp19: opp-1766400000 {
opp-hz = /bits/ 64 <1766400000>;
opp-peak-kBps = <6220000 19353600>;
};
cpu4_opp20: opp-1843200000 {
opp-hz = /bits/ 64 <1843200000>;
opp-peak-kBps = <6220000 19353600>;
};
cpu4_opp21: opp-1920000000 {
opp-hz = /bits/ 64 <1920000000>;
opp-peak-kBps = <7216000 19353600>;
};
cpu4_opp22: opp-1996800000 {
opp-hz = /bits/ 64 <1996800000>;
opp-peak-kBps = <7216000 20889600>;
};
cpu4_opp23: opp-2092800000 {
opp-hz = /bits/ 64 <2092800000>;
opp-peak-kBps = <7216000 20889600>;
};
cpu4_opp24: opp-2169600000 {
opp-hz = /bits/ 64 <2169600000>;
opp-peak-kBps = <7216000 20889600>;
};
cpu4_opp25: opp-2246400000 {
opp-hz = /bits/ 64 <2246400000>;
opp-peak-kBps = <7216000 20889600>;
};
cpu4_opp26: opp-2323200000 {
opp-hz = /bits/ 64 <2323200000>;
opp-peak-kBps = <7216000 20889600>;
};
cpu4_opp27: opp-2400000000 {
opp-hz = /bits/ 64 <2400000000>;
opp-peak-kBps = <7216000 22425600>;
};
cpu4_opp28: opp-2476800000 {
opp-hz = /bits/ 64 <2476800000>;
opp-peak-kBps = <7216000 22425600>;
};
cpu4_opp29: opp-2553600000 {
opp-hz = /bits/ 64 <2553600000>;
opp-peak-kBps = <7216000 22425600>;
};
cpu4_opp30: opp-2649600000 {
opp-hz = /bits/ 64 <2649600000>;
opp-peak-kBps = <7216000 22425600>;
};
cpu4_opp31: opp-2745600000 {
opp-hz = /bits/ 64 <2745600000>;
opp-peak-kBps = <7216000 25497600>;
};
cpu4_opp32: opp-2803200000 {
opp-hz = /bits/ 64 <2803200000>;
opp-peak-kBps = <7216000 25497600>;
};
};
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
......@@ -805,6 +1090,25 @@ rng: rng@793000 {
clock-names = "core";
};
qup_opp_table: qup-opp-table {
compatible = "operating-points-v2";
opp-19200000 {
opp-hz = /bits/ 64 <19200000>;
required-opps = <&rpmhpd_opp_min_svs>;
};
opp-75000000 {
opp-hz = /bits/ 64 <75000000>;
required-opps = <&rpmhpd_opp_low_svs>;
};
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
required-opps = <&rpmhpd_opp_svs>;
};
};
qupv3_id_0: geniqup@8c0000 {
compatible = "qcom,geni-se-qup";
reg = <0 0x008c0000 0 0x6000>;
......@@ -826,6 +1130,8 @@ i2c0: i2c@880000 {
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&rpmhpd SDM845_CX>;
operating-points-v2 = <&qup_opp_table>;
status = "disabled";
};
......@@ -850,6 +1156,8 @@ uart0: serial@880000 {
pinctrl-names = "default";
pinctrl-0 = <&qup_uart0_default>;
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd SDM845_CX>;
operating-points-v2 = <&qup_opp_table>;
status = "disabled";
};
......@@ -863,6 +1171,8 @@ i2c1: i2c@884000 {
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&rpmhpd SDM845_CX>;
operating-points-v2 = <&qup_opp_table>;
status = "disabled";
};
......@@ -887,6 +1197,8 @@ uart1: serial@884000 {
pinctrl-names = "default";
pinctrl-0 = <&qup_uart1_default>;
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd SDM845_CX>;
operating-points-v2 = <&qup_opp_table>;
status = "disabled";
};
......@@ -900,6 +1212,8 @@ i2c2: i2c@888000 {
interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&rpmhpd SDM845_CX>;
operating-points-v2 = <&qup_opp_table>;
status = "disabled";
};
......@@ -924,6 +1238,8 @@ uart2: serial@888000 {
pinctrl-names = "default";
pinctrl-0 = <&qup_uart2_default>;
interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd SDM845_CX>;
operating-points-v2 = <&qup_opp_table>;
status = "disabled";
};
......@@ -937,6 +1253,8 @@ i2c3: i2c@88c000 {
interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&rpmhpd SDM845_CX>;
operating-points-v2 = <&qup_opp_table>;
status = "disabled";
};
......@@ -961,6 +1279,8 @@ uart3: serial@88c000 {
pinctrl-names = "default";
pinctrl-0 = <&qup_uart3_default>;
interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd SDM845_CX>;
operating-points-v2 = <&qup_opp_table>;
status = "disabled";
};
......@@ -974,6 +1294,8 @@ i2c4: i2c@890000 {
interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&rpmhpd SDM845_CX>;
operating-points-v2 = <&qup_opp_table>;
status = "disabled";
};
......@@ -998,6 +1320,8 @@ uart4: serial@890000 {
pinctrl-names = "default";
pinctrl-0 = <&qup_uart4_default>;
interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd SDM845_CX>;
operating-points-v2 = <&qup_opp_table>;
status = "disabled";
};
......@@ -1011,6 +1335,8 @@ i2c5: i2c@894000 {
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&rpmhpd SDM845_CX>;
operating-points-v2 = <&qup_opp_table>;
status = "disabled";
};
......@@ -1035,6 +1361,8 @@ uart5: serial@894000 {
pinctrl-names = "default";
pinctrl-0 = <&qup_uart5_default>;
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd SDM845_CX>;
operating-points-v2 = <&qup_opp_table>;
status = "disabled";
};
......@@ -1048,6 +1376,8 @@ i2c6: i2c@898000 {
interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&rpmhpd SDM845_CX>;
operating-points-v2 = <&qup_opp_table>;
status = "disabled";
};
......@@ -1072,6 +1402,8 @@ uart6: serial@898000 {
pinctrl-names = "default";
pinctrl-0 = <&qup_uart6_default>;
interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd SDM845_CX>;
operating-points-v2 = <&qup_opp_table>;
status = "disabled";
};
......@@ -1085,6 +1417,8 @@ i2c7: i2c@89c000 {
interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&rpmhpd SDM845_CX>;
operating-points-v2 = <&qup_opp_table>;
status = "disabled";
};
......@@ -1109,6 +1443,8 @@ uart7: serial@89c000 {
pinctrl-names = "default";
pinctrl-0 = <&qup_uart7_default>;
interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd SDM845_CX>;
operating-points-v2 = <&qup_opp_table>;
status = "disabled";
};
};
......@@ -1134,6 +1470,8 @@ i2c8: i2c@a80000 {
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&rpmhpd SDM845_CX>;
operating-points-v2 = <&qup_opp_table>;
status = "disabled";
};
......@@ -1158,6 +1496,8 @@ uart8: serial@a80000 {
pinctrl-names = "default";
pinctrl-0 = <&qup_uart8_default>;
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd SDM845_CX>;
operating-points-v2 = <&qup_opp_table>;
status = "disabled";
};
......@@ -1171,6 +1511,8 @@ i2c9: i2c@a84000 {
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&rpmhpd SDM845_CX>;
operating-points-v2 = <&qup_opp_table>;
status = "disabled";
};
......@@ -1195,6 +1537,8 @@ uart9: serial@a84000 {
pinctrl-names = "default";
pinctrl-0 = <&qup_uart9_default>;
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd SDM845_CX>;
operating-points-v2 = <&qup_opp_table>;
status = "disabled";
};
......@@ -1208,6 +1552,8 @@ i2c10: i2c@a88000 {
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&rpmhpd SDM845_CX>;
operating-points-v2 = <&qup_opp_table>;
status = "disabled";
};
......@@ -1232,6 +1578,8 @@ uart10: serial@a88000 {
pinctrl-names = "default";
pinctrl-0 = <&qup_uart10_default>;
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd SDM845_CX>;
operating-points-v2 = <&qup_opp_table>;
status = "disabled";
};
......@@ -1245,6 +1593,8 @@ i2c11: i2c@a8c000 {
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&rpmhpd SDM845_CX>;
operating-points-v2 = <&qup_opp_table>;
status = "disabled";
};
......@@ -1269,6 +1619,8 @@ uart11: serial@a8c000 {
pinctrl-names = "default";
pinctrl-0 = <&qup_uart11_default>;
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd SDM845_CX>;
operating-points-v2 = <&qup_opp_table>;
status = "disabled";
};
......@@ -1282,6 +1634,8 @@ i2c12: i2c@a90000 {
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&rpmhpd SDM845_CX>;
operating-points-v2 = <&qup_opp_table>;
status = "disabled";
};
......@@ -1306,6 +1660,8 @@ uart12: serial@a90000 {
pinctrl-names = "default";
pinctrl-0 = <&qup_uart12_default>;
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd SDM845_CX>;
operating-points-v2 = <&qup_opp_table>;
status = "disabled";
};
......@@ -1319,6 +1675,8 @@ i2c13: i2c@a94000 {
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&rpmhpd SDM845_CX>;
operating-points-v2 = <&qup_opp_table>;
status = "disabled";
};
......@@ -1343,6 +1701,8 @@ uart13: serial@a94000 {
pinctrl-names = "default";
pinctrl-0 = <&qup_uart13_default>;
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd SDM845_CX>;
operating-points-v2 = <&qup_opp_table>;
status = "disabled";
};
......@@ -1356,6 +1716,8 @@ i2c14: i2c@a98000 {
interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&rpmhpd SDM845_CX>;
operating-points-v2 = <&qup_opp_table>;
status = "disabled";
};
......@@ -1380,6 +1742,8 @@ uart14: serial@a98000 {
pinctrl-names = "default";
pinctrl-0 = <&qup_uart14_default>;
interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd SDM845_CX>;
operating-points-v2 = <&qup_opp_table>;
status = "disabled";
};
......@@ -1393,6 +1757,8 @@ i2c15: i2c@a9c000 {
interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&rpmhpd SDM845_CX>;
operating-points-v2 = <&qup_opp_table>;
status = "disabled";
};
......@@ -1417,6 +1783,8 @@ uart15: serial@a9c000 {
pinctrl-names = "default";
pinctrl-0 = <&qup_uart15_default>;
interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd SDM845_CX>;
operating-points-v2 = <&qup_opp_table>;
status = "disabled";
};
};
......@@ -1692,7 +2060,9 @@ mmss_noc: interconnect@1740000 {
ufs_mem_hc: ufshc@1d84000 {
compatible = "qcom,sdm845-ufshc", "qcom,ufshc",
"jedec,ufs-2.0";
reg = <0 0x01d84000 0 0x2500>;
reg = <0 0x01d84000 0 0x2500>,
<0 0x01d90000 0 0x8000>;
reg-names = "std", "ice";
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
phys = <&ufs_mem_phy_lanes>;
phy-names = "ufsphy";
......@@ -1712,7 +2082,8 @@ ufs_mem_hc: ufshc@1d84000 {
"ref_clk",
"tx_lane0_sync_clk",
"rx_lane0_sync_clk",
"rx_lane1_sync_clk";
"rx_lane1_sync_clk",
"ice_core_clk";
clocks =
<&gcc GCC_UFS_PHY_AXI_CLK>,
<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
......@@ -1721,7 +2092,8 @@ ufs_mem_hc: ufshc@1d84000 {
<&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
<&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
freq-table-hz =
<50000000 200000000>,
<0 0>,
......@@ -1730,7 +2102,8 @@ ufs_mem_hc: ufshc@1d84000 {
<0 0>,
<0 0>,
<0 0>,
<0 0>;
<0 0>,
<0 300000000>;
status = "disabled";
};
......@@ -2911,8 +3284,58 @@ sdhc_2: sdhci@8804000 {
<&gcc GCC_SDCC2_APPS_CLK>;
clock-names = "iface", "core";
iommus = <&apps_smmu 0xa0 0xf>;
power-domains = <&rpmhpd SDM845_CX>;
operating-points-v2 = <&sdhc2_opp_table>;
status = "disabled";
sdhc2_opp_table: sdhc2-opp-table {
compatible = "operating-points-v2";
opp-9600000 {
opp-hz = /bits/ 64 <9600000>;
required-opps = <&rpmhpd_opp_min_svs>;
};
opp-19200000 {
opp-hz = /bits/ 64 <19200000>;
required-opps = <&rpmhpd_opp_low_svs>;
};
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
required-opps = <&rpmhpd_opp_svs>;
};
opp-201500000 {
opp-hz = /bits/ 64 <201500000>;
required-opps = <&rpmhpd_opp_svs_l1>;
};
};
};
qspi_opp_table: qspi-opp-table {
compatible = "operating-points-v2";
opp-19200000 {
opp-hz = /bits/ 64 <19200000>;
required-opps = <&rpmhpd_opp_min_svs>;
};
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
required-opps = <&rpmhpd_opp_low_svs>;
};
opp-150000000 {
opp-hz = /bits/ 64 <150000000>;
required-opps = <&rpmhpd_opp_svs>;
};
opp-300000000 {
opp-hz = /bits/ 64 <300000000>;
required-opps = <&rpmhpd_opp_nom>;
};
};
qspi: spi@88df000 {
......@@ -2924,6 +3347,8 @@ qspi: spi@88df000 {
clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
<&gcc GCC_QSPI_CORE_CLK>;
clock-names = "iface", "core";
power-domains = <&rpmhpd SDM845_CX>;
operating-points-v2 = <&qspi_opp_table>;
status = "disabled";
};
......@@ -3296,6 +3721,35 @@ clock_camcc: clock-controller@ad00000 {
#power-domain-cells = <1>;
};
dsi_opp_table: dsi-opp-table {
compatible = "operating-points-v2";
opp-19200000 {
opp-hz = /bits/ 64 <19200000>;
required-opps = <&rpmhpd_opp_min_svs>;
};
opp-180000000 {
opp-hz = /bits/ 64 <180000000>;
required-opps = <&rpmhpd_opp_low_svs>;
};
opp-275000000 {
opp-hz = /bits/ 64 <275000000>;
required-opps = <&rpmhpd_opp_svs>;
};
opp-328580000 {
opp-hz = /bits/ 64 <328580000>;
required-opps = <&rpmhpd_opp_svs_l1>;
};
opp-358000000 {
opp-hz = /bits/ 64 <358000000>;
required-opps = <&rpmhpd_opp_nom>;
};
};
mdss: mdss@ae00000 {
compatible = "qcom,sdm845-mdss";
reg = <0 0x0ae00000 0 0x1000>;
......@@ -3340,6 +3794,8 @@ mdss_mdp: mdp@ae01000 {
<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
assigned-clock-rates = <300000000>,
<19200000>;
operating-points-v2 = <&mdp_opp_table>;
power-domains = <&rpmhpd SDM845_CX>;
interrupt-parent = <&mdss>;
interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
......@@ -3364,6 +3820,30 @@ dpu_intf2_out: endpoint {
};
};
};
mdp_opp_table: mdp-opp-table {
compatible = "operating-points-v2";
opp-19200000 {
opp-hz = /bits/ 64 <19200000>;
required-opps = <&rpmhpd_opp_min_svs>;
};
opp-171428571 {
opp-hz = /bits/ 64 <171428571>;
required-opps = <&rpmhpd_opp_low_svs>;
};
opp-344000000 {
opp-hz = /bits/ 64 <344000000>;
required-opps = <&rpmhpd_opp_svs_l1>;
};
opp-430000000 {
opp-hz = /bits/ 64 <430000000>;
required-opps = <&rpmhpd_opp_nom>;
};
};
};
dsi0: dsi@ae94000 {
......@@ -3386,6 +3866,8 @@ dsi0: dsi@ae94000 {
"core",
"iface",
"bus";
operating-points-v2 = <&dsi_opp_table>;
power-domains = <&rpmhpd SDM845_CX>;
phys = <&dsi0_phy>;
phy-names = "dsi";
......@@ -3450,6 +3932,8 @@ dsi1: dsi@ae96000 {
"core",
"iface",
"bus";
operating-points-v2 = <&dsi_opp_table>;
power-domains = <&rpmhpd SDM845_CX>;
phys = <&dsi1_phy>;
phy-names = "dsi";
......@@ -3724,6 +4208,21 @@ spmi_bus: spmi@c440000 {
cell-index = <0>;
};
imem@146bf000 {
compatible = "simple-mfd";
reg = <0 0x146bf000 0 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0x146bf000 0x1000>;
pil-reloc@94c {
compatible = "qcom,pil-reloc-info";
reg = <0x94c 0xc8>;
};
};
apps_smmu: iommu@15000000 {
compatible = "qcom,sdm845-smmu-500", "arm,mmu-500";
reg = <0 0x15000000 0 0x80000>;
......
arch/arm64/boot/dts/qcom/sm8150-mtp.dts
View file @ c6e2e454
......@@ -408,3 +408,24 @@ &ufs_mem_phy {
vdda-pll-supply = <&vreg_l3c_1p2>;
vdda-pll-max-microamp = <19000>;
};
&usb_1_hsphy {
status = "okay";
vdda-pll-supply = <&vdd_usb_hs_core>;
vdda33-supply = <&vdda_usb_hs_3p1>;
vdda18-supply = <&vdda_usb_hs_1p8>;
};
&usb_1_qmpphy {
status = "okay";
vdda-phy-supply = <&vreg_l3c_1p2>;
vdda-pll-supply = <&vdda_usb_ss_dp_core_1>;
};
&usb_1 {
status = "okay";
};
&usb_1_dwc3 {
dr_mode = "peripheral";
};
arch/arm64/boot/dts/qcom/sm8150.dtsi
View file @ c6e2e454
......@@ -10,6 +10,7 @@
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,gcc-sm8150.h>
#include <dt-bindings/thermal/thermal.h>
/ {
interrupt-parent = <&intc>;
......@@ -46,6 +47,7 @@ CPU0: cpu@0 {
enable-method = "psci";
next-level-cache = <&L2_0>;
qcom,freq-domain = <&cpufreq_hw 0>;
#cooling-cells = <2>;
L2_0: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
......@@ -62,6 +64,7 @@ CPU1: cpu@100 {
enable-method = "psci";
next-level-cache = <&L2_100>;
qcom,freq-domain = <&cpufreq_hw 0>;
#cooling-cells = <2>;
L2_100: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
......@@ -76,6 +79,7 @@ CPU2: cpu@200 {
enable-method = "psci";
next-level-cache = <&L2_200>;
qcom,freq-domain = <&cpufreq_hw 0>;
#cooling-cells = <2>;
L2_200: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
......@@ -89,6 +93,7 @@ CPU3: cpu@300 {
enable-method = "psci";
next-level-cache = <&L2_300>;
qcom,freq-domain = <&cpufreq_hw 0>;
#cooling-cells = <2>;
L2_300: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
......@@ -102,6 +107,7 @@ CPU4: cpu@400 {
enable-method = "psci";
next-level-cache = <&L2_400>;
qcom,freq-domain = <&cpufreq_hw 1>;
#cooling-cells = <2>;
L2_400: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
......@@ -115,6 +121,7 @@ CPU5: cpu@500 {
enable-method = "psci";
next-level-cache = <&L2_500>;
qcom,freq-domain = <&cpufreq_hw 1>;
#cooling-cells = <2>;
L2_500: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
......@@ -128,6 +135,7 @@ CPU6: cpu@600 {
enable-method = "psci";
next-level-cache = <&L2_600>;
qcom,freq-domain = <&cpufreq_hw 1>;
#cooling-cells = <2>;
L2_600: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
......@@ -141,6 +149,7 @@ CPU7: cpu@700 {
enable-method = "psci";
next-level-cache = <&L2_700>;
qcom,freq-domain = <&cpufreq_hw 2>;
#cooling-cells = <2>;
L2_700: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
......@@ -621,6 +630,98 @@ glink-edge {
};
};
usb_1_hsphy: phy@88e2000 {
compatible = "qcom,sm8150-usb-hs-phy",
"qcom,usb-snps-hs-7nm-phy";
reg = <0 0x088e2000 0 0x400>;
status = "disabled";
#phy-cells = <0>;
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "ref";
resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
};
usb_1_qmpphy: phy@88e9000 {
compatible = "qcom,sm8150-qmp-usb3-phy";
reg = <0 0x088e9000 0 0x18c>,
<0 0x088e8000 0 0x10>;
reg-names = "reg-base", "dp_com";
status = "disabled";
#clock-cells = <1>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
<&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_USB3_PRIM_CLKREF_CLK>,
<&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
clock-names = "aux", "ref_clk_src", "ref", "com_aux";
resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
<&gcc GCC_USB3_PHY_PRIM_BCR>;
reset-names = "phy", "common";
usb_1_ssphy: lanes@88e9200 {
reg = <0 0x088e9200 0 0x200>,
<0 0x088e9400 0 0x200>,
<0 0x088e9c00 0 0x218>,
<0 0x088e9600 0 0x200>,
<0 0x088e9800 0 0x200>,
<0 0x088e9a00 0 0x100>;
#phy-cells = <0>;
clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
clock-names = "pipe0";
clock-output-names = "usb3_phy_pipe_clk_src";
};
};
usb_1: usb@a6f8800 {
compatible = "qcom,sm8150-dwc3", "qcom,dwc3";
reg = <0 0x0a6f8800 0 0x400>;
status = "disabled";
#address-cells = <2>;
#size-cells = <2>;
ranges;
dma-ranges;
clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
<&gcc GCC_USB30_PRIM_MASTER_CLK>,
<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
<&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
<&gcc GCC_USB30_PRIM_SLEEP_CLK>,
<&gcc GCC_USB3_SEC_CLKREF_CLK>;
clock-names = "cfg_noc", "core", "iface", "mock_utmi",
"sleep", "xo";
assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
<&gcc GCC_USB30_PRIM_MASTER_CLK>;
assigned-clock-rates = <19200000>, <150000000>;
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hs_phy_irq", "ss_phy_irq",
"dm_hs_phy_irq", "dp_hs_phy_irq";
power-domains = <&gcc USB30_PRIM_GDSC>;
resets = <&gcc GCC_USB30_PRIM_BCR>;
usb_1_dwc3: dwc3@a600000 {
compatible = "snps,dwc3";
reg = <0 0x0a600000 0 0xcd00>;
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
phy-names = "usb2-phy", "usb3-phy";
};
};
aoss_qmp: power-controller@c300000 {
compatible = "qcom,sm8150-aoss-qmp";
reg = <0x0 0x0c300000 0x0 0x100000>;
......@@ -631,6 +732,28 @@ aoss_qmp: power-controller@c300000 {
#power-domain-cells = <1>;
};
tsens0: thermal-sensor@c263000 {
compatible = "qcom,sm8150-tsens", "qcom,tsens-v2";
reg = <0 0x0c263000 0 0x1ff>, /* TM */
<0 0x0c222000 0 0x1ff>; /* SROT */
#qcom,sensors = <16>;
interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "uplow", "critical";
#thermal-sensor-cells = <1>;
};
tsens1: thermal-sensor@c265000 {
compatible = "qcom,sm8150-tsens", "qcom,tsens-v2";
reg = <0 0x0c265000 0 0x1ff>, /* TM */
<0 0x0c223000 0 0x1ff>; /* SROT */
#qcom,sensors = <8>;
interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "uplow", "critical";
#thermal-sensor-cells = <1>;
};
spmi_bus: spmi@c440000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0x0 0x0c440000 0x0 0x0001100>,
......@@ -864,4 +987,784 @@ timer {
<GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
};
thermal-zones {
cpu0-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens0 1>;
trips {
cpu0_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "passive";
};
cpu0_alert1: trip-point1 {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
cpu0_crit: cpu_crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu0_alert0>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu0_alert1>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cpu1-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens0 2>;
trips {
cpu1_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "passive";
};
cpu1_alert1: trip-point1 {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
cpu1_crit: cpu_crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu1_alert0>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu1_alert1>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cpu2-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens0 3>;
trips {
cpu2_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "passive";
};
cpu2_alert1: trip-point1 {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
cpu2_crit: cpu_crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu2_alert0>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu2_alert1>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cpu3-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens0 4>;
trips {
cpu3_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "passive";
};
cpu3_alert1: trip-point1 {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
cpu3_crit: cpu_crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu3_alert0>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu3_alert1>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cpu4-top-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens0 7>;
trips {
cpu4_top_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "passive";
};
cpu4_top_alert1: trip-point1 {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
cpu4_top_crit: cpu_crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu4_top_alert0>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu4_top_alert1>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cpu5-top-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens0 8>;
trips {
cpu5_top_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "passive";
};
cpu5_top_alert1: trip-point1 {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
cpu5_top_crit: cpu_crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu5_top_alert0>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu5_top_alert1>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cpu6-top-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens0 9>;
trips {
cpu6_top_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "passive";
};
cpu6_top_alert1: trip-point1 {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
cpu6_top_crit: cpu_crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu6_top_alert0>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu6_top_alert1>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cpu7-top-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens0 10>;
trips {
cpu7_top_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "passive";
};
cpu7_top_alert1: trip-point1 {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
cpu7_top_crit: cpu_crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu7_top_alert0>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu7_top_alert1>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cpu4-bottom-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens0 11>;
trips {
cpu4_bottom_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "passive";
};
cpu4_bottom_alert1: trip-point1 {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
cpu4_bottom_crit: cpu_crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu4_bottom_alert0>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu4_bottom_alert1>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cpu5-bottom-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens0 12>;
trips {
cpu5_bottom_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "passive";
};
cpu5_bottom_alert1: trip-point1 {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
cpu5_bottom_crit: cpu_crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu5_bottom_alert0>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu5_bottom_alert1>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cpu6-bottom-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens0 13>;
trips {
cpu6_bottom_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "passive";
};
cpu6_bottom_alert1: trip-point1 {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
cpu6_bottom_crit: cpu_crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu6_bottom_alert0>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu6_bottom_alert1>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cpu7-bottom-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens0 14>;
trips {
cpu7_bottom_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "passive";
};
cpu7_bottom_alert1: trip-point1 {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
cpu7_bottom_crit: cpu_crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu7_bottom_alert0>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu7_bottom_alert1>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
aoss0-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens0 0>;
trips {
aoss0_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
};
};
};
cluster0-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens0 5>;
trips {
cluster0_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
};
cluster0_crit: cluster0_crit {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
};
};
};
cluster1-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens0 6>;
trips {
cluster1_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
};
cluster1_crit: cluster1_crit {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
};
};
};
gpu-thermal-top {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens0 15>;
trips {
gpu1_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
};
};
};
aoss1-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens1 0>;
trips {
aoss1_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
};
};
};
wlan-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens1 1>;
trips {
wlan_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
};
};
};
video-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens1 2>;
trips {
video_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
};
};
};
mem-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens1 3>;
trips {
mem_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
};
};
};
q6-hvx-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens1 4>;
trips {
q6_hvx_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
};
};
};
camera-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens1 5>;
trips {
camera_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
};
};
};
compute-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens1 6>;
trips {
compute_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
};
};
};
modem-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens1 7>;
trips {
modem_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
};
};
};
npu-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens1 8>;
trips {
npu_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
};
};
};
modem-vec-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens1 9>;
trips {
modem_vec_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
};
};
};
modem-scl-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens1 10>;
trips {
modem_scl_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
};
};
};
gpu-thermal-bottom {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens1 11>;
trips {
gpu2_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
};
};
};
};
};
arch/arm64/boot/dts/qcom/sm8250-mtp.dts
View file @ c6e2e454
......@@ -7,6 +7,10 @@
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include "sm8250.dtsi"
#include "pm8150.dtsi"
#include "pm8150b.dtsi"
#include "pm8150l.dtsi"
#include "pm8009.dtsi"
/ {
model = "Qualcomm Technologies, Inc. SM8250 MTP";
......@@ -51,6 +55,11 @@ vreg_s6c_0p88: smpc6-regulator {
};
};
&adsp {
status = "okay";
firmware-name = "qcom/sm8250/adsp.mbn";
};
&apps_rsc {
pm8150-rpmh-regulators {
compatible = "qcom,pm8150-rpmh-regulators";
......@@ -136,13 +145,6 @@ vreg_l10a_1p8: ldo10 {
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l11a_0p75: ldo11 {
regulator-name = "vreg_l11a_0p75";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l12a_1p8: ldo12 {
regulator-name = "vreg_l12a_1p8";
regulator-min-microvolt = <1800000>;
......@@ -351,10 +353,24 @@ vreg_l7f_1p8: ldo7 {
};
};
&cdsp {
status = "okay";
firmware-name = "qcom/sm8250/cdsp.mbn";
};
&qupv3_id_1 {
status = "okay";
};
&slpi {
status = "okay";
firmware-name = "qcom/sm8250/slpi.mbn";
};
&tlmm {
gpio-reserved-ranges = <28 4>, <40 4>;
};
&uart2 {
status = "okay";
};
......
arch/arm64/boot/dts/qcom/sm8250.dtsi
View file @ c6e2e454
......@@ -6,6 +6,8 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-sm8250.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
#include <dt-bindings/power/qcom-aoss-qmp.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
......@@ -15,6 +17,49 @@ / {
#address-cells = <2>;
#size-cells = <2>;
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
i2c5 = &i2c5;
i2c6 = &i2c6;
i2c7 = &i2c7;
i2c8 = &i2c8;
i2c9 = &i2c9;
i2c10 = &i2c10;
i2c11 = &i2c11;
i2c12 = &i2c12;
i2c13 = &i2c13;
i2c14 = &i2c14;
i2c15 = &i2c15;
i2c16 = &i2c16;
i2c17 = &i2c17;
i2c18 = &i2c18;
i2c19 = &i2c19;
spi0 = &spi0;
spi1 = &spi1;
spi2 = &spi2;
spi3 = &spi3;
spi4 = &spi4;
spi5 = &spi5;
spi6 = &spi6;
spi7 = &spi7;
spi8 = &spi8;
spi9 = &spi9;
spi10 = &spi10;
spi11 = &spi11;
spi12 = &spi12;
spi13 = &spi13;
spi14 = &spi14;
spi15 = &spi15;
spi16 = &spi16;
spi17 = &spi17;
spi18 = &spi18;
spi19 = &spi19;
};
chosen { };
clocks {
......@@ -144,12 +189,6 @@ scm: scm {
};
};
tcsr_mutex: hwlock {
compatible = "qcom,tcsr-mutex";
syscon = <&tcsr_mutex_regs 0 0x1000>;
#hwlock-cells = <1>;
};
memory@80000000 {
device_type = "memory";
/* We expect the bootloader to fill in the size */
......@@ -269,6 +308,78 @@ smem: qcom,smem {
hwlocks = <&tcsr_mutex 3>;
};
smp2p-adsp {
compatible = "qcom,smp2p";
qcom,smem = <443>, <429>;
interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
IPCC_MPROC_SIGNAL_SMP2P
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc IPCC_CLIENT_LPASS
IPCC_MPROC_SIGNAL_SMP2P>;
qcom,local-pid = <0>;
qcom,remote-pid = <2>;
smp2p_adsp_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
smp2p_adsp_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
};
smp2p-cdsp {
compatible = "qcom,smp2p";
qcom,smem = <94>, <432>;
interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
IPCC_MPROC_SIGNAL_SMP2P
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc IPCC_CLIENT_CDSP
IPCC_MPROC_SIGNAL_SMP2P>;
qcom,local-pid = <0>;
qcom,remote-pid = <5>;
smp2p_cdsp_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
smp2p_cdsp_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
};
smp2p-slpi {
compatible = "qcom,smp2p";
qcom,smem = <481>, <430>;
interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
IPCC_MPROC_SIGNAL_SMP2P
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc IPCC_CLIENT_SLPI
IPCC_MPROC_SIGNAL_SMP2P>;
qcom,local-pid = <0>;
qcom,remote-pid = <3>;
smp2p_slpi_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
smp2p_slpi_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
};
soc: soc@0 {
#address-cells = <2>;
#size-cells = <2>;
......@@ -286,27 +397,581 @@ gcc: clock-controller@100000 {
clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;
};
ipcc: mailbox@408000 {
compatible = "qcom,sm8250-ipcc", "qcom,ipcc";
reg = <0 0x00408000 0 0x1000>;
interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <3>;
#mbox-cells = <2>;
};
qupv3_id_2: geniqup@8c0000 {
compatible = "qcom,geni-se-qup";
reg = <0x0 0x008c0000 0x0 0x6000>;
clock-names = "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "disabled";
i2c14: i2c@880000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00880000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c14_default>;
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi14: spi@880000 {
compatible = "qcom,geni-spi";
reg = <0 0x00880000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi14_default>;
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c15: i2c@884000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00884000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c15_default>;
interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi15: spi@884000 {
compatible = "qcom,geni-spi";
reg = <0 0x00884000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi15_default>;
interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c16: i2c@888000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00888000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c16_default>;
interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi16: spi@888000 {
compatible = "qcom,geni-spi";
reg = <0 0x00888000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi16_default>;
interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c17: i2c@88c000 {
compatible = "qcom,geni-i2c";
reg = <0 0x0088c000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c17_default>;
interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi17: spi@88c000 {
compatible = "qcom,geni-spi";
reg = <0 0x0088c000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi17_default>;
interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c18: i2c@890000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00890000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c18_default>;
interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi18: spi@890000 {
compatible = "qcom,geni-spi";
reg = <0 0x00890000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi18_default>;
interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c19: i2c@894000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00894000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c19_default>;
interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi19: spi@894000 {
compatible = "qcom,geni-spi";
reg = <0 0x00894000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi19_default>;
interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
qupv3_id_0: geniqup@9c0000 {
compatible = "qcom,geni-se-qup";
reg = <0x0 0x009c0000 0x0 0x6000>;
clock-names = "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "disabled";
i2c0: i2c@980000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00980000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c0_default>;
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi0: spi@980000 {
compatible = "qcom,geni-spi";
reg = <0 0x00980000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi0_default>;
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c1: i2c@984000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00984000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c1_default>;
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi1: spi@984000 {
compatible = "qcom,geni-spi";
reg = <0 0x00984000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi1_default>;
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c2: i2c@988000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00988000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c2_default>;
interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi2: spi@988000 {
compatible = "qcom,geni-spi";
reg = <0 0x00988000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi2_default>;
interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c3: i2c@98c000 {
compatible = "qcom,geni-i2c";
reg = <0 0x0098c000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c3_default>;
interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi3: spi@98c000 {
compatible = "qcom,geni-spi";
reg = <0 0x0098c000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi3_default>;
interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c4: i2c@990000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00990000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c4_default>;
interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi4: spi@990000 {
compatible = "qcom,geni-spi";
reg = <0 0x00990000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi4_default>;
interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c5: i2c@994000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00994000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c5_default>;
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi5: spi@994000 {
compatible = "qcom,geni-spi";
reg = <0 0x00994000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi5_default>;
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c6: i2c@998000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00998000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c6_default>;
interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi6: spi@998000 {
compatible = "qcom,geni-spi";
reg = <0 0x00998000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi6_default>;
interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c7: i2c@99c000 {
compatible = "qcom,geni-i2c";
reg = <0 0x0099c000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c7_default>;
interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi7: spi@99c000 {
compatible = "qcom,geni-spi";
reg = <0 0x0099c000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi7_default>;
interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
qupv3_id_1: geniqup@ac0000 {
compatible = "qcom,geni-se-qup";
reg = <0x0 0x00ac0000 0x0 0x6000>;
clock-names = "m-ahb", "s-ahb";
clocks = <&gcc 133>, <&gcc 134>;
clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "disabled";
i2c8: i2c@a80000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00a80000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c8_default>;
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi8: spi@a80000 {
compatible = "qcom,geni-spi";
reg = <0 0x00a80000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi8_default>;
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c9: i2c@a84000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00a84000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c9_default>;
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi9: spi@a84000 {
compatible = "qcom,geni-spi";
reg = <0 0x00a84000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi9_default>;
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c10: i2c@a88000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00a88000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c10_default>;
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi10: spi@a88000 {
compatible = "qcom,geni-spi";
reg = <0 0x00a88000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi10_default>;
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c11: i2c@a8c000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00a8c000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c11_default>;
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi11: spi@a8c000 {
compatible = "qcom,geni-spi";
reg = <0 0x00a8c000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi11_default>;
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c12: i2c@a90000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00a90000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c12_default>;
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi12: spi@a90000 {
compatible = "qcom,geni-spi";
reg = <0 0x00a90000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi12_default>;
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
uart2: serial@a90000 {
compatible = "qcom,geni-debug-uart";
reg = <0x0 0x00a90000 0x0 0x4000>;
clock-names = "se";
clocks = <&gcc 113>;
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
i2c13: i2c@a94000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00a94000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c13_default>;
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi13: spi@a94000 {
compatible = "qcom,geni-spi";
reg = <0 0x00a94000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi13_default>;
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
ufs_mem_hc: ufs@1d84000 {
ufs_mem_hc: ufshc@1d84000 {
compatible = "qcom,sm8250-ufshc", "qcom,ufshc",
"jedec,ufs-2.0";
reg = <0 0x01d84000 0 0x3000>;
......@@ -376,13 +1041,87 @@ ufs_mem_phy_lanes: lanes@1d87400 {
};
};
intc: interrupt-controller@17a00000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
<0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
tcsr_mutex: hwlock@1f40000 {
compatible = "qcom,tcsr-mutex";
reg = <0x0 0x01f40000 0x0 0x40000>;
#hwlock-cells = <1>;
};
slpi: remoteproc@5c00000 {
compatible = "qcom,sm8250-slpi-pas";
reg = <0 0x05c00000 0 0x4000>;
interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
<&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
<&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
<&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
<&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog", "fatal", "ready",
"handover", "stop-ack";
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>,
<&rpmhpd SM8250_LCX>,
<&rpmhpd SM8250_LMX>;
power-domain-names = "load_state", "lcx", "lmx";
memory-region = <&slpi_mem>;
qcom,smem-states = <&smp2p_slpi_out 0>;
qcom,smem-state-names = "stop";
status = "disabled";
glink-edge {
interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc IPCC_CLIENT_SLPI
IPCC_MPROC_SIGNAL_GLINK_QMP>;
label = "lpass";
qcom,remote-pid = <3>;
};
};
cdsp: remoteproc@8300000 {
compatible = "qcom,sm8250-cdsp-pas";
reg = <0 0x08300000 0 0x10000>;
interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
<&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
<&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
<&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
<&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog", "fatal", "ready",
"handover", "stop-ack";
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>,
<&rpmhpd SM8250_CX>;
power-domain-names = "load_state", "cx";
memory-region = <&cdsp_mem>;
qcom,smem-states = <&smp2p_cdsp_out 0>;
qcom,smem-state-names = "stop";
status = "disabled";
glink-edge {
interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc IPCC_CLIENT_CDSP
IPCC_MPROC_SIGNAL_GLINK_QMP>;
label = "lpass";
qcom,remote-pid = <5>;
};
};
pdc: interrupt-controller@b220000 {
......@@ -395,7 +1134,20 @@ pdc: interrupt-controller@b220000 {
interrupt-controller;
};
spmi: qcom,spmi@c440000 {
aoss_qmp: qmp@c300000 {
compatible = "qcom,sm8250-aoss-qmp";
reg = <0 0x0c300000 0 0x100000>;
interrupts-extended = <&ipcc IPCC_CLIENT_AOP
IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc IPCC_CLIENT_AOP
IPCC_MPROC_SIGNAL_GLINK_QMP>;
#clock-cells = <0>;
#power-domain-cells = <1>;
};
spmi_bus: spmi@c440000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0x0 0x0c440000 0x0 0x0001100>,
<0x0 0x0c600000 0x0 0x2000000>,
......@@ -413,82 +1165,633 @@ spmi: qcom,spmi@c440000 {
#interrupt-cells = <4>;
};
apps_rsc: rsc@18200000 {
label = "apps_rsc";
compatible = "qcom,rpmh-rsc";
reg = <0x0 0x18200000 0x0 0x10000>,
<0x0 0x18210000 0x0 0x10000>,
<0x0 0x18220000 0x0 0x10000>;
reg-names = "drv-0", "drv-1", "drv-2";
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
qcom,tcs-offset = <0xd00>;
qcom,drv-id = <2>;
qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
<WAKE_TCS 3>, <CONTROL_TCS 1>;
tlmm: pinctrl@f100000 {
compatible = "qcom,sm8250-pinctrl";
reg = <0 0x0f100000 0 0x300000>,
<0 0x0f500000 0 0x300000>,
<0 0x0f900000 0 0x300000>;
reg-names = "west", "south", "north";
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&tlmm 0 0 180>;
wakeup-parent = <&pdc>;
rpmhcc: clock-controller {
compatible = "qcom,sm8250-rpmh-clk";
#clock-cells = <1>;
clock-names = "xo";
clocks = <&xo_board>;
qup_i2c0_default: qup-i2c0-default {
mux {
pins = "gpio28", "gpio29";
function = "qup0";
};
rpmhpd: power-controller {
compatible = "qcom,sm8250-rpmhpd";
#power-domain-cells = <1>;
operating-points-v2 = <&rpmhpd_opp_table>;
config {
pins = "gpio28", "gpio29";
drive-strength = <2>;
bias-disable;
};
};
rpmhpd_opp_table: opp-table {
compatible = "operating-points-v2";
qup_i2c1_default: qup-i2c1-default {
pinmux {
pins = "gpio4", "gpio5";
function = "qup1";
};
rpmhpd_opp_ret: opp1 {
opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
config {
pins = "gpio4", "gpio5";
drive-strength = <2>;
bias-disable;
};
};
rpmhpd_opp_min_svs: opp2 {
opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
qup_i2c2_default: qup-i2c2-default {
mux {
pins = "gpio115", "gpio116";
function = "qup2";
};
rpmhpd_opp_low_svs: opp3 {
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
config {
pins = "gpio115", "gpio116";
drive-strength = <2>;
bias-disable;
};
};
rpmhpd_opp_svs: opp4 {
opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
qup_i2c3_default: qup-i2c3-default {
mux {
pins = "gpio119", "gpio120";
function = "qup3";
};
rpmhpd_opp_svs_l1: opp5 {
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
config {
pins = "gpio119", "gpio120";
drive-strength = <2>;
bias-disable;
};
};
rpmhpd_opp_nom: opp6 {
opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
qup_i2c4_default: qup-i2c4-default {
mux {
pins = "gpio8", "gpio9";
function = "qup4";
};
rpmhpd_opp_nom_l1: opp7 {
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
config {
pins = "gpio8", "gpio9";
drive-strength = <2>;
bias-disable;
};
};
rpmhpd_opp_nom_l2: opp8 {
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
qup_i2c5_default: qup-i2c5-default {
mux {
pins = "gpio12", "gpio13";
function = "qup5";
};
rpmhpd_opp_turbo: opp9 {
opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
config {
pins = "gpio12", "gpio13";
drive-strength = <2>;
bias-disable;
};
};
rpmhpd_opp_turbo_l1: opp10 {
opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
qup_i2c6_default: qup-i2c6-default {
mux {
pins = "gpio16", "gpio17";
function = "qup6";
};
config {
pins = "gpio16", "gpio17";
drive-strength = <2>;
bias-disable;
};
};
qup_i2c7_default: qup-i2c7-default {
mux {
pins = "gpio20", "gpio21";
function = "qup7";
};
tcsr_mutex_regs: syscon@1f40000 {
compatible = "syscon";
reg = <0x0 0x01f40000 0x0 0x40000>;
config {
pins = "gpio20", "gpio21";
drive-strength = <2>;
bias-disable;
};
};
qup_i2c8_default: qup-i2c8-default {
mux {
pins = "gpio24", "gpio25";
function = "qup8";
};
config {
pins = "gpio24", "gpio25";
drive-strength = <2>;
bias-disable;
};
};
qup_i2c9_default: qup-i2c9-default {
mux {
pins = "gpio125", "gpio126";
function = "qup9";
};
config {
pins = "gpio125", "gpio126";
drive-strength = <2>;
bias-disable;
};
};
qup_i2c10_default: qup-i2c10-default {
mux {
pins = "gpio129", "gpio130";
function = "qup10";
};
config {
pins = "gpio129", "gpio130";
drive-strength = <2>;
bias-disable;
};
};
qup_i2c11_default: qup-i2c11-default {
mux {
pins = "gpio60", "gpio61";
function = "qup11";
};
config {
pins = "gpio60", "gpio61";
drive-strength = <2>;
bias-disable;
};
};
qup_i2c12_default: qup-i2c12-default {
mux {
pins = "gpio32", "gpio33";
function = "qup12";
};
config {
pins = "gpio32", "gpio33";
drive-strength = <2>;
bias-disable;
};
};
qup_i2c13_default: qup-i2c13-default {
mux {
pins = "gpio36", "gpio37";
function = "qup13";
};
config {
pins = "gpio36", "gpio37";
drive-strength = <2>;
bias-disable;
};
};
qup_i2c14_default: qup-i2c14-default {
mux {
pins = "gpio40", "gpio41";
function = "qup14";
};
config {
pins = "gpio40", "gpio41";
drive-strength = <2>;
bias-disable;
};
};
qup_i2c15_default: qup-i2c15-default {
mux {
pins = "gpio44", "gpio45";
function = "qup15";
};
config {
pins = "gpio44", "gpio45";
drive-strength = <2>;
bias-disable;
};
};
qup_i2c16_default: qup-i2c16-default {
mux {
pins = "gpio48", "gpio49";
function = "qup16";
};
config {
pins = "gpio48", "gpio49";
drive-strength = <2>;
bias-disable;
};
};
qup_i2c17_default: qup-i2c17-default {
mux {
pins = "gpio52", "gpio53";
function = "qup17";
};
config {
pins = "gpio52", "gpio53";
drive-strength = <2>;
bias-disable;
};
};
qup_i2c18_default: qup-i2c18-default {
mux {
pins = "gpio56", "gpio57";
function = "qup18";
};
config {
pins = "gpio56", "gpio57";
drive-strength = <2>;
bias-disable;
};
};
qup_i2c19_default: qup-i2c19-default {
mux {
pins = "gpio0", "gpio1";
function = "qup19";
};
config {
pins = "gpio0", "gpio1";
drive-strength = <2>;
bias-disable;
};
};
qup_spi0_default: qup-spi0-default {
mux {
pins = "gpio28", "gpio29",
"gpio30", "gpio31";
function = "qup0";
};
config {
pins = "gpio28", "gpio29",
"gpio30", "gpio31";
drive-strength = <6>;
bias-disable;
};
};
qup_spi1_default: qup-spi1-default {
mux {
pins = "gpio4", "gpio5",
"gpio6", "gpio7";
function = "qup1";
};
config {
pins = "gpio4", "gpio5",
"gpio6", "gpio7";
drive-strength = <6>;
bias-disable;
};
};
qup_spi2_default: qup-spi2-default {
mux {
pins = "gpio115", "gpio116",
"gpio117", "gpio118";
function = "qup2";
};
config {
pins = "gpio115", "gpio116",
"gpio117", "gpio118";
drive-strength = <6>;
bias-disable;
};
};
qup_spi3_default: qup-spi3-default {
mux {
pins = "gpio119", "gpio120",
"gpio121", "gpio122";
function = "qup3";
};
config {
pins = "gpio119", "gpio120",
"gpio121", "gpio122";
drive-strength = <6>;
bias-disable;
};
};
qup_spi4_default: qup-spi4-default {
mux {
pins = "gpio8", "gpio9",
"gpio10", "gpio11";
function = "qup4";
};
config {
pins = "gpio8", "gpio9",
"gpio10", "gpio11";
drive-strength = <6>;
bias-disable;
};
};
qup_spi5_default: qup-spi5-default {
mux {
pins = "gpio12", "gpio13",
"gpio14", "gpio15";
function = "qup5";
};
config {
pins = "gpio12", "gpio13",
"gpio14", "gpio15";
drive-strength = <6>;
bias-disable;
};
};
qup_spi6_default: qup-spi6-default {
mux {
pins = "gpio16", "gpio17",
"gpio18", "gpio19";
function = "qup6";
};
config {
pins = "gpio16", "gpio17",
"gpio18", "gpio19";
drive-strength = <6>;
bias-disable;
};
};
qup_spi7_default: qup-spi7-default {
mux {
pins = "gpio20", "gpio21",
"gpio22", "gpio23";
function = "qup7";
};
config {
pins = "gpio20", "gpio21",
"gpio22", "gpio23";
drive-strength = <6>;
bias-disable;
};
};
qup_spi8_default: qup-spi8-default {
mux {
pins = "gpio24", "gpio25",
"gpio26", "gpio27";
function = "qup8";
};
config {
pins = "gpio24", "gpio25",
"gpio26", "gpio27";
drive-strength = <6>;
bias-disable;
};
};
qup_spi9_default: qup-spi9-default {
mux {
pins = "gpio125", "gpio126",
"gpio127", "gpio128";
function = "qup9";
};
config {
pins = "gpio125", "gpio126",
"gpio127", "gpio128";
drive-strength = <6>;
bias-disable;
};
};
qup_spi10_default: qup-spi10-default {
mux {
pins = "gpio129", "gpio130",
"gpio131", "gpio132";
function = "qup10";
};
config {
pins = "gpio129", "gpio130",
"gpio131", "gpio132";
drive-strength = <6>;
bias-disable;
};
};
qup_spi11_default: qup-spi11-default {
mux {
pins = "gpio60", "gpio61",
"gpio62", "gpio63";
function = "qup11";
};
config {
pins = "gpio60", "gpio61",
"gpio62", "gpio63";
drive-strength = <6>;
bias-disable;
};
};
qup_spi12_default: qup-spi12-default {
mux {
pins = "gpio32", "gpio33",
"gpio34", "gpio35";
function = "qup12";
};
config {
pins = "gpio32", "gpio33",
"gpio34", "gpio35";
drive-strength = <6>;
bias-disable;
};
};
qup_spi13_default: qup-spi13-default {
mux {
pins = "gpio36", "gpio37",
"gpio38", "gpio39";
function = "qup13";
};
config {
pins = "gpio36", "gpio37",
"gpio38", "gpio39";
drive-strength = <6>;
bias-disable;
};
};
qup_spi14_default: qup-spi14-default {
mux {
pins = "gpio40", "gpio41",
"gpio42", "gpio43";
function = "qup14";
};
config {
pins = "gpio40", "gpio41",
"gpio42", "gpio43";
drive-strength = <6>;
bias-disable;
};
};
qup_spi15_default: qup-spi15-default {
mux {
pins = "gpio44", "gpio45",
"gpio46", "gpio47";
function = "qup15";
};
config {
pins = "gpio44", "gpio45",
"gpio46", "gpio47";
drive-strength = <6>;
bias-disable;
};
};
qup_spi16_default: qup-spi16-default {
mux {
pins = "gpio48", "gpio49",
"gpio50", "gpio51";
function = "qup16";
};
config {
pins = "gpio48", "gpio49",
"gpio50", "gpio51";
drive-strength = <6>;
bias-disable;
};
};
qup_spi17_default: qup-spi17-default {
mux {
pins = "gpio52", "gpio53",
"gpio54", "gpio55";
function = "qup17";
};
config {
pins = "gpio52", "gpio53",
"gpio54", "gpio55";
drive-strength = <6>;
bias-disable;
};
};
qup_spi18_default: qup-spi18-default {
mux {
pins = "gpio56", "gpio57",
"gpio58", "gpio59";
function = "qup18";
};
config {
pins = "gpio56", "gpio57",
"gpio58", "gpio59";
drive-strength = <6>;
bias-disable;
};
};
qup_spi19_default: qup-spi19-default {
mux {
pins = "gpio0", "gpio1",
"gpio2", "gpio3";
function = "qup19";
};
config {
pins = "gpio0", "gpio1",
"gpio2", "gpio3";
drive-strength = <6>;
bias-disable;
};
};
};
adsp: remoteproc@17300000 {
compatible = "qcom,sm8250-adsp-pas";
reg = <0 0x17300000 0 0x100>;
interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
<&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog", "fatal", "ready",
"handover", "stop-ack";
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>,
<&rpmhpd SM8250_LCX>,
<&rpmhpd SM8250_LMX>;
power-domain-names = "load_state", "lcx", "lmx";
memory-region = <&adsp_mem>;
qcom,smem-states = <&smp2p_adsp_out 0>;
qcom,smem-state-names = "stop";
status = "disabled";
glink-edge {
interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc IPCC_CLIENT_LPASS
IPCC_MPROC_SIGNAL_GLINK_QMP>;
label = "lpass";
qcom,remote-pid = <2>;
};
};
intc: interrupt-controller@17a00000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
<0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
watchdog@17c10000 {
compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt";
reg = <0 0x17c10000 0 0x1000>;
clocks = <&sleep_clk>;
};
timer@17c20000 {
......@@ -550,6 +1853,78 @@ frame@17c2d000 {
};
};
apps_rsc: rsc@18200000 {
label = "apps_rsc";
compatible = "qcom,rpmh-rsc";
reg = <0x0 0x18200000 0x0 0x10000>,
<0x0 0x18210000 0x0 0x10000>,
<0x0 0x18220000 0x0 0x10000>;
reg-names = "drv-0", "drv-1", "drv-2";
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
qcom,tcs-offset = <0xd00>;
qcom,drv-id = <2>;
qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
<WAKE_TCS 3>, <CONTROL_TCS 1>;
rpmhcc: clock-controller {
compatible = "qcom,sm8250-rpmh-clk";
#clock-cells = <1>;
clock-names = "xo";
clocks = <&xo_board>;
};
rpmhpd: power-controller {
compatible = "qcom,sm8250-rpmhpd";
#power-domain-cells = <1>;
operating-points-v2 = <&rpmhpd_opp_table>;
rpmhpd_opp_table: opp-table {
compatible = "operating-points-v2";
rpmhpd_opp_ret: opp1 {
opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
};
rpmhpd_opp_min_svs: opp2 {
opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
};
rpmhpd_opp_low_svs: opp3 {
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
};
rpmhpd_opp_svs: opp4 {
opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
};
rpmhpd_opp_svs_l1: opp5 {
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
};
rpmhpd_opp_nom: opp6 {
opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
};
rpmhpd_opp_nom_l1: opp7 {
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
};
rpmhpd_opp_nom_l2: opp8 {
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
};
rpmhpd_opp_turbo: opp9 {
opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
};
rpmhpd_opp_turbo_l1: opp10 {
opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
};
};
};
};
};
timer {
......
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