Commit c6fc7e64 authored by Sujith Manoharan's avatar Sujith Manoharan Committed by John W. Linville

ath9k: Remove pcieSerDesWrite

This HW config option is always set to true and is not needed.
Signed-off-by: default avatarSujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent 28148db7
......@@ -754,6 +754,9 @@ static void ar9003_hw_init_mode_gain_regs(struct ath_hw *ah)
static void ar9003_hw_configpcipowersave(struct ath_hw *ah,
bool power_off)
{
unsigned int i;
struct ar5416IniArray *array;
/*
* Increase L1 Entry Latency. Some WB222 boards don't have
* this change in eeprom/OTP.
......@@ -779,10 +782,6 @@ static void ar9003_hw_configpcipowersave(struct ath_hw *ah,
* Configire PCIE after Ini init. SERDES values now come from ini file
* This enables PCIe low power mode.
*/
if (ah->config.pcieSerDesWrite) {
unsigned int i;
struct ar5416IniArray *array;
array = power_off ? &ah->iniPcieSerdes :
&ah->iniPcieSerdesLowPower;
......@@ -791,7 +790,6 @@ static void ar9003_hw_configpcipowersave(struct ath_hw *ah,
INI_RA(array, i, 0),
INI_RA(array, i, 1));
}
}
}
/* Sets up the AR9003 hardware familiy callbacks */
......
......@@ -454,7 +454,6 @@ static void ath9k_hw_init_config(struct ath_hw *ah)
}
ah->config.rx_intr_mitigation = true;
ah->config.pcieSerDesWrite = true;
/*
* We need this for PCI devices only (Cardbus, PCI, miniPCI)
......
......@@ -283,7 +283,6 @@ struct ath9k_ops_config {
int additional_swba_backoff;
int ack_6mb;
u32 cwm_ignore_extcca;
bool pcieSerDesWrite;
u8 pcie_clock_req;
u32 pcie_waen;
u8 analog_shiftreg;
......
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