Commit c8176892 authored by Paul Mackerras's avatar Paul Mackerras

Merge bk://ppc@ppc.bkbits.net/for-linus-ppc

into samba.org:/stuff/paulus/kernel/for-linus-ppc
parents 13ea5e83 413c4569
......@@ -57,14 +57,5 @@ config FCC_QS6612
bool "QS6612"
endchoice
comment "Generic MPC8260 Options"
config DCACHE_DISABLE
bool "Disable data cache"
help
This option allows you to run the kernel with data cache disabled.
Say Y if you experience CPM lock-ups.
endmenu
......@@ -468,11 +468,6 @@ CONFIG_SCC_CONSOLE=y
CONFIG_FCC2_ENET=y
# CONFIG_FCC3_ENET is not set
#
# Generic MPC8260 Options
#
CONFIG_DCACHE_DISABLE=y
#
# USB support
#
......
......@@ -460,11 +460,6 @@ CONFIG_SCC_ENET=y
#
CONFIG_SCC_CONSOLE=y
#
# Generic MPC8260 Options
#
# CONFIG_DCACHE_DISABLE is not set
#
# USB support
#
......
......@@ -75,11 +75,7 @@ _GLOBAL(__setup_cpu_745x)
setup_common_caches:
mfspr r11,HID0
andi. r0,r11,HID0_DCE
#ifdef CONFIG_DCACHE_DISABLE
ori r11,r11,HID0_ICE
#else
ori r11,r11,HID0_ICE|HID0_DCE
#endif
ori r8,r11,HID0_ICFI
bne 1f /* don't invalidate the D-cache */
ori r8,r8,HID0_DCI /* unless it wasn't enabled */
......
......@@ -165,12 +165,12 @@ int show_cpuinfo(struct seq_file *m, void *v)
return 0;
pvr = cpu_data[i].pvr;
lpj = cpu_data[i].loops_per_jiffy;
seq_printf(m, "processor\t: %d\n", i);
#else
pvr = mfspr(PVR);
lpj = loops_per_jiffy;
#endif
seq_printf(m, "processor\t: %d\n", i);
seq_printf(m, "cpu\t\t: ");
if (cur_cpu_spec[i]->pvr_mask)
......
......@@ -121,7 +121,7 @@
#define MPC10X_MCTLR_EXT_MEM_START_2 0x8c /* Banks 4-7 */
#define MPC10X_MCTLR_MEM_END_1 0x90 /* Banks 0-3 */
#define MPC10X_MCTLR_MEM_END_2i 0x94 /* Banks 4-7 */
#define MPC10X_MCTLR_MEM_END_2 0x94 /* Banks 4-7 */
#define MPC10X_MCTLR_EXT_MEM_END_1 0x98 /* Banks 0-3 */
#define MPC10X_MCTLR_EXT_MEM_END_2 0x9c /* Banks 4-7 */
......
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