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Commit c821045f authored by Michal Simek's avatar Michal Simek
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arm64: zynqmp: Add pinctrl description for all boards 

The commit 1dccb5ec ("dt-bindings: pinctrl: Add binding for ZynqMP
pinctrl driver") and commit 8b242ca7 ("pinctrl: Add Xilinx ZynqMP
pinctrl driver support") add support for Xilinx ZynqMP pinctrl driver
that's why describe pins configuration for current boards.
Signed-off-by: default avatarMichal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/d8bc42600da85f5a23d977d4b61e6528720573e5.1623684253.git.michal.simek@xilinx.com
parent d8e4bc0b
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arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts
View file @ c821045f
...@@ -2,7 +2,7 @@ ...@@ -2,7 +2,7 @@
/* /*
* dts file for Xilinx ZynqMP zc1751-xm015-dc1 * dts file for Xilinx ZynqMP zc1751-xm015-dc1
* *
* (C) Copyright 2015 - 2019, Xilinx, Inc. * (C) Copyright 2015 - 2021, Xilinx, Inc.
* *
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@xilinx.com>
*/ */
...@@ -12,6 +12,7 @@ ...@@ -12,6 +12,7 @@
#include "zynqmp.dtsi" #include "zynqmp.dtsi"
#include "zynqmp-clk-ccf.dtsi" #include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
/ { / {
model = "ZynqMP zc1751-xm015-dc1 RevA"; model = "ZynqMP zc1751-xm015-dc1 RevA";
...@@ -73,6 +74,8 @@ &gem3 { ...@@ -73,6 +74,8 @@ &gem3 {
status = "okay"; status = "okay";
phy-handle = <&phy0>; phy-handle = <&phy0>;
phy-mode = "rgmii-id"; phy-mode = "rgmii-id";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gem3_default>;
phy0: ethernet-phy@0 { phy0: ethernet-phy@0 {
reg = <0>; reg = <0>;
}; };
...@@ -80,12 +83,19 @@ phy0: ethernet-phy@0 { ...@@ -80,12 +83,19 @@ phy0: ethernet-phy@0 {
&gpio { &gpio {
status = "okay"; status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_default>;
}; };
&i2c1 { &i2c1 {
status = "okay"; status = "okay";
clock-frequency = <400000>; clock-frequency = <400000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1_default>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio 36 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>;
eeprom: eeprom@55 { eeprom: eeprom@55 {
compatible = "atmel,24c64"; /* 24AA64 */ compatible = "atmel,24c64"; /* 24AA64 */
...@@ -93,6 +103,216 @@ eeprom: eeprom@55 { ...@@ -93,6 +103,216 @@ eeprom: eeprom@55 {
}; };
}; };
&pinctrl0 {
status = "okay";
pinctrl_i2c1_default: i2c1-default {
mux {
groups = "i2c1_9_grp";
function = "i2c1";
};
conf {
groups = "i2c1_9_grp";
bias-pull-up;
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
};
pinctrl_i2c1_gpio: i2c1-gpio {
mux {
groups = "gpio0_36_grp", "gpio0_37_grp";
function = "gpio0";
};
conf {
groups = "gpio0_36_grp", "gpio0_37_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
};
pinctrl_uart0_default: uart0-default {
mux {
groups = "uart0_8_grp";
function = "uart0";
};
conf {
groups = "uart0_8_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
conf-rx {
pins = "MIO34";
bias-high-impedance;
};
conf-tx {
pins = "MIO35";
bias-disable;
};
};
pinctrl_usb0_default: usb0-default {
mux {
groups = "usb0_0_grp";
function = "usb0";
};
conf {
groups = "usb0_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
conf-rx {
pins = "MIO52", "MIO53", "MIO55";
bias-high-impedance;
};
conf-tx {
pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
"MIO60", "MIO61", "MIO62", "MIO63";
bias-disable;
};
};
pinctrl_gem3_default: gem3-default {
mux {
function = "ethernet3";
groups = "ethernet3_0_grp";
};
conf {
groups = "ethernet3_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
conf-rx {
pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
"MIO75";
bias-high-impedance;
low-power-disable;
};
conf-tx {
pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
"MIO69";
bias-disable;
low-power-enable;
};
mux-mdio {
function = "mdio3";
groups = "mdio3_0_grp";
};
conf-mdio {
groups = "mdio3_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
bias-disable;
};
};
pinctrl_sdhci0_default: sdhci0-default {
mux {
groups = "sdio0_0_grp";
function = "sdio0";
};
conf {
groups = "sdio0_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
bias-disable;
};
mux-cd {
groups = "sdio0_cd_0_grp";
function = "sdio0_cd";
};
conf-cd {
groups = "sdio0_cd_0_grp";
bias-high-impedance;
bias-pull-up;
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
mux-wp {
groups = "sdio0_wp_0_grp";
function = "sdio0_wp";
};
conf-wp {
groups = "sdio0_wp_0_grp";
bias-high-impedance;
bias-pull-up;
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
};
pinctrl_sdhci1_default: sdhci1-default {
mux {
groups = "sdio1_0_grp";
function = "sdio1";
};
conf {
groups = "sdio1_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
bias-disable;
};
mux-cd {
groups = "sdio1_cd_0_grp";
function = "sdio1_cd";
};
conf-cd {
groups = "sdio1_cd_0_grp";
bias-high-impedance;
bias-pull-up;
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
mux-wp {
groups = "sdio1_wp_0_grp";
function = "sdio1_wp";
};
conf-wp {
groups = "sdio1_wp_0_grp";
bias-high-impedance;
bias-pull-up;
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
};
pinctrl_gpio_default: gpio-default {
mux {
function = "gpio0";
groups = "gpio0_38_grp";
};
conf {
groups = "gpio0_38_grp";
bias-disable;
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
};
};
&rtc { &rtc {
status = "okay"; status = "okay";
}; };
...@@ -113,20 +333,28 @@ &sata { ...@@ -113,20 +333,28 @@ &sata {
/* eMMC */ /* eMMC */
&sdhci0 { &sdhci0 {
status = "okay"; status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdhci0_default>;
bus-width = <8>; bus-width = <8>;
}; };
/* SD1 with level shifter */ /* SD1 with level shifter */
&sdhci1 { &sdhci1 {
status = "okay"; status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdhci1_default>;
}; };
&uart0 { &uart0 {
status = "okay"; status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0_default>;
}; };
/* ULPI SMSC USB3320 */ /* ULPI SMSC USB3320 */
&usb0 { &usb0 {
status = "okay"; status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0_default>;
dr_mode = "host"; dr_mode = "host";
}; };
arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts
View file @ c821045f
...@@ -2,7 +2,7 @@ ...@@ -2,7 +2,7 @@
/* /*
* dts file for Xilinx ZynqMP zc1751-xm016-dc2 * dts file for Xilinx ZynqMP zc1751-xm016-dc2
* *
* (C) Copyright 2015 - 2019, Xilinx, Inc. * (C) Copyright 2015 - 2021, Xilinx, Inc.
* *
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@xilinx.com>
*/ */
...@@ -12,6 +12,7 @@ ...@@ -12,6 +12,7 @@
#include "zynqmp.dtsi" #include "zynqmp.dtsi"
#include "zynqmp-clk-ccf.dtsi" #include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
/ { / {
model = "ZynqMP zc1751-xm016-dc2 RevA"; model = "ZynqMP zc1751-xm016-dc2 RevA";
...@@ -42,10 +43,14 @@ memory@0 { ...@@ -42,10 +43,14 @@ memory@0 {
&can0 { &can0 {
status = "okay"; status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can0_default>;
}; };
&can1 { &can1 {
status = "okay"; status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can1_default>;
}; };
&fpd_dma_chan1 { &fpd_dma_chan1 {
...@@ -84,6 +89,8 @@ &gem2 { ...@@ -84,6 +89,8 @@ &gem2 {
status = "okay"; status = "okay";
phy-handle = <&phy0>; phy-handle = <&phy0>;
phy-mode = "rgmii-id"; phy-mode = "rgmii-id";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gem2_default>;
phy0: ethernet-phy@5 { phy0: ethernet-phy@5 {
reg = <5>; reg = <5>;
ti,rx-internal-delay = <0x8>; ti,rx-internal-delay = <0x8>;
...@@ -100,6 +107,11 @@ &gpio { ...@@ -100,6 +107,11 @@ &gpio {
&i2c0 { &i2c0 {
status = "okay"; status = "okay";
clock-frequency = <400000>; clock-frequency = <400000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c0_default>;
pinctrl-1 = <&pinctrl_i2c0_gpio>;
scl-gpios = <&gpio 6 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio 7 GPIO_ACTIVE_HIGH>;
tca6416_u26: gpio@20 { tca6416_u26: gpio@20 {
compatible = "ti,tca6416"; compatible = "ti,tca6416";
...@@ -115,6 +127,285 @@ rtc@68 { ...@@ -115,6 +127,285 @@ rtc@68 {
}; };
}; };
&pinctrl0 {
status = "okay";
pinctrl_can0_default: can0-default {
mux {
function = "can0";
groups = "can0_9_grp";
};
conf {
groups = "can0_9_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
conf-rx {
pins = "MIO38";
bias-high-impedance;
};
conf-tx {
pins = "MIO39";
bias-disable;
};
};
pinctrl_can1_default: can1-default {
mux {
function = "can1";
groups = "can1_8_grp";
};
conf {
groups = "can1_8_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
conf-rx {
pins = "MIO33";
bias-high-impedance;
};
conf-tx {
pins = "MIO32";
bias-disable;
};
};
pinctrl_i2c0_default: i2c0-default {
mux {
groups = "i2c0_1_grp";
function = "i2c0";
};
conf {
groups = "i2c0_1_grp";
bias-pull-up;
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
};
pinctrl_i2c0_gpio: i2c0-gpio {
mux {
groups = "gpio0_6_grp", "gpio0_7_grp";
function = "gpio0";
};
conf {
groups = "gpio0_6_grp", "gpio0_7_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
};
pinctrl_uart0_default: uart0-default {
mux {
groups = "uart0_10_grp";
function = "uart0";
};
conf {
groups = "uart0_10_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
conf-rx {
pins = "MIO42";
bias-high-impedance;
};
conf-tx {
pins = "MIO43";
bias-disable;
};
};
pinctrl_uart1_default: uart1-default {
mux {
groups = "uart1_10_grp";
function = "uart1";
};
conf {
groups = "uart1_10_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
conf-rx {
pins = "MIO41";
bias-high-impedance;
};
conf-tx {
pins = "MIO40";
bias-disable;
};
};
pinctrl_usb1_default: usb1-default {
mux {
groups = "usb1_0_grp";
function = "usb1";
};
conf {
groups = "usb1_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
conf-rx {
pins = "MIO64", "MIO65", "MIO67";
bias-high-impedance;
};
conf-tx {
pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71",
"MIO72", "MIO73", "MIO74", "MIO75";
bias-disable;
};
};
pinctrl_gem2_default: gem2-default {
mux {
function = "ethernet2";
groups = "ethernet2_0_grp";
};
conf {
groups = "ethernet2_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
conf-rx {
pins = "MIO58", "MIO59", "MIO60", "MIO61", "MIO62",
"MIO63";
bias-high-impedance;
low-power-disable;
};
conf-tx {
pins = "MIO52", "MIO53", "MIO54", "MIO55", "MIO56",
"MIO57";
bias-disable;
low-power-enable;
};
mux-mdio {
function = "mdio2";
groups = "mdio2_0_grp";
};
conf-mdio {
groups = "mdio2_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
bias-disable;
};
};
pinctrl_nand0_default: nand0-default {
mux {
groups = "nand0_0_grp";
function = "nand0";
};
conf {
groups = "nand0_0_grp";
bias-pull-up;
};
mux-ce {
groups = "nand0_ce_0_grp";
function = "nand0_ce";
};
conf-ce {
groups = "nand0_ce_0_grp";
bias-pull-up;
};
mux-rb {
groups = "nand0_rb_0_grp";
function = "nand0_rb";
};
conf-rb {
groups = "nand0_rb_0_grp";
bias-pull-up;
};
mux-dqs {
groups = "nand0_dqs_0_grp";
function = "nand0_dqs";
};
conf-dqs {
groups = "nand0_dqs_0_grp";
bias-pull-up;
};
};
pinctrl_spi0_default: spi0-default {
mux {
groups = "spi0_0_grp";
function = "spi0";
};
conf {
groups = "spi0_0_grp";
bias-disable;
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
mux-cs {
groups = "spi0_ss_0_grp", "spi0_ss_1_grp",
"spi0_ss_2_grp";
function = "spi0_ss";
};
conf-cs {
groups = "spi0_ss_0_grp", "spi0_ss_1_grp",
"spi0_ss_2_grp";
bias-disable;
};
};
pinctrl_spi1_default: spi1-default {
mux {
groups = "spi1_3_grp";
function = "spi1";
};
conf {
groups = "spi1_3_grp";
bias-disable;
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
mux-cs {
groups = "spi1_ss_9_grp", "spi1_ss_10_grp",
"spi1_ss_11_grp";
function = "spi1_ss";
};
conf-cs {
groups = "spi1_ss_9_grp", "spi1_ss_10_grp",
"spi1_ss_11_grp";
bias-disable;
};
};
};
&rtc { &rtc {
status = "okay"; status = "okay";
}; };
...@@ -122,6 +413,8 @@ &rtc { ...@@ -122,6 +413,8 @@ &rtc {
&spi0 { &spi0 {
status = "okay"; status = "okay";
num-cs = <1>; num-cs = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0_default>;
spi0_flash0: flash@0 { spi0_flash0: flash@0 {
#address-cells = <1>; #address-cells = <1>;
...@@ -140,6 +433,8 @@ partition@0 { ...@@ -140,6 +433,8 @@ partition@0 {
&spi1 { &spi1 {
status = "okay"; status = "okay";
num-cs = <1>; num-cs = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1_default>;
spi1_flash0: flash@0 { spi1_flash0: flash@0 {
#address-cells = <1>; #address-cells = <1>;
...@@ -158,13 +453,19 @@ partition@0 { ...@@ -158,13 +453,19 @@ partition@0 {
/* ULPI SMSC USB3320 */ /* ULPI SMSC USB3320 */
&usb1 { &usb1 {
status = "okay"; status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1_default>;
dr_mode = "host"; dr_mode = "host";
}; };
&uart0 { &uart0 {
status = "okay"; status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0_default>;
}; };
&uart1 { &uart1 {
status = "okay"; status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_default>;
}; };
arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts
View file @ c821045f
...@@ -2,7 +2,7 @@ ...@@ -2,7 +2,7 @@
/* /*
* dts file for Xilinx ZynqMP zc1751-xm019-dc5 * dts file for Xilinx ZynqMP zc1751-xm019-dc5
* *
* (C) Copyright 2015 - 2019, Xilinx, Inc. * (C) Copyright 2015 - 2021, Xilinx, Inc.
* *
* Siva Durga Prasad <siva.durga.paladugu@xilinx.com> * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@xilinx.com>
...@@ -13,6 +13,7 @@ ...@@ -13,6 +13,7 @@
#include "zynqmp.dtsi" #include "zynqmp.dtsi"
#include "zynqmp-clk-ccf.dtsi" #include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
/ { / {
model = "ZynqMP zc1751-xm019-dc5 RevA"; model = "ZynqMP zc1751-xm019-dc5 RevA";
...@@ -74,6 +75,8 @@ &gem1 { ...@@ -74,6 +75,8 @@ &gem1 {
status = "okay"; status = "okay";
phy-handle = <&phy0>; phy-handle = <&phy0>;
phy-mode = "rgmii-id"; phy-mode = "rgmii-id";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gem1_default>;
phy0: ethernet-phy@0 { phy0: ethernet-phy@0 {
reg = <0>; reg = <0>;
}; };
...@@ -85,41 +88,365 @@ &gpio { ...@@ -85,41 +88,365 @@ &gpio {
&i2c0 { &i2c0 {
status = "okay"; status = "okay";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c0_default>;
pinctrl-1 = <&pinctrl_i2c0_gpio>;
scl-gpios = <&gpio 74 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio 75 GPIO_ACTIVE_HIGH>;
}; };
&i2c1 { &i2c1 {
status = "okay"; status = "okay";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1_default>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio 76 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio 77 GPIO_ACTIVE_HIGH>;
};
&pinctrl0 {
status = "okay";
pinctrl_i2c0_default: i2c0-default {
mux {
groups = "i2c0_18_grp";
function = "i2c0";
};
conf {
groups = "i2c0_18_grp";
bias-pull-up;
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
};
pinctrl_i2c0_gpio: i2c0-gpio {
mux {
groups = "gpio0_74_grp", "gpio0_75_grp";
function = "gpio0";
};
conf {
groups = "gpio0_74_grp", "gpio0_75_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
};
pinctrl_i2c1_default: i2c1-default {
mux {
groups = "i2c1_19_grp";
function = "i2c1";
};
conf {
groups = "i2c1_19_grp";
bias-pull-up;
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
};
pinctrl_i2c1_gpio: i2c1-gpio {
mux {
groups = "gpio0_76_grp", "gpio0_77_grp";
function = "gpio0";
};
conf {
groups = "gpio0_76_grp", "gpio0_77_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
};
pinctrl_uart0_default: uart0-default {
mux {
groups = "uart0_17_grp";
function = "uart0";
};
conf {
groups = "uart0_17_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
conf-rx {
pins = "MIO70";
bias-high-impedance;
};
conf-tx {
pins = "MIO71";
bias-disable;
};
};
pinctrl_uart1_default: uart1-default {
mux {
groups = "uart1_18_grp";
function = "uart1";
};
conf {
groups = "uart1_18_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
conf-rx {
pins = "MIO73";
bias-high-impedance;
};
conf-tx {
pins = "MIO72";
bias-disable;
};
};
pinctrl_gem1_default: gem1-default {
mux {
function = "ethernet1";
groups = "ethernet1_0_grp";
};
conf {
groups = "ethernet1_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
conf-rx {
pins = "MIO44", "MIO45", "MIO46", "MIO47", "MIO48",
"MIO49";
bias-high-impedance;
low-power-disable;
};
conf-tx {
pins = "MIO38", "MIO39", "MIO40", "MIO41", "MIO42",
"MIO43";
bias-disable;
low-power-enable;
};
mux-mdio {
function = "mdio1";
groups = "mdio1_0_grp";
};
conf-mdio {
groups = "mdio1_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
bias-disable;
};
};
pinctrl_sdhci0_default: sdhci0-default {
mux {
groups = "sdio0_0_grp";
function = "sdio0";
};
conf {
groups = "sdio0_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
bias-disable;
};
mux-cd {
groups = "sdio0_cd_0_grp";
function = "sdio0_cd";
};
conf-cd {
groups = "sdio0_cd_0_grp";
bias-high-impedance;
bias-pull-up;
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
mux-wp {
groups = "sdio0_wp_0_grp";
function = "sdio0_wp";
};
conf-wp {
groups = "sdio0_wp_0_grp";
bias-high-impedance;
bias-pull-up;
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
};
pinctrl_watchdog0_default: watchdog0-default {
mux-clk {
groups = "swdt0_clk_1_grp";
function = "swdt0_clk";
};
conf-clk {
groups = "swdt0_clk_1_grp";
bias-pull-up;
};
mux-rst {
groups = "swdt0_rst_1_grp";
function = "swdt0_rst";
};
conf-rst {
groups = "swdt0_rst_1_grp";
bias-disable;
slew-rate = <SLEW_RATE_SLOW>;
};
};
pinctrl_ttc0_default: ttc0-default {
mux-clk {
groups = "ttc0_clk_0_grp";
function = "ttc0_clk";
};
conf-clk {
groups = "ttc0_clk_0_grp";
bias-pull-up;
};
mux-wav {
groups = "ttc0_wav_0_grp";
function = "ttc0_wav";
};
conf-wav {
groups = "ttc0_wav_0_grp";
bias-disable;
slew-rate = <SLEW_RATE_SLOW>;
};
};
pinctrl_ttc1_default: ttc1-default {
mux-clk {
groups = "ttc1_clk_0_grp";
function = "ttc1_clk";
};
conf-clk {
groups = "ttc1_clk_0_grp";
bias-pull-up;
};
mux-wav {
groups = "ttc1_wav_0_grp";
function = "ttc1_wav";
};
conf-wav {
groups = "ttc1_wav_0_grp";
bias-disable;
slew-rate = <SLEW_RATE_SLOW>;
};
};
pinctrl_ttc2_default: ttc2-default {
mux-clk {
groups = "ttc2_clk_0_grp";
function = "ttc2_clk";
};
conf-clk {
groups = "ttc2_clk_0_grp";
bias-pull-up;
};
mux-wav {
groups = "ttc2_wav_0_grp";
function = "ttc2_wav";
};
conf-wav {
groups = "ttc2_wav_0_grp";
bias-disable;
slew-rate = <SLEW_RATE_SLOW>;
};
};
pinctrl_ttc3_default: ttc3-default {
mux-clk {
groups = "ttc3_clk_0_grp";
function = "ttc3_clk";
};
conf-clk {
groups = "ttc3_clk_0_grp";
bias-pull-up;
};
mux-wav {
groups = "ttc3_wav_0_grp";
function = "ttc3_wav";
};
conf-wav {
groups = "ttc3_wav_0_grp";
bias-disable;
slew-rate = <SLEW_RATE_SLOW>;
};
};
}; };
&sdhci0 { &sdhci0 {
status = "okay"; status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdhci0_default>;
no-1-8-v; no-1-8-v;
}; };
&ttc0 { &ttc0 {
status = "okay"; status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ttc0_default>;
}; };
&ttc1 { &ttc1 {
status = "okay"; status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ttc1_default>;
}; };
&ttc2 { &ttc2 {
status = "okay"; status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ttc2_default>;
}; };
&ttc3 { &ttc3 {
status = "okay"; status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ttc3_default>;
}; };
&uart0 { &uart0 {
status = "okay"; status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0_default>;
}; };
&uart1 { &uart1 {
status = "okay"; status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_default>;
}; };
&watchdog0 { &watchdog0 {
status = "okay"; status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_watchdog0_default>;
}; };
arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
View file @ c821045f
...@@ -2,7 +2,7 @@ ...@@ -2,7 +2,7 @@
/* /*
* dts file for Xilinx ZynqMP ZCU100 revC * dts file for Xilinx ZynqMP ZCU100 revC
* *
* (C) Copyright 2016 - 2019, Xilinx, Inc. * (C) Copyright 2016 - 2021, Xilinx, Inc.
* *
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@xilinx.com>
* Nathalie Chan King Choy * Nathalie Chan King Choy
...@@ -15,6 +15,7 @@ ...@@ -15,6 +15,7 @@
#include <dt-bindings/input/input.h> #include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
#include <dt-bindings/phy/phy.h> #include <dt-bindings/phy/phy.h>
/ { / {
...@@ -160,6 +161,11 @@ &gpio { ...@@ -160,6 +161,11 @@ &gpio {
&i2c1 { &i2c1 {
status = "okay"; status = "okay";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1_default>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio 4 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
clock-frequency = <100000>; clock-frequency = <100000>;
i2c-mux@75 { /* u11 */ i2c-mux@75 { /* u11 */
compatible = "nxp,pca9548"; compatible = "nxp,pca9548";
...@@ -237,8 +243,222 @@ i2csw_7: i2c@7 { ...@@ -237,8 +243,222 @@ i2csw_7: i2c@7 {
}; };
}; };
&psgtr { &pinctrl0 {
status = "okay"; status = "okay";
pinctrl_i2c1_default: i2c1-default {
mux {
groups = "i2c1_1_grp";
function = "i2c1";
};
conf {
groups = "i2c1_1_grp";
bias-pull-up;
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
};
pinctrl_i2c1_gpio: i2c1-gpio {
mux {
groups = "gpio0_4_grp", "gpio0_5_grp";
function = "gpio0";
};
conf {
groups = "gpio0_4_grp", "gpio0_5_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
};
pinctrl_sdhci0_default: sdhci0-default {
mux {
groups = "sdio0_3_grp";
function = "sdio0";
};
conf {
groups = "sdio0_3_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
bias-disable;
};
mux-cd {
groups = "sdio0_cd_0_grp";
function = "sdio0_cd";
};
conf-cd {
groups = "sdio0_cd_0_grp";
bias-high-impedance;
bias-pull-up;
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
};
pinctrl_sdhci1_default: sdhci1-default {
mux {
groups = "sdio1_2_grp";
function = "sdio1";
};
conf {
groups = "sdio1_2_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
bias-disable;
};
};
pinctrl_spi0_default: spi0-default {
mux {
groups = "spi0_3_grp";
function = "spi0";
};
conf {
groups = "spi0_3_grp";
bias-disable;
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
mux-cs {
groups = "spi0_ss_9_grp";
function = "spi0_ss";
};
conf-cs {
groups = "spi0_ss_9_grp";
bias-disable;
};
};
pinctrl_spi1_default: spi1-default {
mux {
groups = "spi1_0_grp";
function = "spi1";
};
conf {
groups = "spi1_0_grp";
bias-disable;
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
mux-cs {
groups = "spi1_ss_0_grp";
function = "spi1_ss";
};
conf-cs {
groups = "spi1_ss_0_grp";
bias-disable;
};
};
pinctrl_uart0_default: uart0-default {
mux {
groups = "uart0_0_grp";
function = "uart0";
};
conf {
groups = "uart0_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
conf-rx {
pins = "MIO3";
bias-high-impedance;
};
conf-tx {
pins = "MIO2";
bias-disable;
};
};
pinctrl_uart1_default: uart1-default {
mux {
groups = "uart1_0_grp";
function = "uart1";
};
conf {
groups = "uart1_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
conf-rx {
pins = "MIO1";
bias-high-impedance;
};
conf-tx {
pins = "MIO0";
bias-disable;
};
};
pinctrl_usb0_default: usb0-default {
mux {
groups = "usb0_0_grp";
function = "usb0";
};
conf {
groups = "usb0_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
conf-rx {
pins = "MIO52", "MIO53", "MIO55";
bias-high-impedance;
};
conf-tx {
pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
"MIO60", "MIO61", "MIO62", "MIO63";
bias-disable;
};
};
pinctrl_usb1_default: usb1-default {
mux {
groups = "usb1_0_grp";
function = "usb1";
};
conf {
groups = "usb1_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
conf-rx {
pins = "MIO64", "MIO65", "MIO67";
bias-high-impedance;
};
conf-tx {
pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71",
"MIO72", "MIO73", "MIO74", "MIO75";
bias-disable;
};
};
};
&psgtr {
/* usb3, dps */ /* usb3, dps */
clocks = <&si5335a_0>, <&si5335a_1>; clocks = <&si5335a_0>, <&si5335a_1>;
clock-names = "ref0", "ref1"; clock-names = "ref0", "ref1";
...@@ -253,12 +473,16 @@ &sdhci0 { ...@@ -253,12 +473,16 @@ &sdhci0 {
status = "okay"; status = "okay";
no-1-8-v; no-1-8-v;
disable-wp; disable-wp;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdhci0_default>;
xlnx,mio-bank = <0>; xlnx,mio-bank = <0>;
}; };
&sdhci1 { &sdhci1 {
status = "okay"; status = "okay";
bus-width = <0x4>; bus-width = <0x4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdhci1_default>;
xlnx,mio-bank = <0>; xlnx,mio-bank = <0>;
non-removable; non-removable;
disable-wp; disable-wp;
...@@ -279,16 +503,22 @@ &spi0 { /* Low Speed connector */ ...@@ -279,16 +503,22 @@ &spi0 { /* Low Speed connector */
status = "okay"; status = "okay";
label = "LS-SPI0"; label = "LS-SPI0";
num-cs = <1>; num-cs = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0_default>;
}; };
&spi1 { /* High Speed connector */ &spi1 { /* High Speed connector */
status = "okay"; status = "okay";
label = "HS-SPI1"; label = "HS-SPI1";
num-cs = <1>; num-cs = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1_default>;
}; };
&uart0 { &uart0 {
status = "okay"; status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0_default>;
bluetooth { bluetooth {
compatible = "ti,wl1831-st"; compatible = "ti,wl1831-st";
enable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; enable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;
...@@ -297,18 +527,23 @@ bluetooth { ...@@ -297,18 +527,23 @@ bluetooth {
&uart1 { &uart1 {
status = "okay"; status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_default>;
}; };
/* ULPI SMSC USB3320 */ /* ULPI SMSC USB3320 */
&usb0 { &usb0 {
status = "okay"; status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0_default>;
dr_mode = "peripheral"; dr_mode = "peripheral";
}; };
/* ULPI SMSC USB3320 */ /* ULPI SMSC USB3320 */
&usb1 { &usb1 {
status = "okay"; status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1_default>;
dr_mode = "host"; dr_mode = "host";
}; };
......
arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
View file @ c821045f
...@@ -2,7 +2,7 @@ ...@@ -2,7 +2,7 @@
/* /*
* dts file for Xilinx ZynqMP ZCU102 RevA * dts file for Xilinx ZynqMP ZCU102 RevA
* *
* (C) Copyright 2015 - 2019, Xilinx, Inc. * (C) Copyright 2015 - 2021, Xilinx, Inc.
* *
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@xilinx.com>
*/ */
...@@ -13,6 +13,7 @@ ...@@ -13,6 +13,7 @@
#include "zynqmp-clk-ccf.dtsi" #include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/input/input.h> #include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
#include <dt-bindings/phy/phy.h> #include <dt-bindings/phy/phy.h>
/ { / {
...@@ -150,6 +151,8 @@ refhdmi: refhdmi { ...@@ -150,6 +151,8 @@ refhdmi: refhdmi {
&can1 { &can1 {
status = "okay"; status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can1_default>;
}; };
&dcc { &dcc {
...@@ -192,6 +195,8 @@ &gem3 { ...@@ -192,6 +195,8 @@ &gem3 {
status = "okay"; status = "okay";
phy-handle = <&phy0>; phy-handle = <&phy0>;
phy-mode = "rgmii-id"; phy-mode = "rgmii-id";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gem3_default>;
phy0: ethernet-phy@21 { phy0: ethernet-phy@21 {
reg = <21>; reg = <21>;
ti,rx-internal-delay = <0x8>; ti,rx-internal-delay = <0x8>;
...@@ -203,11 +208,18 @@ phy0: ethernet-phy@21 { ...@@ -203,11 +208,18 @@ phy0: ethernet-phy@21 {
&gpio { &gpio {
status = "okay"; status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_default>;
}; };
&i2c0 { &i2c0 {
status = "okay"; status = "okay";
clock-frequency = <400000>; clock-frequency = <400000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c0_default>;
pinctrl-1 = <&pinctrl_i2c0_gpio>;
scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
tca6416_u97: gpio@20 { tca6416_u97: gpio@20 {
compatible = "ti,tca6416"; compatible = "ti,tca6416";
...@@ -468,6 +480,11 @@ max20751@73 { /* u96 */ ...@@ -468,6 +480,11 @@ max20751@73 { /* u96 */
&i2c1 { &i2c1 {
status = "okay"; status = "okay";
clock-frequency = <400000>; clock-frequency = <400000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1_default>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
/* PL i2c via PCA9306 - u45 */ /* PL i2c via PCA9306 - u45 */
i2c-mux@74 { /* u34 */ i2c-mux@74 { /* u34 */
...@@ -642,6 +659,269 @@ i2c@7 { ...@@ -642,6 +659,269 @@ i2c@7 {
}; };
}; };
&pinctrl0 {
status = "okay";
pinctrl_i2c0_default: i2c0-default {
mux {
groups = "i2c0_3_grp";
function = "i2c0";
};
conf {
groups = "i2c0_3_grp";
bias-pull-up;
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
};
pinctrl_i2c0_gpio: i2c0-gpio {
mux {
groups = "gpio0_14_grp", "gpio0_15_grp";
function = "gpio0";
};
conf {
groups = "gpio0_14_grp", "gpio0_15_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
};
pinctrl_i2c1_default: i2c1-default {
mux {
groups = "i2c1_4_grp";
function = "i2c1";
};
conf {
groups = "i2c1_4_grp";
bias-pull-up;
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
};
pinctrl_i2c1_gpio: i2c1-gpio {
mux {
groups = "gpio0_16_grp", "gpio0_17_grp";
function = "gpio0";
};
conf {
groups = "gpio0_16_grp", "gpio0_17_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
};
pinctrl_uart0_default: uart0-default {
mux {
groups = "uart0_4_grp";
function = "uart0";
};
conf {
groups = "uart0_4_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
conf-rx {
pins = "MIO18";
bias-high-impedance;
};
conf-tx {
pins = "MIO19";
bias-disable;
};
};
pinctrl_uart1_default: uart1-default {
mux {
groups = "uart1_5_grp";
function = "uart1";
};
conf {
groups = "uart1_5_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
conf-rx {
pins = "MIO21";
bias-high-impedance;
};
conf-tx {
pins = "MIO20";
bias-disable;
};
};
pinctrl_usb0_default: usb0-default {
mux {
groups = "usb0_0_grp";
function = "usb0";
};
conf {
groups = "usb0_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
conf-rx {
pins = "MIO52", "MIO53", "MIO55";
bias-high-impedance;
};
conf-tx {
pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
"MIO60", "MIO61", "MIO62", "MIO63";
bias-disable;
};
};
pinctrl_gem3_default: gem3-default {
mux {
function = "ethernet3";
groups = "ethernet3_0_grp";
};
conf {
groups = "ethernet3_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
conf-rx {
pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
"MIO75";
bias-high-impedance;
low-power-disable;
};
conf-tx {
pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
"MIO69";
bias-disable;
low-power-enable;
};
mux-mdio {
function = "mdio3";
groups = "mdio3_0_grp";
};
conf-mdio {
groups = "mdio3_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
bias-disable;
};
};
pinctrl_can1_default: can1-default {
mux {
function = "can1";
groups = "can1_6_grp";
};
conf {
groups = "can1_6_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
conf-rx {
pins = "MIO25";
bias-high-impedance;
};
conf-tx {
pins = "MIO24";
bias-disable;
};
};
pinctrl_sdhci1_default: sdhci1-default {
mux {
groups = "sdio1_0_grp";
function = "sdio1";
};
conf {
groups = "sdio1_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
bias-disable;
};
mux-cd {
groups = "sdio1_cd_0_grp";
function = "sdio1_cd";
};
conf-cd {
groups = "sdio1_cd_0_grp";
bias-high-impedance;
bias-pull-up;
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
mux-wp {
groups = "sdio1_wp_0_grp";
function = "sdio1_wp";
};
conf-wp {
groups = "sdio1_wp_0_grp";
bias-high-impedance;
bias-pull-up;
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
};
pinctrl_gpio_default: gpio-default {
mux-sw {
function = "gpio0";
groups = "gpio0_22_grp", "gpio0_23_grp";
};
conf-sw {
groups = "gpio0_22_grp", "gpio0_23_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
mux-msp {
function = "gpio0";
groups = "gpio0_13_grp", "gpio0_38_grp";
};
conf-msp {
groups = "gpio0_13_grp", "gpio0_38_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
conf-pull-up {
pins = "MIO22", "MIO23";
bias-pull-up;
};
conf-pull-none {
pins = "MIO13", "MIO38";
bias-disable;
};
};
};
&pcie { &pcie {
status = "okay"; status = "okay";
}; };
...@@ -676,20 +956,28 @@ &sata { ...@@ -676,20 +956,28 @@ &sata {
&sdhci1 { &sdhci1 {
status = "okay"; status = "okay";
no-1-8-v; no-1-8-v;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdhci1_default>;
xlnx,mio-bank = <1>; xlnx,mio-bank = <1>;
}; };
&uart0 { &uart0 {
status = "okay"; status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0_default>;
}; };
&uart1 { &uart1 {
status = "okay"; status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_default>;
}; };
/* ULPI SMSC USB3320 */ /* ULPI SMSC USB3320 */
&usb0 { &usb0 {
status = "okay"; status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0_default>;
dr_mode = "host"; dr_mode = "host";
}; };
......
arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
View file @ c821045f
...@@ -2,7 +2,7 @@ ...@@ -2,7 +2,7 @@
/* /*
* dts file for Xilinx ZynqMP ZCU104 * dts file for Xilinx ZynqMP ZCU104
* *
* (C) Copyright 2017 - 2019, Xilinx, Inc. * (C) Copyright 2017 - 2021, Xilinx, Inc.
* *
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@xilinx.com>
*/ */
...@@ -12,6 +12,7 @@ ...@@ -12,6 +12,7 @@
#include "zynqmp.dtsi" #include "zynqmp.dtsi"
#include "zynqmp-clk-ccf.dtsi" #include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
#include <dt-bindings/phy/phy.h> #include <dt-bindings/phy/phy.h>
/ { / {
...@@ -59,6 +60,8 @@ clock_8t49n287_3: clk27 { ...@@ -59,6 +60,8 @@ clock_8t49n287_3: clk27 {
&can1 { &can1 {
status = "okay"; status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can1_default>;
}; };
&dcc { &dcc {
...@@ -101,6 +104,8 @@ &gem3 { ...@@ -101,6 +104,8 @@ &gem3 {
status = "okay"; status = "okay";
phy-handle = <&phy0>; phy-handle = <&phy0>;
phy-mode = "rgmii-id"; phy-mode = "rgmii-id";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gem3_default>;
phy0: ethernet-phy@c { phy0: ethernet-phy@c {
reg = <0xc>; reg = <0xc>;
ti,rx-internal-delay = <0x8>; ti,rx-internal-delay = <0x8>;
...@@ -117,6 +122,11 @@ &gpio { ...@@ -117,6 +122,11 @@ &gpio {
&i2c1 { &i2c1 {
status = "okay"; status = "okay";
clock-frequency = <400000>; clock-frequency = <400000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1_default>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
/* Another connection to this bus via PL i2c via PCA9306 - u45 */ /* Another connection to this bus via PL i2c via PCA9306 - u45 */
i2c-mux@74 { /* u34 */ i2c-mux@74 { /* u34 */
...@@ -207,6 +217,204 @@ i2c@7 { ...@@ -207,6 +217,204 @@ i2c@7 {
}; };
}; };
&pinctrl0 {
status = "okay";
pinctrl_can1_default: can1-default {
mux {
function = "can1";
groups = "can1_6_grp";
};
conf {
groups = "can1_6_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
drive-strength = <12>;
};
conf-rx {
pins = "MIO25";
bias-high-impedance;
};
conf-tx {
pins = "MIO24";
bias-disable;
};
};
pinctrl_i2c1_default: i2c1-default {
mux {
groups = "i2c1_4_grp";
function = "i2c1";
};
conf {
groups = "i2c1_4_grp";
bias-pull-up;
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
drive-strength = <12>;
};
};
pinctrl_i2c1_gpio: i2c1-gpio {
mux {
groups = "gpio0_16_grp", "gpio0_17_grp";
function = "gpio0";
};
conf {
groups = "gpio0_16_grp", "gpio0_17_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
drive-strength = <12>;
};
};
pinctrl_gem3_default: gem3-default {
mux {
function = "ethernet3";
groups = "ethernet3_0_grp";
};
conf {
groups = "ethernet3_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
drive-strength = <12>;
};
conf-rx {
pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
"MIO75";
bias-high-impedance;
low-power-disable;
};
conf-tx {
pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
"MIO69";
bias-disable;
low-power-enable;
};
mux-mdio {
function = "mdio3";
groups = "mdio3_0_grp";
};
conf-mdio {
groups = "mdio3_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
bias-disable;
};
};
pinctrl_sdhci1_default: sdhci1-default {
mux {
groups = "sdio1_0_grp";
function = "sdio1";
};
conf {
groups = "sdio1_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
bias-disable;
drive-strength = <12>;
};
mux-cd {
groups = "sdio1_cd_0_grp";
function = "sdio1_cd";
};
conf-cd {
groups = "sdio1_cd_0_grp";
bias-high-impedance;
bias-pull-up;
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
};
pinctrl_uart0_default: uart0-default {
mux {
groups = "uart0_4_grp";
function = "uart0";
};
conf {
groups = "uart0_4_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
drive-strength = <12>;
};
conf-rx {
pins = "MIO18";
bias-high-impedance;
};
conf-tx {
pins = "MIO19";
bias-disable;
};
};
pinctrl_uart1_default: uart1-default {
mux {
groups = "uart1_5_grp";
function = "uart1";
};
conf {
groups = "uart1_5_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
drive-strength = <12>;
};
conf-rx {
pins = "MIO21";
bias-high-impedance;
};
conf-tx {
pins = "MIO20";
bias-disable;
};
};
pinctrl_usb0_default: usb0-default {
mux {
groups = "usb0_0_grp";
function = "usb0";
};
conf {
groups = "usb0_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
drive-strength = <12>;
};
conf-rx {
pins = "MIO52", "MIO53", "MIO55";
bias-high-impedance;
};
conf-tx {
pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
"MIO60", "MIO61", "MIO62", "MIO63";
bias-disable;
};
};
};
&rtc { &rtc {
status = "okay"; status = "okay";
}; };
...@@ -237,21 +445,29 @@ &sata { ...@@ -237,21 +445,29 @@ &sata {
&sdhci1 { &sdhci1 {
status = "okay"; status = "okay";
no-1-8-v; no-1-8-v;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdhci1_default>;
xlnx,mio-bank = <1>; xlnx,mio-bank = <1>;
disable-wp; disable-wp;
}; };
&uart0 { &uart0 {
status = "okay"; status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0_default>;
}; };
&uart1 { &uart1 {
status = "okay"; status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_default>;
}; };
/* ULPI SMSC USB3320 */ /* ULPI SMSC USB3320 */
&usb0 { &usb0 {
status = "okay"; status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0_default>;
dr_mode = "host"; dr_mode = "host";
}; };
......
arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts
View file @ c821045f
...@@ -2,7 +2,7 @@ ...@@ -2,7 +2,7 @@
/* /*
* dts file for Xilinx ZynqMP ZCU104 * dts file for Xilinx ZynqMP ZCU104
* *
* (C) Copyright 2017 - 2020, Xilinx, Inc. * (C) Copyright 2017 - 2021, Xilinx, Inc.
* *
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@xilinx.com>
*/ */
...@@ -12,6 +12,7 @@ ...@@ -12,6 +12,7 @@
#include "zynqmp.dtsi" #include "zynqmp.dtsi"
#include "zynqmp-clk-ccf.dtsi" #include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
#include <dt-bindings/phy/phy.h> #include <dt-bindings/phy/phy.h>
/ { / {
...@@ -64,6 +65,8 @@ clock_8t49n287_3: clk27 { ...@@ -64,6 +65,8 @@ clock_8t49n287_3: clk27 {
&can1 { &can1 {
status = "okay"; status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can1_default>;
}; };
&dcc { &dcc {
...@@ -106,6 +109,8 @@ &gem3 { ...@@ -106,6 +109,8 @@ &gem3 {
status = "okay"; status = "okay";
phy-handle = <&phy0>; phy-handle = <&phy0>;
phy-mode = "rgmii-id"; phy-mode = "rgmii-id";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gem3_default>;
phy0: ethernet-phy@c { phy0: ethernet-phy@c {
reg = <0xc>; reg = <0xc>;
ti,rx-internal-delay = <0x8>; ti,rx-internal-delay = <0x8>;
...@@ -122,6 +127,11 @@ &gpio { ...@@ -122,6 +127,11 @@ &gpio {
&i2c1 { &i2c1 {
status = "okay"; status = "okay";
clock-frequency = <400000>; clock-frequency = <400000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1_default>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
tca6416_u97: gpio@20 { tca6416_u97: gpio@20 {
compatible = "ti,tca6416"; compatible = "ti,tca6416";
...@@ -219,6 +229,204 @@ i2c@7 { ...@@ -219,6 +229,204 @@ i2c@7 {
}; };
}; };
&pinctrl0 {
status = "okay";
pinctrl_can1_default: can1-default {
mux {
function = "can1";
groups = "can1_6_grp";
};
conf {
groups = "can1_6_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
drive-strength = <12>;
};
conf-rx {
pins = "MIO25";
bias-high-impedance;
};
conf-tx {
pins = "MIO24";
bias-disable;
};
};
pinctrl_i2c1_default: i2c1-default {
mux {
groups = "i2c1_4_grp";
function = "i2c1";
};
conf {
groups = "i2c1_4_grp";
bias-pull-up;
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
drive-strength = <12>;
};
};
pinctrl_i2c1_gpio: i2c1-gpio {
mux {
groups = "gpio0_16_grp", "gpio0_17_grp";
function = "gpio0";
};
conf {
groups = "gpio0_16_grp", "gpio0_17_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
drive-strength = <12>;
};
};
pinctrl_gem3_default: gem3-default {
mux {
function = "ethernet3";
groups = "ethernet3_0_grp";
};
conf {
groups = "ethernet3_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
drive-strength = <12>;
};
conf-rx {
pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
"MIO75";
bias-high-impedance;
low-power-disable;
};
conf-tx {
pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
"MIO69";
bias-disable;
low-power-enable;
};
mux-mdio {
function = "mdio3";
groups = "mdio3_0_grp";
};
conf-mdio {
groups = "mdio3_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
bias-disable;
};
};
pinctrl_sdhci1_default: sdhci1-default {
mux {
groups = "sdio1_0_grp";
function = "sdio1";
};
conf {
groups = "sdio1_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
bias-disable;
drive-strength = <12>;
};
mux-cd {
groups = "sdio1_cd_0_grp";
function = "sdio1_cd";
};
conf-cd {
groups = "sdio1_cd_0_grp";
bias-high-impedance;
bias-pull-up;
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
};
pinctrl_uart0_default: uart0-default {
mux {
groups = "uart0_4_grp";
function = "uart0";
};
conf {
groups = "uart0_4_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
drive-strength = <12>;
};
conf-rx {
pins = "MIO18";
bias-high-impedance;
};
conf-tx {
pins = "MIO19";
bias-disable;
};
};
pinctrl_uart1_default: uart1-default {
mux {
groups = "uart1_5_grp";
function = "uart1";
};
conf {
groups = "uart1_5_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
drive-strength = <12>;
};
conf-rx {
pins = "MIO21";
bias-high-impedance;
};
conf-tx {
pins = "MIO20";
bias-disable;
};
};
pinctrl_usb0_default: usb0-default {
mux {
groups = "usb0_0_grp";
function = "usb0";
};
conf {
groups = "usb0_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
drive-strength = <12>;
};
conf-rx {
pins = "MIO52", "MIO53", "MIO55";
bias-high-impedance;
};
conf-tx {
pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
"MIO60", "MIO61", "MIO62", "MIO63";
bias-disable;
};
};
};
&qspi { &qspi {
status = "okay"; status = "okay";
flash@0 { flash@0 {
...@@ -259,21 +467,29 @@ &sata { ...@@ -259,21 +467,29 @@ &sata {
&sdhci1 { &sdhci1 {
status = "okay"; status = "okay";
no-1-8-v; no-1-8-v;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdhci1_default>;
xlnx,mio-bank = <1>; xlnx,mio-bank = <1>;
disable-wp; disable-wp;
}; };
&uart0 { &uart0 {
status = "okay"; status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0_default>;
}; };
&uart1 { &uart1 {
status = "okay"; status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_default>;
}; };
/* ULPI SMSC USB3320 */ /* ULPI SMSC USB3320 */
&usb0 { &usb0 {
status = "okay"; status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0_default>;
dr_mode = "host"; dr_mode = "host";
}; };
......
arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
View file @ c821045f
...@@ -2,7 +2,7 @@ ...@@ -2,7 +2,7 @@
/* /*
* dts file for Xilinx ZynqMP ZCU106 * dts file for Xilinx ZynqMP ZCU106
* *
* (C) Copyright 2016 - 2019, Xilinx, Inc. * (C) Copyright 2016 - 2021, Xilinx, Inc.
* *
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@xilinx.com>
*/ */
...@@ -13,6 +13,7 @@ ...@@ -13,6 +13,7 @@
#include "zynqmp-clk-ccf.dtsi" #include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/input/input.h> #include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
#include <dt-bindings/phy/phy.h> #include <dt-bindings/phy/phy.h>
/ { / {
...@@ -150,6 +151,8 @@ refhdmi: refhdmi { ...@@ -150,6 +151,8 @@ refhdmi: refhdmi {
&can1 { &can1 {
status = "okay"; status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can1_default>;
}; };
&dcc { &dcc {
...@@ -204,6 +207,8 @@ &gem3 { ...@@ -204,6 +207,8 @@ &gem3 {
status = "okay"; status = "okay";
phy-handle = <&phy0>; phy-handle = <&phy0>;
phy-mode = "rgmii-id"; phy-mode = "rgmii-id";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gem3_default>;
phy0: ethernet-phy@c { phy0: ethernet-phy@c {
reg = <0xc>; reg = <0xc>;
ti,rx-internal-delay = <0x8>; ti,rx-internal-delay = <0x8>;
...@@ -215,11 +220,18 @@ phy0: ethernet-phy@c { ...@@ -215,11 +220,18 @@ phy0: ethernet-phy@c {
&gpio { &gpio {
status = "okay"; status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_default>;
}; };
&i2c0 { &i2c0 {
status = "okay"; status = "okay";
clock-frequency = <400000>; clock-frequency = <400000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c0_default>;
pinctrl-1 = <&pinctrl_i2c0_gpio>;
scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
tca6416_u97: gpio@20 { tca6416_u97: gpio@20 {
compatible = "ti,tca6416"; compatible = "ti,tca6416";
...@@ -478,6 +490,11 @@ max20751@73 { /* u96 */ ...@@ -478,6 +490,11 @@ max20751@73 { /* u96 */
&i2c1 { &i2c1 {
status = "okay"; status = "okay";
clock-frequency = <400000>; clock-frequency = <400000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1_default>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
/* PL i2c via PCA9306 - u45 */ /* PL i2c via PCA9306 - u45 */
i2c-mux@74 { /* u34 */ i2c-mux@74 { /* u34 */
...@@ -652,6 +669,269 @@ i2c@7 { ...@@ -652,6 +669,269 @@ i2c@7 {
}; };
}; };
&pinctrl0 {
status = "okay";
pinctrl_i2c0_default: i2c0-default {
mux {
groups = "i2c0_3_grp";
function = "i2c0";
};
conf {
groups = "i2c0_3_grp";
bias-pull-up;
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
};
pinctrl_i2c0_gpio: i2c0-gpio {
mux {
groups = "gpio0_14_grp", "gpio0_15_grp";
function = "gpio0";
};
conf {
groups = "gpio0_14_grp", "gpio0_15_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
};
pinctrl_i2c1_default: i2c1-default {
mux {
groups = "i2c1_4_grp";
function = "i2c1";
};
conf {
groups = "i2c1_4_grp";
bias-pull-up;
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
};
pinctrl_i2c1_gpio: i2c1-gpio {
mux {
groups = "gpio0_16_grp", "gpio0_17_grp";
function = "gpio0";
};
conf {
groups = "gpio0_16_grp", "gpio0_17_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
};
pinctrl_uart0_default: uart0-default {
mux {
groups = "uart0_4_grp";
function = "uart0";
};
conf {
groups = "uart0_4_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
conf-rx {
pins = "MIO18";
bias-high-impedance;
};
conf-tx {
pins = "MIO19";
bias-disable;
};
};
pinctrl_uart1_default: uart1-default {
mux {
groups = "uart1_5_grp";
function = "uart1";
};
conf {
groups = "uart1_5_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
conf-rx {
pins = "MIO21";
bias-high-impedance;
};
conf-tx {
pins = "MIO20";
bias-disable;
};
};
pinctrl_usb0_default: usb0-default {
mux {
groups = "usb0_0_grp";
function = "usb0";
};
conf {
groups = "usb0_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
conf-rx {
pins = "MIO52", "MIO53", "MIO55";
bias-high-impedance;
};
conf-tx {
pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
"MIO60", "MIO61", "MIO62", "MIO63";
bias-disable;
};
};
pinctrl_gem3_default: gem3-default {
mux {
function = "ethernet3";
groups = "ethernet3_0_grp";
};
conf {
groups = "ethernet3_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
conf-rx {
pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
"MIO75";
bias-high-impedance;
low-power-disable;
};
conf-tx {
pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
"MIO69";
bias-disable;
low-power-enable;
};
mux-mdio {
function = "mdio3";
groups = "mdio3_0_grp";
};
conf-mdio {
groups = "mdio3_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
bias-disable;
};
};
pinctrl_can1_default: can1-default {
mux {
function = "can1";
groups = "can1_6_grp";
};
conf {
groups = "can1_6_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
conf-rx {
pins = "MIO25";
bias-high-impedance;
};
conf-tx {
pins = "MIO24";
bias-disable;
};
};
pinctrl_sdhci1_default: sdhci1-default {
mux {
groups = "sdio1_0_grp";
function = "sdio1";
};
conf {
groups = "sdio1_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
bias-disable;
};
mux-cd {
groups = "sdio1_cd_0_grp";
function = "sdio1_cd";
};
conf-cd {
groups = "sdio1_cd_0_grp";
bias-high-impedance;
bias-pull-up;
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
mux-wp {
groups = "sdio1_wp_0_grp";
function = "sdio1_wp";
};
conf-wp {
groups = "sdio1_wp_0_grp";
bias-high-impedance;
bias-pull-up;
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
};
pinctrl_gpio_default: gpio-default {
mux {
function = "gpio0";
groups = "gpio0_22_grp", "gpio0_23_grp";
};
conf {
groups = "gpio0_22_grp", "gpio0_23_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
mux-msp {
function = "gpio0";
groups = "gpio0_13_grp", "gpio0_38_grp";
};
conf-msp {
groups = "gpio0_13_grp", "gpio0_38_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
conf-pull-up {
pins = "MIO22";
bias-pull-up;
};
conf-pull-none {
pins = "MIO13", "MIO23", "MIO38";
bias-disable;
};
};
};
&psgtr { &psgtr {
status = "okay"; status = "okay";
/* nc, sata, usb3, dp */ /* nc, sata, usb3, dp */
...@@ -682,20 +962,28 @@ &sata { ...@@ -682,20 +962,28 @@ &sata {
&sdhci1 { &sdhci1 {
status = "okay"; status = "okay";
no-1-8-v; no-1-8-v;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdhci1_default>;
xlnx,mio-bank = <1>; xlnx,mio-bank = <1>;
}; };
&uart0 { &uart0 {
status = "okay"; status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0_default>;
}; };
&uart1 { &uart1 {
status = "okay"; status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_default>;
}; };
/* ULPI SMSC USB3320 */ /* ULPI SMSC USB3320 */
&usb0 { &usb0 {
status = "okay"; status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0_default>;
dr_mode = "host"; dr_mode = "host";
}; };
......
arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
View file @ c821045f
...@@ -2,7 +2,7 @@ ...@@ -2,7 +2,7 @@
/* /*
* dts file for Xilinx ZynqMP ZCU111 * dts file for Xilinx ZynqMP ZCU111
* *
* (C) Copyright 2017 - 2019, Xilinx, Inc. * (C) Copyright 2017 - 2021, Xilinx, Inc.
* *
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@xilinx.com>
*/ */
...@@ -13,6 +13,7 @@ ...@@ -13,6 +13,7 @@
#include "zynqmp-clk-ccf.dtsi" #include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/input/input.h> #include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
#include <dt-bindings/phy/phy.h> #include <dt-bindings/phy/phy.h>
/ { / {
...@@ -166,6 +167,8 @@ &gem3 { ...@@ -166,6 +167,8 @@ &gem3 {
status = "okay"; status = "okay";
phy-handle = <&phy0>; phy-handle = <&phy0>;
phy-mode = "rgmii-id"; phy-mode = "rgmii-id";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gem3_default>;
phy0: ethernet-phy@c { phy0: ethernet-phy@c {
reg = <0xc>; reg = <0xc>;
ti,rx-internal-delay = <0x8>; ti,rx-internal-delay = <0x8>;
...@@ -177,11 +180,18 @@ phy0: ethernet-phy@c { ...@@ -177,11 +180,18 @@ phy0: ethernet-phy@c {
&gpio { &gpio {
status = "okay"; status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_default>;
}; };
&i2c0 { &i2c0 {
status = "okay"; status = "okay";
clock-frequency = <400000>; clock-frequency = <400000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c0_default>;
pinctrl-1 = <&pinctrl_i2c0_gpio>;
scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
tca6416_u22: gpio@20 { tca6416_u22: gpio@20 {
compatible = "ti,tca6416"; compatible = "ti,tca6416";
...@@ -357,6 +367,11 @@ i2c@3 { ...@@ -357,6 +367,11 @@ i2c@3 {
&i2c1 { &i2c1 {
status = "okay"; status = "okay";
clock-frequency = <400000>; clock-frequency = <400000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1_default>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
i2c-mux@74 { /* u26 */ i2c-mux@74 { /* u26 */
compatible = "nxp,pca9548"; compatible = "nxp,pca9548";
...@@ -545,6 +560,210 @@ i2c@7 { ...@@ -545,6 +560,210 @@ i2c@7 {
}; };
}; };
&pinctrl0 {
status = "okay";
pinctrl_i2c0_default: i2c0-default {
mux {
groups = "i2c0_3_grp";
function = "i2c0";
};
conf {
groups = "i2c0_3_grp";
bias-pull-up;
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
};
pinctrl_i2c0_gpio: i2c0-gpio {
mux {
groups = "gpio0_14_grp", "gpio0_15_grp";
function = "gpio0";
};
conf {
groups = "gpio0_14_grp", "gpio0_15_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
};
pinctrl_i2c1_default: i2c1-default {
mux {
groups = "i2c1_4_grp";
function = "i2c1";
};
conf {
groups = "i2c1_4_grp";
bias-pull-up;
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
};
pinctrl_i2c1_gpio: i2c1-gpio {
mux {
groups = "gpio0_16_grp", "gpio0_17_grp";
function = "gpio0";
};
conf {
groups = "gpio0_16_grp", "gpio0_17_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
};
pinctrl_uart0_default: uart0-default {
mux {
groups = "uart0_4_grp";
function = "uart0";
};
conf {
groups = "uart0_4_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
conf-rx {
pins = "MIO18";
bias-high-impedance;
};
conf-tx {
pins = "MIO19";
bias-disable;
};
};
pinctrl_usb0_default: usb0-default {
mux {
groups = "usb0_0_grp";
function = "usb0";
};
conf {
groups = "usb0_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
conf-rx {
pins = "MIO52", "MIO53", "MIO55";
bias-high-impedance;
};
conf-tx {
pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
"MIO60", "MIO61", "MIO62", "MIO63";
bias-disable;
};
};
pinctrl_gem3_default: gem3-default {
mux {
function = "ethernet3";
groups = "ethernet3_0_grp";
};
conf {
groups = "ethernet3_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
conf-rx {
pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
"MIO75";
bias-high-impedance;
low-power-disable;
};
conf-tx {
pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
"MIO69";
bias-disable;
low-power-enable;
};
mux-mdio {
function = "mdio3";
groups = "mdio3_0_grp";
};
conf-mdio {
groups = "mdio3_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
bias-disable;
};
};
pinctrl_sdhci1_default: sdhci1-default {
mux {
groups = "sdio1_0_grp";
function = "sdio1";
};
conf {
groups = "sdio1_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
bias-disable;
};
mux-cd {
groups = "sdio1_cd_0_grp";
function = "sdio1_cd";
};
conf-cd {
groups = "sdio1_cd_0_grp";
bias-high-impedance;
bias-pull-up;
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
};
pinctrl_gpio_default: gpio-default {
mux {
function = "gpio0";
groups = "gpio0_22_grp", "gpio0_23_grp";
};
conf {
groups = "gpio0_22_grp", "gpio0_23_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
mux-msp {
function = "gpio0";
groups = "gpio0_13_grp", "gpio0_38_grp";
};
conf-msp {
groups = "gpio0_13_grp", "gpio0_38_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
conf-pull-up {
pins = "MIO22";
bias-pull-up;
};
conf-pull-none {
pins = "MIO13", "MIO23", "MIO38";
bias-disable;
};
};
};
&psgtr { &psgtr {
status = "okay"; status = "okay";
/* nc, sata, usb3, dp */ /* nc, sata, usb3, dp */
...@@ -574,17 +793,23 @@ &sata { ...@@ -574,17 +793,23 @@ &sata {
/* SD1 with level shifter */ /* SD1 with level shifter */
&sdhci1 { &sdhci1 {
status = "okay"; status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdhci1_default>;
no-1-8-v; no-1-8-v;
xlnx,mio-bank = <1>; xlnx,mio-bank = <1>;
}; };
&uart0 { &uart0 {
status = "okay"; status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0_default>;
}; };
/* ULPI SMSC USB3320 */ /* ULPI SMSC USB3320 */
&usb0 { &usb0 {
status = "okay"; status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0_default>;
dr_mode = "host"; dr_mode = "host";
}; };
......
arch/arm64/boot/dts/xilinx/zynqmp.dtsi
View file @ c821045f
...@@ -193,6 +193,11 @@ zynqmp_reset: reset-controller { ...@@ -193,6 +193,11 @@ zynqmp_reset: reset-controller {
compatible = "xlnx,zynqmp-reset"; compatible = "xlnx,zynqmp-reset";
#reset-cells = <1>; #reset-cells = <1>;
}; };
pinctrl0: pinctrl {
compatible = "xlnx,zynqmp-pinctrl";
status = "disabled";
};
}; };
}; };
......
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