Commit c836fec5 authored by Jim Qu's avatar Jim Qu Committed by Alex Deucher

drm/amd/amdgpu: post card if there is real hw resetting performed

Check whether we need to post rather than whether the asic is
posted.  There are some cases (e.g., GPU reset or resume from
hibernate) where we need to force post even if the asic has
been posted.
Signed-off-by: default avatarJim Qu <Jim.Qu@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 9ca70356
...@@ -1482,6 +1482,9 @@ struct amdgpu_device { ...@@ -1482,6 +1482,9 @@ struct amdgpu_device {
spinlock_t gtt_list_lock; spinlock_t gtt_list_lock;
struct list_head gtt_list; struct list_head gtt_list;
/* record hw reset is performed */
bool has_hw_reset;
}; };
static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev) static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
...@@ -1700,7 +1703,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring) ...@@ -1700,7 +1703,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
int amdgpu_gpu_reset(struct amdgpu_device *adev); int amdgpu_gpu_reset(struct amdgpu_device *adev);
bool amdgpu_need_backup(struct amdgpu_device *adev); bool amdgpu_need_backup(struct amdgpu_device *adev);
void amdgpu_pci_config_reset(struct amdgpu_device *adev); void amdgpu_pci_config_reset(struct amdgpu_device *adev);
bool amdgpu_card_posted(struct amdgpu_device *adev); bool amdgpu_need_post(struct amdgpu_device *adev);
void amdgpu_update_display_priority(struct amdgpu_device *adev); void amdgpu_update_display_priority(struct amdgpu_device *adev);
int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data); int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data);
......
...@@ -100,7 +100,7 @@ static bool igp_read_bios_from_vram(struct amdgpu_device *adev) ...@@ -100,7 +100,7 @@ static bool igp_read_bios_from_vram(struct amdgpu_device *adev)
resource_size_t size = 256 * 1024; /* ??? */ resource_size_t size = 256 * 1024; /* ??? */
if (!(adev->flags & AMD_IS_APU)) if (!(adev->flags & AMD_IS_APU))
if (!amdgpu_card_posted(adev)) if (amdgpu_need_post(adev))
return false; return false;
adev->bios = NULL; adev->bios = NULL;
......
...@@ -619,26 +619,30 @@ void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc) ...@@ -619,26 +619,30 @@ void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc)
* GPU helpers function. * GPU helpers function.
*/ */
/** /**
* amdgpu_card_posted - check if the hw has already been initialized * amdgpu_need_post - check if the hw need post or not
* *
* @adev: amdgpu_device pointer * @adev: amdgpu_device pointer
* *
* Check if the asic has been initialized (all asics). * Check if the asic has been initialized (all asics) at driver startup
* Used at driver startup. * or post is needed if hw reset is performed.
* Returns true if initialized or false if not. * Returns true if need or false if not.
*/ */
bool amdgpu_card_posted(struct amdgpu_device *adev) bool amdgpu_need_post(struct amdgpu_device *adev)
{ {
uint32_t reg; uint32_t reg;
if (adev->has_hw_reset) {
adev->has_hw_reset = false;
return true;
}
/* then check MEM_SIZE, in case the crtcs are off */ /* then check MEM_SIZE, in case the crtcs are off */
reg = RREG32(mmCONFIG_MEMSIZE); reg = RREG32(mmCONFIG_MEMSIZE);
if (reg) if (reg)
return true;
return false; return false;
return true;
} }
static bool amdgpu_vpost_needed(struct amdgpu_device *adev) static bool amdgpu_vpost_needed(struct amdgpu_device *adev)
...@@ -665,7 +669,7 @@ static bool amdgpu_vpost_needed(struct amdgpu_device *adev) ...@@ -665,7 +669,7 @@ static bool amdgpu_vpost_needed(struct amdgpu_device *adev)
return true; return true;
} }
} }
return !amdgpu_card_posted(adev); return amdgpu_need_post(adev);
} }
/** /**
...@@ -2071,7 +2075,7 @@ int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon) ...@@ -2071,7 +2075,7 @@ int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon)
amdgpu_atombios_scratch_regs_restore(adev); amdgpu_atombios_scratch_regs_restore(adev);
/* post card */ /* post card */
if (!amdgpu_card_posted(adev) || !resume) { if (amdgpu_need_post(adev)) {
r = amdgpu_atom_asic_init(adev->mode_info.atom_context); r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
if (r) if (r)
DRM_ERROR("amdgpu asic init failed\n"); DRM_ERROR("amdgpu asic init failed\n");
......
...@@ -1176,6 +1176,7 @@ static int cik_gpu_pci_config_reset(struct amdgpu_device *adev) ...@@ -1176,6 +1176,7 @@ static int cik_gpu_pci_config_reset(struct amdgpu_device *adev)
if (RREG32(mmCONFIG_MEMSIZE) != 0xffffffff) { if (RREG32(mmCONFIG_MEMSIZE) != 0xffffffff) {
/* enable BM */ /* enable BM */
pci_set_master(adev->pdev); pci_set_master(adev->pdev);
adev->has_hw_reset = true;
r = 0; r = 0;
break; break;
} }
......
...@@ -721,6 +721,7 @@ static int vi_gpu_pci_config_reset(struct amdgpu_device *adev) ...@@ -721,6 +721,7 @@ static int vi_gpu_pci_config_reset(struct amdgpu_device *adev)
if (RREG32(mmCONFIG_MEMSIZE) != 0xffffffff) { if (RREG32(mmCONFIG_MEMSIZE) != 0xffffffff) {
/* enable BM */ /* enable BM */
pci_set_master(adev->pdev); pci_set_master(adev->pdev);
adev->has_hw_reset = true;
return 0; return 0;
} }
udelay(1); udelay(1);
......
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