Commit c8f5a878 authored by Thomas Petazzoni's avatar Thomas Petazzoni Committed by Gregory CLEMENT

ARM: mvebu: use DT properties to fine-tune the L2 configuration

In order to optimize the L2 cache performance, this commit adjusts the
configuration of the L2 on the Cortex-A9 based Marvell EBU processors
(Armada 375, 38x and 39x), using the appropriate DT properties.

We enable double linefill, incr double linefill, data prefetch and
disable double linefill on wrap. This matches the configuration that
was fine tuned in the Marvell BSP.
Signed-off-by: default avatarThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: default avatarGregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: default avatarGregory CLEMENT <gregory.clement@free-electrons.com>
parent 449e1d64
...@@ -176,6 +176,10 @@ L2: cache-controller@8000 { ...@@ -176,6 +176,10 @@ L2: cache-controller@8000 {
reg = <0x8000 0x1000>; reg = <0x8000 0x1000>;
cache-unified; cache-unified;
cache-level = <2>; cache-level = <2>;
arm,double-linefill-incr = <1>;
arm,double-linefill-wrap = <0>;
arm,double-linefill = <1>;
prefetch-data = <1>;
}; };
scu@c000 { scu@c000 {
......
...@@ -143,6 +143,10 @@ L2: cache-controller@8000 { ...@@ -143,6 +143,10 @@ L2: cache-controller@8000 {
reg = <0x8000 0x1000>; reg = <0x8000 0x1000>;
cache-unified; cache-unified;
cache-level = <2>; cache-level = <2>;
arm,double-linefill-incr = <1>;
arm,double-linefill-wrap = <0>;
arm,double-linefill = <1>;
prefetch-data = <1>;
}; };
scu@c000 { scu@c000 {
......
...@@ -104,6 +104,10 @@ L2: cache-controller@8000 { ...@@ -104,6 +104,10 @@ L2: cache-controller@8000 {
reg = <0x8000 0x1000>; reg = <0x8000 0x1000>;
cache-unified; cache-unified;
cache-level = <2>; cache-level = <2>;
arm,double-linefill-incr = <1>;
arm,double-linefill-wrap = <0>;
arm,double-linefill = <1>;
prefetch-data = <1>;
}; };
scu@c000 { scu@c000 {
......
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