Commit c912f19e authored by Marc Kleine-Budde's avatar Marc Kleine-Budde

can: mcp251xfd: introduce struct mcp251xfd_tx_ring::nr and ::fifo_nr and make use of it

This patch removes the hard coded assumption that the TX ring uses
hardware FIFO 1. This allows the hardware FIFO 1 to be used for RX and
the next free FIFO for TX.

This gives the opportunity to minimize the number of SPI transfers in
the IRQ handler. The read of the IRQ status register and RX FIFO
status registers can be combined into single SPI transfer. If the RX
ring uses FIFO 1, the overall length of the transfer is smaller than
in the original layout, where the RX FIFO comes after the TX FIFO.

Link: https://lore.kernel.org/all/20220217103826.2299157-2-mkl@pengutronix.deSigned-off-by: default avatarMarc Kleine-Budde <mkl@pengutronix.de>
parent 2a68dd86
...@@ -78,7 +78,7 @@ int mcp251xfd_chip_fifo_init(const struct mcp251xfd_priv *priv) ...@@ -78,7 +78,7 @@ int mcp251xfd_chip_fifo_init(const struct mcp251xfd_priv *priv)
if (err) if (err)
return err; return err;
/* FIFO 1 - TX */ /* TX FIFO */
val = FIELD_PREP(MCP251XFD_REG_FIFOCON_FSIZE_MASK, val = FIELD_PREP(MCP251XFD_REG_FIFOCON_FSIZE_MASK,
tx_ring->obj_num - 1) | tx_ring->obj_num - 1) |
MCP251XFD_REG_FIFOCON_TXEN | MCP251XFD_REG_FIFOCON_TXEN |
...@@ -99,7 +99,7 @@ int mcp251xfd_chip_fifo_init(const struct mcp251xfd_priv *priv) ...@@ -99,7 +99,7 @@ int mcp251xfd_chip_fifo_init(const struct mcp251xfd_priv *priv)
MCP251XFD_REG_FIFOCON_TXAT_UNLIMITED); MCP251XFD_REG_FIFOCON_TXAT_UNLIMITED);
err = regmap_write(priv->map_reg, err = regmap_write(priv->map_reg,
MCP251XFD_REG_FIFOCON(MCP251XFD_TX_FIFO), MCP251XFD_REG_FIFOCON(priv->tx->fifo_nr),
val); val);
if (err) if (err)
return err; return err;
......
...@@ -207,10 +207,10 @@ static void mcp251xfd_dump_tx_ring(const struct mcp251xfd_priv *priv, ...@@ -207,10 +207,10 @@ static void mcp251xfd_dump_tx_ring(const struct mcp251xfd_priv *priv,
.val = tx->base, .val = tx->base,
}, { }, {
.key = MCP251XFD_DUMP_OBJECT_RING_KEY_NR, .key = MCP251XFD_DUMP_OBJECT_RING_KEY_NR,
.val = 0, .val = tx->nr,
}, { }, {
.key = MCP251XFD_DUMP_OBJECT_RING_KEY_FIFO_NR, .key = MCP251XFD_DUMP_OBJECT_RING_KEY_FIFO_NR,
.val = MCP251XFD_TX_FIFO, .val = tx->fifo_nr,
}, { }, {
.key = MCP251XFD_DUMP_OBJECT_RING_KEY_OBJ_NUM, .key = MCP251XFD_DUMP_OBJECT_RING_KEY_OBJ_NUM,
.val = tx->obj_num, .val = tx->obj_num,
......
...@@ -2,7 +2,7 @@ ...@@ -2,7 +2,7 @@
// //
// mcp251xfd - Microchip MCP251xFD Family CAN controller driver // mcp251xfd - Microchip MCP251xFD Family CAN controller driver
// //
// Copyright (c) 2019, 2020 Pengutronix, // Copyright (c) 2019, 2020, 2021 Pengutronix,
// Marc Kleine-Budde <kernel@pengutronix.de> // Marc Kleine-Budde <kernel@pengutronix.de>
// //
...@@ -47,22 +47,32 @@ mcp251xfd_regmap_nocrc_gather_write(void *context, ...@@ -47,22 +47,32 @@ mcp251xfd_regmap_nocrc_gather_write(void *context,
return spi_sync_transfer(spi, xfer, ARRAY_SIZE(xfer)); return spi_sync_transfer(spi, xfer, ARRAY_SIZE(xfer));
} }
static inline bool mcp251xfd_update_bits_read_reg(unsigned int reg) static inline bool
mcp251xfd_update_bits_read_reg(const struct mcp251xfd_priv *priv,
unsigned int reg)
{ {
struct mcp251xfd_rx_ring *ring;
int n;
switch (reg) { switch (reg) {
case MCP251XFD_REG_INT: case MCP251XFD_REG_INT:
case MCP251XFD_REG_TEFCON: case MCP251XFD_REG_TEFCON:
case MCP251XFD_REG_FIFOCON(MCP251XFD_RX_FIFO(0)):
case MCP251XFD_REG_FLTCON(0): case MCP251XFD_REG_FLTCON(0):
case MCP251XFD_REG_ECCSTAT: case MCP251XFD_REG_ECCSTAT:
case MCP251XFD_REG_CRC: case MCP251XFD_REG_CRC:
return false; return false;
case MCP251XFD_REG_CON: case MCP251XFD_REG_CON:
case MCP251XFD_REG_FIFOSTA(MCP251XFD_RX_FIFO(0)):
case MCP251XFD_REG_OSC: case MCP251XFD_REG_OSC:
case MCP251XFD_REG_ECCCON: case MCP251XFD_REG_ECCCON:
return true; return true;
default: default:
mcp251xfd_for_each_rx_ring(priv, ring, n) {
if (reg == MCP251XFD_REG_FIFOCON(ring->fifo_nr))
return false;
if (reg == MCP251XFD_REG_FIFOSTA(ring->fifo_nr))
return true;
}
WARN(1, "Status of reg 0x%04x unknown.\n", reg); WARN(1, "Status of reg 0x%04x unknown.\n", reg);
} }
...@@ -92,7 +102,7 @@ mcp251xfd_regmap_nocrc_update_bits(void *context, unsigned int reg, ...@@ -92,7 +102,7 @@ mcp251xfd_regmap_nocrc_update_bits(void *context, unsigned int reg,
last_byte = mcp251xfd_last_byte_set(mask); last_byte = mcp251xfd_last_byte_set(mask);
len = last_byte - first_byte + 1; len = last_byte - first_byte + 1;
if (mcp251xfd_update_bits_read_reg(reg)) { if (mcp251xfd_update_bits_read_reg(priv, reg)) {
struct spi_transfer xfer[2] = { }; struct spi_transfer xfer[2] = { };
struct spi_message msg; struct spi_message msg;
......
...@@ -136,9 +136,11 @@ void mcp251xfd_ring_init(struct mcp251xfd_priv *priv) ...@@ -136,9 +136,11 @@ void mcp251xfd_ring_init(struct mcp251xfd_priv *priv)
tx_ring->head = 0; tx_ring->head = 0;
tx_ring->tail = 0; tx_ring->tail = 0;
tx_ring->base = mcp251xfd_get_tef_obj_addr(tx_ring->obj_num); tx_ring->base = mcp251xfd_get_tef_obj_addr(tx_ring->obj_num);
tx_ring->nr = 0;
tx_ring->fifo_nr = MCP251XFD_TX_FIFO;
/* FIFO request to send */ /* FIFO request to send */
addr = MCP251XFD_REG_FIFOCON(MCP251XFD_TX_FIFO); addr = MCP251XFD_REG_FIFOCON(tx_ring->fifo_nr);
val = MCP251XFD_REG_FIFOCON_TXREQ | MCP251XFD_REG_FIFOCON_UINC; val = MCP251XFD_REG_FIFOCON_TXREQ | MCP251XFD_REG_FIFOCON_UINC;
len = mcp251xfd_cmd_prepare_write_reg(priv, &tx_ring->rts_buf, len = mcp251xfd_cmd_prepare_write_reg(priv, &tx_ring->rts_buf,
addr, val, val); addr, val, val);
......
...@@ -521,6 +521,8 @@ struct mcp251xfd_tx_ring { ...@@ -521,6 +521,8 @@ struct mcp251xfd_tx_ring {
unsigned int tail; unsigned int tail;
u16 base; u16 base;
u8 nr;
u8 fifo_nr;
u8 obj_num; u8 obj_num;
u8 obj_size; u8 obj_size;
...@@ -779,7 +781,7 @@ mcp251xfd_tx_tail_get_from_chip(const struct mcp251xfd_priv *priv, ...@@ -779,7 +781,7 @@ mcp251xfd_tx_tail_get_from_chip(const struct mcp251xfd_priv *priv,
int err; int err;
err = regmap_read(priv->map_reg, err = regmap_read(priv->map_reg,
MCP251XFD_REG_FIFOSTA(MCP251XFD_TX_FIFO), MCP251XFD_REG_FIFOSTA(priv->tx->fifo_nr),
&fifo_sta); &fifo_sta);
if (err) if (err)
return err; return err;
......
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