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Commit c945d022 authored by Linus Torvalds's avatar Linus Torvalds
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Merge branch 'x86-platform-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull x86 platform updates from Ingo Molnar:
 "Misc platform updates: SGI UV4 support additions, intel-mid Merrifield
  enhancements and purge of old code"

* 'x86-platform-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (21 commits)
  x86/platform/UV/NMI: Fix uneccessary kABI breakage
  x86/platform/UV: Clean up the NMI code to match current coding style
  x86/platform/UV: Ensure uv_system_init is called when necessary
  x86/platform/UV: Initialize PCH GPP_D_0 NMI Pin to be NMI source
  x86/platform/UV: Verify NMI action is valid, default is standard
  x86/platform/UV: Add basic CPU NMI health check
  x86/platform/UV: Add Support for UV4 Hubless NMIs
  x86/platform/UV: Add Support for UV4 Hubless systems
  x86/platform/UV: Clean up the UV APIC code
  x86/platform/intel-mid: Move watchdog registration to arch_initcall()
  x86/platform/intel-mid: Don't shadow error code of mp_map_gsi_to_irq()
  x86/platform/intel-mid: Allocate RTC interrupt for Merrifield
  x86/ioapic: Return suitable error code in mp_map_gsi_to_irq()
  x86/platform/UV: Fix 2 socket config problem
  x86/platform/UV: Fix panic with missing UVsystab support
  x86/platform/intel-mid: Enable RTC on Intel Merrifield
  x86/platform/intel: Remove PMIC GPIO block support
  x86/platform/intel-mid: Make intel_scu_device_register() static
  x86/platform/intel-mid: Enable GPIO keys on Merrifield
  x86/platform/intel-mid: Get rid of duplication of IPC handler
  ...
parents 8b5abde1 d48085f0
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Showing with 796 additions and 860 deletions
arch/x86/include/asm/intel-mid.h
View file @ c945d022
......@@ -27,7 +27,6 @@ extern void intel_mid_pwr_power_off(void);
extern int intel_mid_pwr_get_lss_id(struct pci_dev *pdev);
extern int get_gpio_by_name(const char *name);
extern void intel_scu_device_register(struct platform_device *pdev);
extern int __init sfi_parse_mrtc(struct sfi_table_header *table);
extern int __init sfi_parse_mtmr(struct sfi_table_header *table);
extern int sfi_mrtc_num;
......@@ -42,10 +41,8 @@ struct devs_id {
char name[SFI_NAME_LEN + 1];
u8 type;
u8 delay;
u8 msic;
void *(*get_platform_data)(void *info);
/* Custom handler for devices */
void (*device_handler)(struct sfi_device_table_entry *pentry,
struct devs_id *dev);
};
#define sfi_device(i) \
......
arch/x86/include/asm/uv/uv.h
View file @ c945d022
......@@ -10,6 +10,7 @@ struct mm_struct;
extern enum uv_system_type get_uv_system_type(void);
extern int is_uv_system(void);
extern int is_uv_hubless(void);
extern void uv_cpu_init(void);
extern void uv_nmi_init(void);
extern void uv_system_init(void);
......@@ -23,6 +24,7 @@ extern const struct cpumask *uv_flush_tlb_others(const struct cpumask *cpumask,
static inline enum uv_system_type get_uv_system_type(void) { return UV_NONE; }
static inline int is_uv_system(void) { return 0; }
static inline int is_uv_hubless(void) { return 0; }
static inline void uv_cpu_init(void) { }
static inline void uv_system_init(void) { }
static inline const struct cpumask *
......
arch/x86/include/asm/uv/uv_hub.h
View file @ c945d022
......@@ -772,6 +772,7 @@ static inline int uv_num_possible_blades(void)
/* Per Hub NMI support */
extern void uv_nmi_setup(void);
extern void uv_nmi_setup_hubless(void);
/* BMC sets a bit this MMR non-zero before sending an NMI */
#define UVH_NMI_MMR UVH_SCRATCH5
......@@ -799,6 +800,8 @@ struct uv_hub_nmi_s {
atomic_t read_mmr_count; /* count of MMR reads */
atomic_t nmi_count; /* count of true UV NMIs */
unsigned long nmi_value; /* last value read from NMI MMR */
bool hub_present; /* false means UV hubless system */
bool pch_owner; /* indicates this hub owns PCH */
};
struct uv_cpu_nmi_s {
......
arch/x86/kernel/apic/io_apic.c
View file @ c945d022
......@@ -1107,12 +1107,12 @@ int mp_map_gsi_to_irq(u32 gsi, unsigned int flags, struct irq_alloc_info *info)
ioapic = mp_find_ioapic(gsi);
if (ioapic < 0)
return -1;
return -ENODEV;
pin = mp_find_ioapic_pin(ioapic, gsi);
idx = find_irq_entry(ioapic, pin, mp_INT);
if ((flags & IOAPIC_MAP_CHECK) && idx < 0)
return -1;
return -ENODEV;
return mp_map_pin_to_irq(gsi, idx, ioapic, pin, flags, info);
}
......
arch/x86/kernel/apic/x2apic_uv_x.c
View file @ c945d022
......@@ -41,40 +41,44 @@
DEFINE_PER_CPU(int, x2apic_extra_bits);
#define PR_DEVEL(fmt, args...) pr_devel("%s: " fmt, __func__, args)
static enum uv_system_type uv_system_type;
static u64 gru_start_paddr, gru_end_paddr;
static u64 gru_dist_base, gru_first_node_paddr = -1LL, gru_last_node_paddr;
static u64 gru_dist_lmask, gru_dist_umask;
static union uvh_apicid uvh_apicid;
/* info derived from CPUID */
static enum uv_system_type uv_system_type;
static bool uv_hubless_system;
static u64 gru_start_paddr, gru_end_paddr;
static u64 gru_dist_base, gru_first_node_paddr = -1LL, gru_last_node_paddr;
static u64 gru_dist_lmask, gru_dist_umask;
static union uvh_apicid uvh_apicid;
/* Information derived from CPUID: */
static struct {
unsigned int apicid_shift;
unsigned int apicid_mask;
unsigned int socketid_shift; /* aka pnode_shift for UV1/2/3 */
unsigned int pnode_mask;
unsigned int gpa_shift;
unsigned int gnode_shift;
} uv_cpuid;
int uv_min_hub_revision_id;
EXPORT_SYMBOL_GPL(uv_min_hub_revision_id);
unsigned int uv_apicid_hibits;
EXPORT_SYMBOL_GPL(uv_apicid_hibits);
static struct apic apic_x2apic_uv_x;
static struct uv_hub_info_s uv_hub_info_node0;
/* Set this to use hardware error handler instead of kernel panic */
/* Set this to use hardware error handler instead of kernel panic: */
static int disable_uv_undefined_panic = 1;
unsigned long uv_undefined(char *str)
{
if (likely(!disable_uv_undefined_panic))
panic("UV: error: undefined MMR: %s\n", str);
else
pr_crit("UV: error: undefined MMR: %s\n", str);
return ~0ul; /* cause a machine fault */
/* Cause a machine fault: */
return ~0ul;
}
EXPORT_SYMBOL(uv_undefined);
......@@ -85,18 +89,19 @@ static unsigned long __init uv_early_read_mmr(unsigned long addr)
mmr = early_ioremap(UV_LOCAL_MMR_BASE | addr, sizeof(*mmr));
val = *mmr;
early_iounmap(mmr, sizeof(*mmr));
return val;
}
static inline bool is_GRU_range(u64 start, u64 end)
{
if (gru_dist_base) {
u64 su = start & gru_dist_umask; /* upper (incl pnode) bits */
u64 sl = start & gru_dist_lmask; /* base offset bits */
u64 su = start & gru_dist_umask; /* Upper (incl pnode) bits */
u64 sl = start & gru_dist_lmask; /* Base offset bits */
u64 eu = end & gru_dist_umask;
u64 el = end & gru_dist_lmask;
/* Must reside completely within a single GRU range */
/* Must reside completely within a single GRU range: */
return (sl == gru_dist_base && el == gru_dist_base &&
su >= gru_first_node_paddr &&
su <= gru_last_node_paddr &&
......@@ -133,13 +138,14 @@ static int __init early_get_pnodeid(void)
break;
case UV4_HUB_PART_NUMBER:
uv_min_hub_revision_id += UV4_HUB_REVISION_BASE - 1;
uv_cpuid.gnode_shift = 2; /* min partition is 4 sockets */
break;
}
uv_hub_info->hub_revision = uv_min_hub_revision_id;
uv_cpuid.pnode_mask = (1 << m_n_config.s.n_skt) - 1;
pnode = (node_id.s.node_id >> 1) & uv_cpuid.pnode_mask;
uv_cpuid.gpa_shift = 46; /* default unless changed */
uv_cpuid.gpa_shift = 46; /* Default unless changed */
pr_info("UV: rev:%d part#:%x nodeid:%04x n_skt:%d pnmsk:%x pn:%x\n",
node_id.s.revision, node_id.s.part_number, node_id.s.node_id,
......@@ -147,11 +153,12 @@ static int __init early_get_pnodeid(void)
return pnode;
}
/* [copied from arch/x86/kernel/cpu/topology.c:detect_extended_topology()] */
#define SMT_LEVEL 0 /* leaf 0xb SMT level */
#define INVALID_TYPE 0 /* leaf 0xb sub-leaf types */
#define SMT_TYPE 1
#define CORE_TYPE 2
/* [Copied from arch/x86/kernel/cpu/topology.c:detect_extended_topology()] */
#define SMT_LEVEL 0 /* Leaf 0xb SMT level */
#define INVALID_TYPE 0 /* Leaf 0xb sub-leaf types */
#define SMT_TYPE 1
#define CORE_TYPE 2
#define LEAFB_SUBTYPE(ecx) (((ecx) >> 8) & 0xff)
#define BITS_SHIFT_NEXT_LEVEL(eax) ((eax) & 0x1f)
......@@ -165,11 +172,13 @@ static void set_x2apic_bits(void)
pr_info("UV: CPU does not have CPUID.11\n");
return;
}
cpuid_count(0xb, SMT_LEVEL, &eax, &ebx, &ecx, &edx);
if (ebx == 0 || (LEAFB_SUBTYPE(ecx) != SMT_TYPE)) {
pr_info("UV: CPUID.11 not implemented\n");
return;
}
sid_shift = BITS_SHIFT_NEXT_LEVEL(eax);
sub_index = 1;
do {
......@@ -180,8 +189,9 @@ static void set_x2apic_bits(void)
}
sub_index++;
} while (LEAFB_SUBTYPE(ecx) != INVALID_TYPE);
uv_cpuid.apicid_shift = 0;
uv_cpuid.apicid_mask = (~(-1 << sid_shift));
uv_cpuid.apicid_shift = 0;
uv_cpuid.apicid_mask = (~(-1 << sid_shift));
uv_cpuid.socketid_shift = sid_shift;
}
......@@ -192,10 +202,8 @@ static void __init early_get_apic_socketid_shift(void)
set_x2apic_bits();
pr_info("UV: apicid_shift:%d apicid_mask:0x%x\n",
uv_cpuid.apicid_shift, uv_cpuid.apicid_mask);
pr_info("UV: socketid_shift:%d pnode_mask:0x%x\n",
uv_cpuid.socketid_shift, uv_cpuid.pnode_mask);
pr_info("UV: apicid_shift:%d apicid_mask:0x%x\n", uv_cpuid.apicid_shift, uv_cpuid.apicid_mask);
pr_info("UV: socketid_shift:%d pnode_mask:0x%x\n", uv_cpuid.socketid_shift, uv_cpuid.pnode_mask);
}
/*
......@@ -208,10 +216,8 @@ static void __init uv_set_apicid_hibit(void)
union uv1h_lb_target_physical_apic_id_mask_u apicid_mask;
if (is_uv1_hub()) {
apicid_mask.v =
uv_early_read_mmr(UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK);
uv_apicid_hibits =
apicid_mask.s1.bit_enables & UV_APICID_HIBIT_MASK;
apicid_mask.v = uv_early_read_mmr(UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK);
uv_apicid_hibits = apicid_mask.s1.bit_enables & UV_APICID_HIBIT_MASK;
}
}
......@@ -220,20 +226,26 @@ static int __init uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
int pnodeid;
int uv_apic;
if (strncmp(oem_id, "SGI", 3) != 0)
if (strncmp(oem_id, "SGI", 3) != 0) {
if (strncmp(oem_id, "NSGI", 4) == 0) {
uv_hubless_system = true;
pr_info("UV: OEM IDs %s/%s, HUBLESS\n",
oem_id, oem_table_id);
}
return 0;
}
if (numa_off) {
pr_err("UV: NUMA is off, disabling UV support\n");
return 0;
}
/* Setup early hub type field in uv_hub_info for Node 0 */
/* Set up early hub type field in uv_hub_info for Node 0 */
uv_cpu_info->p_uv_hub_info = &uv_hub_info_node0;
/*
* Determine UV arch type.
* SGI: UV100/1000
* SGI: UV100/1000
* SGI2: UV2000/3000
* SGI3: UV300 (truncated to 4 chars because of different varieties)
* SGI4: UV400 (truncated to 4 chars because of different varieties)
......@@ -249,31 +261,32 @@ static int __init uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
pnodeid = early_get_pnodeid();
early_get_apic_socketid_shift();
x86_platform.is_untracked_pat_range = uv_is_untracked_pat_range;
x86_platform.is_untracked_pat_range = uv_is_untracked_pat_range;
x86_platform.nmi_init = uv_nmi_init;
if (!strcmp(oem_table_id, "UVX")) { /* most common */
if (!strcmp(oem_table_id, "UVX")) {
/* This is the most common hardware variant: */
uv_system_type = UV_X2APIC;
uv_apic = 0;
} else if (!strcmp(oem_table_id, "UVH")) { /* only UV1 systems */
} else if (!strcmp(oem_table_id, "UVH")) {
/* Only UV1 systems: */
uv_system_type = UV_NON_UNIQUE_APIC;
__this_cpu_write(x2apic_extra_bits,
pnodeid << uvh_apicid.s.pnode_shift);
__this_cpu_write(x2apic_extra_bits, pnodeid << uvh_apicid.s.pnode_shift);
uv_set_apicid_hibit();
uv_apic = 1;
} else if (!strcmp(oem_table_id, "UVL")) { /* only used for */
uv_system_type = UV_LEGACY_APIC; /* very small systems */
} else if (!strcmp(oem_table_id, "UVL")) {
/* Only used for very small systems: */
uv_system_type = UV_LEGACY_APIC;
uv_apic = 0;
} else {
goto badbios;
}
pr_info("UV: OEM IDs %s/%s, System/HUB Types %d/%d, uv_apic %d\n",
oem_id, oem_table_id, uv_system_type,
uv_min_hub_revision_id, uv_apic);
pr_info("UV: OEM IDs %s/%s, System/HUB Types %d/%d, uv_apic %d\n", oem_id, oem_table_id, uv_system_type, uv_min_hub_revision_id, uv_apic);
return uv_apic;
......@@ -294,6 +307,12 @@ int is_uv_system(void)
}
EXPORT_SYMBOL_GPL(is_uv_system);
int is_uv_hubless(void)
{
return uv_hubless_system;
}
EXPORT_SYMBOL_GPL(is_uv_hubless);
void **__uv_hub_info_list;
EXPORT_SYMBOL_GPL(__uv_hub_info_list);
......@@ -306,16 +325,18 @@ EXPORT_SYMBOL_GPL(uv_possible_blades);
unsigned long sn_rtc_cycles_per_second;
EXPORT_SYMBOL(sn_rtc_cycles_per_second);
/* the following values are used for the per node hub info struct */
static __initdata unsigned short *_node_to_pnode;
static __initdata unsigned short _min_socket, _max_socket;
static __initdata unsigned short _min_pnode, _max_pnode, _gr_table_len;
static __initdata struct uv_gam_range_entry *uv_gre_table;
static __initdata struct uv_gam_parameters *uv_gp_table;
static __initdata unsigned short *_socket_to_node;
static __initdata unsigned short *_socket_to_pnode;
static __initdata unsigned short *_pnode_to_socket;
static __initdata struct uv_gam_range_s *_gr_table;
/* The following values are used for the per node hub info struct */
static __initdata unsigned short *_node_to_pnode;
static __initdata unsigned short _min_socket, _max_socket;
static __initdata unsigned short _min_pnode, _max_pnode, _gr_table_len;
static __initdata struct uv_gam_range_entry *uv_gre_table;
static __initdata struct uv_gam_parameters *uv_gp_table;
static __initdata unsigned short *_socket_to_node;
static __initdata unsigned short *_socket_to_pnode;
static __initdata unsigned short *_pnode_to_socket;
static __initdata struct uv_gam_range_s *_gr_table;
#define SOCK_EMPTY ((unsigned short)~0)
extern int uv_hub_info_version(void)
......@@ -324,7 +345,7 @@ extern int uv_hub_info_version(void)
}
EXPORT_SYMBOL(uv_hub_info_version);
/* Build GAM range lookup table */
/* Build GAM range lookup table: */
static __init void build_uv_gr_table(void)
{
struct uv_gam_range_entry *gre = uv_gre_table;
......@@ -342,25 +363,24 @@ static __init void build_uv_gr_table(void)
for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) {
if (gre->type == UV_GAM_RANGE_TYPE_HOLE) {
if (!ram_limit) { /* mark hole between ram/non-ram */
if (!ram_limit) {
/* Mark hole between RAM/non-RAM: */
ram_limit = last_limit;
last_limit = gre->limit;
lsid++;
continue;
}
last_limit = gre->limit;
pr_info("UV: extra hole in GAM RE table @%d\n",
(int)(gre - uv_gre_table));
pr_info("UV: extra hole in GAM RE table @%d\n", (int)(gre - uv_gre_table));
continue;
}
if (_max_socket < gre->sockid) {
pr_err("UV: GAM table sockid(%d) too large(>%d) @%d\n",
gre->sockid, _max_socket,
(int)(gre - uv_gre_table));
pr_err("UV: GAM table sockid(%d) too large(>%d) @%d\n", gre->sockid, _max_socket, (int)(gre - uv_gre_table));
continue;
}
sid = gre->sockid - _min_socket;
if (lsid < sid) { /* new range */
if (lsid < sid) {
/* New range: */
grt = &_gr_table[indx];
grt->base = lindx;
grt->nasid = gre->nasid;
......@@ -369,27 +389,32 @@ static __init void build_uv_gr_table(void)
lindx = indx++;
continue;
}
if (lsid == sid && !ram_limit) { /* update range */
if (grt->limit == last_limit) { /* .. if contiguous */
/* Update range: */
if (lsid == sid && !ram_limit) {
/* .. if contiguous: */
if (grt->limit == last_limit) {
grt->limit = last_limit = gre->limit;
continue;
}
}
if (!ram_limit) { /* non-contiguous ram range */
/* Non-contiguous RAM range: */
if (!ram_limit) {
grt++;
grt->base = lindx;
grt->nasid = gre->nasid;
grt->limit = last_limit = gre->limit;
continue;
}
grt++; /* non-contiguous/non-ram */
grt->base = grt - _gr_table; /* base is this entry */
/* Non-contiguous/non-RAM: */
grt++;
/* base is this entry */
grt->base = grt - _gr_table;
grt->nasid = gre->nasid;
grt->limit = last_limit = gre->limit;
lsid++;
}
/* shorten table if possible */
/* Shorten table if possible */
grt++;
i = grt - _gr_table;
if (i < _gr_table_len) {
......@@ -403,16 +428,15 @@ static __init void build_uv_gr_table(void)
}
}
/* display resultant gam range table */
/* Display resultant GAM range table: */
for (i = 0, grt = _gr_table; i < _gr_table_len; i++, grt++) {
unsigned long start, end;
int gb = grt->base;
unsigned long start = gb < 0 ? 0 :
(unsigned long)_gr_table[gb].limit << UV_GAM_RANGE_SHFT;
unsigned long end =
(unsigned long)grt->limit << UV_GAM_RANGE_SHFT;
pr_info("UV: GAM Range %2d %04x 0x%013lx-0x%013lx (%d)\n",
i, grt->nasid, start, end, gb);
start = gb < 0 ? 0 : (unsigned long)_gr_table[gb].limit << UV_GAM_RANGE_SHFT;
end = (unsigned long)grt->limit << UV_GAM_RANGE_SHFT;
pr_info("UV: GAM Range %2d %04x 0x%013lx-0x%013lx (%d)\n", i, grt->nasid, start, end, gb);
}
}
......@@ -423,16 +447,19 @@ static int uv_wakeup_secondary(int phys_apicid, unsigned long start_rip)
pnode = uv_apicid_to_pnode(phys_apicid);
phys_apicid |= uv_apicid_hibits;
val = (1UL << UVH_IPI_INT_SEND_SHFT) |
(phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
APIC_DM_INIT;
uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
val = (1UL << UVH_IPI_INT_SEND_SHFT) |
(phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
APIC_DM_STARTUP;
uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
return 0;
......@@ -566,7 +593,7 @@ static struct apic apic_x2apic_uv_x __ro_after_init = {
.apic_id_registered = uv_apic_id_registered,
.irq_delivery_mode = dest_Fixed,
.irq_dest_mode = 0, /* physical */
.irq_dest_mode = 0, /* Physical */
.target_cpus = online_target_cpus,
.disable_esr = 0,
......@@ -627,23 +654,22 @@ static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
switch (i) {
case 0:
m_redirect = UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR;
m_overlay = UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR;
m_overlay = UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR;
break;
case 1:
m_redirect = UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR;
m_overlay = UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR;
m_overlay = UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR;
break;
case 2:
m_redirect = UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR;
m_overlay = UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR;
m_overlay = UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR;
break;
}
alias.v = uv_read_local_mmr(m_overlay);
if (alias.s.enable && alias.s.base == 0) {
*size = (1UL << alias.s.m_alias);
redirect.v = uv_read_local_mmr(m_redirect);
*base = (unsigned long)redirect.s.dest_base
<< DEST_SHIFT;
*base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
return;
}
}
......@@ -652,8 +678,7 @@ static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
enum map_type {map_wb, map_uc};
static __init void map_high(char *id, unsigned long base, int pshift,
int bshift, int max_pnode, enum map_type map_type)
static __init void map_high(char *id, unsigned long base, int pshift, int bshift, int max_pnode, enum map_type map_type)
{
unsigned long bytes, paddr;
......@@ -678,16 +703,19 @@ static __init void map_gru_distributed(unsigned long c)
int nid;
gru.v = c;
/* only base bits 42:28 relevant in dist mode */
/* Only base bits 42:28 relevant in dist mode */
gru_dist_base = gru.v & 0x000007fff0000000UL;
if (!gru_dist_base) {
pr_info("UV: Map GRU_DIST base address NULL\n");
return;
}
bytes = 1UL << UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
gru_dist_lmask = ((1UL << uv_hub_info->m_val) - 1) & ~(bytes - 1);
gru_dist_umask = ~((1UL << uv_hub_info->m_val) - 1);
gru_dist_base &= gru_dist_lmask; /* Clear bits above M */
for_each_online_node(nid) {
paddr = ((u64)uv_node_to_pnode(nid) << uv_hub_info->m_val) |
gru_dist_base;
......@@ -695,11 +723,12 @@ static __init void map_gru_distributed(unsigned long c)
gru_first_node_paddr = min(paddr, gru_first_node_paddr);
gru_last_node_paddr = max(paddr, gru_last_node_paddr);
}
/* Save upper (63:M) bits of address only for is_GRU_range */
gru_first_node_paddr &= gru_dist_umask;
gru_last_node_paddr &= gru_dist_umask;
pr_debug("UV: Map GRU_DIST base 0x%016llx 0x%016llx - 0x%016llx\n",
gru_dist_base, gru_first_node_paddr, gru_last_node_paddr);
pr_debug("UV: Map GRU_DIST base 0x%016llx 0x%016llx - 0x%016llx\n", gru_dist_base, gru_first_node_paddr, gru_last_node_paddr);
}
static __init void map_gru_high(int max_pnode)
......@@ -719,6 +748,7 @@ static __init void map_gru_high(int max_pnode)
map_gru_distributed(gru.v);
return;
}
base = (gru.v & mask) >> shift;
map_high("GRU", base, shift, shift, max_pnode, map_wb);
gru_start_paddr = ((u64)base << shift);
......@@ -772,8 +802,8 @@ static __init void map_mmioh_high_uv3(int index, int min_pnode, int max_pnode)
id = mmiohs[index].id;
overlay.v = uv_read_local_mmr(mmiohs[index].overlay);
pr_info("UV: %s overlay 0x%lx base:0x%x m_io:%d\n",
id, overlay.v, overlay.s3.base, overlay.s3.m_io);
pr_info("UV: %s overlay 0x%lx base:0x%x m_io:%d\n", id, overlay.v, overlay.s3.base, overlay.s3.m_io);
if (!overlay.s3.enable) {
pr_info("UV: %s disabled\n", id);
return;
......@@ -784,7 +814,8 @@ static __init void map_mmioh_high_uv3(int index, int min_pnode, int max_pnode)
m_io = overlay.s3.m_io;
mmr = mmiohs[index].redirect;
n = UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH;
min_pnode *= 2; /* convert to NASID */
/* Convert to NASID: */
min_pnode *= 2;
max_pnode *= 2;
max_io = lnasid = fi = li = -1;
......@@ -793,16 +824,18 @@ static __init void map_mmioh_high_uv3(int index, int min_pnode, int max_pnode)
redirect.v = uv_read_local_mmr(mmr + i * 8);
nasid = redirect.s3.nasid;
/* Invalid NASID: */
if (nasid < min_pnode || max_pnode < nasid)
nasid = -1; /* invalid NASID */
nasid = -1;
if (nasid == lnasid) {
li = i;
if (i != n-1) /* last entry check */
/* Last entry check: */
if (i != n-1)
continue;
}
/* check if we have a cached (or last) redirect to print */
/* Check if we have a cached (or last) redirect to print: */
if (lnasid != -1 || (i == n-1 && nasid != -1)) {
unsigned long addr1, addr2;
int f, l;
......@@ -814,12 +847,9 @@ static __init void map_mmioh_high_uv3(int index, int min_pnode, int max_pnode)
f = fi;
l = li;
}
addr1 = (base << shift) +
f * (1ULL << m_io);
addr2 = (base << shift) +
(l + 1) * (1ULL << m_io);
pr_info("UV: %s[%03d..%03d] NASID 0x%04x ADDR 0x%016lx - 0x%016lx\n",
id, fi, li, lnasid, addr1, addr2);
addr1 = (base << shift) + f * (1ULL << m_io);
addr2 = (base << shift) + (l + 1) * (1ULL << m_io);
pr_info("UV: %s[%03d..%03d] NASID 0x%04x ADDR 0x%016lx - 0x%016lx\n", id, fi, li, lnasid, addr1, addr2);
if (max_io < l)
max_io = l;
}
......@@ -827,8 +857,7 @@ static __init void map_mmioh_high_uv3(int index, int min_pnode, int max_pnode)
lnasid = nasid;
}
pr_info("UV: %s base:0x%lx shift:%d M_IO:%d MAX_IO:%d\n",
id, base, shift, m_io, max_io);
pr_info("UV: %s base:0x%lx shift:%d M_IO:%d MAX_IO:%d\n", id, base, shift, m_io, max_io);
if (max_io >= 0)
map_high(id, base, shift, m_io, max_io, map_uc);
......@@ -841,36 +870,35 @@ static __init void map_mmioh_high(int min_pnode, int max_pnode)
int shift, enable, m_io, n_io;
if (is_uv3_hub() || is_uv4_hub()) {
/* Map both MMIOH Regions */
/* Map both MMIOH regions: */
map_mmioh_high_uv3(0, min_pnode, max_pnode);
map_mmioh_high_uv3(1, min_pnode, max_pnode);
return;
}
if (is_uv1_hub()) {
mmr = UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR;
shift = UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
mmioh.v = uv_read_local_mmr(mmr);
enable = !!mmioh.s1.enable;
base = mmioh.s1.base;
m_io = mmioh.s1.m_io;
n_io = mmioh.s1.n_io;
mmr = UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR;
shift = UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
mmioh.v = uv_read_local_mmr(mmr);
enable = !!mmioh.s1.enable;
base = mmioh.s1.base;
m_io = mmioh.s1.m_io;
n_io = mmioh.s1.n_io;
} else if (is_uv2_hub()) {
mmr = UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR;
shift = UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
mmioh.v = uv_read_local_mmr(mmr);
enable = !!mmioh.s2.enable;
base = mmioh.s2.base;
m_io = mmioh.s2.m_io;
n_io = mmioh.s2.n_io;
} else
mmr = UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR;
shift = UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
mmioh.v = uv_read_local_mmr(mmr);
enable = !!mmioh.s2.enable;
base = mmioh.s2.base;
m_io = mmioh.s2.m_io;
n_io = mmioh.s2.n_io;
} else {
return;
}
if (enable) {
max_pnode &= (1 << n_io) - 1;
pr_info(
"UV: base:0x%lx shift:%d N_IO:%d M_IO:%d max_pnode:0x%x\n",
base, shift, m_io, n_io, max_pnode);
pr_info("UV: base:0x%lx shift:%d N_IO:%d M_IO:%d max_pnode:0x%x\n", base, shift, m_io, n_io, max_pnode);
map_high("MMIOH", base, shift, m_io, max_pnode, map_uc);
} else {
pr_info("UV: MMIOH disabled\n");
......@@ -888,16 +916,16 @@ static __init void uv_rtc_init(void)
long status;
u64 ticks_per_sec;
status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK,
&ticks_per_sec);
status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK, &ticks_per_sec);
if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) {
printk(KERN_WARNING
"unable to determine platform RTC clock frequency, "
"guessing.\n");
/* BIOS gives wrong value for clock freq. so guess */
pr_warn("UV: unable to determine platform RTC clock frequency, guessing.\n");
/* BIOS gives wrong value for clock frequency, so guess: */
sn_rtc_cycles_per_second = 1000000000000UL / 30000UL;
} else
} else {
sn_rtc_cycles_per_second = ticks_per_sec;
}
}
/*
......@@ -908,19 +936,19 @@ static void uv_heartbeat(unsigned long ignored)
struct timer_list *timer = &uv_scir_info->timer;
unsigned char bits = uv_scir_info->state;
/* flip heartbeat bit */
/* Flip heartbeat bit: */
bits ^= SCIR_CPU_HEARTBEAT;
/* is this cpu idle? */
/* Is this CPU idle? */
if (idle_cpu(raw_smp_processor_id()))
bits &= ~SCIR_CPU_ACTIVITY;
else
bits |= SCIR_CPU_ACTIVITY;
/* update system controller interface reg */
/* Update system controller interface reg: */
uv_set_scir_bits(bits);
/* enable next timer period */
/* Enable next timer period: */
mod_timer(timer, jiffies + SCIR_CPU_HB_INTERVAL);
}
......@@ -935,7 +963,7 @@ static int uv_heartbeat_enable(unsigned int cpu)
add_timer_on(timer, cpu);
uv_cpu_scir_info(cpu)->enabled = 1;
/* also ensure that boot cpu is enabled */
/* Also ensure that boot CPU is enabled: */
cpu = 0;
}
return 0;
......@@ -968,9 +996,11 @@ static __init int uv_init_heartbeat(void)
{
int cpu;
if (is_uv_system())
if (is_uv_system()) {
for_each_online_cpu(cpu)
uv_heartbeat_enable(cpu);
}
return 0;
}
......@@ -979,14 +1009,10 @@ late_initcall(uv_init_heartbeat);
#endif /* !CONFIG_HOTPLUG_CPU */
/* Direct Legacy VGA I/O traffic to designated IOH */
int uv_set_vga_state(struct pci_dev *pdev, bool decode,
unsigned int command_bits, u32 flags)
int uv_set_vga_state(struct pci_dev *pdev, bool decode, unsigned int command_bits, u32 flags)
{
int domain, bus, rc;
PR_DEVEL("devfn %x decode %d cmd %x flags %d\n",
pdev->devfn, decode, command_bits, flags);
if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
return 0;
......@@ -997,13 +1023,12 @@ int uv_set_vga_state(struct pci_dev *pdev, bool decode,
bus = pdev->bus->number;
rc = uv_bios_set_legacy_vga_target(decode, domain, bus);
PR_DEVEL("vga decode %d %x:%x, rc: %d\n", decode, domain, bus, rc);
return rc;
}
/*
* Called on each cpu to initialize the per_cpu UV data area.
* Called on each CPU to initialize the per_cpu UV data area.
* FIXME: hotplug not supported yet
*/
void uv_cpu_init(void)
......@@ -1030,90 +1055,79 @@ static void get_mn(struct mn *mnp)
union uvh_rh_gam_config_mmr_u m_n_config;
union uv3h_gr0_gam_gr_config_u m_gr_config;
m_n_config.v = uv_read_local_mmr(UVH_RH_GAM_CONFIG_MMR);
mnp->n_val = m_n_config.s.n_skt;
/* Make sure the whole structure is well initialized: */
memset(mnp, 0, sizeof(*mnp));
m_n_config.v = uv_read_local_mmr(UVH_RH_GAM_CONFIG_MMR);
mnp->n_val = m_n_config.s.n_skt;
if (is_uv4_hub()) {
mnp->m_val = 0;
mnp->n_lshift = 0;
mnp->m_val = 0;
mnp->n_lshift = 0;
} else if (is_uv3_hub()) {
mnp->m_val = m_n_config.s3.m_skt;
m_gr_config.v = uv_read_local_mmr(UV3H_GR0_GAM_GR_CONFIG);
mnp->n_lshift = m_gr_config.s3.m_skt;
mnp->m_val = m_n_config.s3.m_skt;
m_gr_config.v = uv_read_local_mmr(UV3H_GR0_GAM_GR_CONFIG);
mnp->n_lshift = m_gr_config.s3.m_skt;
} else if (is_uv2_hub()) {
mnp->m_val = m_n_config.s2.m_skt;
mnp->n_lshift = mnp->m_val == 40 ? 40 : 39;
mnp->m_val = m_n_config.s2.m_skt;
mnp->n_lshift = mnp->m_val == 40 ? 40 : 39;
} else if (is_uv1_hub()) {
mnp->m_val = m_n_config.s1.m_skt;
mnp->n_lshift = mnp->m_val;
mnp->m_val = m_n_config.s1.m_skt;
mnp->n_lshift = mnp->m_val;
}
mnp->m_shift = mnp->m_val ? 64 - mnp->m_val : 0;
}
void __init uv_init_hub_info(struct uv_hub_info_s *hub_info)
void __init uv_init_hub_info(struct uv_hub_info_s *hi)
{
struct mn mn = {0}; /* avoid unitialized warnings */
union uvh_node_id_u node_id;
struct mn mn;
get_mn(&mn);
hub_info->m_val = mn.m_val;
hub_info->n_val = mn.n_val;
hub_info->m_shift = mn.m_shift;
hub_info->n_lshift = mn.n_lshift ? mn.n_lshift : 0;
hub_info->hub_revision = uv_hub_info->hub_revision;
hub_info->pnode_mask = uv_cpuid.pnode_mask;
hub_info->min_pnode = _min_pnode;
hub_info->min_socket = _min_socket;
hub_info->pnode_to_socket = _pnode_to_socket;
hub_info->socket_to_node = _socket_to_node;
hub_info->socket_to_pnode = _socket_to_pnode;
hub_info->gr_table_len = _gr_table_len;
hub_info->gr_table = _gr_table;
hub_info->gpa_mask = mn.m_val ?
hi->gpa_mask = mn.m_val ?
(1UL << (mn.m_val + mn.n_val)) - 1 :
(1UL << uv_cpuid.gpa_shift) - 1;
node_id.v = uv_read_local_mmr(UVH_NODE_ID);
hub_info->gnode_extra =
(node_id.s.node_id & ~((1 << mn.n_val) - 1)) >> 1;
hub_info->gnode_upper =
((unsigned long)hub_info->gnode_extra << mn.m_val);
hi->m_val = mn.m_val;
hi->n_val = mn.n_val;
hi->m_shift = mn.m_shift;
hi->n_lshift = mn.n_lshift ? mn.n_lshift : 0;
hi->hub_revision = uv_hub_info->hub_revision;
hi->pnode_mask = uv_cpuid.pnode_mask;
hi->min_pnode = _min_pnode;
hi->min_socket = _min_socket;
hi->pnode_to_socket = _pnode_to_socket;
hi->socket_to_node = _socket_to_node;
hi->socket_to_pnode = _socket_to_pnode;
hi->gr_table_len = _gr_table_len;
hi->gr_table = _gr_table;
node_id.v = uv_read_local_mmr(UVH_NODE_ID);
uv_cpuid.gnode_shift = max_t(unsigned int, uv_cpuid.gnode_shift, mn.n_val);
hi->gnode_extra = (node_id.s.node_id & ~((1 << uv_cpuid.gnode_shift) - 1)) >> 1;
hi->gnode_upper = (unsigned long)hi->gnode_extra << mn.m_val;
if (uv_gp_table) {
hub_info->global_mmr_base = uv_gp_table->mmr_base;
hub_info->global_mmr_shift = uv_gp_table->mmr_shift;
hub_info->global_gru_base = uv_gp_table->gru_base;
hub_info->global_gru_shift = uv_gp_table->gru_shift;
hub_info->gpa_shift = uv_gp_table->gpa_shift;
hub_info->gpa_mask = (1UL << hub_info->gpa_shift) - 1;
hi->global_mmr_base = uv_gp_table->mmr_base;
hi->global_mmr_shift = uv_gp_table->mmr_shift;
hi->global_gru_base = uv_gp_table->gru_base;
hi->global_gru_shift = uv_gp_table->gru_shift;
hi->gpa_shift = uv_gp_table->gpa_shift;
hi->gpa_mask = (1UL << hi->gpa_shift) - 1;
} else {
hub_info->global_mmr_base =
uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
~UV_MMR_ENABLE;
hub_info->global_mmr_shift = _UV_GLOBAL_MMR64_PNODE_SHIFT;
hi->global_mmr_base = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) & ~UV_MMR_ENABLE;
hi->global_mmr_shift = _UV_GLOBAL_MMR64_PNODE_SHIFT;
}
get_lowmem_redirect(
&hub_info->lowmem_remap_base, &hub_info->lowmem_remap_top);
hub_info->apic_pnode_shift = uv_cpuid.socketid_shift;
/* show system specific info */
pr_info("UV: N:%d M:%d m_shift:%d n_lshift:%d\n",
hub_info->n_val, hub_info->m_val,
hub_info->m_shift, hub_info->n_lshift);
pr_info("UV: gpa_mask/shift:0x%lx/%d pnode_mask:0x%x apic_pns:%d\n",
hub_info->gpa_mask, hub_info->gpa_shift,
hub_info->pnode_mask, hub_info->apic_pnode_shift);
get_lowmem_redirect(&hi->lowmem_remap_base, &hi->lowmem_remap_top);
pr_info("UV: mmr_base/shift:0x%lx/%ld gru_base/shift:0x%lx/%ld\n",
hub_info->global_mmr_base, hub_info->global_mmr_shift,
hub_info->global_gru_base, hub_info->global_gru_shift);
hi->apic_pnode_shift = uv_cpuid.socketid_shift;
pr_info("UV: gnode_upper:0x%lx gnode_extra:0x%x\n",
hub_info->gnode_upper, hub_info->gnode_extra);
/* Show system specific info: */
pr_info("UV: N:%d M:%d m_shift:%d n_lshift:%d\n", hi->n_val, hi->m_val, hi->m_shift, hi->n_lshift);
pr_info("UV: gpa_mask/shift:0x%lx/%d pnode_mask:0x%x apic_pns:%d\n", hi->gpa_mask, hi->gpa_shift, hi->pnode_mask, hi->apic_pnode_shift);
pr_info("UV: mmr_base/shift:0x%lx/%ld gru_base/shift:0x%lx/%ld\n", hi->global_mmr_base, hi->global_mmr_shift, hi->global_gru_base, hi->global_gru_shift);
pr_info("UV: gnode_upper:0x%lx gnode_extra:0x%x\n", hi->gnode_upper, hi->gnode_extra);
}
static void __init decode_gam_params(unsigned long ptr)
......@@ -1139,12 +1153,9 @@ static void __init decode_gam_rng_tbl(unsigned long ptr)
for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) {
if (!index) {
pr_info("UV: GAM Range Table...\n");
pr_info("UV: # %20s %14s %5s %4s %5s %3s %2s\n",
"Range", "", "Size", "Type", "NASID",
"SID", "PN");
pr_info("UV: # %20s %14s %5s %4s %5s %3s %2s\n", "Range", "", "Size", "Type", "NASID", "SID", "PN");
}
pr_info(
"UV: %2d: 0x%014lx-0x%014lx %5luG %3d %04x %02x %02x\n",
pr_info("UV: %2d: 0x%014lx-0x%014lx %5luG %3d %04x %02x %02x\n",
index++,
(unsigned long)lgre << UV_GAM_RANGE_SHFT,
(unsigned long)gre->limit << UV_GAM_RANGE_SHFT,
......@@ -1162,29 +1173,32 @@ static void __init decode_gam_rng_tbl(unsigned long ptr)
if (pnode_max < gre->pnode)
pnode_max = gre->pnode;
}
_min_socket = sock_min;
_max_socket = sock_max;
_min_pnode = pnode_min;
_max_pnode = pnode_max;
_gr_table_len = index;
pr_info(
"UV: GRT: %d entries, sockets(min:%x,max:%x) pnodes(min:%x,max:%x)\n",
index, _min_socket, _max_socket, _min_pnode, _max_pnode);
_min_socket = sock_min;
_max_socket = sock_max;
_min_pnode = pnode_min;
_max_pnode = pnode_max;
_gr_table_len = index;
pr_info("UV: GRT: %d entries, sockets(min:%x,max:%x) pnodes(min:%x,max:%x)\n", index, _min_socket, _max_socket, _min_pnode, _max_pnode);
}
static void __init decode_uv_systab(void)
static int __init decode_uv_systab(void)
{
struct uv_systab *st;
int i;
if (uv_hub_info->hub_revision < UV4_HUB_REVISION_BASE)
return 0; /* No extended UVsystab required */
st = uv_systab;
if ((!st || st->revision < UV_SYSTAB_VERSION_UV4) && !is_uv4_hub())
return;
if (st->revision != UV_SYSTAB_VERSION_UV4_LATEST) {
pr_crit(
"UV: BIOS UVsystab version(%x) mismatch, expecting(%x)\n",
st->revision, UV_SYSTAB_VERSION_UV4_LATEST);
BUG();
if ((!st) || (st->revision < UV_SYSTAB_VERSION_UV4_LATEST)) {
int rev = st ? st->revision : 0;
pr_err("UV: BIOS UVsystab version(%x) mismatch, expecting(%x)\n", rev, UV_SYSTAB_VERSION_UV4_LATEST);
pr_err("UV: Cannot support UV operations, switching to generic PC\n");
uv_system_type = UV_NONE;
return -EINVAL;
}
for (i = 0; st->entry[i].type != UV_SYSTAB_TYPE_UNUSED; i++) {
......@@ -1205,10 +1219,11 @@ static void __init decode_uv_systab(void)
break;
}
}
return 0;
}
/*
* Setup physical blade translations from UVH_NODE_PRESENT_TABLE
* Set up physical blade translations from UVH_NODE_PRESENT_TABLE
* .. NB: UVH_NODE_PRESENT_TABLE is going away,
* .. being replaced by GAM Range Table
*/
......@@ -1244,14 +1259,13 @@ static void __init build_socket_tables(void)
if (!gre) {
if (is_uv1_hub() || is_uv2_hub() || is_uv3_hub()) {
pr_info("UV: No UVsystab socket table, ignoring\n");
return; /* not required */
return;
}
pr_crit(
"UV: Error: UVsystab address translations not available!\n");
pr_crit("UV: Error: UVsystab address translations not available!\n");
BUG();
}
/* build socket id -> node id, pnode */
/* Build socket id -> node id, pnode */
num = maxsock - minsock + 1;
bytes = num * sizeof(_socket_to_node[0]);
_socket_to_node = kmalloc(bytes, GFP_KERNEL);
......@@ -1268,27 +1282,27 @@ static void __init build_socket_tables(void)
for (i = 0; i < nump; i++)
_pnode_to_socket[i] = SOCK_EMPTY;
/* fill in pnode/node/addr conversion list values */
/* Fill in pnode/node/addr conversion list values: */
pr_info("UV: GAM Building socket/pnode conversion tables\n");
for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) {
if (gre->type == UV_GAM_RANGE_TYPE_HOLE)
continue;
i = gre->sockid - minsock;
/* Duplicate: */
if (_socket_to_pnode[i] != SOCK_EMPTY)
continue; /* duplicate */
continue;
_socket_to_pnode[i] = gre->pnode;
i = gre->pnode - minpnode;
_pnode_to_socket[i] = gre->sockid;
pr_info(
"UV: sid:%02x type:%d nasid:%04x pn:%02x pn2s:%2x\n",
pr_info("UV: sid:%02x type:%d nasid:%04x pn:%02x pn2s:%2x\n",
gre->sockid, gre->type, gre->nasid,
_socket_to_pnode[gre->sockid - minsock],
_pnode_to_socket[gre->pnode - minpnode]);
}
/* Set socket -> node values */
/* Set socket -> node values: */
lnid = -1;
for_each_present_cpu(cpu) {
int nid = cpu_to_node(cpu);
......@@ -1304,7 +1318,7 @@ static void __init build_socket_tables(void)
sockid, apicid, nid);
}
/* Setup physical blade to pnode translation from GAM Range Table */
/* Set up physical blade to pnode translation from GAM Range Table: */
bytes = num_possible_nodes() * sizeof(_node_to_pnode[0]);
_node_to_pnode = kmalloc(bytes, GFP_KERNEL);
BUG_ON(!_node_to_pnode);
......@@ -1314,8 +1328,7 @@ static void __init build_socket_tables(void)
for (sockid = minsock; sockid <= maxsock; sockid++) {
if (lnid == _socket_to_node[sockid - minsock]) {
_node_to_pnode[lnid] =
_socket_to_pnode[sockid - minsock];
_node_to_pnode[lnid] = _socket_to_pnode[sockid - minsock];
break;
}
}
......@@ -1332,8 +1345,7 @@ static void __init build_socket_tables(void)
pr_info("UV: Checking socket->node/pnode for identity maps\n");
if (minsock == 0) {
for (i = 0; i < num; i++)
if (_socket_to_node[i] == SOCK_EMPTY ||
i != _socket_to_node[i])
if (_socket_to_node[i] == SOCK_EMPTY || i != _socket_to_node[i])
break;
if (i >= num) {
kfree(_socket_to_node);
......@@ -1354,7 +1366,7 @@ static void __init build_socket_tables(void)
}
}
void __init uv_system_init(void)
static void __init uv_system_init_hub(void)
{
struct uv_hub_info_s hub_info = {0};
int bytes, cpu, nodeid;
......@@ -1372,8 +1384,13 @@ void __init uv_system_init(void)
map_low_mmrs();
uv_bios_init(); /* get uv_systab for decoding */
decode_uv_systab();
/* Get uv_systab for decoding: */
uv_bios_init();
/* If there's an UVsystab problem then abort UV init: */
if (decode_uv_systab() < 0)
return;
build_socket_tables();
build_uv_gr_table();
uv_init_hub_info(&hub_info);
......@@ -1381,14 +1398,10 @@ void __init uv_system_init(void)
if (!_node_to_pnode)
boot_init_possible_blades(&hub_info);
/* uv_num_possible_blades() is really the hub count */
pr_info("UV: Found %d hubs, %d nodes, %d cpus\n",
uv_num_possible_blades(),
num_possible_nodes(),
num_possible_cpus());
/* uv_num_possible_blades() is really the hub count: */
pr_info("UV: Found %d hubs, %d nodes, %d CPUs\n", uv_num_possible_blades(), num_possible_nodes(), num_possible_cpus());
uv_bios_get_sn_info(0, &uv_type, &sn_partition_id, &sn_coherency_id,
&sn_region_size, &system_serial_number);
uv_bios_get_sn_info(0, &uv_type, &sn_partition_id, &sn_coherency_id, &sn_region_size, &system_serial_number);
hub_info.coherency_domain_number = sn_coherency_id;
uv_rtc_init();
......@@ -1401,33 +1414,31 @@ void __init uv_system_init(void)
struct uv_hub_info_s *new_hub;
if (__uv_hub_info_list[nodeid]) {
pr_err("UV: Node %d UV HUB already initialized!?\n",
nodeid);
pr_err("UV: Node %d UV HUB already initialized!?\n", nodeid);
BUG();
}
/* Allocate new per hub info list */
new_hub = (nodeid == 0) ?
&uv_hub_info_node0 :
kzalloc_node(bytes, GFP_KERNEL, nodeid);
new_hub = (nodeid == 0) ? &uv_hub_info_node0 : kzalloc_node(bytes, GFP_KERNEL, nodeid);
BUG_ON(!new_hub);
__uv_hub_info_list[nodeid] = new_hub;
new_hub = uv_hub_info_list(nodeid);
BUG_ON(!new_hub);
*new_hub = hub_info;
/* Use information from GAM table if available */
/* Use information from GAM table if available: */
if (_node_to_pnode)
new_hub->pnode = _node_to_pnode[nodeid];
else /* Fill in during cpu loop */
else /* Or fill in during CPU loop: */
new_hub->pnode = 0xffff;
new_hub->numa_blade_id = uv_node_to_blade_id(nodeid);
new_hub->memory_nid = -1;
new_hub->nr_possible_cpus = 0;
new_hub->nr_online_cpus = 0;
}
/* Initialize per cpu info */
/* Initialize per CPU info: */
for_each_possible_cpu(cpu) {
int apicid = per_cpu(x86_cpu_to_apicid, cpu);
int numa_node_id;
......@@ -1438,22 +1449,24 @@ void __init uv_system_init(void)
pnode = uv_apicid_to_pnode(apicid);
uv_cpu_info_per(cpu)->p_uv_hub_info = uv_hub_info_list(nodeid);
uv_cpu_info_per(cpu)->blade_cpu_id =
uv_cpu_hub_info(cpu)->nr_possible_cpus++;
uv_cpu_info_per(cpu)->blade_cpu_id = uv_cpu_hub_info(cpu)->nr_possible_cpus++;
if (uv_cpu_hub_info(cpu)->memory_nid == -1)
uv_cpu_hub_info(cpu)->memory_nid = cpu_to_node(cpu);
if (nodeid != numa_node_id && /* init memoryless node */
/* Init memoryless node: */
if (nodeid != numa_node_id &&
uv_hub_info_list(numa_node_id)->pnode == 0xffff)
uv_hub_info_list(numa_node_id)->pnode = pnode;
else if (uv_cpu_hub_info(cpu)->pnode == 0xffff)
uv_cpu_hub_info(cpu)->pnode = pnode;
uv_cpu_scir_info(cpu)->offset = uv_scir_offset(apicid);
}
for_each_node(nodeid) {
unsigned short pnode = uv_hub_info_list(nodeid)->pnode;
/* Add pnode info for pre-GAM list nodes without cpus */
/* Add pnode info for pre-GAM list nodes without CPUs: */
if (pnode == 0xffff) {
unsigned long paddr;
......@@ -1479,15 +1492,30 @@ void __init uv_system_init(void)
uv_scir_register_cpu_notifier();
proc_mkdir("sgi_uv", NULL);
/* register Legacy VGA I/O redirection handler */
/* Register Legacy VGA I/O redirection handler: */
pci_register_set_vga_state(uv_set_vga_state);
/*
* For a kdump kernel the reset must be BOOT_ACPI, not BOOT_EFI, as
* EFI is not enabled in the kdump kernel.
* EFI is not enabled in the kdump kernel:
*/
if (is_kdump_kernel())
reboot_type = BOOT_ACPI;
}
/*
* There is a small amount of UV specific code needed to initialize a
* UV system that does not have a "UV HUB" (referred to as "hubless").
*/
void __init uv_system_init(void)
{
if (likely(!is_uv_system() && !is_uv_hubless()))
return;
if (is_uv_system())
uv_system_init_hub();
else
uv_nmi_setup_hubless();
}
apic_driver(apic_x2apic_uv_x);
arch/x86/kernel/smpboot.c
View file @ c945d022
......@@ -1347,8 +1347,7 @@ void __init native_smp_prepare_cpus(unsigned int max_cpus)
pr_info("CPU0: ");
print_cpu_info(&cpu_data(0));
if (is_uv_system())
uv_system_init();
uv_system_init();
set_mtrr_aps_delayed_init();
......
arch/x86/platform/intel-mid/device_libs/Makefile
View file @ c945d022
......@@ -5,14 +5,12 @@ obj-$(subst m,y,$(CONFIG_MMC_SDHCI_PCI)) += platform_mrfld_sd.o
# WiFi
obj-$(subst m,y,$(CONFIG_BRCMFMAC_SDIO)) += platform_bcm43xx.o
# IPC Devices
obj-y += platform_ipc.o
obj-$(subst m,y,$(CONFIG_MFD_INTEL_MSIC)) += platform_msic.o
obj-$(subst m,y,$(CONFIG_SND_MFLD_MACHINE)) += platform_msic_audio.o
obj-$(subst m,y,$(CONFIG_GPIO_MSIC)) += platform_msic_gpio.o
obj-$(subst m,y,$(CONFIG_MFD_INTEL_MSIC)) += platform_msic_ocd.o
obj-$(subst m,y,$(CONFIG_MFD_INTEL_MSIC)) += platform_msic_battery.o
obj-$(subst m,y,$(CONFIG_INTEL_MID_POWER_BUTTON)) += platform_msic_power_btn.o
obj-$(subst m,y,$(CONFIG_GPIO_INTEL_PMIC)) += platform_pmic_gpio.o
obj-$(subst m,y,$(CONFIG_INTEL_MFLD_THERMAL)) += platform_msic_thermal.o
# SPI Devices
obj-$(subst m,y,$(CONFIG_SPI_SPIDEV)) += platform_mrfld_spidev.o
......@@ -28,4 +26,5 @@ obj-$(subst m,y,$(CONFIG_GPIO_PCA953X)) += platform_pcal9555a.o
obj-$(subst m,y,$(CONFIG_GPIO_PCA953X)) += platform_tca6416.o
# MISC Devices
obj-$(subst m,y,$(CONFIG_KEYBOARD_GPIO)) += platform_gpio_keys.o
obj-$(subst m,y,$(CONFIG_RTC_DRV_CMOS)) += platform_mrfld_rtc.o
obj-$(subst m,y,$(CONFIG_INTEL_MID_WATCHDOG)) += platform_mrfld_wdt.o
arch/x86/platform/intel-mid/device_libs/platform_gpio_keys.c
View file @ c945d022
......@@ -32,6 +32,9 @@ static struct gpio_keys_button gpio_button[] = {
{SW_LID, -1, 1, "lid_switch", EV_SW, 0, 20},
{KEY_VOLUMEUP, -1, 1, "vol_up", EV_KEY, 0, 20},
{KEY_VOLUMEDOWN, -1, 1, "vol_down", EV_KEY, 0, 20},
{KEY_MUTE, -1, 1, "mute_enable", EV_KEY, 0, 20},
{KEY_VOLUMEUP, -1, 1, "volume_up", EV_KEY, 0, 20},
{KEY_VOLUMEDOWN, -1, 1, "volume_down", EV_KEY, 0, 20},
{KEY_CAMERA, -1, 1, "camera_full", EV_KEY, 0, 20},
{KEY_CAMERA_FOCUS, -1, 1, "camera_half", EV_KEY, 0, 20},
{SW_KEYPAD_SLIDE, -1, 1, "MagSw1", EV_SW, 0, 20},
......
arch/x86/platform/intel-mid/device_libs/platform_ipc.c deleted 100644 → 0
View file @ 8b5abde1
/*
* platform_ipc.c: IPC platform library file
*
* (C) Copyright 2013 Intel Corporation
* Author: Sathyanarayanan Kuppuswamy <sathyanarayanan.kuppuswamy@intel.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; version 2
* of the License.
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/sfi.h>
#include <linux/gpio.h>
#include <asm/intel-mid.h>
#include "platform_ipc.h"
void __init ipc_device_handler(struct sfi_device_table_entry *pentry,
struct devs_id *dev)
{
struct platform_device *pdev;
void *pdata = NULL;
static struct resource res __initdata = {
.name = "IRQ",
.flags = IORESOURCE_IRQ,
};
pr_debug("IPC bus, name = %16.16s, irq = 0x%2x\n",
pentry->name, pentry->irq);
/*
* We need to call platform init of IPC devices to fill misc_pdata
* structure. It will be used in msic_init for initialization.
*/
if (dev != NULL)
pdata = dev->get_platform_data(pentry);
/*
* On Medfield the platform device creation is handled by the MSIC
* MFD driver so we don't need to do it here.
*/
if (intel_mid_has_msic())
return;
pdev = platform_device_alloc(pentry->name, 0);
if (pdev == NULL) {
pr_err("out of memory for SFI platform device '%s'.\n",
pentry->name);
return;
}
res.start = pentry->irq;
platform_device_add_resources(pdev, &res, 1);
pdev->dev.platform_data = pdata;
intel_scu_device_register(pdev);
}
static const struct devs_id pmic_audio_dev_id __initconst = {
.name = "pmic_audio",
.type = SFI_DEV_TYPE_IPC,
.delay = 1,
.device_handler = &ipc_device_handler,
};
sfi_device(pmic_audio_dev_id);
arch/x86/platform/intel-mid/device_libs/platform_ipc.h deleted 100644 → 0
View file @ 8b5abde1
/*
* platform_ipc.h: IPC platform library header file
*
* (C) Copyright 2013 Intel Corporation
* Author: Sathyanarayanan Kuppuswamy <sathyanarayanan.kuppuswamy@intel.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; version 2
* of the License.
*/
#ifndef _PLATFORM_IPC_H_
#define _PLATFORM_IPC_H_
void __init
ipc_device_handler(struct sfi_device_table_entry *pentry, struct devs_id *dev);
#endif
arch/x86/platform/intel-mid/device_libs/platform_mrfld_rtc.c 0 → 100644
View file @ c945d022
/*
* Intel Merrifield legacy RTC initialization file
*
* (C) Copyright 2017 Intel Corporation
*
* Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; version 2
* of the License.
*/
#include <linux/init.h>
#include <asm/hw_irq.h>
#include <asm/intel-mid.h>
#include <asm/io_apic.h>
#include <asm/time.h>
#include <asm/x86_init.h>
static int __init mrfld_legacy_rtc_alloc_irq(void)
{
struct irq_alloc_info info;
int ret;
if (!x86_platform.legacy.rtc)
return -ENODEV;
ioapic_set_alloc_attr(&info, NUMA_NO_NODE, 1, 0);
ret = mp_map_gsi_to_irq(RTC_IRQ, IOAPIC_MAP_ALLOC, &info);
if (ret < 0) {
pr_info("Failed to allocate RTC interrupt. Disabling RTC\n");
x86_platform.legacy.rtc = 0;
return ret;
}
return 0;
}
static int __init mrfld_legacy_rtc_init(void)
{
if (intel_mid_identify_cpu() != INTEL_MID_CPU_CHIP_TANGIER)
return -ENODEV;
return mrfld_legacy_rtc_alloc_irq();
}
arch_initcall(mrfld_legacy_rtc_init);
arch/x86/platform/intel-mid/device_libs/platform_mrfld_wdt.c
View file @ c945d022
......@@ -28,9 +28,9 @@ static struct platform_device wdt_dev = {
static int tangier_probe(struct platform_device *pdev)
{
int gsi;
struct irq_alloc_info info;
struct intel_mid_wdt_pdata *pdata = pdev->dev.platform_data;
int gsi, irq;
if (!pdata)
return -EINVAL;
......@@ -38,10 +38,10 @@ static int tangier_probe(struct platform_device *pdev)
/* IOAPIC builds identity mapping between GSI and IRQ on MID */
gsi = pdata->irq;
ioapic_set_alloc_attr(&info, cpu_to_node(0), 1, 0);
if (mp_map_gsi_to_irq(gsi, IOAPIC_MAP_ALLOC, &info) <= 0) {
dev_warn(&pdev->dev, "cannot find interrupt %d in ioapic\n",
gsi);
return -EINVAL;
irq = mp_map_gsi_to_irq(gsi, IOAPIC_MAP_ALLOC, &info);
if (irq < 0) {
dev_warn(&pdev->dev, "cannot find interrupt %d in ioapic\n", gsi);
return irq;
}
return 0;
......@@ -82,4 +82,4 @@ static int __init register_mid_wdt(void)
return 0;
}
rootfs_initcall(register_mid_wdt);
arch_initcall(register_mid_wdt);
arch/x86/platform/intel-mid/device_libs/platform_msic_audio.c
View file @ c945d022
......@@ -20,7 +20,6 @@
#include <asm/intel-mid.h>
#include "platform_msic.h"
#include "platform_ipc.h"
static void *msic_audio_platform_data(void *info)
{
......@@ -40,8 +39,8 @@ static const struct devs_id msic_audio_dev_id __initconst = {
.name = "msic_audio",
.type = SFI_DEV_TYPE_IPC,
.delay = 1,
.msic = 1,
.get_platform_data = &msic_audio_platform_data,
.device_handler = &ipc_device_handler,
};
sfi_device(msic_audio_dev_id);
arch/x86/platform/intel-mid/device_libs/platform_msic_battery.c
View file @ c945d022
......@@ -19,7 +19,6 @@
#include <asm/intel-mid.h>
#include "platform_msic.h"
#include "platform_ipc.h"
static void __init *msic_battery_platform_data(void *info)
{
......@@ -30,8 +29,8 @@ static const struct devs_id msic_battery_dev_id __initconst = {
.name = "msic_battery",
.type = SFI_DEV_TYPE_IPC,
.delay = 1,
.msic = 1,
.get_platform_data = &msic_battery_platform_data,
.device_handler = &ipc_device_handler,
};
sfi_device(msic_battery_dev_id);
arch/x86/platform/intel-mid/device_libs/platform_msic_gpio.c
View file @ c945d022
......@@ -20,7 +20,6 @@
#include <asm/intel-mid.h>
#include "platform_msic.h"
#include "platform_ipc.h"
static void __init *msic_gpio_platform_data(void *info)
{
......@@ -41,8 +40,8 @@ static const struct devs_id msic_gpio_dev_id __initconst = {
.name = "msic_gpio",
.type = SFI_DEV_TYPE_IPC,
.delay = 1,
.msic = 1,
.get_platform_data = &msic_gpio_platform_data,
.device_handler = &ipc_device_handler,
};
sfi_device(msic_gpio_dev_id);
arch/x86/platform/intel-mid/device_libs/platform_msic_ocd.c
View file @ c945d022
......@@ -20,7 +20,6 @@
#include <asm/intel-mid.h>
#include "platform_msic.h"
#include "platform_ipc.h"
static void __init *msic_ocd_platform_data(void *info)
{
......@@ -42,8 +41,8 @@ static const struct devs_id msic_ocd_dev_id __initconst = {
.name = "msic_ocd",
.type = SFI_DEV_TYPE_IPC,
.delay = 1,
.msic = 1,
.get_platform_data = &msic_ocd_platform_data,
.device_handler = &ipc_device_handler,
};
sfi_device(msic_ocd_dev_id);
arch/x86/platform/intel-mid/device_libs/platform_msic_power_btn.c
View file @ c945d022
......@@ -18,7 +18,6 @@
#include <asm/intel-mid.h>
#include "platform_msic.h"
#include "platform_ipc.h"
static void __init *msic_power_btn_platform_data(void *info)
{
......@@ -29,8 +28,8 @@ static const struct devs_id msic_power_btn_dev_id __initconst = {
.name = "msic_power_btn",
.type = SFI_DEV_TYPE_IPC,
.delay = 1,
.msic = 1,
.get_platform_data = &msic_power_btn_platform_data,
.device_handler = &ipc_device_handler,
};
sfi_device(msic_power_btn_dev_id);
arch/x86/platform/intel-mid/device_libs/platform_msic_thermal.c
View file @ c945d022
......@@ -19,7 +19,6 @@
#include <asm/intel-mid.h>
#include "platform_msic.h"
#include "platform_ipc.h"
static void __init *msic_thermal_platform_data(void *info)
{
......@@ -30,8 +29,8 @@ static const struct devs_id msic_thermal_dev_id __initconst = {
.name = "msic_thermal",
.type = SFI_DEV_TYPE_IPC,
.delay = 1,
.msic = 1,
.get_platform_data = &msic_thermal_platform_data,
.device_handler = &ipc_device_handler,
};
sfi_device(msic_thermal_dev_id);
arch/x86/platform/intel-mid/device_libs/platform_pmic_gpio.c deleted 100644 → 0
View file @ 8b5abde1
/*
* platform_pmic_gpio.c: PMIC GPIO platform data initialization file
*
* (C) Copyright 2013 Intel Corporation
* Author: Sathyanarayanan Kuppuswamy <sathyanarayanan.kuppuswamy@intel.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; version 2
* of the License.
*/
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/scatterlist.h>
#include <linux/gpio.h>
#include <linux/init.h>
#include <linux/sfi.h>
#include <linux/intel_pmic_gpio.h>
#include <asm/intel-mid.h>
#include "platform_ipc.h"
static void __init *pmic_gpio_platform_data(void *info)
{
static struct intel_pmic_gpio_platform_data pmic_gpio_pdata;
int gpio_base = get_gpio_by_name("pmic_gpio_base");
if (gpio_base < 0)
gpio_base = 64;
pmic_gpio_pdata.gpio_base = gpio_base;
pmic_gpio_pdata.irq_base = gpio_base + INTEL_MID_IRQ_OFFSET;
pmic_gpio_pdata.gpiointr = 0xffffeff8;
return &pmic_gpio_pdata;
}
static const struct devs_id pmic_gpio_spi_dev_id __initconst = {
.name = "pmic_gpio",
.type = SFI_DEV_TYPE_SPI,
.delay = 1,
.get_platform_data = &pmic_gpio_platform_data,
};
static const struct devs_id pmic_gpio_ipc_dev_id __initconst = {
.name = "pmic_gpio",
.type = SFI_DEV_TYPE_IPC,
.delay = 1,
.get_platform_data = &pmic_gpio_platform_data,
.device_handler = &ipc_device_handler
};
sfi_device(pmic_gpio_spi_dev_id);
sfi_device(pmic_gpio_ipc_dev_id);
arch/x86/platform/intel-mid/mrfld.c
View file @ c945d022
......@@ -91,6 +91,7 @@ static unsigned long __init tangier_calibrate_tsc(void)
static void __init tangier_arch_setup(void)
{
x86_platform.calibrate_tsc = tangier_calibrate_tsc;
x86_platform.legacy.rtc = 1;
}
/* tangier arch ops */
......
arch/x86/platform/intel-mid/sfi.c
View file @ c945d022
......@@ -15,7 +15,6 @@
#include <linux/interrupt.h>
#include <linux/scatterlist.h>
#include <linux/sfi.h>
#include <linux/intel_pmic_gpio.h>
#include <linux/spi/spi.h>
#include <linux/i2c.h>
#include <linux/skbuff.h>
......@@ -226,7 +225,7 @@ int get_gpio_by_name(const char *name)
return -EINVAL;
}
void __init intel_scu_device_register(struct platform_device *pdev)
static void __init intel_scu_ipc_device_register(struct platform_device *pdev)
{
if (ipc_next_dev == MAX_IPCDEVS)
pr_err("too many SCU IPC devices");
......@@ -335,10 +334,22 @@ static void __init sfi_handle_ipc_dev(struct sfi_device_table_entry *pentry,
pr_debug("IPC bus, name = %16.16s, irq = 0x%2x\n",
pentry->name, pentry->irq);
/*
* We need to call platform init of IPC devices to fill misc_pdata
* structure. It will be used in msic_init for initialization.
*/
pdata = intel_mid_sfi_get_pdata(dev, pentry);
if (IS_ERR(pdata))
return;
/*
* On Medfield the platform device creation is handled by the MSIC
* MFD driver so we don't need to do it here.
*/
if (dev->msic && intel_mid_has_msic())
return;
pdev = platform_device_alloc(pentry->name, 0);
if (pdev == NULL) {
pr_err("out of memory for SFI platform device '%s'.\n",
......@@ -348,7 +359,10 @@ static void __init sfi_handle_ipc_dev(struct sfi_device_table_entry *pentry,
install_irq_resource(pdev, pentry->irq);
pdev->dev.platform_data = pdata;
platform_device_add(pdev);
if (dev->delay)
intel_scu_ipc_device_register(pdev);
else
platform_device_add(pdev);
}
static void __init sfi_handle_spi_dev(struct sfi_device_table_entry *pentry,
......@@ -503,27 +517,23 @@ static int __init sfi_parse_devs(struct sfi_table_header *table)
if (!dev)
continue;
if (dev->device_handler) {
dev->device_handler(pentry, dev);
} else {
switch (pentry->type) {
case SFI_DEV_TYPE_IPC:
sfi_handle_ipc_dev(pentry, dev);
break;
case SFI_DEV_TYPE_SPI:
sfi_handle_spi_dev(pentry, dev);
break;
case SFI_DEV_TYPE_I2C:
sfi_handle_i2c_dev(pentry, dev);
break;
case SFI_DEV_TYPE_SD:
sfi_handle_sd_dev(pentry, dev);
break;
case SFI_DEV_TYPE_UART:
case SFI_DEV_TYPE_HSI:
default:
break;
}
switch (pentry->type) {
case SFI_DEV_TYPE_IPC:
sfi_handle_ipc_dev(pentry, dev);
break;
case SFI_DEV_TYPE_SPI:
sfi_handle_spi_dev(pentry, dev);
break;
case SFI_DEV_TYPE_I2C:
sfi_handle_i2c_dev(pentry, dev);
break;
case SFI_DEV_TYPE_SD:
sfi_handle_sd_dev(pentry, dev);
break;
case SFI_DEV_TYPE_UART:
case SFI_DEV_TYPE_HSI:
default:
break;
}
}
return 0;
......
arch/x86/platform/uv/uv_nmi.c
View file @ c945d022
......@@ -45,8 +45,8 @@
*
* Handle system-wide NMI events generated by the global 'power nmi' command.
*
* Basic operation is to field the NMI interrupt on each cpu and wait
* until all cpus have arrived into the nmi handler. If some cpus do not
* Basic operation is to field the NMI interrupt on each CPU and wait
* until all CPU's have arrived into the nmi handler. If some CPU's do not
* make it into the handler, try and force them in with the IPI(NMI) signal.
*
* We also have to lessen UV Hub MMR accesses as much as possible as this
......@@ -56,7 +56,7 @@
* To do this we register our primary NMI notifier on the NMI_UNKNOWN
* chain. This reduces the number of false NMI calls when the perf
* tools are running which generate an enormous number of NMIs per
* second (~4M/s for 1024 cpu threads). Our secondary NMI handler is
* second (~4M/s for 1024 CPU threads). Our secondary NMI handler is
* very short as it only checks that if it has been "pinged" with the
* IPI(NMI) signal as mentioned above, and does not read the UV Hub's MMR.
*
......@@ -65,8 +65,20 @@
static struct uv_hub_nmi_s **uv_hub_nmi_list;
DEFINE_PER_CPU(struct uv_cpu_nmi_s, uv_cpu_nmi);
EXPORT_PER_CPU_SYMBOL_GPL(uv_cpu_nmi);
/* UV hubless values */
#define NMI_CONTROL_PORT 0x70
#define NMI_DUMMY_PORT 0x71
#define PAD_OWN_GPP_D_0 0x2c
#define GPI_NMI_STS_GPP_D_0 0x164
#define GPI_NMI_ENA_GPP_D_0 0x174
#define STS_GPP_D_0_MASK 0x1
#define PAD_CFG_DW0_GPP_D_0 0x4c0
#define GPIROUTNMI (1ul << 17)
#define PCH_PCR_GPIO_1_BASE 0xfdae0000ul
#define PCH_PCR_GPIO_ADDRESS(offset) (int *)((u64)(pch_base) | (u64)(offset))
static u64 *pch_base;
static unsigned long nmi_mmr;
static unsigned long nmi_mmr_clear;
static unsigned long nmi_mmr_pending;
......@@ -100,7 +112,7 @@ static int param_get_local64(char *buffer, const struct kernel_param *kp)
static int param_set_local64(const char *val, const struct kernel_param *kp)
{
/* clear on any write */
/* Clear on any write */
local64_set((local64_t *)kp->arg, 0);
return 0;
}
......@@ -144,16 +156,80 @@ module_param_named(wait_count, uv_nmi_wait_count, int, 0644);
static int uv_nmi_retry_count = 500;
module_param_named(retry_count, uv_nmi_retry_count, int, 0644);
/*
* Valid NMI Actions:
* "dump" - dump process stack for each cpu
* "ips" - dump IP info for each cpu
* "kdump" - do crash dump
* "kdb" - enter KDB (default)
* "kgdb" - enter KGDB
*/
static char uv_nmi_action[8] = "kdb";
module_param_string(action, uv_nmi_action, sizeof(uv_nmi_action), 0644);
static bool uv_pch_intr_enable = true;
static bool uv_pch_intr_now_enabled;
module_param_named(pch_intr_enable, uv_pch_intr_enable, bool, 0644);
static bool uv_pch_init_enable = true;
module_param_named(pch_init_enable, uv_pch_init_enable, bool, 0644);
static int uv_nmi_debug;
module_param_named(debug, uv_nmi_debug, int, 0644);
#define nmi_debug(fmt, ...) \
do { \
if (uv_nmi_debug) \
pr_info(fmt, ##__VA_ARGS__); \
} while (0)
/* Valid NMI Actions */
#define ACTION_LEN 16
static struct nmi_action {
char *action;
char *desc;
} valid_acts[] = {
{ "kdump", "do kernel crash dump" },
{ "dump", "dump process stack for each cpu" },
{ "ips", "dump Inst Ptr info for each cpu" },
{ "kdb", "enter KDB (needs kgdboc= assignment)" },
{ "kgdb", "enter KGDB (needs gdb target remote)" },
{ "health", "check if CPUs respond to NMI" },
};
typedef char action_t[ACTION_LEN];
static action_t uv_nmi_action = { "dump" };
static int param_get_action(char *buffer, const struct kernel_param *kp)
{
return sprintf(buffer, "%s\n", uv_nmi_action);
}
static int param_set_action(const char *val, const struct kernel_param *kp)
{
int i;
int n = ARRAY_SIZE(valid_acts);
char arg[ACTION_LEN], *p;
/* (remove possible '\n') */
strncpy(arg, val, ACTION_LEN - 1);
arg[ACTION_LEN - 1] = '\0';
p = strchr(arg, '\n');
if (p)
*p = '\0';
for (i = 0; i < n; i++)
if (!strcmp(arg, valid_acts[i].action))
break;
if (i < n) {
strcpy(uv_nmi_action, arg);
pr_info("UV: New NMI action:%s\n", uv_nmi_action);
return 0;
}
pr_err("UV: Invalid NMI action:%s, valid actions are:\n", arg);
for (i = 0; i < n; i++)
pr_err("UV: %-8s - %s\n",
valid_acts[i].action, valid_acts[i].desc);
return -EINVAL;
}
static const struct kernel_param_ops param_ops_action = {
.get = param_get_action,
.set = param_set_action,
};
#define param_check_action(name, p) __param_check(name, p, action_t)
module_param_named(action, uv_nmi_action, action, 0644);
static inline bool uv_nmi_action_is(const char *action)
{
......@@ -192,8 +268,200 @@ static inline void uv_local_mmr_clear_nmi(void)
}
/*
* If first cpu in on this hub, set hub_nmi "in_nmi" and "owner" values and
* return true. If first cpu in on the system, set global "in_nmi" flag.
* UV hubless NMI handler functions
*/
static inline void uv_reassert_nmi(void)
{
/* (from arch/x86/include/asm/mach_traps.h) */
outb(0x8f, NMI_CONTROL_PORT);
inb(NMI_DUMMY_PORT); /* dummy read */
outb(0x0f, NMI_CONTROL_PORT);
inb(NMI_DUMMY_PORT); /* dummy read */
}
static void uv_init_hubless_pch_io(int offset, int mask, int data)
{
int *addr = PCH_PCR_GPIO_ADDRESS(offset);
int readd = readl(addr);
if (mask) { /* OR in new data */
int writed = (readd & ~mask) | data;
nmi_debug("UV:PCH: %p = %x & %x | %x (%x)\n",
addr, readd, ~mask, data, writed);
writel(writed, addr);
} else if (readd & data) { /* clear status bit */
nmi_debug("UV:PCH: %p = %x\n", addr, data);
writel(data, addr);
}
(void)readl(addr); /* flush write data */
}
static void uv_nmi_setup_hubless_intr(void)
{
uv_pch_intr_now_enabled = uv_pch_intr_enable;
uv_init_hubless_pch_io(
PAD_CFG_DW0_GPP_D_0, GPIROUTNMI,
uv_pch_intr_now_enabled ? GPIROUTNMI : 0);
nmi_debug("UV:NMI: GPP_D_0 interrupt %s\n",
uv_pch_intr_now_enabled ? "enabled" : "disabled");
}
static struct init_nmi {
unsigned int offset;
unsigned int mask;
unsigned int data;
} init_nmi[] = {
{ /* HOSTSW_OWN_GPP_D_0 */
.offset = 0x84,
.mask = 0x1,
.data = 0x0, /* ACPI Mode */
},
/* Clear status: */
{ /* GPI_INT_STS_GPP_D_0 */
.offset = 0x104,
.mask = 0x0,
.data = 0x1, /* Clear Status */
},
{ /* GPI_GPE_STS_GPP_D_0 */
.offset = 0x124,
.mask = 0x0,
.data = 0x1, /* Clear Status */
},
{ /* GPI_SMI_STS_GPP_D_0 */
.offset = 0x144,
.mask = 0x0,
.data = 0x1, /* Clear Status */
},
{ /* GPI_NMI_STS_GPP_D_0 */
.offset = 0x164,
.mask = 0x0,
.data = 0x1, /* Clear Status */
},
/* Disable interrupts: */
{ /* GPI_INT_EN_GPP_D_0 */
.offset = 0x114,
.mask = 0x1,
.data = 0x0, /* Disable interrupt generation */
},
{ /* GPI_GPE_EN_GPP_D_0 */
.offset = 0x134,
.mask = 0x1,
.data = 0x0, /* Disable interrupt generation */
},
{ /* GPI_SMI_EN_GPP_D_0 */
.offset = 0x154,
.mask = 0x1,
.data = 0x0, /* Disable interrupt generation */
},
{ /* GPI_NMI_EN_GPP_D_0 */
.offset = 0x174,
.mask = 0x1,
.data = 0x0, /* Disable interrupt generation */
},
/* Setup GPP_D_0 Pad Config: */
{ /* PAD_CFG_DW0_GPP_D_0 */
.offset = 0x4c0,
.mask = 0xffffffff,
.data = 0x82020100,
/*
* 31:30 Pad Reset Config (PADRSTCFG): = 2h # PLTRST# (default)
*
* 29 RX Pad State Select (RXPADSTSEL): = 0 # Raw RX pad state directly
* from RX buffer (default)
*
* 28 RX Raw Override to '1' (RXRAW1): = 0 # No Override
*
* 26:25 RX Level/Edge Configuration (RXEVCFG):
* = 0h # Level
* = 1h # Edge
*
* 23 RX Invert (RXINV): = 0 # No Inversion (signal active high)
*
* 20 GPIO Input Route IOxAPIC (GPIROUTIOXAPIC):
* = 0 # Routing does not cause peripheral IRQ...
* # (we want an NMI not an IRQ)
*
* 19 GPIO Input Route SCI (GPIROUTSCI): = 0 # Routing does not cause SCI.
* 18 GPIO Input Route SMI (GPIROUTSMI): = 0 # Routing does not cause SMI.
* 17 GPIO Input Route NMI (GPIROUTNMI): = 1 # Routing can cause NMI.
*
* 11:10 Pad Mode (PMODE1/0): = 0h = GPIO control the Pad.
* 9 GPIO RX Disable (GPIORXDIS):
* = 0 # Enable the input buffer (active low enable)
*
* 8 GPIO TX Disable (GPIOTXDIS):
* = 1 # Disable the output buffer; i.e. Hi-Z
*
* 1 GPIO RX State (GPIORXSTATE): This is the current internal RX pad state..
* 0 GPIO TX State (GPIOTXSTATE):
* = 0 # (Leave at default)
*/
},
/* Pad Config DW1 */
{ /* PAD_CFG_DW1_GPP_D_0 */
.offset = 0x4c4,
.mask = 0x3c00,
.data = 0, /* Termination = none (default) */
},
};
static void uv_init_hubless_pch_d0(void)
{
int i, read;
read = *PCH_PCR_GPIO_ADDRESS(PAD_OWN_GPP_D_0);
if (read != 0) {
pr_info("UV: Hubless NMI already configured\n");
return;
}
nmi_debug("UV: Initializing UV Hubless NMI on PCH\n");
for (i = 0; i < ARRAY_SIZE(init_nmi); i++) {
uv_init_hubless_pch_io(init_nmi[i].offset,
init_nmi[i].mask,
init_nmi[i].data);
}
}
static int uv_nmi_test_hubless(struct uv_hub_nmi_s *hub_nmi)
{
int *pstat = PCH_PCR_GPIO_ADDRESS(GPI_NMI_STS_GPP_D_0);
int status = *pstat;
hub_nmi->nmi_value = status;
atomic_inc(&hub_nmi->read_mmr_count);
if (!(status & STS_GPP_D_0_MASK)) /* Not a UV external NMI */
return 0;
*pstat = STS_GPP_D_0_MASK; /* Is a UV NMI: clear GPP_D_0 status */
(void)*pstat; /* Flush write */
return 1;
}
static int uv_test_nmi(struct uv_hub_nmi_s *hub_nmi)
{
if (hub_nmi->hub_present)
return uv_nmi_test_mmr(hub_nmi);
if (hub_nmi->pch_owner) /* Only PCH owner can check status */
return uv_nmi_test_hubless(hub_nmi);
return -1;
}
/*
* If first CPU in on this hub, set hub_nmi "in_nmi" and "owner" values and
* return true. If first CPU in on the system, set global "in_nmi" flag.
*/
static int uv_set_in_nmi(int cpu, struct uv_hub_nmi_s *hub_nmi)
{
......@@ -214,6 +482,7 @@ static int uv_check_nmi(struct uv_hub_nmi_s *hub_nmi)
{
int cpu = smp_processor_id();
int nmi = 0;
int nmi_detected = 0;
local64_inc(&uv_nmi_count);
this_cpu_inc(uv_cpu_nmi.queries);
......@@ -224,35 +493,48 @@ static int uv_check_nmi(struct uv_hub_nmi_s *hub_nmi)
break;
if (raw_spin_trylock(&hub_nmi->nmi_lock)) {
nmi_detected = uv_test_nmi(hub_nmi);
/* check hub MMR NMI flag */
if (uv_nmi_test_mmr(hub_nmi)) {
/* Check flag for UV external NMI */
if (nmi_detected > 0) {
uv_set_in_nmi(cpu, hub_nmi);
nmi = 1;
break;
}
/* MMR NMI flag is clear */
/* A non-PCH node in a hubless system waits for NMI */
else if (nmi_detected < 0)
goto slave_wait;
/* MMR/PCH NMI flag is clear */
raw_spin_unlock(&hub_nmi->nmi_lock);
} else {
/* wait a moment for the hub nmi locker to set flag */
cpu_relax();
/* Wait a moment for the HUB NMI locker to set flag */
slave_wait: cpu_relax();
udelay(uv_nmi_slave_delay);
/* re-check hub in_nmi flag */
/* Re-check hub in_nmi flag */
nmi = atomic_read(&hub_nmi->in_nmi);
if (nmi)
break;
}
/* check if this BMC missed setting the MMR NMI flag */
/*
* Check if this BMC missed setting the MMR NMI flag (or)
* UV hubless system where only PCH owner can check flag
*/
if (!nmi) {
nmi = atomic_read(&uv_in_nmi);
if (nmi)
uv_set_in_nmi(cpu, hub_nmi);
}
/* If we're holding the hub lock, release it now */
if (nmi_detected < 0)
raw_spin_unlock(&hub_nmi->nmi_lock);
} while (0);
if (!nmi)
......@@ -269,12 +551,15 @@ static inline void uv_clear_nmi(int cpu)
if (cpu == atomic_read(&hub_nmi->cpu_owner)) {
atomic_set(&hub_nmi->cpu_owner, -1);
atomic_set(&hub_nmi->in_nmi, 0);
uv_local_mmr_clear_nmi();
if (hub_nmi->hub_present)
uv_local_mmr_clear_nmi();
else
uv_reassert_nmi();
raw_spin_unlock(&hub_nmi->nmi_lock);
}
}
/* Ping non-responding cpus attemping to force them into the NMI handler */
/* Ping non-responding CPU's attemping to force them into the NMI handler */
static void uv_nmi_nr_cpus_ping(void)
{
int cpu;
......@@ -285,7 +570,7 @@ static void uv_nmi_nr_cpus_ping(void)
apic->send_IPI_mask(uv_nmi_cpu_mask, APIC_DM_NMI);
}
/* Clean up flags for cpus that ignored both NMI and ping */
/* Clean up flags for CPU's that ignored both NMI and ping */
static void uv_nmi_cleanup_mask(void)
{
int cpu;
......@@ -297,11 +582,12 @@ static void uv_nmi_cleanup_mask(void)
}
}
/* Loop waiting as cpus enter nmi handler */
/* Loop waiting as CPU's enter NMI handler */
static int uv_nmi_wait_cpus(int first)
{
int i, j, k, n = num_online_cpus();
int last_k = 0, waiting = 0;
int cpu = smp_processor_id();
if (first) {
cpumask_copy(uv_nmi_cpu_mask, cpu_online_mask);
......@@ -310,6 +596,12 @@ static int uv_nmi_wait_cpus(int first)
k = n - cpumask_weight(uv_nmi_cpu_mask);
}
/* PCH NMI causes only one CPU to respond */
if (first && uv_pch_intr_now_enabled) {
cpumask_clear_cpu(cpu, uv_nmi_cpu_mask);
return n - k - 1;
}
udelay(uv_nmi_initial_delay);
for (i = 0; i < uv_nmi_retry_count; i++) {
int loop_delay = uv_nmi_loop_delay;
......@@ -325,13 +617,13 @@ static int uv_nmi_wait_cpus(int first)
k = n;
break;
}
if (last_k != k) { /* abort if no new cpus coming in */
if (last_k != k) { /* abort if no new CPU's coming in */
last_k = k;
waiting = 0;
} else if (++waiting > uv_nmi_wait_count)
break;
/* extend delay if waiting only for cpu 0 */
/* Extend delay if waiting only for CPU 0: */
if (waiting && (n - k) == 1 &&
cpumask_test_cpu(0, uv_nmi_cpu_mask))
loop_delay *= 100;
......@@ -342,29 +634,29 @@ static int uv_nmi_wait_cpus(int first)
return n - k;
}
/* Wait until all slave cpus have entered UV NMI handler */
/* Wait until all slave CPU's have entered UV NMI handler */
static void uv_nmi_wait(int master)
{
/* indicate this cpu is in */
/* Indicate this CPU is in: */
this_cpu_write(uv_cpu_nmi.state, UV_NMI_STATE_IN);
/* if not the first cpu in (the master), then we are a slave cpu */
/* If not the first CPU in (the master), then we are a slave CPU */
if (!master)
return;
do {
/* wait for all other cpus to gather here */
/* Wait for all other CPU's to gather here */
if (!uv_nmi_wait_cpus(1))
break;
/* if not all made it in, send IPI NMI to them */
pr_alert("UV: Sending NMI IPI to %d non-responding CPUs: %*pbl\n",
/* If not all made it in, send IPI NMI to them */
pr_alert("UV: Sending NMI IPI to %d CPUs: %*pbl\n",
cpumask_weight(uv_nmi_cpu_mask),
cpumask_pr_args(uv_nmi_cpu_mask));
uv_nmi_nr_cpus_ping();
/* if all cpus are in, then done */
/* If all CPU's are in, then done */
if (!uv_nmi_wait_cpus(0))
break;
......@@ -416,7 +708,7 @@ static void uv_nmi_dump_state_cpu(int cpu, struct pt_regs *regs)
this_cpu_write(uv_cpu_nmi.state, UV_NMI_STATE_DUMP_DONE);
}
/* Trigger a slave cpu to dump it's state */
/* Trigger a slave CPU to dump it's state */
static void uv_nmi_trigger_dump(int cpu)
{
int retry = uv_nmi_trigger_delay;
......@@ -437,7 +729,7 @@ static void uv_nmi_trigger_dump(int cpu)
uv_cpu_nmi_per(cpu).state = UV_NMI_STATE_DUMP_DONE;
}
/* Wait until all cpus ready to exit */
/* Wait until all CPU's ready to exit */
static void uv_nmi_sync_exit(int master)
{
atomic_dec(&uv_nmi_cpus_in_nmi);
......@@ -451,7 +743,23 @@ static void uv_nmi_sync_exit(int master)
}
}
/* Walk through cpu list and dump state of each */
/* Current "health" check is to check which CPU's are responsive */
static void uv_nmi_action_health(int cpu, struct pt_regs *regs, int master)
{
if (master) {
int in = atomic_read(&uv_nmi_cpus_in_nmi);
int out = num_online_cpus() - in;
pr_alert("UV: NMI CPU health check (non-responding:%d)\n", out);
atomic_set(&uv_nmi_slave_continue, SLAVE_EXIT);
} else {
while (!atomic_read(&uv_nmi_slave_continue))
cpu_relax();
}
uv_nmi_sync_exit(master);
}
/* Walk through CPU list and dump state of each */
static void uv_nmi_dump_state(int cpu, struct pt_regs *regs, int master)
{
if (master) {
......@@ -538,7 +846,7 @@ static inline int uv_nmi_kdb_reason(void)
#else /* !CONFIG_KGDB_KDB */
static inline int uv_nmi_kdb_reason(void)
{
/* Insure user is expecting to attach gdb remote */
/* Ensure user is expecting to attach gdb remote */
if (uv_nmi_action_is("kgdb"))
return 0;
......@@ -563,7 +871,7 @@ static void uv_call_kgdb_kdb(int cpu, struct pt_regs *regs, int master)
if (reason < 0)
return;
/* call KGDB NMI handler as MASTER */
/* Call KGDB NMI handler as MASTER */
ret = kgdb_nmicallin(cpu, X86_TRAP_NMI, regs, reason,
&uv_nmi_slave_continue);
if (ret) {
......@@ -571,7 +879,7 @@ static void uv_call_kgdb_kdb(int cpu, struct pt_regs *regs, int master)
atomic_set(&uv_nmi_slave_continue, SLAVE_EXIT);
}
} else {
/* wait for KGDB signal that it's ready for slaves to enter */
/* Wait for KGDB signal that it's ready for slaves to enter */
int sig;
do {
......@@ -579,7 +887,7 @@ static void uv_call_kgdb_kdb(int cpu, struct pt_regs *regs, int master)
sig = atomic_read(&uv_nmi_slave_continue);
} while (!sig);
/* call KGDB as slave */
/* Call KGDB as slave */
if (sig == SLAVE_CONTINUE)
kgdb_nmicallback(cpu, regs);
}
......@@ -623,18 +931,23 @@ int uv_handle_nmi(unsigned int reason, struct pt_regs *regs)
strncpy(uv_nmi_action, "dump", strlen(uv_nmi_action));
}
/* Pause as all cpus enter the NMI handler */
/* Pause as all CPU's enter the NMI handler */
uv_nmi_wait(master);
/* Dump state of each cpu */
if (uv_nmi_action_is("ips") || uv_nmi_action_is("dump"))
/* Process actions other than "kdump": */
if (uv_nmi_action_is("health")) {
uv_nmi_action_health(cpu, regs, master);
} else if (uv_nmi_action_is("ips") || uv_nmi_action_is("dump")) {
uv_nmi_dump_state(cpu, regs, master);
/* Call KGDB/KDB if enabled */
else if (uv_nmi_action_is("kdb") || uv_nmi_action_is("kgdb"))
} else if (uv_nmi_action_is("kdb") || uv_nmi_action_is("kgdb")) {
uv_call_kgdb_kdb(cpu, regs, master);
} else {
if (master)
pr_alert("UV: unknown NMI action: %s\n", uv_nmi_action);
uv_nmi_sync_exit(master);
}
/* Clear per_cpu "in nmi" flag */
/* Clear per_cpu "in_nmi" flag */
this_cpu_write(uv_cpu_nmi.state, UV_NMI_STATE_OUT);
/* Clear MMR NMI flag on each hub */
......@@ -648,6 +961,7 @@ int uv_handle_nmi(unsigned int reason, struct pt_regs *regs)
atomic_set(&uv_nmi_cpu, -1);
atomic_set(&uv_in_nmi, 0);
atomic_set(&uv_nmi_kexec_failed, 0);
atomic_set(&uv_nmi_slave_continue, SLAVE_CLEAR);
}
uv_nmi_touch_watchdogs();
......@@ -657,7 +971,7 @@ int uv_handle_nmi(unsigned int reason, struct pt_regs *regs)
}
/*
* NMI handler for pulling in CPUs when perf events are grabbing our NMI
* NMI handler for pulling in CPU's when perf events are grabbing our NMI
*/
static int uv_handle_nmi_ping(unsigned int reason, struct pt_regs *regs)
{
......@@ -690,35 +1004,62 @@ void uv_nmi_init(void)
unsigned int value;
/*
* Unmask NMI on all cpus
* Unmask NMI on all CPU's
*/
value = apic_read(APIC_LVT1) | APIC_DM_NMI;
value &= ~APIC_LVT_MASKED;
apic_write(APIC_LVT1, value);
}
void uv_nmi_setup(void)
/* Setup HUB NMI info */
void __init uv_nmi_setup_common(bool hubbed)
{
int size = sizeof(void *) * (1 << NODES_SHIFT);
int cpu, nid;
int cpu;
/* Setup hub nmi info */
uv_nmi_setup_mmrs();
uv_hub_nmi_list = kzalloc(size, GFP_KERNEL);
pr_info("UV: NMI hub list @ 0x%p (%d)\n", uv_hub_nmi_list, size);
nmi_debug("UV: NMI hub list @ 0x%p (%d)\n", uv_hub_nmi_list, size);
BUG_ON(!uv_hub_nmi_list);
size = sizeof(struct uv_hub_nmi_s);
for_each_present_cpu(cpu) {
nid = cpu_to_node(cpu);
int nid = cpu_to_node(cpu);
if (uv_hub_nmi_list[nid] == NULL) {
uv_hub_nmi_list[nid] = kzalloc_node(size,
GFP_KERNEL, nid);
BUG_ON(!uv_hub_nmi_list[nid]);
raw_spin_lock_init(&(uv_hub_nmi_list[nid]->nmi_lock));
atomic_set(&uv_hub_nmi_list[nid]->cpu_owner, -1);
uv_hub_nmi_list[nid]->hub_present = hubbed;
uv_hub_nmi_list[nid]->pch_owner = (nid == 0);
}
uv_hub_nmi_per(cpu) = uv_hub_nmi_list[nid];
}
BUG_ON(!alloc_cpumask_var(&uv_nmi_cpu_mask, GFP_KERNEL));
}
/* Setup for UV Hub systems */
void __init uv_nmi_setup(void)
{
uv_nmi_setup_mmrs();
uv_nmi_setup_common(true);
uv_register_nmi_notifier();
pr_info("UV: Hub NMI enabled\n");
}
/* Setup for UV Hubless systems */
void __init uv_nmi_setup_hubless(void)
{
uv_nmi_setup_common(false);
pch_base = xlate_dev_mem_ptr(PCH_PCR_GPIO_1_BASE);
nmi_debug("UV: PCH base:%p from 0x%lx, GPP_D_0\n",
pch_base, PCH_PCR_GPIO_1_BASE);
if (uv_pch_init_enable)
uv_init_hubless_pch_d0();
uv_init_hubless_pch_io(GPI_NMI_ENA_GPP_D_0,
STS_GPP_D_0_MASK, STS_GPP_D_0_MASK);
uv_nmi_setup_hubless_intr();
/* Ensure NMI enabled in Processor Interface Reg: */
uv_reassert_nmi();
uv_register_nmi_notifier();
pr_info("UV: Hubless NMI enabled\n");
}
drivers/platform/x86/Kconfig
View file @ c945d022
......@@ -816,13 +816,6 @@ config INTEL_SCU_IPC_UTIL
low level access for debug work and updating the firmware. Say
N unless you will be doing this on an Intel MID platform.
config GPIO_INTEL_PMIC
bool "Intel PMIC GPIO support"
depends on INTEL_SCU_IPC && GPIOLIB
---help---
Say Y here to support GPIO via the SCU IPC interface
on Intel MID platforms.
config INTEL_MID_POWER_BUTTON
tristate "power button driver for Intel MID platforms"
depends on INTEL_SCU_IPC && INPUT
......
drivers/platform/x86/Makefile
View file @ c945d022
......@@ -50,7 +50,6 @@ obj-$(CONFIG_INTEL_SCU_IPC) += intel_scu_ipc.o
obj-$(CONFIG_INTEL_SCU_IPC_UTIL) += intel_scu_ipcutil.o
obj-$(CONFIG_INTEL_MFLD_THERMAL) += intel_mid_thermal.o
obj-$(CONFIG_INTEL_IPS) += intel_ips.o
obj-$(CONFIG_GPIO_INTEL_PMIC) += intel_pmic_gpio.o
obj-$(CONFIG_XO1_RFKILL) += xo1-rfkill.o
obj-$(CONFIG_XO15_EBOOK) += xo15-ebook.o
obj-$(CONFIG_IBM_RTL) += ibm_rtl.o
......
drivers/platform/x86/intel_pmic_gpio.c deleted 100644 → 0
View file @ 8b5abde1
/* Moorestown PMIC GPIO (access through IPC) driver
* Copyright (c) 2008 - 2009, Intel Corporation.
*
* Author: Alek Du <alek.du@intel.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
/* Supports:
* Moorestown platform PMIC chip
*/
#define pr_fmt(fmt) "%s: " fmt, __func__
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/stddef.h>
#include <linux/slab.h>
#include <linux/ioport.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/gpio/driver.h>
#include <asm/intel_scu_ipc.h>
#include <linux/device.h>
#include <linux/intel_pmic_gpio.h>
#include <linux/platform_device.h>
#define DRIVER_NAME "pmic_gpio"
/* register offset that IPC driver should use
* 8 GPIO + 8 GPOSW (6 controllable) + 8GPO
*/
enum pmic_gpio_register {
GPIO0 = 0xE0,
GPIO7 = 0xE7,
GPIOINT = 0xE8,
GPOSWCTL0 = 0xEC,
GPOSWCTL5 = 0xF1,
GPO = 0xF4,
};
/* bits definition for GPIO & GPOSW */
#define GPIO_DRV 0x01
#define GPIO_DIR 0x02
#define GPIO_DIN 0x04
#define GPIO_DOU 0x08
#define GPIO_INTCTL 0x30
#define GPIO_DBC 0xc0
#define GPOSW_DRV 0x01
#define GPOSW_DOU 0x08
#define GPOSW_RDRV 0x30
#define GPIO_UPDATE_TYPE 0x80000000
#define NUM_GPIO 24
struct pmic_gpio {
struct mutex buslock;
struct gpio_chip chip;
void *gpiointr;
int irq;
unsigned irq_base;
unsigned int update_type;
u32 trigger_type;
};
static void pmic_program_irqtype(int gpio, int type)
{
if (type & IRQ_TYPE_EDGE_RISING)
intel_scu_ipc_update_register(GPIO0 + gpio, 0x20, 0x20);
else
intel_scu_ipc_update_register(GPIO0 + gpio, 0x00, 0x20);
if (type & IRQ_TYPE_EDGE_FALLING)
intel_scu_ipc_update_register(GPIO0 + gpio, 0x10, 0x10);
else
intel_scu_ipc_update_register(GPIO0 + gpio, 0x00, 0x10);
};
static int pmic_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
{
if (offset >= 8) {
pr_err("only pin 0-7 support input\n");
return -1;/* we only have 8 GPIO can use as input */
}
return intel_scu_ipc_update_register(GPIO0 + offset,
GPIO_DIR, GPIO_DIR);
}
static int pmic_gpio_direction_output(struct gpio_chip *chip,
unsigned offset, int value)
{
int rc = 0;
if (offset < 8)/* it is GPIO */
rc = intel_scu_ipc_update_register(GPIO0 + offset,
GPIO_DRV | (value ? GPIO_DOU : 0),
GPIO_DRV | GPIO_DOU | GPIO_DIR);
else if (offset < 16)/* it is GPOSW */
rc = intel_scu_ipc_update_register(GPOSWCTL0 + offset - 8,
GPOSW_DRV | (value ? GPOSW_DOU : 0),
GPOSW_DRV | GPOSW_DOU | GPOSW_RDRV);
else if (offset > 15 && offset < 24)/* it is GPO */
rc = intel_scu_ipc_update_register(GPO,
value ? 1 << (offset - 16) : 0,
1 << (offset - 16));
else {
pr_err("invalid PMIC GPIO pin %d!\n", offset);
WARN_ON(1);
}
return rc;
}
static int pmic_gpio_get(struct gpio_chip *chip, unsigned offset)
{
u8 r;
int ret;
/* we only have 8 GPIO pins we can use as input */
if (offset >= 8)
return -EOPNOTSUPP;
ret = intel_scu_ipc_ioread8(GPIO0 + offset, &r);
if (ret < 0)
return ret;
return r & GPIO_DIN;
}
static void pmic_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
if (offset < 8)/* it is GPIO */
intel_scu_ipc_update_register(GPIO0 + offset,
GPIO_DRV | (value ? GPIO_DOU : 0),
GPIO_DRV | GPIO_DOU);
else if (offset < 16)/* it is GPOSW */
intel_scu_ipc_update_register(GPOSWCTL0 + offset - 8,
GPOSW_DRV | (value ? GPOSW_DOU : 0),
GPOSW_DRV | GPOSW_DOU | GPOSW_RDRV);
else if (offset > 15 && offset < 24) /* it is GPO */
intel_scu_ipc_update_register(GPO,
value ? 1 << (offset - 16) : 0,
1 << (offset - 16));
}
/*
* This is called from genirq with pg->buslock locked and
* irq_desc->lock held. We can not access the scu bus here, so we
* store the change and update in the bus_sync_unlock() function below
*/
static int pmic_irq_type(struct irq_data *data, unsigned type)
{
struct pmic_gpio *pg = irq_data_get_irq_chip_data(data);
u32 gpio = data->irq - pg->irq_base;
if (gpio >= pg->chip.ngpio)
return -EINVAL;
pg->trigger_type = type;
pg->update_type = gpio | GPIO_UPDATE_TYPE;
return 0;
}
static int pmic_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
{
struct pmic_gpio *pg = gpiochip_get_data(chip);
return pg->irq_base + offset;
}
static void pmic_bus_lock(struct irq_data *data)
{
struct pmic_gpio *pg = irq_data_get_irq_chip_data(data);
mutex_lock(&pg->buslock);
}
static void pmic_bus_sync_unlock(struct irq_data *data)
{
struct pmic_gpio *pg = irq_data_get_irq_chip_data(data);
if (pg->update_type) {
unsigned int gpio = pg->update_type & ~GPIO_UPDATE_TYPE;
pmic_program_irqtype(gpio, pg->trigger_type);
pg->update_type = 0;
}
mutex_unlock(&pg->buslock);
}
/* the gpiointr register is read-clear, so just do nothing. */
static void pmic_irq_unmask(struct irq_data *data) { }
static void pmic_irq_mask(struct irq_data *data) { }
static struct irq_chip pmic_irqchip = {
.name = "PMIC-GPIO",
.irq_mask = pmic_irq_mask,
.irq_unmask = pmic_irq_unmask,
.irq_set_type = pmic_irq_type,
.irq_bus_lock = pmic_bus_lock,
.irq_bus_sync_unlock = pmic_bus_sync_unlock,
};
static irqreturn_t pmic_irq_handler(int irq, void *data)
{
struct pmic_gpio *pg = data;
u8 intsts = *((u8 *)pg->gpiointr + 4);
int gpio;
irqreturn_t ret = IRQ_NONE;
for (gpio = 0; gpio < 8; gpio++) {
if (intsts & (1 << gpio)) {
pr_debug("pmic pin %d triggered\n", gpio);
generic_handle_irq(pg->irq_base + gpio);
ret = IRQ_HANDLED;
}
}
return ret;
}
static int platform_pmic_gpio_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
int irq = platform_get_irq(pdev, 0);
struct intel_pmic_gpio_platform_data *pdata = dev->platform_data;
struct pmic_gpio *pg;
int retval;
int i;
if (irq < 0) {
dev_dbg(dev, "no IRQ line\n");
return -EINVAL;
}
if (!pdata || !pdata->gpio_base || !pdata->irq_base) {
dev_dbg(dev, "incorrect or missing platform data\n");
return -EINVAL;
}
pg = kzalloc(sizeof(*pg), GFP_KERNEL);
if (!pg)
return -ENOMEM;
dev_set_drvdata(dev, pg);
pg->irq = irq;
/* setting up SRAM mapping for GPIOINT register */
pg->gpiointr = ioremap_nocache(pdata->gpiointr, 8);
if (!pg->gpiointr) {
pr_err("Can not map GPIOINT\n");
retval = -EINVAL;
goto err2;
}
pg->irq_base = pdata->irq_base;
pg->chip.label = "intel_pmic";
pg->chip.direction_input = pmic_gpio_direction_input;
pg->chip.direction_output = pmic_gpio_direction_output;
pg->chip.get = pmic_gpio_get;
pg->chip.set = pmic_gpio_set;
pg->chip.to_irq = pmic_gpio_to_irq;
pg->chip.base = pdata->gpio_base;
pg->chip.ngpio = NUM_GPIO;
pg->chip.can_sleep = 1;
pg->chip.parent = dev;
mutex_init(&pg->buslock);
pg->chip.parent = dev;
retval = gpiochip_add_data(&pg->chip, pg);
if (retval) {
pr_err("Can not add pmic gpio chip\n");
goto err;
}
retval = request_irq(pg->irq, pmic_irq_handler, 0, "pmic", pg);
if (retval) {
pr_warn("Interrupt request failed\n");
goto fail_request_irq;
}
for (i = 0; i < 8; i++) {
irq_set_chip_and_handler_name(i + pg->irq_base,
&pmic_irqchip,
handle_simple_irq,
"demux");
irq_set_chip_data(i + pg->irq_base, pg);
}
return 0;
fail_request_irq:
gpiochip_remove(&pg->chip);
err:
iounmap(pg->gpiointr);
err2:
kfree(pg);
return retval;
}
/* at the same time, register a platform driver
* this supports the sfi 0.81 fw */
static struct platform_driver platform_pmic_gpio_driver = {
.driver = {
.name = DRIVER_NAME,
},
.probe = platform_pmic_gpio_probe,
};
static int __init platform_pmic_gpio_init(void)
{
return platform_driver_register(&platform_pmic_gpio_driver);
}
subsys_initcall(platform_pmic_gpio_init);
include/linux/intel_pmic_gpio.h deleted 100644 → 0
View file @ 8b5abde1
#ifndef LINUX_INTEL_PMIC_H
#define LINUX_INTEL_PMIC_H
struct intel_pmic_gpio_platform_data {
/* the first IRQ of the chip */
unsigned irq_base;
/* number assigned to the first GPIO */
unsigned gpio_base;
/* sram address for gpiointr register, the langwell chip will map
* the PMIC spi GPIO expander's GPIOINTR register in sram.
*/
unsigned gpiointr;
};
#endif
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