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Kirill Smelkov
linux
Commits
c9ee46a9
Commit
c9ee46a9
authored
Oct 11, 2010
by
Russell King
Browse files
Options
Browse Files
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Plain Diff
Merge branch 'for-rmk-next' of
git://git.pengutronix.de/git/imx/linux-2.6
into devel-stable
parents
4fa04665
81490fcd
Changes
90
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Inline
Side-by-side
Showing
90 changed files
with
3003 additions
and
1245 deletions
+3003
-1245
arch/arm/configs/mx27_defconfig
arch/arm/configs/mx27_defconfig
+12
-3
arch/arm/configs/mx31pdk_defconfig
arch/arm/configs/mx31pdk_defconfig
+0
-44
arch/arm/configs/mx3_defconfig
arch/arm/configs/mx3_defconfig
+1
-1
arch/arm/configs/mx51_defconfig
arch/arm/configs/mx51_defconfig
+3
-6
arch/arm/mach-imx/Kconfig
arch/arm/mach-imx/Kconfig
+12
-2
arch/arm/mach-imx/Makefile
arch/arm/mach-imx/Makefile
+1
-0
arch/arm/mach-imx/clock-imx1.c
arch/arm/mach-imx/clock-imx1.c
+1
-1
arch/arm/mach-imx/clock-imx21.c
arch/arm/mach-imx/clock-imx21.c
+3
-3
arch/arm/mach-imx/clock-imx27.c
arch/arm/mach-imx/clock-imx27.c
+24
-24
arch/arm/mach-imx/devices-imx1.h
arch/arm/mach-imx/devices-imx1.h
+8
-6
arch/arm/mach-imx/devices-imx21.h
arch/arm/mach-imx/devices-imx21.h
+21
-15
arch/arm/mach-imx/devices-imx27.h
arch/arm/mach-imx/devices-imx27.h
+28
-23
arch/arm/mach-imx/devices.c
arch/arm/mach-imx/devices.c
+0
-56
arch/arm/mach-imx/devices.h
arch/arm/mach-imx/devices.h
+0
-3
arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
+4
-4
arch/arm/mach-imx/mach-cpuimx27.c
arch/arm/mach-imx/mach-cpuimx27.c
+3
-3
arch/arm/mach-imx/mach-imx27_visstrim_m10.c
arch/arm/mach-imx/mach-imx27_visstrim_m10.c
+263
-0
arch/arm/mach-imx/mach-imx27lite.c
arch/arm/mach-imx/mach-imx27lite.c
+2
-6
arch/arm/mach-imx/mach-mx1ads.c
arch/arm/mach-imx/mach-mx1ads.c
+2
-2
arch/arm/mach-imx/mach-mx21ads.c
arch/arm/mach-imx/mach-mx21ads.c
+1
-1
arch/arm/mach-imx/mach-mx27_3ds.c
arch/arm/mach-imx/mach-mx27_3ds.c
+2
-6
arch/arm/mach-imx/mach-mx27ads.c
arch/arm/mach-imx/mach-mx27ads.c
+3
-3
arch/arm/mach-imx/mach-mxt_td60.c
arch/arm/mach-imx/mach-mxt_td60.c
+4
-9
arch/arm/mach-imx/mach-pca100.c
arch/arm/mach-imx/mach-pca100.c
+6
-9
arch/arm/mach-imx/mach-pcm038.c
arch/arm/mach-imx/mach-pcm038.c
+4
-4
arch/arm/mach-imx/mach-scb9328.c
arch/arm/mach-imx/mach-scb9328.c
+1
-1
arch/arm/mach-imx/pcm970-baseboard.c
arch/arm/mach-imx/pcm970-baseboard.c
+2
-2
arch/arm/mach-mx25/Kconfig
arch/arm/mach-mx25/Kconfig
+4
-2
arch/arm/mach-mx25/clock.c
arch/arm/mach-mx25/clock.c
+25
-3
arch/arm/mach-mx25/devices-imx25.h
arch/arm/mach-mx25/devices-imx25.h
+37
-25
arch/arm/mach-mx25/devices.c
arch/arm/mach-mx25/devices.c
+0
-58
arch/arm/mach-mx25/devices.h
arch/arm/mach-mx25/devices.h
+0
-3
arch/arm/mach-mx25/eukrea_mbimxsd-baseboard.c
arch/arm/mach-mx25/eukrea_mbimxsd-baseboard.c
+9
-3
arch/arm/mach-mx25/mach-cpuimx25.c
arch/arm/mach-mx25/mach-cpuimx25.c
+2
-3
arch/arm/mach-mx25/mach-mx25_3ds.c
arch/arm/mach-mx25/mach-mx25_3ds.c
+2
-3
arch/arm/mach-mx3/Kconfig
arch/arm/mach-mx3/Kconfig
+9
-2
arch/arm/mach-mx3/Makefile
arch/arm/mach-mx3/Makefile
+0
-1
arch/arm/mach-mx3/clock-imx31.c
arch/arm/mach-mx3/clock-imx31.c
+5
-5
arch/arm/mach-mx3/clock-imx35.c
arch/arm/mach-mx3/clock-imx35.c
+18
-10
arch/arm/mach-mx3/cpu.c
arch/arm/mach-mx3/cpu.c
+37
-10
arch/arm/mach-mx3/devices-imx31.h
arch/arm/mach-mx3/devices-imx31.h
+26
-23
arch/arm/mach-mx3/devices-imx35.h
arch/arm/mach-mx3/devices-imx35.h
+34
-17
arch/arm/mach-mx3/devices.c
arch/arm/mach-mx3/devices.c
+0
-63
arch/arm/mach-mx3/devices.h
arch/arm/mach-mx3/devices.h
+0
-4
arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c
arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c
+16
-3
arch/arm/mach-mx3/mach-cpuimx35.c
arch/arm/mach-mx3/mach-cpuimx35.c
+8
-30
arch/arm/mach-mx3/mach-mx31ads.c
arch/arm/mach-mx3/mach-mx31ads.c
+1
-1
arch/arm/mach-mx3/mach-mx35_3ds.c
arch/arm/mach-mx3/mach-mx35_3ds.c
+48
-3
arch/arm/mach-mx3/mach-pcm043.c
arch/arm/mach-mx3/mach-pcm043.c
+11
-4
arch/arm/mach-mx3/mm.c
arch/arm/mach-mx3/mm.c
+18
-0
arch/arm/mach-mx5/Kconfig
arch/arm/mach-mx5/Kconfig
+14
-0
arch/arm/mach-mx5/Makefile
arch/arm/mach-mx5/Makefile
+1
-0
arch/arm/mach-mx5/board-cpuimx51.c
arch/arm/mach-mx5/board-cpuimx51.c
+7
-7
arch/arm/mach-mx5/board-mx51_3ds.c
arch/arm/mach-mx5/board-mx51_3ds.c
+37
-5
arch/arm/mach-mx5/board-mx51_babbage.c
arch/arm/mach-mx5/board-mx51_babbage.c
+54
-18
arch/arm/mach-mx5/board-mx51_efikamx.c
arch/arm/mach-mx5/board-mx51_efikamx.c
+121
-0
arch/arm/mach-mx5/clock-mx51.c
arch/arm/mach-mx5/clock-mx51.c
+204
-27
arch/arm/mach-mx5/devices-imx51.h
arch/arm/mach-mx5/devices-imx51.h
+38
-0
arch/arm/mach-mx5/devices.c
arch/arm/mach-mx5/devices.c
+0
-114
arch/arm/mach-mx5/devices.h
arch/arm/mach-mx5/devices.h
+0
-6
arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c
arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c
+4
-3
arch/arm/plat-mxc/Kconfig
arch/arm/plat-mxc/Kconfig
+12
-0
arch/arm/plat-mxc/Makefile
arch/arm/plat-mxc/Makefile
+1
-0
arch/arm/plat-mxc/audmux-v2.c
arch/arm/plat-mxc/audmux-v2.c
+7
-1
arch/arm/plat-mxc/devices/Kconfig
arch/arm/plat-mxc/devices/Kconfig
+10
-0
arch/arm/plat-mxc/devices/Makefile
arch/arm/plat-mxc/devices/Makefile
+5
-4
arch/arm/plat-mxc/devices/platform-esdhc.c
arch/arm/plat-mxc/devices/platform-esdhc.c
+31
-0
arch/arm/plat-mxc/devices/platform-fec.c
arch/arm/plat-mxc/devices/platform-fec.c
+58
-0
arch/arm/plat-mxc/devices/platform-imx-dma.c
arch/arm/plat-mxc/devices/platform-imx-dma.c
+129
-0
arch/arm/plat-mxc/devices/platform-imx-i2c.c
arch/arm/plat-mxc/devices/platform-imx-i2c.c
+77
-7
arch/arm/plat-mxc/devices/platform-imx-ssi.c
arch/arm/plat-mxc/devices/platform-imx-ssi.c
+107
-0
arch/arm/plat-mxc/devices/platform-imx-uart.c
arch/arm/plat-mxc/devices/platform-imx-uart.c
+115
-22
arch/arm/plat-mxc/devices/platform-mxc_nand.c
arch/arm/plat-mxc/devices/platform-mxc_nand.c
+62
-23
arch/arm/plat-mxc/devices/platform-spi_imx.c
arch/arm/plat-mxc/devices/platform-spi_imx.c
+80
-9
arch/arm/plat-mxc/ehci.c
arch/arm/plat-mxc/ehci.c
+2
-2
arch/arm/plat-mxc/epit.c
arch/arm/plat-mxc/epit.c
+242
-0
arch/arm/plat-mxc/gpio.c
arch/arm/plat-mxc/gpio.c
+1
-1
arch/arm/plat-mxc/include/mach/common.h
arch/arm/plat-mxc/include/mach/common.h
+1
-0
arch/arm/plat-mxc/include/mach/devices-common.h
arch/arm/plat-mxc/include/mach/devices-common.h
+81
-27
arch/arm/plat-mxc/include/mach/esdhc.h
arch/arm/plat-mxc/include/mach/esdhc.h
+16
-0
arch/arm/plat-mxc/include/mach/iomux-mx51.h
arch/arm/plat-mxc/include/mach/iomux-mx51.h
+53
-8
arch/arm/plat-mxc/include/mach/mx21.h
arch/arm/plat-mxc/include/mach/mx21.h
+1
-1
arch/arm/plat-mxc/include/mach/mx25.h
arch/arm/plat-mxc/include/mach/mx25.h
+14
-1
arch/arm/plat-mxc/include/mach/mx27.h
arch/arm/plat-mxc/include/mach/mx27.h
+1
-1
arch/arm/plat-mxc/include/mach/mx31.h
arch/arm/plat-mxc/include/mach/mx31.h
+10
-1
arch/arm/plat-mxc/include/mach/mx35.h
arch/arm/plat-mxc/include/mach/mx35.h
+17
-15
arch/arm/plat-mxc/include/mach/mx3x.h
arch/arm/plat-mxc/include/mach/mx3x.h
+9
-14
arch/arm/plat-mxc/include/mach/mx51.h
arch/arm/plat-mxc/include/mach/mx51.h
+309
-348
drivers/spi/Kconfig
drivers/spi/Kconfig
+16
-0
drivers/spi/spi_imx.c
drivers/spi/spi_imx.c
+335
-67
No files found.
arch/arm/configs/mx27_defconfig
View file @
c9ee46a9
...
@@ -21,8 +21,14 @@ CONFIG_ARCH_MX2=y
...
@@ -21,8 +21,14 @@ CONFIG_ARCH_MX2=y
CONFIG_MACH_MX27=y
CONFIG_MACH_MX27=y
CONFIG_MACH_MX27ADS=y
CONFIG_MACH_MX27ADS=y
CONFIG_MACH_PCM038=y
CONFIG_MACH_PCM038=y
CONFIG_MACH_CPUIMX27=y
CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2=y
CONFIG_MACH_EUKREA_CPUIMX27_USEUART4=y
CONFIG_MACH_MX27_3DS=y
CONFIG_MACH_MX27_3DS=y
CONFIG_MACH_IMX27_VISSTRIM_M10=y
CONFIG_MACH_IMX27LITE=y
CONFIG_MACH_IMX27LITE=y
CONFIG_MACH_PCA100=y
CONFIG_MACH_MXT_TD60=y
CONFIG_MXC_IRQ_PRIOR=y
CONFIG_MXC_IRQ_PRIOR=y
CONFIG_MXC_PWM=y
CONFIG_MXC_PWM=y
CONFIG_NO_HZ=y
CONFIG_NO_HZ=y
...
@@ -76,7 +82,9 @@ CONFIG_INPUT_EVDEV=y
...
@@ -76,7 +82,9 @@ CONFIG_INPUT_EVDEV=y
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_INPUT_MOUSE is not set
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_ADS7846=m
# CONFIG_SERIO is not set
# CONFIG_SERIO is not set
CONFIG_SERIAL_8250=m
CONFIG_SERIAL_IMX=y
CONFIG_SERIAL_IMX=y
CONFIG_SERIAL_IMX_CONSOLE=y
CONFIG_SERIAL_IMX_CONSOLE=y
# CONFIG_LEGACY_PTYS is not set
# CONFIG_LEGACY_PTYS is not set
...
@@ -85,19 +93,20 @@ CONFIG_I2C=y
...
@@ -85,19 +93,20 @@ CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_IMX=y
CONFIG_I2C_IMX=y
CONFIG_SPI=y
CONFIG_SPI=y
CONFIG_SPI_
BITBANG
=y
CONFIG_SPI_
IMX
=y
CONFIG_W1=y
CONFIG_W1=y
CONFIG_W1_MASTER_MXC=y
CONFIG_W1_MASTER_MXC=y
CONFIG_W1_SLAVE_THERM=y
CONFIG_W1_SLAVE_THERM=y
# CONFIG_HWMON is not set
# CONFIG_HWMON is not set
CONFIG_FB=y
CONFIG_FB=y
CONFIG_FB_IMX=y
CONFIG_FB_IMX=y
# CONFIG_VGA_CONSOLE is not set
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_FONTS=y
CONFIG_FONTS=y
CONFIG_FONT_8x8=y
CONFIG_FONT_8x8=y
# CONFIG_HID_SUPPORT is not set
# CONFIG_HID_SUPPORT is not set
# CONFIG_USB_SUPPORT is not set
CONFIG_USB=m
# CONFIG_USB_DEVICE_CLASS is not set
CONFIG_USB_ULPI=y
CONFIG_MMC=y
CONFIG_MMC=y
CONFIG_MMC_MXC=y
CONFIG_MMC_MXC=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_CLASS=y
...
...
arch/arm/configs/mx31pdk_defconfig
deleted
100644 → 0
View file @
4fa04665
# CONFIG_LOCALVERSION_AUTO is not set
# CONFIG_SWAP is not set
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
# CONFIG_COMPAT_BRK is not set
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_MXC=y
# CONFIG_MACH_MX31ADS is not set
CONFIG_MACH_MX31_3DS=y
CONFIG_AEABI=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_NET_KEY=y
CONFIG_INET=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
# CONFIG_INET_LRO is not set
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
# CONFIG_FIRMWARE_IN_KERNEL is not set
# CONFIG_BLK_DEV is not set
# CONFIG_MISC_DEVICES is not set
CONFIG_NETDEVICES=y
CONFIG_NET_ETHERNET=y
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_SERIO is not set
# CONFIG_DEVKMEM is not set
CONFIG_SERIAL_IMX=y
CONFIG_SERIAL_IMX_CONSOLE=y
# CONFIG_LEGACY_PTYS is not set
# CONFIG_HW_RANDOM is not set
# CONFIG_HWMON is not set
# CONFIG_VGA_CONSOLE is not set
# CONFIG_HID_SUPPORT is not set
# CONFIG_USB_SUPPORT is not set
# CONFIG_DNOTIFY is not set
# CONFIG_ENABLE_WARN_DEPRECATED is not set
# CONFIG_ENABLE_MUST_CHECK is not set
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
# CONFIG_CRYPTO_ANSI_CPRNG is not set
# CONFIG_CRC32 is not set
arch/arm/configs/mx3_defconfig
View file @
c9ee46a9
...
@@ -24,6 +24,7 @@ CONFIG_MACH_PCM043=y
...
@@ -24,6 +24,7 @@ CONFIG_MACH_PCM043=y
CONFIG_MACH_ARMADILLO5X0=y
CONFIG_MACH_ARMADILLO5X0=y
CONFIG_MACH_MX35_3DS=y
CONFIG_MACH_MX35_3DS=y
CONFIG_MACH_KZM_ARM11_01=y
CONFIG_MACH_KZM_ARM11_01=y
CONFIG_MACH_EUKREA_CPUIMX35=y
CONFIG_MXC_IRQ_PRIOR=y
CONFIG_MXC_IRQ_PRIOR=y
CONFIG_MXC_PWM=y
CONFIG_MXC_PWM=y
CONFIG_NO_HZ=y
CONFIG_NO_HZ=y
...
@@ -108,7 +109,6 @@ CONFIG_MMC=y
...
@@ -108,7 +109,6 @@ CONFIG_MMC=y
CONFIG_MMC_MXC=y
CONFIG_MMC_MXC=y
CONFIG_DMADEVICES=y
CONFIG_DMADEVICES=y
# CONFIG_DNOTIFY is not set
# CONFIG_DNOTIFY is not set
CONFIG_INOTIFY=y
CONFIG_TMPFS=y
CONFIG_TMPFS=y
CONFIG_JFFS2_FS=y
CONFIG_JFFS2_FS=y
CONFIG_UBIFS_FS=y
CONFIG_UBIFS_FS=y
...
...
arch/arm/configs/mx51_defconfig
View file @
c9ee46a9
...
@@ -15,6 +15,8 @@ CONFIG_MODULE_SRCVERSION_ALL=y
...
@@ -15,6 +15,8 @@ CONFIG_MODULE_SRCVERSION_ALL=y
CONFIG_ARCH_MXC=y
CONFIG_ARCH_MXC=y
CONFIG_ARCH_MX5=y
CONFIG_ARCH_MX5=y
CONFIG_MACH_MX51_BABBAGE=y
CONFIG_MACH_MX51_BABBAGE=y
CONFIG_MACH_MX51_3DS=y
CONFIG_MACH_EUKREA_CPUIMX51=y
CONFIG_NO_HZ=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_PREEMPT_VOLUNTARY=y
CONFIG_PREEMPT_VOLUNTARY=y
...
@@ -69,7 +71,6 @@ CONFIG_REALTEK_PHY=y
...
@@ -69,7 +71,6 @@ CONFIG_REALTEK_PHY=y
CONFIG_NATIONAL_PHY=y
CONFIG_NATIONAL_PHY=y
CONFIG_STE10XP=y
CONFIG_STE10XP=y
CONFIG_LSI_ET1011C_PHY=y
CONFIG_LSI_ET1011C_PHY=y
CONFIG_FIXED_PHY=y
CONFIG_MDIO_BITBANG=y
CONFIG_MDIO_BITBANG=y
CONFIG_MDIO_GPIO=y
CONFIG_MDIO_GPIO=y
CONFIG_NET_ETHERNET=y
CONFIG_NET_ETHERNET=y
...
@@ -100,7 +101,6 @@ CONFIG_I2C_ALGOPCF=m
...
@@ -100,7 +101,6 @@ CONFIG_I2C_ALGOPCF=m
CONFIG_I2C_ALGOPCA=m
CONFIG_I2C_ALGOPCA=m
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_SYSFS=y
# CONFIG_HWMON is not set
# CONFIG_HWMON is not set
# CONFIG_VGA_CONSOLE is not set
# CONFIG_HID_SUPPORT is not set
# CONFIG_HID_SUPPORT is not set
CONFIG_USB=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_HCD=y
...
@@ -117,13 +117,11 @@ CONFIG_EXT2_FS_XATTR=y
...
@@ -117,13 +117,11 @@ CONFIG_EXT2_FS_XATTR=y
CONFIG_EXT2_FS_POSIX_ACL=y
CONFIG_EXT2_FS_POSIX_ACL=y
CONFIG_EXT2_FS_SECURITY=y
CONFIG_EXT2_FS_SECURITY=y
CONFIG_EXT3_FS=y
CONFIG_EXT3_FS=y
CONFIG_EXT3_DEFAULTS_TO_ORDERED=y
CONFIG_EXT3_FS_POSIX_ACL=y
CONFIG_EXT3_FS_POSIX_ACL=y
CONFIG_EXT3_FS_SECURITY=y
CONFIG_EXT3_FS_SECURITY=y
CONFIG_EXT4_FS=y
CONFIG_EXT4_FS=y
CONFIG_EXT4_FS_POSIX_ACL=y
CONFIG_EXT4_FS_POSIX_ACL=y
CONFIG_EXT4_FS_SECURITY=y
CONFIG_EXT4_FS_SECURITY=y
CONFIG_INOTIFY=y
CONFIG_QUOTA=y
CONFIG_QUOTA=y
CONFIG_QUOTA_NETLINK_INTERFACE=y
CONFIG_QUOTA_NETLINK_INTERFACE=y
# CONFIG_PRINT_QUOTA_WARNING is not set
# CONFIG_PRINT_QUOTA_WARNING is not set
...
@@ -136,6 +134,7 @@ CONFIG_ZISOFS=y
...
@@ -136,6 +134,7 @@ CONFIG_ZISOFS=y
CONFIG_UDF_FS=m
CONFIG_UDF_FS=m
CONFIG_MSDOS_FS=m
CONFIG_MSDOS_FS=m
CONFIG_VFAT_FS=y
CONFIG_VFAT_FS=y
CONFIG_TMPFS=y
CONFIG_CONFIGFS_FS=m
CONFIG_CONFIGFS_FS=m
CONFIG_NFS_FS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
CONFIG_NFS_V3=y
...
@@ -151,7 +150,6 @@ CONFIG_NLS_UTF8=y
...
@@ -151,7 +150,6 @@ CONFIG_NLS_UTF8=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_FS=y
CONFIG_DEBUG_FS=y
CONFIG_DEBUG_KERNEL=y
CONFIG_DEBUG_KERNEL=y
# CONFIG_DETECT_SOFTLOCKUP is not set
# CONFIG_SCHED_DEBUG is not set
# CONFIG_SCHED_DEBUG is not set
# CONFIG_DEBUG_BUGVERBOSE is not set
# CONFIG_DEBUG_BUGVERBOSE is not set
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
...
@@ -159,7 +157,6 @@ CONFIG_DEBUG_KERNEL=y
...
@@ -159,7 +157,6 @@ CONFIG_DEBUG_KERNEL=y
# CONFIG_ARM_UNWIND is not set
# CONFIG_ARM_UNWIND is not set
CONFIG_DEBUG_LL=y
CONFIG_DEBUG_LL=y
CONFIG_EARLY_PRINTK=y
CONFIG_EARLY_PRINTK=y
CONFIG_KEYS=y
CONFIG_SECURITYFS=y
CONFIG_SECURITYFS=y
CONFIG_CRYPTO_DEFLATE=y
CONFIG_CRYPTO_DEFLATE=y
CONFIG_CRYPTO_LZO=y
CONFIG_CRYPTO_LZO=y
...
...
arch/arm/mach-imx/Kconfig
View file @
c9ee46a9
...
@@ -146,8 +146,8 @@ choice
...
@@ -146,8 +146,8 @@ choice
default MACH_EUKREA_MBIMX27_BASEBOARD
default MACH_EUKREA_MBIMX27_BASEBOARD
config MACH_EUKREA_MBIMX27_BASEBOARD
config MACH_EUKREA_MBIMX27_BASEBOARD
prompt
"Eukrea MBIMX27 development board"
bool
"Eukrea MBIMX27 development board"
bool
select IMX_HAVE_PLATFORM_IMX_SSI
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_SPI_IMX
select IMX_HAVE_PLATFORM_SPI_IMX
help
help
...
@@ -163,6 +163,15 @@ config MACH_MX27_3DS
...
@@ -163,6 +163,15 @@ config MACH_MX27_3DS
Include support for MX27PDK platform. This includes specific
Include support for MX27PDK platform. This includes specific
configurations for the board and its peripherals.
configurations for the board and its peripherals.
config MACH_IMX27_VISSTRIM_M10
bool "Vista Silicon i.MX27 Visstrim_m10"
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
help
Include support for Visstrim_m10 platform and its different variants.
This includes specific configurations for the board and its
peripherals.
config MACH_IMX27LITE
config MACH_IMX27LITE
bool "LogicPD MX27 LITEKIT platform"
bool "LogicPD MX27 LITEKIT platform"
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_IMX_UART
...
@@ -173,6 +182,7 @@ config MACH_IMX27LITE
...
@@ -173,6 +182,7 @@ config MACH_IMX27LITE
config MACH_PCA100
config MACH_PCA100
bool "Phytec phyCARD-s (pca100)"
bool "Phytec phyCARD-s (pca100)"
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_SSI
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_SPI_IMX
select IMX_HAVE_PLATFORM_SPI_IMX
...
...
arch/arm/mach-imx/Makefile
View file @
c9ee46a9
...
@@ -27,6 +27,7 @@ obj-$(CONFIG_MACH_PCM038) += mach-pcm038.o
...
@@ -27,6 +27,7 @@ obj-$(CONFIG_MACH_PCM038) += mach-pcm038.o
obj-$(CONFIG_MACH_PCM970_BASEBOARD)
+=
pcm970-baseboard.o
obj-$(CONFIG_MACH_PCM970_BASEBOARD)
+=
pcm970-baseboard.o
obj-$(CONFIG_MACH_MX27_3DS)
+=
mach-mx27_3ds.o
obj-$(CONFIG_MACH_MX27_3DS)
+=
mach-mx27_3ds.o
obj-$(CONFIG_MACH_IMX27LITE)
+=
mach-imx27lite.o
obj-$(CONFIG_MACH_IMX27LITE)
+=
mach-imx27lite.o
obj-$(CONFIG_MACH_IMX27_VISSTRIM_M10)
+=
mach-imx27_visstrim_m10.o
obj-$(CONFIG_MACH_CPUIMX27)
+=
mach-cpuimx27.o
obj-$(CONFIG_MACH_CPUIMX27)
+=
mach-cpuimx27.o
obj-$(CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD)
+=
eukrea_mbimx27-baseboard.o
obj-$(CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD)
+=
eukrea_mbimx27-baseboard.o
obj-$(CONFIG_MACH_PCA100)
+=
mach-pca100.o
obj-$(CONFIG_MACH_PCA100)
+=
mach-pca100.o
...
...
arch/arm/mach-imx/clock-imx1.c
View file @
c9ee46a9
...
@@ -592,7 +592,7 @@ static struct clk_lookup lookups[] __initdata = {
...
@@ -592,7 +592,7 @@ static struct clk_lookup lookups[] __initdata = {
_REGISTER_CLOCK
(
"imx-uart.1"
,
NULL
,
uart_clk
)
_REGISTER_CLOCK
(
"imx-uart.1"
,
NULL
,
uart_clk
)
_REGISTER_CLOCK
(
"imx-uart.2"
,
NULL
,
uart_clk
)
_REGISTER_CLOCK
(
"imx-uart.2"
,
NULL
,
uart_clk
)
_REGISTER_CLOCK
(
"imx-i2c.0"
,
NULL
,
i2c_clk
)
_REGISTER_CLOCK
(
"imx-i2c.0"
,
NULL
,
i2c_clk
)
_REGISTER_CLOCK
(
"
spi_imx
.0"
,
NULL
,
spi_clk
)
_REGISTER_CLOCK
(
"
imx1-cspi
.0"
,
NULL
,
spi_clk
)
_REGISTER_CLOCK
(
"imx-mmc.0"
,
NULL
,
sdhc_clk
)
_REGISTER_CLOCK
(
"imx-mmc.0"
,
NULL
,
sdhc_clk
)
_REGISTER_CLOCK
(
"imx-fb.0"
,
NULL
,
lcdc_clk
)
_REGISTER_CLOCK
(
"imx-fb.0"
,
NULL
,
lcdc_clk
)
_REGISTER_CLOCK
(
NULL
,
"mshc"
,
mshc_clk
)
_REGISTER_CLOCK
(
NULL
,
"mshc"
,
mshc_clk
)
...
...
arch/arm/mach-imx/clock-imx21.c
View file @
c9ee46a9
...
@@ -1172,9 +1172,9 @@ static struct clk_lookup lookups[] = {
...
@@ -1172,9 +1172,9 @@ static struct clk_lookup lookups[] = {
_REGISTER_CLOCK
(
NULL
,
"pwm"
,
pwm_clk
[
0
])
_REGISTER_CLOCK
(
NULL
,
"pwm"
,
pwm_clk
[
0
])
_REGISTER_CLOCK
(
NULL
,
"sdhc1"
,
sdhc_clk
[
0
])
_REGISTER_CLOCK
(
NULL
,
"sdhc1"
,
sdhc_clk
[
0
])
_REGISTER_CLOCK
(
NULL
,
"sdhc2"
,
sdhc_clk
[
1
])
_REGISTER_CLOCK
(
NULL
,
"sdhc2"
,
sdhc_clk
[
1
])
_REGISTER_CLOCK
(
NULL
,
"cspi1"
,
cspi_clk
[
0
])
_REGISTER_CLOCK
(
"imx21-cspi.0"
,
NULL
,
cspi_clk
[
0
])
_REGISTER_CLOCK
(
NULL
,
"cspi2"
,
cspi_clk
[
1
])
_REGISTER_CLOCK
(
"imx21-cspi.1"
,
NULL
,
cspi_clk
[
1
])
_REGISTER_CLOCK
(
NULL
,
"cspi3"
,
cspi_clk
[
2
])
_REGISTER_CLOCK
(
"imx21-cspi.2"
,
NULL
,
cspi_clk
[
2
])
_REGISTER_CLOCK
(
"imx-fb.0"
,
NULL
,
lcdc_clk
[
0
])
_REGISTER_CLOCK
(
"imx-fb.0"
,
NULL
,
lcdc_clk
[
0
])
_REGISTER_CLOCK
(
NULL
,
"csi"
,
csi_clk
[
0
])
_REGISTER_CLOCK
(
NULL
,
"csi"
,
csi_clk
[
0
])
_REGISTER_CLOCK
(
"imx21-hcd.0"
,
NULL
,
usb_clk
[
0
])
_REGISTER_CLOCK
(
"imx21-hcd.0"
,
NULL
,
usb_clk
[
0
])
...
...
arch/arm/mach-imx/clock-imx27.c
View file @
c9ee46a9
...
@@ -594,27 +594,27 @@ DEFINE_CLOCK(uart2_clk1, 0, PCCR1, 30, NULL, NULL, &ipg_clk);
...
@@ -594,27 +594,27 @@ DEFINE_CLOCK(uart2_clk1, 0, PCCR1, 30, NULL, NULL, &ipg_clk);
DEFINE_CLOCK
(
uart1_clk1
,
0
,
PCCR1
,
31
,
NULL
,
NULL
,
&
ipg_clk
);
DEFINE_CLOCK
(
uart1_clk1
,
0
,
PCCR1
,
31
,
NULL
,
NULL
,
&
ipg_clk
);
/* Clocks we cannot directly gate, but drivers need their rates */
/* Clocks we cannot directly gate, but drivers need their rates */
DEFINE_CLOCK
(
cspi1_clk
,
0
,
0
,
0
,
NULL
,
&
cspi1_clk1
,
&
per2_clk
);
DEFINE_CLOCK
(
cspi1_clk
,
0
,
NULL
,
0
,
NULL
,
&
cspi1_clk1
,
&
per2_clk
);
DEFINE_CLOCK
(
cspi2_clk
,
1
,
0
,
0
,
NULL
,
&
cspi2_clk1
,
&
per2_clk
);
DEFINE_CLOCK
(
cspi2_clk
,
1
,
NULL
,
0
,
NULL
,
&
cspi2_clk1
,
&
per2_clk
);
DEFINE_CLOCK
(
cspi3_clk
,
2
,
0
,
0
,
NULL
,
&
cspi13_clk1
,
&
per2_clk
);
DEFINE_CLOCK
(
cspi3_clk
,
2
,
NULL
,
0
,
NULL
,
&
cspi13_clk1
,
&
per2_clk
);
DEFINE_CLOCK
(
sdhc1_clk
,
0
,
0
,
0
,
NULL
,
&
sdhc1_clk1
,
&
per2_clk
);
DEFINE_CLOCK
(
sdhc1_clk
,
0
,
NULL
,
0
,
NULL
,
&
sdhc1_clk1
,
&
per2_clk
);
DEFINE_CLOCK
(
sdhc2_clk
,
1
,
0
,
0
,
NULL
,
&
sdhc2_clk1
,
&
per2_clk
);
DEFINE_CLOCK
(
sdhc2_clk
,
1
,
NULL
,
0
,
NULL
,
&
sdhc2_clk1
,
&
per2_clk
);
DEFINE_CLOCK
(
sdhc3_clk
,
2
,
0
,
0
,
NULL
,
&
sdhc3_clk1
,
&
per2_clk
);
DEFINE_CLOCK
(
sdhc3_clk
,
2
,
NULL
,
0
,
NULL
,
&
sdhc3_clk1
,
&
per2_clk
);
DEFINE_CLOCK
(
pwm_clk
,
0
,
0
,
0
,
NULL
,
&
pwm_clk1
,
&
per1_clk
);
DEFINE_CLOCK
(
pwm_clk
,
0
,
NULL
,
0
,
NULL
,
&
pwm_clk1
,
&
per1_clk
);
DEFINE_CLOCK
(
gpt1_clk
,
0
,
0
,
0
,
NULL
,
&
gpt1_clk1
,
&
per1_clk
);
DEFINE_CLOCK
(
gpt1_clk
,
0
,
NULL
,
0
,
NULL
,
&
gpt1_clk1
,
&
per1_clk
);
DEFINE_CLOCK
(
gpt2_clk
,
1
,
0
,
0
,
NULL
,
&
gpt2_clk1
,
&
per1_clk
);
DEFINE_CLOCK
(
gpt2_clk
,
1
,
NULL
,
0
,
NULL
,
&
gpt2_clk1
,
&
per1_clk
);
DEFINE_CLOCK
(
gpt3_clk
,
2
,
0
,
0
,
NULL
,
&
gpt3_clk1
,
&
per1_clk
);
DEFINE_CLOCK
(
gpt3_clk
,
2
,
NULL
,
0
,
NULL
,
&
gpt3_clk1
,
&
per1_clk
);
DEFINE_CLOCK
(
gpt4_clk
,
3
,
0
,
0
,
NULL
,
&
gpt4_clk1
,
&
per1_clk
);
DEFINE_CLOCK
(
gpt4_clk
,
3
,
NULL
,
0
,
NULL
,
&
gpt4_clk1
,
&
per1_clk
);
DEFINE_CLOCK
(
gpt5_clk
,
4
,
0
,
0
,
NULL
,
&
gpt5_clk1
,
&
per1_clk
);
DEFINE_CLOCK
(
gpt5_clk
,
4
,
NULL
,
0
,
NULL
,
&
gpt5_clk1
,
&
per1_clk
);
DEFINE_CLOCK
(
gpt6_clk
,
5
,
0
,
0
,
NULL
,
&
gpt6_clk1
,
&
per1_clk
);
DEFINE_CLOCK
(
gpt6_clk
,
5
,
NULL
,
0
,
NULL
,
&
gpt6_clk1
,
&
per1_clk
);
DEFINE_CLOCK
(
uart1_clk
,
0
,
0
,
0
,
NULL
,
&
uart1_clk1
,
&
per1_clk
);
DEFINE_CLOCK
(
uart1_clk
,
0
,
NULL
,
0
,
NULL
,
&
uart1_clk1
,
&
per1_clk
);
DEFINE_CLOCK
(
uart2_clk
,
1
,
0
,
0
,
NULL
,
&
uart2_clk1
,
&
per1_clk
);
DEFINE_CLOCK
(
uart2_clk
,
1
,
NULL
,
0
,
NULL
,
&
uart2_clk1
,
&
per1_clk
);
DEFINE_CLOCK
(
uart3_clk
,
2
,
0
,
0
,
NULL
,
&
uart3_clk1
,
&
per1_clk
);
DEFINE_CLOCK
(
uart3_clk
,
2
,
NULL
,
0
,
NULL
,
&
uart3_clk1
,
&
per1_clk
);
DEFINE_CLOCK
(
uart4_clk
,
3
,
0
,
0
,
NULL
,
&
uart4_clk1
,
&
per1_clk
);
DEFINE_CLOCK
(
uart4_clk
,
3
,
NULL
,
0
,
NULL
,
&
uart4_clk1
,
&
per1_clk
);
DEFINE_CLOCK
(
uart5_clk
,
4
,
0
,
0
,
NULL
,
&
uart5_clk1
,
&
per1_clk
);
DEFINE_CLOCK
(
uart5_clk
,
4
,
NULL
,
0
,
NULL
,
&
uart5_clk1
,
&
per1_clk
);
DEFINE_CLOCK
(
uart6_clk
,
5
,
0
,
0
,
NULL
,
&
uart6_clk1
,
&
per1_clk
);
DEFINE_CLOCK
(
uart6_clk
,
5
,
NULL
,
0
,
NULL
,
&
uart6_clk1
,
&
per1_clk
);
DEFINE_CLOCK1
(
lcdc_clk
,
0
,
0
,
0
,
parent
,
&
lcdc_clk1
,
&
per3_clk
);
DEFINE_CLOCK1
(
lcdc_clk
,
0
,
NULL
,
0
,
parent
,
&
lcdc_clk1
,
&
per3_clk
);
DEFINE_CLOCK1
(
csi_clk
,
0
,
0
,
0
,
parent
,
&
csi_clk1
,
&
per4_clk
);
DEFINE_CLOCK1
(
csi_clk
,
0
,
NULL
,
0
,
parent
,
&
csi_clk1
,
&
per4_clk
);
#define _REGISTER_CLOCK(d, n, c) \
#define _REGISTER_CLOCK(d, n, c) \
{ \
{ \
...
@@ -640,9 +640,9 @@ static struct clk_lookup lookups[] = {
...
@@ -640,9 +640,9 @@ static struct clk_lookup lookups[] = {
_REGISTER_CLOCK
(
"mxc-mmc.0"
,
NULL
,
sdhc1_clk
)
_REGISTER_CLOCK
(
"mxc-mmc.0"
,
NULL
,
sdhc1_clk
)
_REGISTER_CLOCK
(
"mxc-mmc.1"
,
NULL
,
sdhc2_clk
)
_REGISTER_CLOCK
(
"mxc-mmc.1"
,
NULL
,
sdhc2_clk
)
_REGISTER_CLOCK
(
"mxc-mmc.2"
,
NULL
,
sdhc3_clk
)
_REGISTER_CLOCK
(
"mxc-mmc.2"
,
NULL
,
sdhc3_clk
)
_REGISTER_CLOCK
(
"
spi_imx
.0"
,
NULL
,
cspi1_clk
)
_REGISTER_CLOCK
(
"
imx27-cspi
.0"
,
NULL
,
cspi1_clk
)
_REGISTER_CLOCK
(
"
spi_imx
.1"
,
NULL
,
cspi2_clk
)
_REGISTER_CLOCK
(
"
imx27-cspi
.1"
,
NULL
,
cspi2_clk
)
_REGISTER_CLOCK
(
"
spi_imx
.2"
,
NULL
,
cspi3_clk
)
_REGISTER_CLOCK
(
"
imx27-cspi
.2"
,
NULL
,
cspi3_clk
)
_REGISTER_CLOCK
(
"imx-fb.0"
,
NULL
,
lcdc_clk
)
_REGISTER_CLOCK
(
"imx-fb.0"
,
NULL
,
lcdc_clk
)
_REGISTER_CLOCK
(
"mx2-camera.0"
,
NULL
,
csi_clk
)
_REGISTER_CLOCK
(
"mx2-camera.0"
,
NULL
,
csi_clk
)
_REGISTER_CLOCK
(
"fsl-usb2-udc"
,
"usb"
,
usb_clk
)
_REGISTER_CLOCK
(
"fsl-usb2-udc"
,
"usb"
,
usb_clk
)
...
...
arch/arm/mach-imx/devices-imx1.h
View file @
c9ee46a9
...
@@ -9,10 +9,12 @@
...
@@ -9,10 +9,12 @@
#include <mach/mx1.h>
#include <mach/mx1.h>
#include <mach/devices-common.h>
#include <mach/devices-common.h>
#define imx1_add_i2c_imx(pdata) \
extern
const
struct
imx_imx_i2c_data
imx1_imx_i2c_data
__initconst
;
imx_add_imx_i2c(0, MX1_I2C_BASE_ADDR, SZ_4K, MX1_INT_I2C, pdata)
#define imx1_add_imx_i2c(pdata) \
imx_add_imx_i2c(&imx1_imx_i2c_data, pdata)
#define imx1_add_imx_uart0(pdata) \
extern
const
struct
imx_imx_uart_3irq_data
imx1_imx_uart_data
[]
__initconst
;
imx_add_imx_uart_3irq(0, MX1_UART1_BASE_ADDR, 0xd0, MX1_INT_UART1RX, MX1_INT_UART1TX, MX1_INT_UART1RTS, pdata)
#define imx1_add_imx_uart(id, pdata) \
#define imx1_add_imx_uart1(pdata) \
imx_add_imx_uart_3irq(&imx1_imx_uart_data[id], pdata)
imx_add_imx_uart_3irq(0, MX1_UART2_BASE_ADDR, 0xd0, MX1_INT_UART2RX, MX1_INT_UART2TX, MX1_INT_UART2RTS, pdata)
#define imx1_add_imx_uart0(pdata) imx1_add_imx_uart(0, pdata)
#define imx1_add_imx_uart1(pdata) imx1_add_imx_uart(1, pdata)
arch/arm/mach-imx/devices-imx21.h
View file @
c9ee46a9
...
@@ -9,22 +9,28 @@
...
@@ -9,22 +9,28 @@
#include <mach/mx21.h>
#include <mach/mx21.h>
#include <mach/devices-common.h>
#include <mach/devices-common.h>
#define imx21_add_i2c_imx(pdata) \
extern
const
struct
imx_imx_i2c_data
imx21_imx_i2c_data
__initconst
;
imx_add_imx_i2c(0, MX2x_I2C_BASE_ADDR, SZ_4K, MX2x_INT_I2C, pdata)
#define imx21_add_imx_i2c(pdata) \
imx_add_imx_i2c(&imx21_imx_i2c_data, pdata)
#define imx21_add_imx_uart0(pdata) \
extern
const
struct
imx_imx_ssi_data
imx21_imx_ssi_data
[]
__initconst
;
imx_add_imx_uart_1irq(0, MX21_UART1_BASE_ADDR, SZ_4K, MX21_INT_UART1, pdata)
#define imx21_add_imx_ssi(id, pdata) \
#define imx21_add_imx_uart1(pdata) \
imx_add_imx_ssi(&imx21_imx_ssi_data[id], pdata)
imx_add_imx_uart_1irq(1, MX21_UART2_BASE_ADDR, SZ_4K, MX21_INT_UART2, pdata)
#define imx21_add_imx_uart2(pdata) \
imx_add_imx_uart_1irq(2, MX21_UART3_BASE_ADDR, SZ_4K, MX21_INT_UART3, pdata)
#define imx21_add_imx_uart3(pdata) \
imx_add_imx_uart_1irq(3, MX21_UART4_BASE_ADDR, SZ_4K, MX21_INT_UART4, pdata)
extern
const
struct
imx_imx_uart_1irq_data
imx21_imx_uart_data
[]
__initconst
;
#define imx21_add_imx_uart(id, pdata) \
imx_add_imx_uart_1irq(&imx21_imx_uart_data[id], pdata)
#define imx21_add_imx_uart0(pdata) imx21_add_imx_uart(0, pdata)
#define imx21_add_imx_uart1(pdata) imx21_add_imx_uart(1, pdata)
#define imx21_add_imx_uart2(pdata) imx21_add_imx_uart(2, pdata)
#define imx21_add_imx_uart3(pdata) imx21_add_imx_uart(3, pdata)
extern
const
struct
imx_mxc_nand_data
imx21_mxc_nand_data
__initconst
;
#define imx21_add_mxc_nand(pdata) \
#define imx21_add_mxc_nand(pdata) \
imx_add_mxc_nand
_v1(MX21_NFC_BASE_ADDR, MX21_INT_NANDFC
, pdata)
imx_add_mxc_nand
(&imx21_mxc_nand_data
, pdata)
#define imx21_add_spi_imx0(pdata) \
extern
const
struct
imx_spi_imx_data
imx21_cspi_data
[]
__initconst
;
imx_add_spi_imx(0, MX21_CSPI1_BASE_ADDR, SZ_4K, MX21_INT_CSPI1, pdata)
#define imx21_add_cspi(id, pdata) \
#define imx21_add_spi_imx1(pdata) \
imx_add_spi_imx(&imx21_cspi_data[id], pdata)
imx_add_spi_imx(1, MX21_CSPI2_BASE_ADDR, SZ_4K, MX21_INT_CSPI2, pdata)
#define imx21_add_spi_imx0(pdata) imx21_add_cspi(0, pdata)
#define imx21_add_spi_imx1(pdata) imx21_add_cspi(1, pdata)
arch/arm/mach-imx/devices-imx27.h
View file @
c9ee46a9
...
@@ -9,30 +9,35 @@
...
@@ -9,30 +9,35 @@
#include <mach/mx27.h>
#include <mach/mx27.h>
#include <mach/devices-common.h>
#include <mach/devices-common.h>
#define imx27_add_i2c_imx0(pdata) \
extern
const
struct
imx_fec_data
imx27_fec_data
__initconst
;
imx_add_imx_i2c(0, MX27_I2C1_BASE_ADDR, SZ_4K, MX27_INT_I2C1, pdata)
#define imx27_add_fec(pdata) \
#define imx27_add_i2c_imx1(pdata) \
imx_add_fec(&imx27_fec_data, pdata)
imx_add_imx_i2c(1, MX27_I2C2_BASE_ADDR, SZ_4K, MX27_INT_I2C2, pdata)
#define imx27_add_imx_uart0(pdata) \
extern
const
struct
imx_imx_i2c_data
imx27_imx_i2c_data
[]
__initconst
;
imx_add_imx_uart_1irq(0, MX27_UART1_BASE_ADDR, SZ_4K, MX27_INT_UART1, pdata)
#define imx27_add_imx_i2c(id, pdata) \
#define imx27_add_imx_uart1(pdata) \
imx_add_imx_i2c(&imx27_imx_i2c_data[id], pdata)
imx_add_imx_uart_1irq(1, MX27_UART2_BASE_ADDR, SZ_4K, MX27_INT_UART2, pdata)
#define imx27_add_imx_uart2(pdata) \
imx_add_imx_uart_1irq(2, MX27_UART3_BASE_ADDR, SZ_4K, MX27_INT_UART3, pdata)
#define imx27_add_imx_uart3(pdata) \
imx_add_imx_uart_1irq(3, MX27_UART4_BASE_ADDR, SZ_4K, MX27_INT_UART4, pdata)
#define imx27_add_imx_uart4(pdata) \
imx_add_imx_uart_1irq(4, MX27_UART5_BASE_ADDR, SZ_4K, MX27_INT_UART5, pdata)
#define imx27_add_imx_uart5(pdata) \
imx_add_imx_uart_1irq(5, MX27_UART6_BASE_ADDR, SZ_4K, MX27_INT_UART6, pdata)
extern
const
struct
imx_imx_ssi_data
imx27_imx_ssi_data
[]
__initconst
;
#define imx27_add_imx_ssi(id, pdata) \
imx_add_imx_ssi(&imx27_imx_ssi_data[id], pdata)
extern
const
struct
imx_imx_uart_1irq_data
imx27_imx_uart_data
[]
__initconst
;
#define imx27_add_imx_uart(id, pdata) \
imx_add_imx_uart_1irq(&imx27_imx_uart_data[id], pdata)
#define imx27_add_imx_uart0(pdata) imx27_add_imx_uart(0, pdata)
#define imx27_add_imx_uart1(pdata) imx27_add_imx_uart(1, pdata)
#define imx27_add_imx_uart2(pdata) imx27_add_imx_uart(2, pdata)
#define imx27_add_imx_uart3(pdata) imx27_add_imx_uart(3, pdata)
#define imx27_add_imx_uart4(pdata) imx27_add_imx_uart(4, pdata)
#define imx27_add_imx_uart5(pdata) imx27_add_imx_uart(5, pdata)
extern
const
struct
imx_mxc_nand_data
imx27_mxc_nand_data
__initconst
;
#define imx27_add_mxc_nand(pdata) \
#define imx27_add_mxc_nand(pdata) \
imx_add_mxc_nand
_v1(MX27_NFC_BASE_ADDR, MX27_INT_NANDFC
, pdata)
imx_add_mxc_nand
(&imx27_mxc_nand_data
, pdata)
#define imx27_add_spi_imx0(pdata) \
extern
const
struct
imx_spi_imx_data
imx27_cspi_data
[]
__initconst
;
imx_add_spi_imx(0, MX27_CSPI1_BASE_ADDR, SZ_4K, MX27_INT_CSPI1, pdata)
#define imx27_add_cspi(id, pdata) \
#define imx27_add_spi_imx1(pdata) \
imx_add_spi_imx(&imx27_cspi_data[id], pdata)
imx_add_spi_imx(1, MX27_CSPI2_BASE_ADDR, SZ_4K, MX27_INT_CSPI2
, pdata)
#define imx27_add_spi_imx0(pdata) imx27_add_cspi(0
, pdata)
#define imx27_add_spi_imx
2(pdata) \
#define imx27_add_spi_imx
1(pdata) imx27_add_cspi(1, pdata)
imx_add_spi_imx(2, MX27_CSPI3_BASE_ADDR, SZ_4K, MX27_INT_CSPI3
, pdata)
#define imx27_add_spi_imx2(pdata) imx27_add_cspi(2
, pdata)
arch/arm/mach-imx/devices.c
View file @
c9ee46a9
...
@@ -314,27 +314,6 @@ struct platform_device mxc_fb_device = {
...
@@ -314,27 +314,6 @@ struct platform_device mxc_fb_device = {
},
},
};
};
#ifdef CONFIG_MACH_MX27
static
struct
resource
mxc_fec_resources
[]
=
{
{
.
start
=
MX27_FEC_BASE_ADDR
,
.
end
=
MX27_FEC_BASE_ADDR
+
SZ_4K
-
1
,
.
flags
=
IORESOURCE_MEM
,
},
{
.
start
=
MX27_INT_FEC
,
.
end
=
MX27_INT_FEC
,
.
flags
=
IORESOURCE_IRQ
,
},
};
struct
platform_device
mxc_fec_device
=
{
.
name
=
"fec"
,
.
id
=
0
,
.
num_resources
=
ARRAY_SIZE
(
mxc_fec_resources
),
.
resource
=
mxc_fec_resources
,
};
#endif
static
struct
resource
mxc_pwm_resources
[]
=
{
static
struct
resource
mxc_pwm_resources
[]
=
{
{
{
.
start
=
MX2x_PWM_BASE_ADDR
,
.
start
=
MX2x_PWM_BASE_ADDR
,
...
@@ -480,41 +459,6 @@ struct platform_device mxc_usbh2 = {
...
@@ -480,41 +459,6 @@ struct platform_device mxc_usbh2 = {
};
};
#endif
#endif
#define DEFINE_IMX_SSI_DMARES(_name, ssin, suffix) \
{ \
.name = _name, \
.start = MX2x_DMA_REQ_SSI ## ssin ## _ ## suffix, \
.end = MX2x_DMA_REQ_SSI ## ssin ## _ ## suffix, \
.flags = IORESOURCE_DMA, \
}
#define DEFINE_IMX_SSI_DEVICE(n, ssin, baseaddr, irq) \
static struct resource imx_ssi_resources ## n[] = { \
{ \
.start = MX2x_SSI ## ssin ## _BASE_ADDR, \
.end = MX2x_SSI ## ssin ## _BASE_ADDR + 0x6f, \
.flags = IORESOURCE_MEM, \
}, { \
.start = MX2x_INT_SSI1, \
.end = MX2x_INT_SSI1, \
.flags = IORESOURCE_IRQ, \
}, \
DEFINE_IMX_SSI_DMARES("tx0", ssin, TX0), \
DEFINE_IMX_SSI_DMARES("rx0", ssin, RX0), \
DEFINE_IMX_SSI_DMARES("tx1", ssin, TX1), \
DEFINE_IMX_SSI_DMARES("rx1", ssin, RX1), \
}; \
\
struct platform_device imx_ssi_device ## n = { \
.name = "imx-ssi", \
.id = n, \
.num_resources = ARRAY_SIZE(imx_ssi_resources ## n), \
.resource = imx_ssi_resources ## n, \
}
DEFINE_IMX_SSI_DEVICE
(
0
,
1
,
MX2x_SSI1_BASE_ADDR
,
MX2x_INT_SSI1
);
DEFINE_IMX_SSI_DEVICE
(
1
,
2
,
MX2x_SSI1_BASE_ADDR
,
MX2x_INT_SSI1
);
/* GPIO port description */
/* GPIO port description */
#define DEFINE_MXC_GPIO_PORT_IRQ(SOC, n, _irq) \
#define DEFINE_MXC_GPIO_PORT_IRQ(SOC, n, _irq) \
{ \
{ \
...
...
arch/arm/mach-imx/devices.h
View file @
c9ee46a9
...
@@ -16,7 +16,6 @@ extern struct platform_device mxc_gpt5;
...
@@ -16,7 +16,6 @@ extern struct platform_device mxc_gpt5;
extern
struct
platform_device
mxc_wdt
;
extern
struct
platform_device
mxc_wdt
;
extern
struct
platform_device
mxc_w1_master_device
;
extern
struct
platform_device
mxc_w1_master_device
;
extern
struct
platform_device
mxc_fb_device
;
extern
struct
platform_device
mxc_fb_device
;
extern
struct
platform_device
mxc_fec_device
;
extern
struct
platform_device
mxc_pwm_device
;
extern
struct
platform_device
mxc_pwm_device
;
extern
struct
platform_device
mxc_sdhc_device0
;
extern
struct
platform_device
mxc_sdhc_device0
;
extern
struct
platform_device
mxc_sdhc_device1
;
extern
struct
platform_device
mxc_sdhc_device1
;
...
@@ -26,7 +25,5 @@ extern struct platform_device mxc_otg_host;
...
@@ -26,7 +25,5 @@ extern struct platform_device mxc_otg_host;
extern
struct
platform_device
mxc_usbh1
;
extern
struct
platform_device
mxc_usbh1
;
extern
struct
platform_device
mxc_usbh2
;
extern
struct
platform_device
mxc_usbh2
;
extern
struct
platform_device
mx21_usbhc_device
;
extern
struct
platform_device
mx21_usbhc_device
;
extern
struct
platform_device
imx_ssi_device0
;
extern
struct
platform_device
imx_ssi_device1
;
extern
struct
platform_device
imx_kpp_device
;
extern
struct
platform_device
imx_kpp_device
;
#endif
#endif
arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
View file @
c9ee46a9
...
@@ -36,13 +36,12 @@
...
@@ -36,13 +36,12 @@
#include <mach/hardware.h>
#include <mach/hardware.h>
#include <mach/mmc.h>
#include <mach/mmc.h>
#include <mach/spi.h>
#include <mach/spi.h>
#include <mach/ssi.h>
#include <mach/audmux.h>
#include <mach/audmux.h>
#include "devices-imx27.h"
#include "devices-imx27.h"
#include "devices.h"
#include "devices.h"
static
int
eukrea_mbimx27_pins
[]
=
{
static
const
int
eukrea_mbimx27_pins
[]
__initconst
=
{
/* UART2 */
/* UART2 */
PE3_PF_UART2_CTS
,
PE3_PF_UART2_CTS
,
PE4_PF_UART2_RTS
,
PE4_PF_UART2_RTS
,
...
@@ -311,7 +310,8 @@ static struct imxmmc_platform_data sdhc_pdata = {
...
@@ -311,7 +310,8 @@ static struct imxmmc_platform_data sdhc_pdata = {
.
dat3_card_detect
=
1
,
.
dat3_card_detect
=
1
,
};
};
struct
imx_ssi_platform_data
eukrea_mbimx27_ssi_pdata
=
{
static
const
struct
imx_ssi_platform_data
eukrea_mbimx27_ssi_pdata
__initconst
=
{
.
flags
=
IMX_SSI_DMA
|
IMX_SSI_USE_I2S_SLAVE
,
.
flags
=
IMX_SSI_DMA
|
IMX_SSI_USE_I2S_SLAVE
,
};
};
...
@@ -357,7 +357,7 @@ void __init eukrea_mbimx27_baseboard_init(void)
...
@@ -357,7 +357,7 @@ void __init eukrea_mbimx27_baseboard_init(void)
i2c_register_board_info
(
0
,
eukrea_mbimx27_i2c_devices
,
i2c_register_board_info
(
0
,
eukrea_mbimx27_i2c_devices
,
ARRAY_SIZE
(
eukrea_mbimx27_i2c_devices
));
ARRAY_SIZE
(
eukrea_mbimx27_i2c_devices
));
mxc_register_device
(
&
imx_ssi_device
0
,
&
eukrea_mbimx27_ssi_pdata
);
imx27_add_imx_ssi
(
0
,
&
eukrea_mbimx27_ssi_pdata
);
#if defined(CONFIG_TOUCHSCREEN_ADS7846) \
#if defined(CONFIG_TOUCHSCREEN_ADS7846) \
|| defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
|| defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
...
...
arch/arm/mach-imx/mach-cpuimx27.c
View file @
c9ee46a9
...
@@ -46,7 +46,7 @@
...
@@ -46,7 +46,7 @@
#include "devices-imx27.h"
#include "devices-imx27.h"
#include "devices.h"
#include "devices.h"
static
int
eukrea_cpuimx27_pins
[]
=
{
static
const
int
eukrea_cpuimx27_pins
[]
__initconst
=
{
/* UART1 */
/* UART1 */
PE12_PF_UART1_TXD
,
PE12_PF_UART1_TXD
,
PE13_PF_UART1_RXD
,
PE13_PF_UART1_RXD
,
...
@@ -157,7 +157,6 @@ cpuimx27_nand_board_info __initconst = {
...
@@ -157,7 +157,6 @@ cpuimx27_nand_board_info __initconst = {
static
struct
platform_device
*
platform_devices
[]
__initdata
=
{
static
struct
platform_device
*
platform_devices
[]
__initdata
=
{
&
eukrea_cpuimx27_nor_mtd_device
,
&
eukrea_cpuimx27_nor_mtd_device
,
&
mxc_fec_device
,
&
mxc_wdt
,
&
mxc_wdt
,
&
mxc_w1_master_device
,
&
mxc_w1_master_device
,
};
};
...
@@ -259,8 +258,9 @@ static void __init eukrea_cpuimx27_init(void)
...
@@ -259,8 +258,9 @@ static void __init eukrea_cpuimx27_init(void)
i2c_register_board_info
(
0
,
eukrea_cpuimx27_i2c_devices
,
i2c_register_board_info
(
0
,
eukrea_cpuimx27_i2c_devices
,
ARRAY_SIZE
(
eukrea_cpuimx27_i2c_devices
));
ARRAY_SIZE
(
eukrea_cpuimx27_i2c_devices
));
imx27_add_i
2c_imx1
(
&
cpuimx27_i2c1_data
);
imx27_add_i
mx_i2c
(
1
,
&
cpuimx27_i2c1_data
);
imx27_add_fec
(
NULL
);
platform_add_devices
(
platform_devices
,
ARRAY_SIZE
(
platform_devices
));
platform_add_devices
(
platform_devices
,
ARRAY_SIZE
(
platform_devices
));
#if defined(CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2)
#if defined(CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2)
...
...
arch/arm/mach-imx/mach-imx27_visstrim_m10.c
0 → 100644
View file @
c9ee46a9
/*
* mach-imx27_visstrim_m10.c
*
* Copyright 2010 Javier Martin <javier.martin@vista-silicon.com>
*
* Based on mach-pcm038.c, mach-pca100.c, mach-mx27ads.c and others.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/platform_device.h>
#include <linux/mtd/physmap.h>
#include <linux/i2c.h>
#include <linux/i2c/pca953x.h>
#include <linux/gpio_keys.h>
#include <linux/input.h>
#include <linux/gpio.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <mach/common.h>
#include <mach/mmc.h>
#include <mach/iomux.h>
#include <mach/mxc_ehci.h>
#include "devices-imx27.h"
#include "devices.h"
#define OTG_PHY_CS_GPIO (GPIO_PORTF + 17)
#define SDHC1_IRQ IRQ_GPIOB(25)
static
const
int
visstrim_m10_pins
[]
__initconst
=
{
/* UART1 (console) */
PE12_PF_UART1_TXD
,
PE13_PF_UART1_RXD
,
PE14_PF_UART1_CTS
,
PE15_PF_UART1_RTS
,
/* FEC */
PD0_AIN_FEC_TXD0
,
PD1_AIN_FEC_TXD1
,
PD2_AIN_FEC_TXD2
,
PD3_AIN_FEC_TXD3
,
PD4_AOUT_FEC_RX_ER
,
PD5_AOUT_FEC_RXD1
,
PD6_AOUT_FEC_RXD2
,
PD7_AOUT_FEC_RXD3
,
PD8_AF_FEC_MDIO
,
PD9_AIN_FEC_MDC
,
PD10_AOUT_FEC_CRS
,
PD11_AOUT_FEC_TX_CLK
,
PD12_AOUT_FEC_RXD0
,
PD13_AOUT_FEC_RX_DV
,
PD14_AOUT_FEC_RX_CLK
,
PD15_AOUT_FEC_COL
,
PD16_AIN_FEC_TX_ER
,
PF23_AIN_FEC_TX_EN
,
/* SDHC1 */
PE18_PF_SD1_D0
,
PE19_PF_SD1_D1
,
PE20_PF_SD1_D2
,
PE21_PF_SD1_D3
,
PE22_PF_SD1_CMD
,
PE23_PF_SD1_CLK
,
/* Both I2Cs */
PD17_PF_I2C_DATA
,
PD18_PF_I2C_CLK
,
PC5_PF_I2C2_SDA
,
PC6_PF_I2C2_SCL
,
/* USB OTG */
OTG_PHY_CS_GPIO
|
GPIO_GPIO
|
GPIO_OUT
,
PC9_PF_USBOTG_DATA0
,
PC11_PF_USBOTG_DATA1
,
PC10_PF_USBOTG_DATA2
,
PC13_PF_USBOTG_DATA3
,
PC12_PF_USBOTG_DATA4
,
PC7_PF_USBOTG_DATA5
,
PC8_PF_USBOTG_DATA6
,
PE25_PF_USBOTG_DATA7
,
PE24_PF_USBOTG_CLK
,
PE2_PF_USBOTG_DIR
,
PE0_PF_USBOTG_NXT
,
PE1_PF_USBOTG_STP
,
PB23_PF_USB_PWR
,
PB24_PF_USB_OC
,
};
/* GPIOs used as events for applications */
static
struct
gpio_keys_button
visstrim_gpio_keys
[]
=
{
{
.
type
=
EV_KEY
,
.
code
=
KEY_RESTART
,
.
gpio
=
(
GPIO_PORTC
+
15
),
.
desc
=
"Default config"
,
.
active_low
=
0
,
.
wakeup
=
1
,
},
{
.
type
=
EV_KEY
,
.
code
=
KEY_RECORD
,
.
gpio
=
(
GPIO_PORTF
+
14
),
.
desc
=
"Record"
,
.
active_low
=
0
,
.
wakeup
=
1
,
},
{
.
type
=
EV_KEY
,
.
code
=
KEY_STOP
,
.
gpio
=
(
GPIO_PORTF
+
13
),
.
desc
=
"Stop"
,
.
active_low
=
0
,
.
wakeup
=
1
,
}
};
static
struct
gpio_keys_platform_data
visstrim_gpio_keys_platform_data
=
{
.
buttons
=
visstrim_gpio_keys
,
.
nbuttons
=
ARRAY_SIZE
(
visstrim_gpio_keys
),
};
static
struct
platform_device
visstrim_gpio_keys_device
=
{
.
name
=
"gpio-keys"
,
.
id
=
-
1
,
.
dev
=
{
.
platform_data
=
&
visstrim_gpio_keys_platform_data
,
},
};
/* Visstrim_SM10 has a microSD slot connected to sdhc1 */
static
int
visstrim_m10_sdhc1_init
(
struct
device
*
dev
,
irq_handler_t
detect_irq
,
void
*
data
)
{
int
ret
;
ret
=
request_irq
(
SDHC1_IRQ
,
detect_irq
,
IRQF_TRIGGER_FALLING
,
"mmc-detect"
,
data
);
return
ret
;
}
static
void
visstrim_m10_sdhc1_exit
(
struct
device
*
dev
,
void
*
data
)
{
free_irq
(
SDHC1_IRQ
,
data
);
}
static
struct
imxmmc_platform_data
visstrim_m10_sdhc_pdata
=
{
.
init
=
visstrim_m10_sdhc1_init
,
.
exit
=
visstrim_m10_sdhc1_exit
,
};
/* Visstrim_SM10 NOR flash */
static
struct
physmap_flash_data
visstrim_m10_flash_data
=
{
.
width
=
2
,
};
static
struct
resource
visstrim_m10_flash_resource
=
{
.
start
=
0xc0000000
,
.
end
=
0xc0000000
+
SZ_64M
-
1
,
.
flags
=
IORESOURCE_MEM
,
};
static
struct
platform_device
visstrim_m10_nor_mtd_device
=
{
.
name
=
"physmap-flash"
,
.
id
=
0
,
.
dev
=
{
.
platform_data
=
&
visstrim_m10_flash_data
,
},
.
num_resources
=
1
,
.
resource
=
&
visstrim_m10_flash_resource
,
};
static
struct
platform_device
*
platform_devices
[]
__initdata
=
{
&
visstrim_gpio_keys_device
,
&
visstrim_m10_nor_mtd_device
,
};
/* Visstrim_M10 uses UART0 as console */
static
const
struct
imxuart_platform_data
uart_pdata
__initconst
=
{
.
flags
=
IMXUART_HAVE_RTSCTS
,
};
/* I2C */
static
const
struct
imxi2c_platform_data
visstrim_m10_i2c_data
__initconst
=
{
.
bitrate
=
100000
,
};
static
struct
pca953x_platform_data
visstrim_m10_pca9555_pdata
=
{
.
gpio_base
=
240
,
/* After MX27 internal GPIOs */
.
invert
=
0
,
};
static
struct
i2c_board_info
visstrim_m10_i2c_devices
[]
=
{
{
I2C_BOARD_INFO
(
"pca9555"
,
0x20
),
.
platform_data
=
&
visstrim_m10_pca9555_pdata
,
},
};
/* USB OTG */
static
int
otg_phy_init
(
struct
platform_device
*
pdev
)
{
gpio_set_value
(
OTG_PHY_CS_GPIO
,
0
);
return
0
;
}
static
struct
mxc_usbh_platform_data
visstrim_m10_usbotg_pdata
=
{
.
init
=
otg_phy_init
,
.
portsc
=
MXC_EHCI_MODE_ULPI
|
MXC_EHCI_UTMI_8BIT
,
.
flags
=
MXC_EHCI_POWER_PINS_ENABLED
,
};
static
void
__init
visstrim_m10_board_init
(
void
)
{
int
ret
;
ret
=
mxc_gpio_setup_multiple_pins
(
visstrim_m10_pins
,
ARRAY_SIZE
(
visstrim_m10_pins
),
"VISSTRIM_M10"
);
if
(
ret
)
pr_err
(
"Failed to setup pins (%d)
\n
"
,
ret
);
imx27_add_imx_uart0
(
&
uart_pdata
);
i2c_register_board_info
(
0
,
visstrim_m10_i2c_devices
,
ARRAY_SIZE
(
visstrim_m10_i2c_devices
));
imx27_add_imx_i2c
(
0
,
&
visstrim_m10_i2c_data
);
imx27_add_imx_i2c
(
1
,
&
visstrim_m10_i2c_data
);
mxc_register_device
(
&
mxc_sdhc_device0
,
&
visstrim_m10_sdhc_pdata
);
mxc_register_device
(
&
mxc_otg_host
,
&
visstrim_m10_usbotg_pdata
);
imx27_add_fec
(
NULL
);
platform_add_devices
(
platform_devices
,
ARRAY_SIZE
(
platform_devices
));
}
static
void
__init
visstrim_m10_timer_init
(
void
)
{
mx27_clocks_init
((
unsigned
long
)
25000000
);
}
static
struct
sys_timer
visstrim_m10_timer
=
{
.
init
=
visstrim_m10_timer_init
,
};
MACHINE_START
(
IMX27_VISSTRIM_M10
,
"Vista Silicon Visstrim_M10"
)
.
phys_io
=
MX27_AIPI_BASE_ADDR
,
.
io_pg_offst
=
((
MX27_AIPI_BASE_ADDR_VIRT
)
>>
18
)
&
0xfffc
,
.
boot_params
=
MX27_PHYS_OFFSET
+
0x100
,
.
map_io
=
mx27_map_io
,
.
init_irq
=
mx27_init_irq
,
.
init_machine
=
visstrim_m10_board_init
,
.
timer
=
&
visstrim_m10_timer
,
MACHINE_END
arch/arm/mach-imx/mach-imx27lite.c
View file @
c9ee46a9
...
@@ -27,7 +27,7 @@
...
@@ -27,7 +27,7 @@
#include "devices-imx27.h"
#include "devices-imx27.h"
#include "devices.h"
#include "devices.h"
static
unsigned
int
mx27lite_pins
[]
=
{
static
const
int
mx27lite_pins
[]
__initconst
=
{
/* UART1 */
/* UART1 */
PE12_PF_UART1_TXD
,
PE12_PF_UART1_TXD
,
PE13_PF_UART1_RXD
,
PE13_PF_UART1_RXD
,
...
@@ -58,16 +58,12 @@ static const struct imxuart_platform_data uart_pdata __initconst = {
...
@@ -58,16 +58,12 @@ static const struct imxuart_platform_data uart_pdata __initconst = {
.
flags
=
IMXUART_HAVE_RTSCTS
,
.
flags
=
IMXUART_HAVE_RTSCTS
,
};
};
static
struct
platform_device
*
platform_devices
[]
__initdata
=
{
&
mxc_fec_device
,
};
static
void
__init
mx27lite_init
(
void
)
static
void
__init
mx27lite_init
(
void
)
{
{
mxc_gpio_setup_multiple_pins
(
mx27lite_pins
,
ARRAY_SIZE
(
mx27lite_pins
),
mxc_gpio_setup_multiple_pins
(
mx27lite_pins
,
ARRAY_SIZE
(
mx27lite_pins
),
"imx27lite"
);
"imx27lite"
);
imx27_add_imx_uart0
(
&
uart_pdata
);
imx27_add_imx_uart0
(
&
uart_pdata
);
platform_add_devices
(
platform_devices
,
ARRAY_SIZE
(
platform_devices
)
);
imx27_add_fec
(
NULL
);
}
}
static
void
__init
mx27lite_timer_init
(
void
)
static
void
__init
mx27lite_timer_init
(
void
)
...
...
arch/arm/mach-imx/mach-mx1ads.c
View file @
c9ee46a9
...
@@ -32,7 +32,7 @@
...
@@ -32,7 +32,7 @@
#include "devices-imx1.h"
#include "devices-imx1.h"
#include "devices.h"
#include "devices.h"
static
int
mx1ads_pins
[]
=
{
static
const
int
mx1ads_pins
[]
__initconst
=
{
/* UART1 */
/* UART1 */
PC9_PF_UART1_CTS
,
PC9_PF_UART1_CTS
,
PC10_PF_UART1_RTS
,
PC10_PF_UART1_RTS
,
...
@@ -131,7 +131,7 @@ static void __init mx1ads_init(void)
...
@@ -131,7 +131,7 @@ static void __init mx1ads_init(void)
i2c_register_board_info
(
0
,
mx1ads_i2c_devices
,
i2c_register_board_info
(
0
,
mx1ads_i2c_devices
,
ARRAY_SIZE
(
mx1ads_i2c_devices
));
ARRAY_SIZE
(
mx1ads_i2c_devices
));
imx1_add_i
2c_imx
(
&
mx1ads_i2c_data
);
imx1_add_i
mx_i2c
(
&
mx1ads_i2c_data
);
}
}
static
void
__init
mx1ads_timer_init
(
void
)
static
void
__init
mx1ads_timer_init
(
void
)
...
...
arch/arm/mach-imx/mach-mx21ads.c
View file @
c9ee46a9
...
@@ -67,7 +67,7 @@
...
@@ -67,7 +67,7 @@
#define MX21ADS_IO_LED4_ON 0x4000
#define MX21ADS_IO_LED4_ON 0x4000
#define MX21ADS_IO_LED3_ON 0x8000
#define MX21ADS_IO_LED3_ON 0x8000
static
unsigned
int
mx21ads_pins
[]
=
{
static
const
int
mx21ads_pins
[]
__initconst
=
{
/* CS8900A */
/* CS8900A */
(
GPIO_PORTE
|
GPIO_GPIO
|
GPIO_IN
|
11
),
(
GPIO_PORTE
|
GPIO_GPIO
|
GPIO_IN
|
11
),
...
...
arch/arm/mach-imx/mach-mx27_3ds.c
View file @
c9ee46a9
...
@@ -33,7 +33,7 @@
...
@@ -33,7 +33,7 @@
#include "devices-imx27.h"
#include "devices-imx27.h"
#include "devices.h"
#include "devices.h"
static
unsigned
int
mx27pdk_pins
[]
=
{
static
const
int
mx27pdk_pins
[]
__initconst
=
{
/* UART1 */
/* UART1 */
PE12_PF_UART1_TXD
,
PE12_PF_UART1_TXD
,
PE13_PF_UART1_RXD
,
PE13_PF_UART1_RXD
,
...
@@ -64,10 +64,6 @@ static const struct imxuart_platform_data uart_pdata __initconst = {
...
@@ -64,10 +64,6 @@ static const struct imxuart_platform_data uart_pdata __initconst = {
.
flags
=
IMXUART_HAVE_RTSCTS
,
.
flags
=
IMXUART_HAVE_RTSCTS
,
};
};
static
struct
platform_device
*
platform_devices
[]
__initdata
=
{
&
mxc_fec_device
,
};
/*
/*
* Matrix keyboard
* Matrix keyboard
*/
*/
...
@@ -94,7 +90,7 @@ static void __init mx27pdk_init(void)
...
@@ -94,7 +90,7 @@ static void __init mx27pdk_init(void)
mxc_gpio_setup_multiple_pins
(
mx27pdk_pins
,
ARRAY_SIZE
(
mx27pdk_pins
),
mxc_gpio_setup_multiple_pins
(
mx27pdk_pins
,
ARRAY_SIZE
(
mx27pdk_pins
),
"mx27pdk"
);
"mx27pdk"
);
imx27_add_imx_uart0
(
&
uart_pdata
);
imx27_add_imx_uart0
(
&
uart_pdata
);
platform_add_devices
(
platform_devices
,
ARRAY_SIZE
(
platform_devices
)
);
imx27_add_fec
(
NULL
);
mxc_register_device
(
&
imx_kpp_device
,
&
mx27_3ds_keymap_data
);
mxc_register_device
(
&
imx_kpp_device
,
&
mx27_3ds_keymap_data
);
}
}
...
...
arch/arm/mach-imx/mach-mx27ads.c
View file @
c9ee46a9
...
@@ -66,7 +66,7 @@
...
@@ -66,7 +66,7 @@
/* to determine the correct external crystal reference */
/* to determine the correct external crystal reference */
#define CKIH_27MHZ_BIT_SET (1 << 3)
#define CKIH_27MHZ_BIT_SET (1 << 3)
static
unsigned
int
mx27ads_pins
[]
=
{
static
const
int
mx27ads_pins
[]
__initconst
=
{
/* UART0 */
/* UART0 */
PE12_PF_UART1_TXD
,
PE12_PF_UART1_TXD
,
PE13_PF_UART1_RXD
,
PE13_PF_UART1_RXD
,
...
@@ -284,7 +284,6 @@ static struct imxmmc_platform_data sdhc2_pdata = {
...
@@ -284,7 +284,6 @@ static struct imxmmc_platform_data sdhc2_pdata = {
static
struct
platform_device
*
platform_devices
[]
__initdata
=
{
static
struct
platform_device
*
platform_devices
[]
__initdata
=
{
&
mx27ads_nor_mtd_device
,
&
mx27ads_nor_mtd_device
,
&
mxc_fec_device
,
&
mxc_w1_master_device
,
&
mxc_w1_master_device
,
};
};
...
@@ -308,11 +307,12 @@ static void __init mx27ads_board_init(void)
...
@@ -308,11 +307,12 @@ static void __init mx27ads_board_init(void)
/* only the i2c master 1 is used on this CPU card */
/* only the i2c master 1 is used on this CPU card */
i2c_register_board_info
(
1
,
mx27ads_i2c_devices
,
i2c_register_board_info
(
1
,
mx27ads_i2c_devices
,
ARRAY_SIZE
(
mx27ads_i2c_devices
));
ARRAY_SIZE
(
mx27ads_i2c_devices
));
imx27_add_i
2c_imx1
(
&
mx27ads_i2c1_data
);
imx27_add_i
mx_i2c
(
1
,
&
mx27ads_i2c1_data
);
mxc_register_device
(
&
mxc_fb_device
,
&
mx27ads_fb_data
);
mxc_register_device
(
&
mxc_fb_device
,
&
mx27ads_fb_data
);
mxc_register_device
(
&
mxc_sdhc_device0
,
&
sdhc1_pdata
);
mxc_register_device
(
&
mxc_sdhc_device0
,
&
sdhc1_pdata
);
mxc_register_device
(
&
mxc_sdhc_device1
,
&
sdhc2_pdata
);
mxc_register_device
(
&
mxc_sdhc_device1
,
&
sdhc2_pdata
);
imx27_add_fec
(
NULL
);
platform_add_devices
(
platform_devices
,
ARRAY_SIZE
(
platform_devices
));
platform_add_devices
(
platform_devices
,
ARRAY_SIZE
(
platform_devices
));
}
}
...
...
arch/arm/mach-imx/mach-mxt_td60.c
View file @
c9ee46a9
...
@@ -37,7 +37,7 @@
...
@@ -37,7 +37,7 @@
#include "devices-imx27.h"
#include "devices-imx27.h"
#include "devices.h"
#include "devices.h"
static
unsigned
int
mxt_td60_pins
[]
__initdata
=
{
static
const
int
mxt_td60_pins
[]
__initconst
=
{
/* UART0 */
/* UART0 */
PE12_PF_UART1_TXD
,
PE12_PF_UART1_TXD
,
PE13_PF_UART1_RXD
,
PE13_PF_UART1_RXD
,
...
@@ -231,10 +231,6 @@ static struct imxmmc_platform_data sdhc1_pdata = {
...
@@ -231,10 +231,6 @@ static struct imxmmc_platform_data sdhc1_pdata = {
.
exit
=
mxt_td60_sdhc1_exit
,
.
exit
=
mxt_td60_sdhc1_exit
,
};
};
static
struct
platform_device
*
platform_devices
[]
__initdata
=
{
&
mxc_fec_device
,
};
static
const
struct
imxuart_platform_data
uart_pdata
__initconst
=
{
static
const
struct
imxuart_platform_data
uart_pdata
__initconst
=
{
.
flags
=
IMXUART_HAVE_RTSCTS
,
.
flags
=
IMXUART_HAVE_RTSCTS
,
};
};
...
@@ -255,12 +251,11 @@ static void __init mxt_td60_board_init(void)
...
@@ -255,12 +251,11 @@ static void __init mxt_td60_board_init(void)
i2c_register_board_info
(
1
,
mxt_td60_i2c2_devices
,
i2c_register_board_info
(
1
,
mxt_td60_i2c2_devices
,
ARRAY_SIZE
(
mxt_td60_i2c2_devices
));
ARRAY_SIZE
(
mxt_td60_i2c2_devices
));
imx27_add_i
2c_imx0
(
&
mxt_td60_i2c0_data
);
imx27_add_i
mx_i2c
(
0
,
&
mxt_td60_i2c0_data
);
imx27_add_i
2c_imx1
(
&
mxt_td60_i2c1_data
);
imx27_add_i
mx_i2c
(
1
,
&
mxt_td60_i2c1_data
);
mxc_register_device
(
&
mxc_fb_device
,
&
mxt_td60_fb_data
);
mxc_register_device
(
&
mxc_fb_device
,
&
mxt_td60_fb_data
);
mxc_register_device
(
&
mxc_sdhc_device0
,
&
sdhc1_pdata
);
mxc_register_device
(
&
mxc_sdhc_device0
,
&
sdhc1_pdata
);
imx27_add_fec
(
NULL
);
platform_add_devices
(
platform_devices
,
ARRAY_SIZE
(
platform_devices
));
}
}
static
void
__init
mxt_td60_timer_init
(
void
)
static
void
__init
mxt_td60_timer_init
(
void
)
...
...
arch/arm/mach-imx/mach-pca100.c
View file @
c9ee46a9
...
@@ -38,7 +38,6 @@
...
@@ -38,7 +38,6 @@
#include <mach/iomux-mx27.h>
#include <mach/iomux-mx27.h>
#include <asm/mach/time.h>
#include <asm/mach/time.h>
#include <mach/audmux.h>
#include <mach/audmux.h>
#include <mach/ssi.h>
#include <mach/mxc_nand.h>
#include <mach/mxc_nand.h>
#include <mach/irqs.h>
#include <mach/irqs.h>
#include <mach/mmc.h>
#include <mach/mmc.h>
...
@@ -55,7 +54,7 @@
...
@@ -55,7 +54,7 @@
#define SPI1_SS1 (GPIO_PORTD + 27)
#define SPI1_SS1 (GPIO_PORTD + 27)
#define SD2_CD (GPIO_PORTC + 29)
#define SD2_CD (GPIO_PORTC + 29)
static
int
pca100_pins
[]
=
{
static
const
int
pca100_pins
[]
__initconst
=
{
/* UART1 */
/* UART1 */
PE12_PF_UART1_TXD
,
PE12_PF_UART1_TXD
,
PE13_PF_UART1_RXD
,
PE13_PF_UART1_RXD
,
...
@@ -174,7 +173,6 @@ pca100_nand_board_info __initconst = {
...
@@ -174,7 +173,6 @@ pca100_nand_board_info __initconst = {
static
struct
platform_device
*
platform_devices
[]
__initdata
=
{
static
struct
platform_device
*
platform_devices
[]
__initdata
=
{
&
mxc_w1_master_device
,
&
mxc_w1_master_device
,
&
mxc_fec_device
,
&
mxc_wdt
,
&
mxc_wdt
,
};
};
...
@@ -193,11 +191,9 @@ static struct i2c_board_info pca100_i2c_devices[] = {
...
@@ -193,11 +191,9 @@ static struct i2c_board_info pca100_i2c_devices[] = {
I2C_BOARD_INFO
(
"at24"
,
0x52
),
/* E0=0, E1=1, E2=0 */
I2C_BOARD_INFO
(
"at24"
,
0x52
),
/* E0=0, E1=1, E2=0 */
.
platform_data
=
&
board_eeprom
,
.
platform_data
=
&
board_eeprom
,
},
{
},
{
I2C_BOARD_INFO
(
"rtc-pcf8563"
,
0x51
),
I2C_BOARD_INFO
(
"pcf8563"
,
0x51
),
.
type
=
"pcf8563"
},
{
},
{
I2C_BOARD_INFO
(
"lm75"
,
0x4a
),
I2C_BOARD_INFO
(
"lm75"
,
0x4a
),
.
type
=
"lm75"
}
}
};
};
...
@@ -252,7 +248,7 @@ static void pca100_ac97_cold_reset(struct snd_ac97 *ac97)
...
@@ -252,7 +248,7 @@ static void pca100_ac97_cold_reset(struct snd_ac97 *ac97)
msleep
(
2
);
msleep
(
2
);
}
}
static
struct
imx_ssi_platform_data
pca100_ssi_pdata
=
{
static
const
struct
imx_ssi_platform_data
pca100_ssi_pdata
__initconst
=
{
.
ac97_reset
=
pca100_ac97_cold_reset
,
.
ac97_reset
=
pca100_ac97_cold_reset
,
.
ac97_warm_reset
=
pca100_ac97_warm_reset
,
.
ac97_warm_reset
=
pca100_ac97_warm_reset
,
.
flags
=
IMX_SSI_USE_AC97
,
.
flags
=
IMX_SSI_USE_AC97
,
...
@@ -389,7 +385,7 @@ static void __init pca100_init(void)
...
@@ -389,7 +385,7 @@ static void __init pca100_init(void)
if
(
ret
)
if
(
ret
)
printk
(
KERN_ERR
"pca100: Failed to setup pins (%d)
\n
"
,
ret
);
printk
(
KERN_ERR
"pca100: Failed to setup pins (%d)
\n
"
,
ret
);
mxc_register_device
(
&
imx_ssi_device
0
,
&
pca100_ssi_pdata
);
imx27_add_imx_ssi
(
0
,
&
pca100_ssi_pdata
);
imx27_add_imx_uart0
(
&
uart_pdata
);
imx27_add_imx_uart0
(
&
uart_pdata
);
...
@@ -401,7 +397,7 @@ static void __init pca100_init(void)
...
@@ -401,7 +397,7 @@ static void __init pca100_init(void)
i2c_register_board_info
(
1
,
pca100_i2c_devices
,
i2c_register_board_info
(
1
,
pca100_i2c_devices
,
ARRAY_SIZE
(
pca100_i2c_devices
));
ARRAY_SIZE
(
pca100_i2c_devices
));
imx27_add_i
2c_imx1
(
&
pca100_i2c1_data
);
imx27_add_i
mx_i2c
(
1
,
&
pca100_i2c1_data
);
#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
mxc_gpio_mode
(
GPIO_PORTD
|
28
|
GPIO_GPIO
|
GPIO_IN
);
mxc_gpio_mode
(
GPIO_PORTD
|
28
|
GPIO_GPIO
|
GPIO_IN
);
...
@@ -436,6 +432,7 @@ static void __init pca100_init(void)
...
@@ -436,6 +432,7 @@ static void __init pca100_init(void)
mxc_register_device
(
&
mxc_fb_device
,
&
pca100_fb_data
);
mxc_register_device
(
&
mxc_fb_device
,
&
pca100_fb_data
);
imx27_add_fec
(
NULL
);
platform_add_devices
(
platform_devices
,
ARRAY_SIZE
(
platform_devices
));
platform_add_devices
(
platform_devices
,
ARRAY_SIZE
(
platform_devices
));
}
}
...
...
arch/arm/mach-imx/mach-pcm038.c
View file @
c9ee46a9
...
@@ -43,7 +43,7 @@
...
@@ -43,7 +43,7 @@
#include "devices-imx27.h"
#include "devices-imx27.h"
#include "devices.h"
#include "devices.h"
static
int
pcm038_pins
[]
=
{
static
const
int
pcm038_pins
[]
__initconst
=
{
/* UART1 */
/* UART1 */
PE12_PF_UART1_TXD
,
PE12_PF_UART1_TXD
,
PE13_PF_UART1_RXD
,
PE13_PF_UART1_RXD
,
...
@@ -173,7 +173,6 @@ pcm038_nand_board_info __initconst = {
...
@@ -173,7 +173,6 @@ pcm038_nand_board_info __initconst = {
static
struct
platform_device
*
platform_devices
[]
__initdata
=
{
static
struct
platform_device
*
platform_devices
[]
__initdata
=
{
&
pcm038_nor_mtd_device
,
&
pcm038_nor_mtd_device
,
&
mxc_w1_master_device
,
&
mxc_w1_master_device
,
&
mxc_fec_device
,
&
pcm038_sram_mtd_device
,
&
pcm038_sram_mtd_device
,
&
mxc_wdt
,
&
mxc_wdt
,
};
};
...
@@ -257,7 +256,7 @@ static struct regulator_init_data cam_data = {
...
@@ -257,7 +256,7 @@ static struct regulator_init_data cam_data = {
.
consumer_supplies
=
cam_consumers
,
.
consumer_supplies
=
cam_consumers
,
};
};
struct
mc13783_regulator_init_data
pcm038_regulators
[]
=
{
st
atic
st
ruct
mc13783_regulator_init_data
pcm038_regulators
[]
=
{
{
{
.
id
=
MC13783_REGU_VCAM
,
.
id
=
MC13783_REGU_VCAM
,
.
init_data
=
&
cam_data
,
.
init_data
=
&
cam_data
,
...
@@ -309,7 +308,7 @@ static void __init pcm038_init(void)
...
@@ -309,7 +308,7 @@ static void __init pcm038_init(void)
i2c_register_board_info
(
1
,
pcm038_i2c_devices
,
i2c_register_board_info
(
1
,
pcm038_i2c_devices
,
ARRAY_SIZE
(
pcm038_i2c_devices
));
ARRAY_SIZE
(
pcm038_i2c_devices
));
imx27_add_i
2c_imx1
(
&
pcm038_i2c1_data
);
imx27_add_i
mx_i2c
(
1
,
&
pcm038_i2c1_data
);
/* PE18 for user-LED D40 */
/* PE18 for user-LED D40 */
mxc_gpio_mode
(
GPIO_PORTE
|
18
|
GPIO_GPIO
|
GPIO_OUT
);
mxc_gpio_mode
(
GPIO_PORTE
|
18
|
GPIO_GPIO
|
GPIO_OUT
);
...
@@ -325,6 +324,7 @@ static void __init pcm038_init(void)
...
@@ -325,6 +324,7 @@ static void __init pcm038_init(void)
mxc_register_device
(
&
mxc_usbh2
,
&
usbh2_pdata
);
mxc_register_device
(
&
mxc_usbh2
,
&
usbh2_pdata
);
imx27_add_fec
(
NULL
);
platform_add_devices
(
platform_devices
,
ARRAY_SIZE
(
platform_devices
));
platform_add_devices
(
platform_devices
,
ARRAY_SIZE
(
platform_devices
));
#ifdef CONFIG_MACH_PCM970_BASEBOARD
#ifdef CONFIG_MACH_PCM970_BASEBOARD
...
...
arch/arm/mach-imx/mach-scb9328.c
View file @
c9ee46a9
...
@@ -95,7 +95,7 @@ static struct platform_device dm9000x_device = {
...
@@ -95,7 +95,7 @@ static struct platform_device dm9000x_device = {
}
}
};
};
static
int
mxc_uart1_pins
[]
=
{
static
const
int
mxc_uart1_pins
[]
=
{
PC9_PF_UART1_CTS
,
PC9_PF_UART1_CTS
,
PC10_PF_UART1_RTS
,
PC10_PF_UART1_RTS
,
PC11_PF_UART1_TXD
,
PC11_PF_UART1_TXD
,
...
...
arch/arm/mach-imx/pcm970-baseboard.c
View file @
c9ee46a9
...
@@ -31,7 +31,7 @@
...
@@ -31,7 +31,7 @@
#include "devices.h"
#include "devices.h"
static
int
pcm970_pins
[]
=
{
static
const
int
pcm970_pins
[]
__initconst
=
{
/* SDHC */
/* SDHC */
PB4_PF_SD2_D0
,
PB4_PF_SD2_D0
,
PB5_PF_SD2_D1
,
PB5_PF_SD2_D1
,
...
@@ -200,7 +200,7 @@ static struct resource pcm970_sja1000_resources[] = {
...
@@ -200,7 +200,7 @@ static struct resource pcm970_sja1000_resources[] = {
},
},
};
};
struct
sja1000_platform_data
pcm970_sja1000_platform_data
=
{
st
atic
st
ruct
sja1000_platform_data
pcm970_sja1000_platform_data
=
{
.
osc_freq
=
16000000
,
.
osc_freq
=
16000000
,
.
ocr
=
OCR_TX1_PULLDOWN
|
OCR_TX0_PUSHPULL
,
.
ocr
=
OCR_TX1_PULLDOWN
|
OCR_TX0_PUSHPULL
,
.
cdr
=
CDR_CBP
,
.
cdr
=
CDR_CBP
,
...
...
arch/arm/mach-mx25/Kconfig
View file @
c9ee46a9
...
@@ -12,6 +12,8 @@ config MACH_EUKREA_CPUIMX25
...
@@ -12,6 +12,8 @@ config MACH_EUKREA_CPUIMX25
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_FLEXCAN
select IMX_HAVE_PLATFORM_ESDHC
select MXC_ULPI if USB_ULPI
select MXC_ULPI if USB_ULPI
choice
choice
...
@@ -20,8 +22,8 @@ choice
...
@@ -20,8 +22,8 @@ choice
default MACH_EUKREA_MBIMXSD25_BASEBOARD
default MACH_EUKREA_MBIMXSD25_BASEBOARD
config MACH_EUKREA_MBIMXSD25_BASEBOARD
config MACH_EUKREA_MBIMXSD25_BASEBOARD
prompt
"Eukrea MBIMXSD development board"
bool
"Eukrea MBIMXSD development board"
bool
select IMX_HAVE_PLATFORM_IMX_SSI
help
help
This adds board specific devices that can be found on Eukrea's
This adds board specific devices that can be found on Eukrea's
MBIMXSD evaluation board.
MBIMXSD evaluation board.
...
...
arch/arm/mach-mx25/clock.c
View file @
c9ee46a9
...
@@ -139,6 +139,16 @@ static unsigned long get_rate_lcdc(struct clk *clk)
...
@@ -139,6 +139,16 @@ static unsigned long get_rate_lcdc(struct clk *clk)
return
get_rate_per
(
7
);
return
get_rate_per
(
7
);
}
}
static
unsigned
long
get_rate_esdhc1
(
struct
clk
*
clk
)
{
return
get_rate_per
(
3
);
}
static
unsigned
long
get_rate_esdhc2
(
struct
clk
*
clk
)
{
return
get_rate_per
(
4
);
}
static
unsigned
long
get_rate_csi
(
struct
clk
*
clk
)
static
unsigned
long
get_rate_csi
(
struct
clk
*
clk
)
{
{
return
get_rate_per
(
0
);
return
get_rate_per
(
0
);
...
@@ -213,6 +223,12 @@ DEFINE_CLOCK(ssi2_per_clk, 0, CCM_CGCR0, 14, get_rate_ipg, NULL, NULL);
...
@@ -213,6 +223,12 @@ DEFINE_CLOCK(ssi2_per_clk, 0, CCM_CGCR0, 14, get_rate_ipg, NULL, NULL);
DEFINE_CLOCK
(
cspi1_clk
,
0
,
CCM_CGCR1
,
5
,
get_rate_ipg
,
NULL
,
NULL
);
DEFINE_CLOCK
(
cspi1_clk
,
0
,
CCM_CGCR1
,
5
,
get_rate_ipg
,
NULL
,
NULL
);
DEFINE_CLOCK
(
cspi2_clk
,
0
,
CCM_CGCR1
,
6
,
get_rate_ipg
,
NULL
,
NULL
);
DEFINE_CLOCK
(
cspi2_clk
,
0
,
CCM_CGCR1
,
6
,
get_rate_ipg
,
NULL
,
NULL
);
DEFINE_CLOCK
(
cspi3_clk
,
0
,
CCM_CGCR1
,
7
,
get_rate_ipg
,
NULL
,
NULL
);
DEFINE_CLOCK
(
cspi3_clk
,
0
,
CCM_CGCR1
,
7
,
get_rate_ipg
,
NULL
,
NULL
);
DEFINE_CLOCK
(
esdhc1_ahb_clk
,
0
,
CCM_CGCR0
,
21
,
get_rate_esdhc1
,
NULL
,
NULL
);
DEFINE_CLOCK
(
esdhc1_per_clk
,
0
,
CCM_CGCR0
,
3
,
get_rate_esdhc1
,
NULL
,
&
esdhc1_ahb_clk
);
DEFINE_CLOCK
(
esdhc2_ahb_clk
,
0
,
CCM_CGCR0
,
22
,
get_rate_esdhc2
,
NULL
,
NULL
);
DEFINE_CLOCK
(
esdhc2_per_clk
,
0
,
CCM_CGCR0
,
4
,
get_rate_esdhc2
,
NULL
,
&
esdhc2_ahb_clk
);
DEFINE_CLOCK
(
fec_ahb_clk
,
0
,
CCM_CGCR0
,
23
,
NULL
,
NULL
,
NULL
);
DEFINE_CLOCK
(
fec_ahb_clk
,
0
,
CCM_CGCR0
,
23
,
NULL
,
NULL
,
NULL
);
DEFINE_CLOCK
(
lcdc_ahb_clk
,
0
,
CCM_CGCR0
,
24
,
NULL
,
NULL
,
NULL
);
DEFINE_CLOCK
(
lcdc_ahb_clk
,
0
,
CCM_CGCR0
,
24
,
NULL
,
NULL
,
NULL
);
DEFINE_CLOCK
(
lcdc_per_clk
,
0
,
CCM_CGCR0
,
7
,
NULL
,
NULL
,
&
lcdc_ahb_clk
);
DEFINE_CLOCK
(
lcdc_per_clk
,
0
,
CCM_CGCR0
,
7
,
NULL
,
NULL
,
&
lcdc_ahb_clk
);
...
@@ -238,6 +254,10 @@ DEFINE_CLOCK(lcdc_clk, 0, CCM_CGCR1, 29, get_rate_lcdc, NULL, &lcdc_per_clk);
...
@@ -238,6 +254,10 @@ DEFINE_CLOCK(lcdc_clk, 0, CCM_CGCR1, 29, get_rate_lcdc, NULL, &lcdc_per_clk);
DEFINE_CLOCK
(
wdt_clk
,
0
,
CCM_CGCR2
,
19
,
get_rate_ipg
,
NULL
,
NULL
);
DEFINE_CLOCK
(
wdt_clk
,
0
,
CCM_CGCR2
,
19
,
get_rate_ipg
,
NULL
,
NULL
);
DEFINE_CLOCK
(
ssi1_clk
,
0
,
CCM_CGCR2
,
11
,
get_rate_ssi1
,
NULL
,
&
ssi1_per_clk
);
DEFINE_CLOCK
(
ssi1_clk
,
0
,
CCM_CGCR2
,
11
,
get_rate_ssi1
,
NULL
,
&
ssi1_per_clk
);
DEFINE_CLOCK
(
ssi2_clk
,
1
,
CCM_CGCR2
,
12
,
get_rate_ssi2
,
NULL
,
&
ssi2_per_clk
);
DEFINE_CLOCK
(
ssi2_clk
,
1
,
CCM_CGCR2
,
12
,
get_rate_ssi2
,
NULL
,
&
ssi2_per_clk
);
DEFINE_CLOCK
(
esdhc1_clk
,
0
,
CCM_CGCR1
,
13
,
get_rate_esdhc1
,
NULL
,
&
esdhc1_per_clk
);
DEFINE_CLOCK
(
esdhc2_clk
,
1
,
CCM_CGCR1
,
14
,
get_rate_esdhc2
,
NULL
,
&
esdhc2_per_clk
);
DEFINE_CLOCK
(
audmux_clk
,
0
,
CCM_CGCR1
,
0
,
NULL
,
NULL
,
NULL
);
DEFINE_CLOCK
(
audmux_clk
,
0
,
CCM_CGCR1
,
0
,
NULL
,
NULL
,
NULL
);
DEFINE_CLOCK
(
csi_clk
,
0
,
CCM_CGCR1
,
4
,
get_rate_csi
,
NULL
,
&
csi_per_clk
);
DEFINE_CLOCK
(
csi_clk
,
0
,
CCM_CGCR1
,
4
,
get_rate_csi
,
NULL
,
&
csi_per_clk
);
DEFINE_CLOCK
(
can1_clk
,
0
,
CCM_CGCR1
,
2
,
get_rate_ipg
,
NULL
,
NULL
);
DEFINE_CLOCK
(
can1_clk
,
0
,
CCM_CGCR1
,
2
,
get_rate_ipg
,
NULL
,
NULL
);
...
@@ -261,9 +281,9 @@ static struct clk_lookup lookups[] = {
...
@@ -261,9 +281,9 @@ static struct clk_lookup lookups[] = {
_REGISTER_CLOCK
(
"mxc-ehci.2"
,
"usb"
,
usbotg_clk
)
_REGISTER_CLOCK
(
"mxc-ehci.2"
,
"usb"
,
usbotg_clk
)
_REGISTER_CLOCK
(
"fsl-usb2-udc"
,
"usb"
,
usbotg_clk
)
_REGISTER_CLOCK
(
"fsl-usb2-udc"
,
"usb"
,
usbotg_clk
)
_REGISTER_CLOCK
(
"mxc_nand.0"
,
NULL
,
nfc_clk
)
_REGISTER_CLOCK
(
"mxc_nand.0"
,
NULL
,
nfc_clk
)
_REGISTER_CLOCK
(
"
spi_imx
.0"
,
NULL
,
cspi1_clk
)
_REGISTER_CLOCK
(
"
imx25-cspi
.0"
,
NULL
,
cspi1_clk
)
_REGISTER_CLOCK
(
"
spi_imx
.1"
,
NULL
,
cspi2_clk
)
_REGISTER_CLOCK
(
"
imx25-cspi
.1"
,
NULL
,
cspi2_clk
)
_REGISTER_CLOCK
(
"
spi_imx
.2"
,
NULL
,
cspi3_clk
)
_REGISTER_CLOCK
(
"
imx25-cspi
.2"
,
NULL
,
cspi3_clk
)
_REGISTER_CLOCK
(
"mxc_pwm.0"
,
NULL
,
pwm1_clk
)
_REGISTER_CLOCK
(
"mxc_pwm.0"
,
NULL
,
pwm1_clk
)
_REGISTER_CLOCK
(
"mxc_pwm.1"
,
NULL
,
pwm2_clk
)
_REGISTER_CLOCK
(
"mxc_pwm.1"
,
NULL
,
pwm2_clk
)
_REGISTER_CLOCK
(
"mxc_pwm.2"
,
NULL
,
pwm3_clk
)
_REGISTER_CLOCK
(
"mxc_pwm.2"
,
NULL
,
pwm3_clk
)
...
@@ -279,6 +299,8 @@ static struct clk_lookup lookups[] = {
...
@@ -279,6 +299,8 @@ static struct clk_lookup lookups[] = {
_REGISTER_CLOCK
(
"imx-wdt.0"
,
NULL
,
wdt_clk
)
_REGISTER_CLOCK
(
"imx-wdt.0"
,
NULL
,
wdt_clk
)
_REGISTER_CLOCK
(
"imx-ssi.0"
,
NULL
,
ssi1_clk
)
_REGISTER_CLOCK
(
"imx-ssi.0"
,
NULL
,
ssi1_clk
)
_REGISTER_CLOCK
(
"imx-ssi.1"
,
NULL
,
ssi2_clk
)
_REGISTER_CLOCK
(
"imx-ssi.1"
,
NULL
,
ssi2_clk
)
_REGISTER_CLOCK
(
"sdhci-esdhc-imx.0"
,
NULL
,
esdhc1_clk
)
_REGISTER_CLOCK
(
"sdhci-esdhc-imx.1"
,
NULL
,
esdhc2_clk
)
_REGISTER_CLOCK
(
"mx2-camera.0"
,
NULL
,
csi_clk
)
_REGISTER_CLOCK
(
"mx2-camera.0"
,
NULL
,
csi_clk
)
_REGISTER_CLOCK
(
NULL
,
"audmux"
,
audmux_clk
)
_REGISTER_CLOCK
(
NULL
,
"audmux"
,
audmux_clk
)
_REGISTER_CLOCK
(
"flexcan.0"
,
NULL
,
can1_clk
)
_REGISTER_CLOCK
(
"flexcan.0"
,
NULL
,
can1_clk
)
...
...
arch/arm/mach-mx25/devices-imx25.h
View file @
c9ee46a9
...
@@ -9,35 +9,47 @@
...
@@ -9,35 +9,47 @@
#include <mach/mx25.h>
#include <mach/mx25.h>
#include <mach/devices-common.h>
#include <mach/devices-common.h>
extern
const
struct
imx_fec_data
imx25_fec_data
__initconst
;
#define imx25_add_fec(pdata) \
imx_add_fec(&imx25_fec_data, pdata)
#define imx25_add_flexcan0(pdata) \
#define imx25_add_flexcan0(pdata) \
imx_add_flexcan(0, MX25_CAN1_BASE_ADDR, SZ_16K, MX25_INT_CAN1, pdata)
imx_add_flexcan(0, MX25_CAN1_BASE_ADDR, SZ_16K, MX25_INT_CAN1, pdata)
#define imx25_add_flexcan1(pdata) \
#define imx25_add_flexcan1(pdata) \
imx_add_flexcan(1, MX25_CAN2_BASE_ADDR, SZ_16K, MX25_INT_CAN2, pdata)
imx_add_flexcan(1, MX25_CAN2_BASE_ADDR, SZ_16K, MX25_INT_CAN2, pdata)
#define imx25_add_imx_i2c0(pdata) \
extern
const
struct
imx_imx_i2c_data
imx25_imx_i2c_data
[]
__initconst
;
imx_add_imx_i2c(0, MX25_I2C1_BASE_ADDR, SZ_16K, MX25_INT_I2C1, pdata)
#define imx25_add_imx_i2c(id, pdata) \
#define imx25_add_imx_i2c1(pdata) \
imx_add_imx_i2c(&imx25_imx_i2c_data[id], pdata)
imx_add_imx_i2c(1, MX25_I2C2_BASE_ADDR, SZ_16K, MX25_INT_I2C2, pdata)
#define imx25_add_imx_i2c0(pdata) imx25_add_imx_i2c(0, pdata)
#define imx25_add_imx_i2c2(pdata) \
#define imx25_add_imx_i2c1(pdata) imx25_add_imx_i2c(1, pdata)
imx_add_imx_i2c(2, MX25_I2C3_BASE_ADDR, SZ_16K, MX25_INT_I2C3, pdata)
#define imx25_add_imx_i2c2(pdata) imx25_add_imx_i2c(2, pdata)
#define imx25_add_imx_uart0(pdata) \
extern
const
struct
imx_imx_ssi_data
imx25_imx_ssi_data
[]
__initconst
;
imx_add_imx_uart_1irq(0, MX25_UART1_BASE_ADDR, SZ_16K, MX25_INT_UART1, pdata)
#define imx25_add_imx_ssi(id, pdata) \
#define imx25_add_imx_uart1(pdata) \
imx_add_imx_ssi(&imx25_imx_ssi_data[id], pdata)
imx_add_imx_uart_1irq(1, MX25_UART2_BASE_ADDR, SZ_16K, MX25_INT_UART2, pdata)
#define imx25_add_imx_uart2(pdata) \
extern
const
struct
imx_imx_uart_1irq_data
imx25_imx_uart_data
[]
__initconst
;
imx_add_imx_uart_1irq(2, MX25_UART3_BASE_ADDR, SZ_16K, MX25_INT_UART3, pdata)
#define imx25_add_imx_uart(id, pdata) \
#define imx25_add_imx_uart3(pdata) \
imx_add_imx_uart_1irq(&imx25_imx_uart_data[id], pdata)
imx_add_imx_uart_1irq(3, MX25_UART4_BASE_ADDR, SZ_16K, MX25_INT_UART4, pdata)
#define imx25_add_imx_uart0(pdata) imx25_add_imx_uart(0, pdata)
#define imx25_add_imx_uart4(pdata) \
#define imx25_add_imx_uart1(pdata) imx25_add_imx_uart(1, pdata)
imx_add_imx_uart_1irq(4, MX25_UART5_BASE_ADDR, SZ_16K, MX25_INT_UART5, pdata)
#define imx25_add_imx_uart2(pdata) imx25_add_imx_uart(2, pdata)
#define imx25_add_imx_uart3(pdata) imx25_add_imx_uart(3, pdata)
#define imx25_add_imx_uart4(pdata) imx25_add_imx_uart(4, pdata)
extern
const
struct
imx_mxc_nand_data
imx25_mxc_nand_data
__initconst
;
#define imx25_add_mxc_nand(pdata) \
#define imx25_add_mxc_nand(pdata) \
imx_add_mxc_nand_v21(MX25_NFC_BASE_ADDR, MX25_INT_NANDFC, pdata)
imx_add_mxc_nand(&imx25_mxc_nand_data, pdata)
#define imx25_add_spi_imx0(pdata) \
extern
const
struct
imx_spi_imx_data
imx25_spi_imx_data
[]
__initconst
;
imx_add_spi_imx(0, MX25_CSPI1_BASE_ADDR, SZ_16K, MX25_INT_CSPI1, pdata)
#define imx25_add_spi_imx(id, pdata) \
#define imx25_add_spi_imx1(pdata) \
imx_add_spi_imx(&imx25_spi_imx_data[id], pdata)
imx_add_spi_imx(1, MX25_CSPI2_BASE_ADDR, SZ_16K, MX25_INT_CSPI2, pdata)
#define imx25_add_spi_imx0(pdata) imx25_add_spi_imx(0, pdata)
#define imx25_add_spi_imx2(pdata) \
#define imx25_add_spi_imx1(pdata) imx25_add_spi_imx(1, pdata)
imx_add_spi_imx(2, MX25_CSPI3_BASE_ADDR, SZ_16K, MX25_INT_CSPI3, pdata)
#define imx25_add_spi_imx2(pdata) imx25_add_spi_imx(2, pdata)
#define imx25_add_esdhc0(pdata) \
imx_add_esdhc(0, MX25_ESDHC1_BASE_ADDR, SZ_16K, MX25_INT_MMC_SDHC1, pdata)
#define imx25_add_esdhc1(pdata) \
imx_add_esdhc(1, MX25_ESDHC2_BASE_ADDR, SZ_16K, MX25_INT_MMC_SDHC2, pdata)
arch/arm/mach-mx25/devices.c
View file @
c9ee46a9
...
@@ -208,26 +208,6 @@ int __init imx25_register_gpios(void)
...
@@ -208,26 +208,6 @@ int __init imx25_register_gpios(void)
return
mxc_gpio_init
(
imx_gpio_ports
,
ARRAY_SIZE
(
imx_gpio_ports
));
return
mxc_gpio_init
(
imx_gpio_ports
,
ARRAY_SIZE
(
imx_gpio_ports
));
}
}
static
struct
resource
mx25_fec_resources
[]
=
{
{
.
start
=
MX25_FEC_BASE_ADDR
,
.
end
=
MX25_FEC_BASE_ADDR
+
0xfff
,
.
flags
=
IORESOURCE_MEM
,
},
{
.
start
=
MX25_INT_FEC
,
.
end
=
MX25_INT_FEC
,
.
flags
=
IORESOURCE_IRQ
,
},
};
struct
platform_device
mx25_fec_device
=
{
.
name
=
"fec"
,
.
id
=
0
,
.
num_resources
=
ARRAY_SIZE
(
mx25_fec_resources
),
.
resource
=
mx25_fec_resources
,
};
static
struct
resource
mx25_rtc_resources
[]
=
{
static
struct
resource
mx25_rtc_resources
[]
=
{
{
{
.
start
=
MX25_DRYICE_BASE_ADDR
,
.
start
=
MX25_DRYICE_BASE_ADDR
,
...
@@ -305,44 +285,6 @@ struct platform_device mx25_kpp_device = {
...
@@ -305,44 +285,6 @@ struct platform_device mx25_kpp_device = {
.
resource
=
mx25_kpp_resources
,
.
resource
=
mx25_kpp_resources
,
};
};
static
struct
resource
imx_ssi_resources0
[]
=
{
{
.
start
=
MX25_SSI1_BASE_ADDR
,
.
end
=
MX25_SSI1_BASE_ADDR
+
0x3fff
,
.
flags
=
IORESOURCE_MEM
,
},
{
.
start
=
MX25_INT_SSI1
,
.
end
=
MX25_INT_SSI1
,
.
flags
=
IORESOURCE_IRQ
,
},
};
static
struct
resource
imx_ssi_resources1
[]
=
{
{
.
start
=
MX25_SSI2_BASE_ADDR
,
.
end
=
MX25_SSI2_BASE_ADDR
+
0x3fff
,
.
flags
=
IORESOURCE_MEM
},
{
.
start
=
MX25_INT_SSI2
,
.
end
=
MX25_INT_SSI2
,
.
flags
=
IORESOURCE_IRQ
,
},
};
struct
platform_device
imx_ssi_device0
=
{
.
name
=
"imx-ssi"
,
.
id
=
0
,
.
num_resources
=
ARRAY_SIZE
(
imx_ssi_resources0
),
.
resource
=
imx_ssi_resources0
,
};
struct
platform_device
imx_ssi_device1
=
{
.
name
=
"imx-ssi"
,
.
id
=
1
,
.
num_resources
=
ARRAY_SIZE
(
imx_ssi_resources1
),
.
resource
=
imx_ssi_resources1
,
};
static
struct
resource
mx25_csi_resources
[]
=
{
static
struct
resource
mx25_csi_resources
[]
=
{
{
{
.
start
=
MX25_CSI_BASE_ADDR
,
.
start
=
MX25_CSI_BASE_ADDR
,
...
...
arch/arm/mach-mx25/devices.h
View file @
c9ee46a9
...
@@ -6,11 +6,8 @@ extern struct platform_device mxc_pwm_device1;
...
@@ -6,11 +6,8 @@ extern struct platform_device mxc_pwm_device1;
extern
struct
platform_device
mxc_pwm_device2
;
extern
struct
platform_device
mxc_pwm_device2
;
extern
struct
platform_device
mxc_pwm_device3
;
extern
struct
platform_device
mxc_pwm_device3
;
extern
struct
platform_device
mxc_keypad_device
;
extern
struct
platform_device
mxc_keypad_device
;
extern
struct
platform_device
mx25_fec_device
;
extern
struct
platform_device
mx25_rtc_device
;
extern
struct
platform_device
mx25_rtc_device
;
extern
struct
platform_device
mx25_fb_device
;
extern
struct
platform_device
mx25_fb_device
;
extern
struct
platform_device
mxc_wdt
;
extern
struct
platform_device
mxc_wdt
;
extern
struct
platform_device
mx25_kpp_device
;
extern
struct
platform_device
mx25_kpp_device
;
extern
struct
platform_device
imx_ssi_device0
;
extern
struct
platform_device
imx_ssi_device1
;
extern
struct
platform_device
mx25_csi_device
;
extern
struct
platform_device
mx25_csi_device
;
arch/arm/mach-mx25/eukrea_mbimxsd-baseboard.c
View file @
c9ee46a9
...
@@ -34,7 +34,6 @@
...
@@ -34,7 +34,6 @@
#include <mach/mx25.h>
#include <mach/mx25.h>
#include <mach/imx-uart.h>
#include <mach/imx-uart.h>
#include <mach/imxfb.h>
#include <mach/imxfb.h>
#include <mach/ssi.h>
#include <mach/audmux.h>
#include <mach/audmux.h>
#include "devices-imx25.h"
#include "devices-imx25.h"
...
@@ -90,6 +89,9 @@ static struct pad_desc eukrea_mbimxsd_pads[] = {
...
@@ -90,6 +89,9 @@ static struct pad_desc eukrea_mbimxsd_pads[] = {
MX25_PAD_KPP_COL2__AUD5_TXC
,
MX25_PAD_KPP_COL2__AUD5_TXC
,
MX25_PAD_KPP_COL1__AUD5_RXD
,
MX25_PAD_KPP_COL1__AUD5_RXD
,
MX25_PAD_KPP_COL0__AUD5_TXD
,
MX25_PAD_KPP_COL0__AUD5_TXD
,
/* CAN */
MX25_PAD_GPIO_D__CAN2_RX
,
MX25_PAD_GPIO_C__CAN2_TX
,
};
};
#define GPIO_LED1 83
#define GPIO_LED1 83
...
@@ -205,7 +207,8 @@ static struct i2c_board_info eukrea_mbimxsd_i2c_devices[] = {
...
@@ -205,7 +207,8 @@ static struct i2c_board_info eukrea_mbimxsd_i2c_devices[] = {
},
},
};
};
struct
imx_ssi_platform_data
eukrea_mbimxsd_ssi_pdata
=
{
static
const
struct
imx_ssi_platform_data
eukrea_mbimxsd_ssi_pdata
__initconst
=
{
.
flags
=
IMX_SSI_SYN
|
IMX_SSI_NET
|
IMX_SSI_USE_I2S_SLAVE
,
.
flags
=
IMX_SSI_SYN
|
IMX_SSI_NET
|
IMX_SSI_USE_I2S_SLAVE
,
};
};
...
@@ -239,7 +242,10 @@ void __init eukrea_mbimxsd25_baseboard_init(void)
...
@@ -239,7 +242,10 @@ void __init eukrea_mbimxsd25_baseboard_init(void)
imx25_add_imx_uart1
(
&
uart_pdata
);
imx25_add_imx_uart1
(
&
uart_pdata
);
mxc_register_device
(
&
mx25_fb_device
,
&
eukrea_mximxsd_fb_pdata
);
mxc_register_device
(
&
mx25_fb_device
,
&
eukrea_mximxsd_fb_pdata
);
mxc_register_device
(
&
imx_ssi_device0
,
&
eukrea_mbimxsd_ssi_pdata
);
imx25_add_imx_ssi
(
0
,
&
eukrea_mbimxsd_ssi_pdata
);
imx25_add_flexcan1
(
NULL
);
imx25_add_esdhc0
(
NULL
);
gpio_request
(
GPIO_LED1
,
"LED1"
);
gpio_request
(
GPIO_LED1
,
"LED1"
);
gpio_direction_output
(
GPIO_LED1
,
1
);
gpio_direction_output
(
GPIO_LED1
,
1
);
...
...
arch/arm/mach-mx25/mach-cpuimx25.c
View file @
c9ee46a9
...
@@ -23,7 +23,6 @@
...
@@ -23,7 +23,6 @@
#include <linux/clk.h>
#include <linux/clk.h>
#include <linux/irq.h>
#include <linux/irq.h>
#include <linux/gpio.h>
#include <linux/gpio.h>
#include <linux/fec.h>
#include <linux/platform_device.h>
#include <linux/platform_device.h>
#include <linux/usb/otg.h>
#include <linux/usb/otg.h>
#include <linux/usb/ulpi.h>
#include <linux/usb/ulpi.h>
...
@@ -67,7 +66,7 @@ static struct pad_desc eukrea_cpuimx25_pads[] = {
...
@@ -67,7 +66,7 @@ static struct pad_desc eukrea_cpuimx25_pads[] = {
MX25_PAD_I2C1_DAT__I2C1_DAT
,
MX25_PAD_I2C1_DAT__I2C1_DAT
,
};
};
static
struct
fec_platform_data
mx25_fec_pdata
=
{
static
const
struct
fec_platform_data
mx25_fec_pdata
__initconst
=
{
.
phy
=
PHY_INTERFACE_MODE_RMII
,
.
phy
=
PHY_INTERFACE_MODE_RMII
,
};
};
...
@@ -129,7 +128,7 @@ static void __init eukrea_cpuimx25_init(void)
...
@@ -129,7 +128,7 @@ static void __init eukrea_cpuimx25_init(void)
imx25_add_imx_uart0
(
&
uart_pdata
);
imx25_add_imx_uart0
(
&
uart_pdata
);
imx25_add_mxc_nand
(
&
eukrea_cpuimx25_nand_board_info
);
imx25_add_mxc_nand
(
&
eukrea_cpuimx25_nand_board_info
);
mxc_register_device
(
&
mx25_rtc_device
,
NULL
);
mxc_register_device
(
&
mx25_rtc_device
,
NULL
);
mxc_register_device
(
&
mx25_fec_device
,
&
mx25_fec_pdata
);
imx25_add_fec
(
&
mx25_fec_pdata
);
i2c_register_board_info
(
0
,
eukrea_cpuimx25_i2c_devices
,
i2c_register_board_info
(
0
,
eukrea_cpuimx25_i2c_devices
,
ARRAY_SIZE
(
eukrea_cpuimx25_i2c_devices
));
ARRAY_SIZE
(
eukrea_cpuimx25_i2c_devices
));
...
...
arch/arm/mach-mx25/mach-mx25_3ds.c
View file @
c9ee46a9
...
@@ -28,7 +28,6 @@
...
@@ -28,7 +28,6 @@
#include <linux/clk.h>
#include <linux/clk.h>
#include <linux/irq.h>
#include <linux/irq.h>
#include <linux/gpio.h>
#include <linux/gpio.h>
#include <linux/fec.h>
#include <linux/platform_device.h>
#include <linux/platform_device.h>
#include <linux/input/matrix_keypad.h>
#include <linux/input/matrix_keypad.h>
...
@@ -99,7 +98,7 @@ static struct pad_desc mx25pdk_pads[] = {
...
@@ -99,7 +98,7 @@ static struct pad_desc mx25pdk_pads[] = {
MX25_PAD_KPP_COL3__KPP_COL3
,
MX25_PAD_KPP_COL3__KPP_COL3
,
};
};
static
struct
fec_platform_data
mx25_fec_pdata
=
{
static
const
struct
fec_platform_data
mx25_fec_pdata
__initconst
=
{
.
phy
=
PHY_INTERFACE_MODE_RMII
,
.
phy
=
PHY_INTERFACE_MODE_RMII
,
};
};
...
@@ -192,7 +191,7 @@ static void __init mx25pdk_init(void)
...
@@ -192,7 +191,7 @@ static void __init mx25pdk_init(void)
mxc_register_device
(
&
mxc_wdt
,
NULL
);
mxc_register_device
(
&
mxc_wdt
,
NULL
);
mx25pdk_fec_reset
();
mx25pdk_fec_reset
();
mxc_register_device
(
&
mx25_fec_device
,
&
mx25_fec_pdata
);
imx25_add_fec
(
&
mx25_fec_pdata
);
mxc_register_device
(
&
mx25_kpp_device
,
&
mx25pdk_keymap_data
);
mxc_register_device
(
&
mx25_kpp_device
,
&
mx25pdk_keymap_data
);
}
}
...
...
arch/arm/mach-mx3/Kconfig
View file @
c9ee46a9
...
@@ -9,6 +9,7 @@ config ARCH_MX35
...
@@ -9,6 +9,7 @@ config ARCH_MX35
bool
bool
select ARCH_MXC_IOMUX_V3
select ARCH_MXC_IOMUX_V3
select ARCH_MXC_AUDMUX_V2
select ARCH_MXC_AUDMUX_V2
select HAVE_EPIT
comment "MX3 platforms:"
comment "MX3 platforms:"
...
@@ -16,6 +17,7 @@ config MACH_MX31ADS
...
@@ -16,6 +17,7 @@ config MACH_MX31ADS
bool "Support MX31ADS platforms"
bool "Support MX31ADS platforms"
select ARCH_MX31
select ARCH_MX31
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_SSI
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_IMX_UART
default y
default y
help
help
...
@@ -117,9 +119,11 @@ config MACH_PCM043
...
@@ -117,9 +119,11 @@ config MACH_PCM043
bool "Support Phytec pcm043 (i.MX35) platforms"
bool "Support Phytec pcm043 (i.MX35) platforms"
select ARCH_MX35
select ARCH_MX35
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_SSI
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_FLEXCAN
select IMX_HAVE_PLATFORM_FLEXCAN
select IMX_HAVE_PLATFORM_ESDHC
select MXC_ULPI if USB_ULPI
select MXC_ULPI if USB_ULPI
help
help
Include support for Phytec pcm043 platform. This includes
Include support for Phytec pcm043 platform. This includes
...
@@ -140,6 +144,7 @@ config MACH_MX35_3DS
...
@@ -140,6 +144,7 @@ config MACH_MX35_3DS
bool "Support MX35PDK platform"
bool "Support MX35PDK platform"
select ARCH_MX35
select ARCH_MX35
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_NAND
default n
default n
help
help
Include support for MX35PDK platform. This includes specific
Include support for MX35PDK platform. This includes specific
...
@@ -159,6 +164,8 @@ config MACH_EUKREA_CPUIMX35
...
@@ -159,6 +164,8 @@ config MACH_EUKREA_CPUIMX35
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_FLEXCAN
select IMX_HAVE_PLATFORM_ESDHC
select MXC_ULPI if USB_ULPI
select MXC_ULPI if USB_ULPI
help
help
Include support for Eukrea CPUIMX35 platform. This includes
Include support for Eukrea CPUIMX35 platform. This includes
...
@@ -170,8 +177,8 @@ choice
...
@@ -170,8 +177,8 @@ choice
default MACH_EUKREA_MBIMXSD35_BASEBOARD
default MACH_EUKREA_MBIMXSD35_BASEBOARD
config MACH_EUKREA_MBIMXSD35_BASEBOARD
config MACH_EUKREA_MBIMXSD35_BASEBOARD
prompt
"Eukrea MBIMXSD development board"
bool
"Eukrea MBIMXSD development board"
bool
select IMX_HAVE_PLATFORM_IMX_SSI
help
help
This adds board specific devices that can be found on Eukrea's
This adds board specific devices that can be found on Eukrea's
MBIMXSD evaluation board.
MBIMXSD evaluation board.
...
...
arch/arm/mach-mx3/Makefile
View file @
c9ee46a9
...
@@ -7,7 +7,6 @@
...
@@ -7,7 +7,6 @@
obj-y
:=
mm.o devices.o cpu.o
obj-y
:=
mm.o devices.o cpu.o
CFLAGS_mm.o
=
-DIMX_NEEDS_DEPRECATED_SYMBOLS
CFLAGS_mm.o
=
-DIMX_NEEDS_DEPRECATED_SYMBOLS
CFLAGS_devices.o
=
-DIMX_NEEDS_DEPRECATED_SYMBOLS
CFLAGS_devices.o
=
-DIMX_NEEDS_DEPRECATED_SYMBOLS
CFLAGS_cpu.o
=
-DIMX_NEEDS_DEPRECATED_SYMBOLS
obj-$(CONFIG_ARCH_MX31)
+=
clock-imx31.o iomux-imx31.o
obj-$(CONFIG_ARCH_MX31)
+=
clock-imx31.o iomux-imx31.o
obj-$(CONFIG_ARCH_MX35)
+=
clock-imx35.o
obj-$(CONFIG_ARCH_MX35)
+=
clock-imx35.o
obj-$(CONFIG_MACH_MX31ADS)
+=
mach-mx31ads.o
obj-$(CONFIG_MACH_MX31ADS)
+=
mach-mx31ads.o
...
...
arch/arm/mach-mx3/clock-imx31.c
View file @
c9ee46a9
...
@@ -477,7 +477,7 @@ DEFINE_CLOCK(epit1_clk, 0, MXC_CCM_CGR0, 6, NULL, NULL, &perclk_clk);
...
@@ -477,7 +477,7 @@ DEFINE_CLOCK(epit1_clk, 0, MXC_CCM_CGR0, 6, NULL, NULL, &perclk_clk);
DEFINE_CLOCK
(
epit2_clk
,
1
,
MXC_CCM_CGR0
,
8
,
NULL
,
NULL
,
&
perclk_clk
);
DEFINE_CLOCK
(
epit2_clk
,
1
,
MXC_CCM_CGR0
,
8
,
NULL
,
NULL
,
&
perclk_clk
);
DEFINE_CLOCK
(
iim_clk
,
0
,
MXC_CCM_CGR0
,
10
,
NULL
,
NULL
,
&
ipg_clk
);
DEFINE_CLOCK
(
iim_clk
,
0
,
MXC_CCM_CGR0
,
10
,
NULL
,
NULL
,
&
ipg_clk
);
DEFINE_CLOCK
(
ata_clk
,
0
,
MXC_CCM_CGR0
,
12
,
NULL
,
NULL
,
&
ipg_clk
);
DEFINE_CLOCK
(
ata_clk
,
0
,
MXC_CCM_CGR0
,
12
,
NULL
,
NULL
,
&
ipg_clk
);
DEFINE_CLOCK
(
sdma_clk1
,
0
,
MXC_CCM_CGR0
,
14
,
NULL
,
&
sdma_clk1
,
&
ahb_clk
);
DEFINE_CLOCK
(
sdma_clk1
,
0
,
MXC_CCM_CGR0
,
14
,
NULL
,
NULL
,
&
ahb_clk
);
DEFINE_CLOCK
(
cspi3_clk
,
2
,
MXC_CCM_CGR0
,
16
,
NULL
,
NULL
,
&
ipg_clk
);
DEFINE_CLOCK
(
cspi3_clk
,
2
,
MXC_CCM_CGR0
,
16
,
NULL
,
NULL
,
&
ipg_clk
);
DEFINE_CLOCK
(
rng_clk
,
0
,
MXC_CCM_CGR0
,
18
,
NULL
,
NULL
,
&
ipg_clk
);
DEFINE_CLOCK
(
rng_clk
,
0
,
MXC_CCM_CGR0
,
18
,
NULL
,
NULL
,
&
ipg_clk
);
DEFINE_CLOCK
(
uart1_clk
,
0
,
MXC_CCM_CGR0
,
20
,
NULL
,
NULL
,
&
perclk_clk
);
DEFINE_CLOCK
(
uart1_clk
,
0
,
MXC_CCM_CGR0
,
20
,
NULL
,
NULL
,
&
perclk_clk
);
...
@@ -525,9 +525,9 @@ DEFINE_CLOCK(ipg_clk, 0, NULL, 0, ipg_get_rate, NULL, &ahb_clk);
...
@@ -525,9 +525,9 @@ DEFINE_CLOCK(ipg_clk, 0, NULL, 0, ipg_get_rate, NULL, &ahb_clk);
static
struct
clk_lookup
lookups
[]
=
{
static
struct
clk_lookup
lookups
[]
=
{
_REGISTER_CLOCK
(
NULL
,
"emi"
,
emi_clk
)
_REGISTER_CLOCK
(
NULL
,
"emi"
,
emi_clk
)
_REGISTER_CLOCK
(
"
spi_imx
.0"
,
NULL
,
cspi1_clk
)
_REGISTER_CLOCK
(
"
imx31-cspi
.0"
,
NULL
,
cspi1_clk
)
_REGISTER_CLOCK
(
"
spi_imx
.1"
,
NULL
,
cspi2_clk
)
_REGISTER_CLOCK
(
"
imx31-cspi
.1"
,
NULL
,
cspi2_clk
)
_REGISTER_CLOCK
(
"
spi_imx
.2"
,
NULL
,
cspi3_clk
)
_REGISTER_CLOCK
(
"
imx31-cspi
.2"
,
NULL
,
cspi3_clk
)
_REGISTER_CLOCK
(
NULL
,
"gpt"
,
gpt_clk
)
_REGISTER_CLOCK
(
NULL
,
"gpt"
,
gpt_clk
)
_REGISTER_CLOCK
(
NULL
,
"pwm"
,
pwm_clk
)
_REGISTER_CLOCK
(
NULL
,
"pwm"
,
pwm_clk
)
_REGISTER_CLOCK
(
"imx-wdt.0"
,
NULL
,
wdog_clk
)
_REGISTER_CLOCK
(
"imx-wdt.0"
,
NULL
,
wdog_clk
)
...
@@ -564,7 +564,7 @@ static struct clk_lookup lookups[] = {
...
@@ -564,7 +564,7 @@ static struct clk_lookup lookups[] = {
_REGISTER_CLOCK
(
NULL
,
"ata"
,
ata_clk
)
_REGISTER_CLOCK
(
NULL
,
"ata"
,
ata_clk
)
_REGISTER_CLOCK
(
NULL
,
"rtic"
,
rtic_clk
)
_REGISTER_CLOCK
(
NULL
,
"rtic"
,
rtic_clk
)
_REGISTER_CLOCK
(
NULL
,
"rng"
,
rng_clk
)
_REGISTER_CLOCK
(
NULL
,
"rng"
,
rng_clk
)
_REGISTER_CLOCK
(
NULL
,
"sdma_ahb"
,
sdma_clk1
)
_REGISTER_CLOCK
(
"imx-sdma"
,
NULL
,
sdma_clk1
)
_REGISTER_CLOCK
(
NULL
,
"sdma_ipg"
,
sdma_clk2
)
_REGISTER_CLOCK
(
NULL
,
"sdma_ipg"
,
sdma_clk2
)
_REGISTER_CLOCK
(
NULL
,
"mstick"
,
mstick1_clk
)
_REGISTER_CLOCK
(
NULL
,
"mstick"
,
mstick1_clk
)
_REGISTER_CLOCK
(
NULL
,
"mstick"
,
mstick2_clk
)
_REGISTER_CLOCK
(
NULL
,
"mstick"
,
mstick2_clk
)
...
...
arch/arm/mach-mx3/clock-imx35.c
View file @
c9ee46a9
...
@@ -364,8 +364,8 @@ DEFINE_CLOCK(cspi2_clk, 1, CCM_CGR0, 12, get_rate_ipg, NULL);
...
@@ -364,8 +364,8 @@ DEFINE_CLOCK(cspi2_clk, 1, CCM_CGR0, 12, get_rate_ipg, NULL);
DEFINE_CLOCK
(
ect_clk
,
0
,
CCM_CGR0
,
14
,
get_rate_ipg
,
NULL
);
DEFINE_CLOCK
(
ect_clk
,
0
,
CCM_CGR0
,
14
,
get_rate_ipg
,
NULL
);
DEFINE_CLOCK
(
edio_clk
,
0
,
CCM_CGR0
,
16
,
NULL
,
NULL
);
DEFINE_CLOCK
(
edio_clk
,
0
,
CCM_CGR0
,
16
,
NULL
,
NULL
);
DEFINE_CLOCK
(
emi_clk
,
0
,
CCM_CGR0
,
18
,
get_rate_ipg
,
NULL
);
DEFINE_CLOCK
(
emi_clk
,
0
,
CCM_CGR0
,
18
,
get_rate_ipg
,
NULL
);
DEFINE_CLOCK
(
epit1_clk
,
0
,
CCM_CGR0
,
20
,
get_rate_ipg
_per
,
NULL
);
DEFINE_CLOCK
(
epit1_clk
,
0
,
CCM_CGR0
,
20
,
get_rate_ipg
,
NULL
);
DEFINE_CLOCK
(
epit2_clk
,
1
,
CCM_CGR0
,
22
,
get_rate_ipg
_per
,
NULL
);
DEFINE_CLOCK
(
epit2_clk
,
1
,
CCM_CGR0
,
22
,
get_rate_ipg
,
NULL
);
DEFINE_CLOCK
(
esai_clk
,
0
,
CCM_CGR0
,
24
,
NULL
,
NULL
);
DEFINE_CLOCK
(
esai_clk
,
0
,
CCM_CGR0
,
24
,
NULL
,
NULL
);
DEFINE_CLOCK
(
esdhc1_clk
,
0
,
CCM_CGR0
,
26
,
get_rate_sdhc
,
NULL
);
DEFINE_CLOCK
(
esdhc1_clk
,
0
,
CCM_CGR0
,
26
,
get_rate_sdhc
,
NULL
);
DEFINE_CLOCK
(
esdhc2_clk
,
1
,
CCM_CGR0
,
28
,
get_rate_sdhc
,
NULL
);
DEFINE_CLOCK
(
esdhc2_clk
,
1
,
CCM_CGR0
,
28
,
get_rate_sdhc
,
NULL
);
...
@@ -451,17 +451,17 @@ static struct clk_lookup lookups[] = {
...
@@ -451,17 +451,17 @@ static struct clk_lookup lookups[] = {
_REGISTER_CLOCK
(
NULL
,
"ata"
,
ata_clk
)
_REGISTER_CLOCK
(
NULL
,
"ata"
,
ata_clk
)
_REGISTER_CLOCK
(
"flexcan.0"
,
NULL
,
can1_clk
)
_REGISTER_CLOCK
(
"flexcan.0"
,
NULL
,
can1_clk
)
_REGISTER_CLOCK
(
"flexcan.1"
,
NULL
,
can2_clk
)
_REGISTER_CLOCK
(
"flexcan.1"
,
NULL
,
can2_clk
)
_REGISTER_CLOCK
(
"
spi_imx
.0"
,
NULL
,
cspi1_clk
)
_REGISTER_CLOCK
(
"
imx35-cspi
.0"
,
NULL
,
cspi1_clk
)
_REGISTER_CLOCK
(
"
spi_imx
.1"
,
NULL
,
cspi2_clk
)
_REGISTER_CLOCK
(
"
imx35-cspi
.1"
,
NULL
,
cspi2_clk
)
_REGISTER_CLOCK
(
NULL
,
"ect"
,
ect_clk
)
_REGISTER_CLOCK
(
NULL
,
"ect"
,
ect_clk
)
_REGISTER_CLOCK
(
NULL
,
"edio"
,
edio_clk
)
_REGISTER_CLOCK
(
NULL
,
"edio"
,
edio_clk
)
_REGISTER_CLOCK
(
NULL
,
"emi"
,
emi_clk
)
_REGISTER_CLOCK
(
NULL
,
"emi"
,
emi_clk
)
_REGISTER_CLOCK
(
NULL
,
"epit"
,
epit1_clk
)
_REGISTER_CLOCK
(
"imx-epit.0"
,
NULL
,
epit1_clk
)
_REGISTER_CLOCK
(
NULL
,
"epit"
,
epit2_clk
)
_REGISTER_CLOCK
(
"imx-epit.1"
,
NULL
,
epit2_clk
)
_REGISTER_CLOCK
(
NULL
,
"esai"
,
esai_clk
)
_REGISTER_CLOCK
(
NULL
,
"esai"
,
esai_clk
)
_REGISTER_CLOCK
(
NULL
,
"sdhc"
,
esdhc1_clk
)
_REGISTER_CLOCK
(
"sdhci-esdhc-imx.0"
,
NULL
,
esdhc1_clk
)
_REGISTER_CLOCK
(
NULL
,
"sdhc"
,
esdhc2_clk
)
_REGISTER_CLOCK
(
"sdhci-esdhc-imx.1"
,
NULL
,
esdhc2_clk
)
_REGISTER_CLOCK
(
NULL
,
"sdhc"
,
esdhc3_clk
)
_REGISTER_CLOCK
(
"sdhci-esdhc-imx.2"
,
NULL
,
esdhc3_clk
)
_REGISTER_CLOCK
(
"fec.0"
,
NULL
,
fec_clk
)
_REGISTER_CLOCK
(
"fec.0"
,
NULL
,
fec_clk
)
_REGISTER_CLOCK
(
NULL
,
"gpio"
,
gpio1_clk
)
_REGISTER_CLOCK
(
NULL
,
"gpio"
,
gpio1_clk
)
_REGISTER_CLOCK
(
NULL
,
"gpio"
,
gpio2_clk
)
_REGISTER_CLOCK
(
NULL
,
"gpio"
,
gpio2_clk
)
...
@@ -482,7 +482,7 @@ static struct clk_lookup lookups[] = {
...
@@ -482,7 +482,7 @@ static struct clk_lookup lookups[] = {
_REGISTER_CLOCK
(
NULL
,
"rtc"
,
rtc_clk
)
_REGISTER_CLOCK
(
NULL
,
"rtc"
,
rtc_clk
)
_REGISTER_CLOCK
(
NULL
,
"rtic"
,
rtic_clk
)
_REGISTER_CLOCK
(
NULL
,
"rtic"
,
rtic_clk
)
_REGISTER_CLOCK
(
NULL
,
"scc"
,
scc_clk
)
_REGISTER_CLOCK
(
NULL
,
"scc"
,
scc_clk
)
_REGISTER_CLOCK
(
NULL
,
"sdma"
,
sdma_clk
)
_REGISTER_CLOCK
(
"imx-sdma"
,
NULL
,
sdma_clk
)
_REGISTER_CLOCK
(
NULL
,
"spba"
,
spba_clk
)
_REGISTER_CLOCK
(
NULL
,
"spba"
,
spba_clk
)
_REGISTER_CLOCK
(
NULL
,
"spdif"
,
spdif_clk
)
_REGISTER_CLOCK
(
NULL
,
"spdif"
,
spdif_clk
)
_REGISTER_CLOCK
(
"imx-ssi.0"
,
NULL
,
ssi1_clk
)
_REGISTER_CLOCK
(
"imx-ssi.0"
,
NULL
,
ssi1_clk
)
...
@@ -535,8 +535,16 @@ int __init mx35_clocks_init()
...
@@ -535,8 +535,16 @@ int __init mx35_clocks_init()
__raw_writel
(
cgr2
,
CCM_BASE
+
CCM_CGR2
);
__raw_writel
(
cgr2
,
CCM_BASE
+
CCM_CGR2
);
__raw_writel
(
cgr3
,
CCM_BASE
+
CCM_CGR3
);
__raw_writel
(
cgr3
,
CCM_BASE
+
CCM_CGR3
);
clk_enable
(
&
iim_clk
);
mx35_read_cpu_rev
();
#ifdef CONFIG_MXC_USE_EPIT
epit_timer_init
(
&
epit1_clk
,
MX35_IO_ADDRESS
(
MX35_EPIT1_BASE_ADDR
),
MX35_INT_EPIT1
);
#else
mxc_timer_init
(
&
gpt_clk
,
mxc_timer_init
(
&
gpt_clk
,
MX35_IO_ADDRESS
(
MX35_GPT1_BASE_ADDR
),
MX35_INT_GPT
);
MX35_IO_ADDRESS
(
MX35_GPT1_BASE_ADDR
),
MX35_INT_GPT
);
#endif
return
0
;
return
0
;
}
}
...
...
arch/arm/mach-mx3/cpu.c
View file @
c9ee46a9
...
@@ -25,15 +25,15 @@ struct mx3_cpu_type {
...
@@ -25,15 +25,15 @@ struct mx3_cpu_type {
};
};
static
struct
mx3_cpu_type
mx31_cpu_type
[]
__initdata
=
{
static
struct
mx3_cpu_type
mx31_cpu_type
[]
__initdata
=
{
{
.
srev
=
0x00
,
.
name
=
"i.MX31(L)"
,
.
v
=
"1.0"
,
.
rev
=
CHIP_REV_1_0
},
{
.
srev
=
0x00
,
.
name
=
"i.MX31(L)"
,
.
v
=
"1.0"
,
.
rev
=
MX3x_CHIP_REV_1_0
},
{
.
srev
=
0x10
,
.
name
=
"i.MX31"
,
.
v
=
"1.1"
,
.
rev
=
CHIP_REV_1_1
},
{
.
srev
=
0x10
,
.
name
=
"i.MX31"
,
.
v
=
"1.1"
,
.
rev
=
MX3x_CHIP_REV_1_1
},
{
.
srev
=
0x11
,
.
name
=
"i.MX31L"
,
.
v
=
"1.1"
,
.
rev
=
CHIP_REV_1_1
},
{
.
srev
=
0x11
,
.
name
=
"i.MX31L"
,
.
v
=
"1.1"
,
.
rev
=
MX3x_CHIP_REV_1_1
},
{
.
srev
=
0x12
,
.
name
=
"i.MX31"
,
.
v
=
"1.15"
,
.
rev
=
CHIP_REV_1_1
},
{
.
srev
=
0x12
,
.
name
=
"i.MX31"
,
.
v
=
"1.15"
,
.
rev
=
MX3x_CHIP_REV_1_1
},
{
.
srev
=
0x13
,
.
name
=
"i.MX31L"
,
.
v
=
"1.15"
,
.
rev
=
CHIP_REV_1_1
},
{
.
srev
=
0x13
,
.
name
=
"i.MX31L"
,
.
v
=
"1.15"
,
.
rev
=
MX3x_CHIP_REV_1_1
},
{
.
srev
=
0x14
,
.
name
=
"i.MX31"
,
.
v
=
"1.2"
,
.
rev
=
CHIP_REV_1_2
},
{
.
srev
=
0x14
,
.
name
=
"i.MX31"
,
.
v
=
"1.2"
,
.
rev
=
MX3x_CHIP_REV_1_2
},
{
.
srev
=
0x15
,
.
name
=
"i.MX31L"
,
.
v
=
"1.2"
,
.
rev
=
CHIP_REV_1_2
},
{
.
srev
=
0x15
,
.
name
=
"i.MX31L"
,
.
v
=
"1.2"
,
.
rev
=
MX3x_CHIP_REV_1_2
},
{
.
srev
=
0x28
,
.
name
=
"i.MX31"
,
.
v
=
"2.0"
,
.
rev
=
CHIP_REV_2_0
},
{
.
srev
=
0x28
,
.
name
=
"i.MX31"
,
.
v
=
"2.0"
,
.
rev
=
MX3x_CHIP_REV_2_0
},
{
.
srev
=
0x29
,
.
name
=
"i.MX31L"
,
.
v
=
"2.0"
,
.
rev
=
CHIP_REV_2_0
},
{
.
srev
=
0x29
,
.
name
=
"i.MX31L"
,
.
v
=
"2.0"
,
.
rev
=
MX3x_CHIP_REV_2_0
},
};
};
void
__init
mx31_read_cpu_rev
(
void
)
void
__init
mx31_read_cpu_rev
(
void
)
...
@@ -41,7 +41,7 @@ void __init mx31_read_cpu_rev(void)
...
@@ -41,7 +41,7 @@ void __init mx31_read_cpu_rev(void)
u32
i
,
srev
;
u32
i
,
srev
;
/* read SREV register from IIM module */
/* read SREV register from IIM module */
srev
=
__raw_readl
(
IO_ADDRESS
(
IIM_BASE_ADDR
+
MXC_IIMSREV
));
srev
=
__raw_readl
(
MX31_IO_ADDRESS
(
MX31_
IIM_BASE_ADDR
+
MXC_IIMSREV
));
for
(
i
=
0
;
i
<
ARRAY_SIZE
(
mx31_cpu_type
);
i
++
)
for
(
i
=
0
;
i
<
ARRAY_SIZE
(
mx31_cpu_type
);
i
++
)
if
(
srev
==
mx31_cpu_type
[
i
].
srev
)
{
if
(
srev
==
mx31_cpu_type
[
i
].
srev
)
{
...
@@ -55,3 +55,30 @@ void __init mx31_read_cpu_rev(void)
...
@@ -55,3 +55,30 @@ void __init mx31_read_cpu_rev(void)
printk
(
KERN_WARNING
"Unknown CPU identifier. srev = %02x
\n
"
,
srev
);
printk
(
KERN_WARNING
"Unknown CPU identifier. srev = %02x
\n
"
,
srev
);
}
}
unsigned
int
mx35_cpu_rev
;
EXPORT_SYMBOL
(
mx35_cpu_rev
);
void
__init
mx35_read_cpu_rev
(
void
)
{
u32
rev
;
char
*
srev
=
"unknown"
;
rev
=
__raw_readl
(
MX35_IO_ADDRESS
(
MX35_IIM_BASE_ADDR
+
MXC_IIMSREV
));
switch
(
rev
)
{
case
0x00
:
mx35_cpu_rev
=
MX3x_CHIP_REV_1_0
;
srev
=
"1.0"
;
break
;
case
0x10
:
mx35_cpu_rev
=
MX3x_CHIP_REV_2_0
;
srev
=
"2.0"
;
break
;
case
0x11
:
mx35_cpu_rev
=
MX3x_CHIP_REV_2_1
;
srev
=
"2.1"
;
break
;
}
printk
(
KERN_INFO
"CPU identified as i.MX35, silicon rev %s
\n
"
,
srev
);
}
arch/arm/mach-mx3/devices-imx31.h
View file @
c9ee46a9
...
@@ -9,30 +9,33 @@
...
@@ -9,30 +9,33 @@
#include <mach/mx31.h>
#include <mach/mx31.h>
#include <mach/devices-common.h>
#include <mach/devices-common.h>
#define imx31_add_imx_i2c0(pdata) \
extern
const
struct
imx_imx_i2c_data
imx31_imx_i2c_data
[]
__initconst
;
imx_add_imx_i2c(0, MX31_I2C1_BASE_ADDR, SZ_4K, MX31_INT_I2C1, pdata)
#define imx31_add_imx_i2c(id, pdata) \
#define imx31_add_imx_i2c1(pdata) \
imx_add_imx_i2c(&imx31_imx_i2c_data[id], pdata)
imx_add_imx_i2c(1, MX31_I2C2_BASE_ADDR, SZ_4K, MX31_INT_I2C2
, pdata)
#define imx31_add_imx_i2c0(pdata) imx31_add_imx_i2c(0
, pdata)
#define imx31_add_imx_i2c
2(pdata) \
#define imx31_add_imx_i2c
1(pdata) imx31_add_imx_i2c(1, pdata)
imx_add_imx_i2c(2, MX31_I2C3_BASE_ADDR, SZ_4K, MX31_INT_I2C3
, pdata)
#define imx31_add_imx_i2c2(pdata) imx31_add_imx_i2c(2
, pdata)
#define imx31_add_imx_uart0(pdata) \
extern
const
struct
imx_imx_ssi_data
imx31_imx_ssi_data
[]
__initconst
;
imx_add_imx_uart_1irq(0, MX31_UART1_BASE_ADDR, SZ_16K, MX31_INT_UART1, pdata)
#define imx31_add_imx_ssi(id, pdata) \
#define imx31_add_imx_uart1(pdata) \
imx_add_imx_ssi(&imx31_imx_ssi_data[id], pdata)
imx_add_imx_uart_1irq(1, MX31_UART2_BASE_ADDR, SZ_16K, MX31_INT_UART2, pdata)
#define imx31_add_imx_uart2(pdata) \
imx_add_imx_uart_1irq(2, MX31_UART3_BASE_ADDR, SZ_16K, MX31_INT_UART3, pdata)
#define imx31_add_imx_uart3(pdata) \
imx_add_imx_uart_1irq(3, MX31_UART4_BASE_ADDR, SZ_16K, MX31_INT_UART4, pdata)
#define imx31_add_imx_uart4(pdata) \
imx_add_imx_uart_1irq(4, MX31_UART5_BASE_ADDR, SZ_16K, MX31_INT_UART5, pdata)
extern
const
struct
imx_imx_uart_1irq_data
imx31_imx_uart_data
[]
__initconst
;
#define imx31_add_imx_uart(id, pdata) \
imx_add_imx_uart_1irq(&imx31_imx_uart_data[id], pdata)
#define imx31_add_imx_uart0(pdata) imx31_add_imx_uart(0, pdata)
#define imx31_add_imx_uart1(pdata) imx31_add_imx_uart(1, pdata)
#define imx31_add_imx_uart2(pdata) imx31_add_imx_uart(2, pdata)
#define imx31_add_imx_uart3(pdata) imx31_add_imx_uart(3, pdata)
#define imx31_add_imx_uart4(pdata) imx31_add_imx_uart(4, pdata)
extern
const
struct
imx_mxc_nand_data
imx31_mxc_nand_data
__initconst
;
#define imx31_add_mxc_nand(pdata) \
#define imx31_add_mxc_nand(pdata) \
imx_add_mxc_nand
_v1(MX31_NFC_BASE_ADDR, MX31_INT_NANDFC
, pdata)
imx_add_mxc_nand
(&imx31_mxc_nand_data
, pdata)
#define imx31_add_spi_imx0(pdata) \
extern
const
struct
imx_spi_imx_data
imx31_cspi_data
[]
__initconst
;
imx_add_spi_imx(0, MX31_CSPI1_BASE_ADDR, SZ_4K, MX31_INT_CSPI1, pdata)
#define imx31_add_cspi(id, pdata) \
#define imx31_add_spi_imx1(pdata) \
imx_add_spi_imx(&imx31_cspi_data[id], pdata)
imx_add_spi_imx(1, MX31_CSPI2_BASE_ADDR, SZ_4K, MX31_INT_CSPI2
, pdata)
#define imx31_add_spi_imx0(pdata) imx31_add_cspi(0
, pdata)
#define imx31_add_spi_imx
2(pdata) \
#define imx31_add_spi_imx
1(pdata) imx31_add_cspi(1, pdata)
imx_add_spi_imx(2, MX31_CSPI3_BASE_ADDR, SZ_4K, MX31_INT_CSPI3
, pdata)
#define imx31_add_spi_imx2(pdata) imx31_add_cspi(2
, pdata)
arch/arm/mach-mx3/devices-imx35.h
View file @
c9ee46a9
...
@@ -9,29 +9,46 @@
...
@@ -9,29 +9,46 @@
#include <mach/mx35.h>
#include <mach/mx35.h>
#include <mach/devices-common.h>
#include <mach/devices-common.h>
extern
const
struct
imx_fec_data
imx35_fec_data
__initconst
;
#define imx35_add_fec(pdata) \
imx_add_fec(&imx35_fec_data, pdata)
#define imx35_add_flexcan0(pdata) \
#define imx35_add_flexcan0(pdata) \
imx_add_flexcan(0, MX35_CAN1_BASE_ADDR, SZ_16K, MX35_INT_CAN1, pdata)
imx_add_flexcan(0, MX35_CAN1_BASE_ADDR, SZ_16K, MX35_INT_CAN1, pdata)
#define imx35_add_flexcan1(pdata) \
#define imx35_add_flexcan1(pdata) \
imx_add_flexcan(1, MX35_CAN2_BASE_ADDR, SZ_16K, MX35_INT_CAN2, pdata)
imx_add_flexcan(1, MX35_CAN2_BASE_ADDR, SZ_16K, MX35_INT_CAN2, pdata)
#define imx35_add_imx_i2c0(pdata) \
extern
const
struct
imx_imx_i2c_data
imx35_imx_i2c_data
[]
__initconst
;
imx_add_imx_i2c(0, MX35_I2C1_BASE_ADDR, SZ_4K, MX35_INT_I2C1, pdata)
#define imx35_add_imx_i2c(id, pdata) \
#define imx35_add_imx_i2c1(pdata) \
imx_add_imx_i2c(&imx35_imx_i2c_data[id], pdata)
imx_add_imx_i2c(1, MX35_I2C2_BASE_ADDR, SZ_4K, MX35_INT_I2C2, pdata)
#define imx35_add_imx_i2c0(pdata) imx35_add_imx_i2c(0, pdata)
#define imx35_add_imx_i2c2(pdata) \
#define imx35_add_imx_i2c1(pdata) imx35_add_imx_i2c(1, pdata)
imx_add_imx_i2c(2, MX35_I2C3_BASE_ADDR, SZ_4K, MX35_INT_I2C3, pdata)
#define imx35_add_imx_i2c2(pdata) imx35_add_imx_i2c(2, pdata)
extern
const
struct
imx_imx_ssi_data
imx35_imx_ssi_data
[]
__initconst
;
#define imx35_add_imx_ssi(id, pdata) \
imx_add_imx_ssi(&imx35_imx_ssi_data[id], pdata)
#define imx35_add_imx_uart0(pdata) \
extern
const
struct
imx_imx_uart_1irq_data
imx35_imx_uart_data
[]
__initconst
;
imx_add_imx_uart_1irq(0, MX35_UART1_BASE_ADDR, SZ_16K, MX35_INT_UART1, pdata)
#define imx35_add_imx_uart(id, pdata) \
#define imx35_add_imx_uart1(pdata) \
imx_add_imx_uart_1irq(&imx35_imx_uart_data[id], pdata)
imx_add_imx_uart_1irq(1, MX35_UART2_BASE_ADDR, SZ_16K, MX35_INT_UART2
, pdata)
#define imx35_add_imx_uart0(pdata) imx35_add_imx_uart(0
, pdata)
#define imx35_add_imx_uart
2(pdata) \
#define imx35_add_imx_uart
1(pdata) imx35_add_imx_uart(1, pdata)
imx_add_imx_uart_1irq(2, MX35_UART3_BASE_ADDR, SZ_16K, MX35_INT_UART3
, pdata)
#define imx35_add_imx_uart2(pdata) imx35_add_imx_uart(2
, pdata)
extern
const
struct
imx_mxc_nand_data
imx35_mxc_nand_data
__initconst
;
#define imx35_add_mxc_nand(pdata) \
#define imx35_add_mxc_nand(pdata) \
imx_add_mxc_nand_v21(MX35_NFC_BASE_ADDR, MX35_INT_NANDFC, pdata)
imx_add_mxc_nand(&imx35_mxc_nand_data, pdata)
extern
const
struct
imx_spi_imx_data
imx35_cspi_data
[]
__initconst
;
#define imx35_add_cspi(id, pdata) \
imx_add_spi_imx(&imx35_cspi_data[id], pdata)
#define imx35_add_spi_imx0(pdata) imx35_add_cspi(0, pdata)
#define imx35_add_spi_imx1(pdata) imx35_add_cspi(1, pdata)
#define imx35_add_spi_imx0(pdata) \
#define imx35_add_esdhc0(pdata) \
imx_add_spi_imx(0, MX35_CSPI1_BASE_ADDR, SZ_4K, MX35_INT_CSPI1, pdata)
imx_add_esdhc(0, MX35_ESDHC1_BASE_ADDR, SZ_16K, MX35_INT_MMC_SDHC1, pdata)
#define imx35_add_spi_imx1(pdata) \
#define imx35_add_esdhc1(pdata) \
imx_add_spi_imx(1, MX35_CSPI2_BASE_ADDR, SZ_4K, MX35_INT_CSPI2, pdata)
imx_add_esdhc(1, MX35_ESDHC2_BASE_ADDR, SZ_16K, MX35_INT_MMC_SDHC2, pdata)
#define imx35_add_esdhc2(pdata) \
imx_add_esdhc(2, MX35_ESDHC3_BASE_ADDR, SZ_16K, MX35_INT_MMC_SDHC3, pdata)
arch/arm/mach-mx3/devices.c
View file @
c9ee46a9
...
@@ -281,65 +281,6 @@ struct platform_device mxc_usbh2 = {
...
@@ -281,65 +281,6 @@ struct platform_device mxc_usbh2 = {
.
num_resources
=
ARRAY_SIZE
(
mxc_usbh2_resources
),
.
num_resources
=
ARRAY_SIZE
(
mxc_usbh2_resources
),
};
};
#if defined(CONFIG_ARCH_MX35)
static
struct
resource
mxc_fec_resources
[]
=
{
{
.
start
=
MXC_FEC_BASE_ADDR
,
.
end
=
MXC_FEC_BASE_ADDR
+
0xfff
,
.
flags
=
IORESOURCE_MEM
,
},
{
.
start
=
MXC_INT_FEC
,
.
end
=
MXC_INT_FEC
,
.
flags
=
IORESOURCE_IRQ
,
},
};
struct
platform_device
mxc_fec_device
=
{
.
name
=
"fec"
,
.
id
=
0
,
.
num_resources
=
ARRAY_SIZE
(
mxc_fec_resources
),
.
resource
=
mxc_fec_resources
,
};
#endif
static
struct
resource
imx_ssi_resources0
[]
=
{
{
.
start
=
SSI1_BASE_ADDR
,
.
end
=
SSI1_BASE_ADDR
+
0xfff
,
.
flags
=
IORESOURCE_MEM
,
},
{
.
start
=
MX31_INT_SSI1
,
.
end
=
MX31_INT_SSI1
,
.
flags
=
IORESOURCE_IRQ
,
},
};
static
struct
resource
imx_ssi_resources1
[]
=
{
{
.
start
=
SSI2_BASE_ADDR
,
.
end
=
SSI2_BASE_ADDR
+
0xfff
,
.
flags
=
IORESOURCE_MEM
},
{
.
start
=
MX31_INT_SSI2
,
.
end
=
MX31_INT_SSI2
,
.
flags
=
IORESOURCE_IRQ
,
},
};
struct
platform_device
imx_ssi_device0
=
{
.
name
=
"imx-ssi"
,
.
id
=
0
,
.
num_resources
=
ARRAY_SIZE
(
imx_ssi_resources0
),
.
resource
=
imx_ssi_resources0
,
};
struct
platform_device
imx_ssi_device1
=
{
.
name
=
"imx-ssi"
,
.
id
=
1
,
.
num_resources
=
ARRAY_SIZE
(
imx_ssi_resources1
),
.
resource
=
imx_ssi_resources1
,
};
static
struct
resource
imx_wdt_resources
[]
=
{
static
struct
resource
imx_wdt_resources
[]
=
{
{
{
.
flags
=
IORESOURCE_MEM
,
.
flags
=
IORESOURCE_MEM
,
...
@@ -410,10 +351,6 @@ static int __init mx3_devices_init(void)
...
@@ -410,10 +351,6 @@ static int __init mx3_devices_init(void)
mxc_usbh1_resources
[
0
].
end
=
MX35_OTG_BASE_ADDR
+
0x5ff
;
mxc_usbh1_resources
[
0
].
end
=
MX35_OTG_BASE_ADDR
+
0x5ff
;
mxc_usbh1_resources
[
1
].
start
=
MXC_INT_USBHS
;
mxc_usbh1_resources
[
1
].
start
=
MXC_INT_USBHS
;
mxc_usbh1_resources
[
1
].
end
=
MXC_INT_USBHS
;
mxc_usbh1_resources
[
1
].
end
=
MXC_INT_USBHS
;
imx_ssi_resources0
[
1
].
start
=
MX35_INT_SSI1
;
imx_ssi_resources0
[
1
].
end
=
MX35_INT_SSI1
;
imx_ssi_resources1
[
1
].
start
=
MX35_INT_SSI2
;
imx_ssi_resources1
[
1
].
end
=
MX35_INT_SSI2
;
imx_wdt_resources
[
0
].
start
=
MX35_WDOG_BASE_ADDR
;
imx_wdt_resources
[
0
].
start
=
MX35_WDOG_BASE_ADDR
;
imx_wdt_resources
[
0
].
end
=
MX35_WDOG_BASE_ADDR
+
0x3fff
;
imx_wdt_resources
[
0
].
end
=
MX35_WDOG_BASE_ADDR
+
0x3fff
;
}
}
...
...
arch/arm/mach-mx3/devices.h
View file @
c9ee46a9
...
@@ -2,7 +2,6 @@ extern struct platform_device mxc_w1_master_device;
...
@@ -2,7 +2,6 @@ extern struct platform_device mxc_w1_master_device;
extern
struct
platform_device
mx3_ipu
;
extern
struct
platform_device
mx3_ipu
;
extern
struct
platform_device
mx3_fb
;
extern
struct
platform_device
mx3_fb
;
extern
struct
platform_device
mx3_camera
;
extern
struct
platform_device
mx3_camera
;
extern
struct
platform_device
mxc_fec_device
;
extern
struct
platform_device
mxcsdhc_device0
;
extern
struct
platform_device
mxcsdhc_device0
;
extern
struct
platform_device
mxcsdhc_device1
;
extern
struct
platform_device
mxcsdhc_device1
;
extern
struct
platform_device
mxc_otg_udc_device
;
extern
struct
platform_device
mxc_otg_udc_device
;
...
@@ -10,9 +9,6 @@ extern struct platform_device mxc_otg_host;
...
@@ -10,9 +9,6 @@ extern struct platform_device mxc_otg_host;
extern
struct
platform_device
mxc_usbh1
;
extern
struct
platform_device
mxc_usbh1
;
extern
struct
platform_device
mxc_usbh2
;
extern
struct
platform_device
mxc_usbh2
;
extern
struct
platform_device
mxc_rnga_device
;
extern
struct
platform_device
mxc_rnga_device
;
extern
struct
platform_device
imx_ssi_device0
;
extern
struct
platform_device
imx_ssi_device1
;
extern
struct
platform_device
imx_ssi_device1
;
extern
struct
platform_device
imx_wdt_device0
;
extern
struct
platform_device
imx_wdt_device0
;
extern
struct
platform_device
imx_rtc_device0
;
extern
struct
platform_device
imx_rtc_device0
;
extern
struct
platform_device
imx_kpp_device
;
extern
struct
platform_device
imx_kpp_device
;
arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c
View file @
c9ee46a9
...
@@ -43,7 +43,6 @@
...
@@ -43,7 +43,6 @@
#include <mach/ipu.h>
#include <mach/ipu.h>
#include <mach/mx3fb.h>
#include <mach/mx3fb.h>
#include <mach/audmux.h>
#include <mach/audmux.h>
#include <mach/ssi.h>
#include "devices-imx35.h"
#include "devices-imx35.h"
#include "devices.h"
#include "devices.h"
...
@@ -120,6 +119,16 @@ static struct pad_desc eukrea_mbimxsd_pads[] = {
...
@@ -120,6 +119,16 @@ static struct pad_desc eukrea_mbimxsd_pads[] = {
MX35_PAD_STXD4__AUDMUX_AUD4_TXD
,
MX35_PAD_STXD4__AUDMUX_AUD4_TXD
,
MX35_PAD_SRXD4__AUDMUX_AUD4_RXD
,
MX35_PAD_SRXD4__AUDMUX_AUD4_RXD
,
MX35_PAD_SCK4__AUDMUX_AUD4_TXC
,
MX35_PAD_SCK4__AUDMUX_AUD4_TXC
,
/* CAN2 */
MX35_PAD_TX5_RX0__CAN2_TXCAN
,
MX35_PAD_TX4_RX1__CAN2_RXCAN
,
/* SDCARD */
MX35_PAD_SD1_CMD__ESDHC1_CMD
,
MX35_PAD_SD1_CLK__ESDHC1_CLK
,
MX35_PAD_SD1_DATA0__ESDHC1_DAT0
,
MX35_PAD_SD1_DATA1__ESDHC1_DAT1
,
MX35_PAD_SD1_DATA2__ESDHC1_DAT2
,
MX35_PAD_SD1_DATA3__ESDHC1_DAT3
,
};
};
#define GPIO_LED1 (2 * 32 + 29)
#define GPIO_LED1 (2 * 32 + 29)
...
@@ -206,7 +215,8 @@ static struct i2c_board_info eukrea_mbimxsd_i2c_devices[] = {
...
@@ -206,7 +215,8 @@ static struct i2c_board_info eukrea_mbimxsd_i2c_devices[] = {
},
},
};
};
struct
imx_ssi_platform_data
eukrea_mbimxsd_ssi_pdata
=
{
static
const
struct
imx_ssi_platform_data
eukrea_mbimxsd_ssi_pdata
__initconst
=
{
.
flags
=
IMX_SSI_SYN
|
IMX_SSI_NET
|
IMX_SSI_USE_I2S_SLAVE
,
.
flags
=
IMX_SSI_SYN
|
IMX_SSI_NET
|
IMX_SSI_USE_I2S_SLAVE
,
};
};
...
@@ -242,7 +252,10 @@ void __init eukrea_mbimxsd35_baseboard_init(void)
...
@@ -242,7 +252,10 @@ void __init eukrea_mbimxsd35_baseboard_init(void)
mxc_register_device
(
&
mx3_ipu
,
&
mx3_ipu_data
);
mxc_register_device
(
&
mx3_ipu
,
&
mx3_ipu_data
);
mxc_register_device
(
&
mx3_fb
,
&
mx3fb_pdata
);
mxc_register_device
(
&
mx3_fb
,
&
mx3fb_pdata
);
mxc_register_device
(
&
imx_ssi_device0
,
&
eukrea_mbimxsd_ssi_pdata
);
imx35_add_imx_ssi
(
0
,
&
eukrea_mbimxsd_ssi_pdata
);
imx35_add_flexcan1
(
NULL
);
imx35_add_esdhc0
(
NULL
);
gpio_request
(
GPIO_LED1
,
"LED1"
);
gpio_request
(
GPIO_LED1
,
"LED1"
);
gpio_direction_output
(
GPIO_LED1
,
1
);
gpio_direction_output
(
GPIO_LED1
,
1
);
...
...
arch/arm/mach-mx3/mach-cpuimx35.c
View file @
c9ee46a9
...
@@ -31,6 +31,7 @@
...
@@ -31,6 +31,7 @@
#include <linux/usb/otg.h>
#include <linux/usb/otg.h>
#include <linux/usb/ulpi.h>
#include <linux/usb/ulpi.h>
#include <linux/fsl_devices.h>
#include <linux/fsl_devices.h>
#include <linux/i2c-gpio.h>
#include <asm/mach-types.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/arch.h>
...
@@ -53,39 +54,16 @@ static const struct imxuart_platform_data uart_pdata __initconst = {
...
@@ -53,39 +54,16 @@ static const struct imxuart_platform_data uart_pdata __initconst = {
};
};
static
const
struct
imxi2c_platform_data
static
const
struct
imxi2c_platform_data
eukrea_cpuimx35_i2c0_data
__initconst
=
{
eukrea_cpuimx35_i2c0_data
__initconst
=
{
.
bitrate
=
5
0000
,
.
bitrate
=
10
0000
,
};
};
#define TSC2007_IRQGPIO (2 * 32 + 2)
static
int
ts_get_pendown_state
(
void
)
{
int
val
=
0
;
gpio_free
(
TSC2007_IRQGPIO
);
gpio_request
(
TSC2007_IRQGPIO
,
NULL
);
gpio_direction_input
(
TSC2007_IRQGPIO
);
val
=
gpio_get_value
(
TSC2007_IRQGPIO
);
gpio_free
(
TSC2007_IRQGPIO
);
gpio_request
(
TSC2007_IRQGPIO
,
NULL
);
return
val
?
0
:
1
;
}
static
int
ts_init
(
void
)
{
gpio_request
(
TSC2007_IRQGPIO
,
NULL
);
return
0
;
}
static
struct
tsc2007_platform_data
tsc2007_info
=
{
static
struct
tsc2007_platform_data
tsc2007_info
=
{
.
model
=
2007
,
.
model
=
2007
,
.
x_plate_ohms
=
180
,
.
x_plate_ohms
=
180
,
.
get_pendown_state
=
ts_get_pendown_state
,
.
init_platform_hw
=
ts_init
,
};
};
#define TSC2007_IRQGPIO (2 * 32 + 2)
static
struct
i2c_board_info
eukrea_cpuimx35_i2c_devices
[]
=
{
static
struct
i2c_board_info
eukrea_cpuimx35_i2c_devices
[]
=
{
{
{
I2C_BOARD_INFO
(
"pcf8563"
,
0x51
),
I2C_BOARD_INFO
(
"pcf8563"
,
0x51
),
...
@@ -98,7 +76,6 @@ static struct i2c_board_info eukrea_cpuimx35_i2c_devices[] = {
...
@@ -98,7 +76,6 @@ static struct i2c_board_info eukrea_cpuimx35_i2c_devices[] = {
};
};
static
struct
platform_device
*
devices
[]
__initdata
=
{
static
struct
platform_device
*
devices
[]
__initdata
=
{
&
mxc_fec_device
,
&
imx_wdt_device0
,
&
imx_wdt_device0
,
};
};
...
@@ -135,18 +112,18 @@ static struct pad_desc eukrea_cpuimx35_pads[] = {
...
@@ -135,18 +112,18 @@ static struct pad_desc eukrea_cpuimx35_pads[] = {
};
};
static
const
struct
mxc_nand_platform_data
static
const
struct
mxc_nand_platform_data
eukrea_cpuimx35_nand_board_info
__initconst
=
{
eukrea_cpuimx35_nand_board_info
__initconst
=
{
.
width
=
1
,
.
width
=
1
,
.
hw_ecc
=
1
,
.
hw_ecc
=
1
,
.
flash_bbt
=
1
,
.
flash_bbt
=
1
,
};
};
static
struct
mxc_usbh_platform_data
otg_pdata
=
{
static
struct
mxc_usbh_platform_data
__maybe_unused
otg_pdata
=
{
.
portsc
=
MXC_EHCI_MODE_UTMI
,
.
portsc
=
MXC_EHCI_MODE_UTMI
,
.
flags
=
MXC_EHCI_INTERFACE_DIFF_UNI
,
.
flags
=
MXC_EHCI_INTERFACE_DIFF_UNI
,
};
};
static
struct
mxc_usbh_platform_data
usbh1_pdata
=
{
static
struct
mxc_usbh_platform_data
__maybe_unused
usbh1_pdata
=
{
.
portsc
=
MXC_EHCI_MODE_SERIAL
,
.
portsc
=
MXC_EHCI_MODE_SERIAL
,
.
flags
=
MXC_EHCI_INTERFACE_SINGLE_UNI
|
MXC_EHCI_INTERNAL_PHY
|
.
flags
=
MXC_EHCI_INTERFACE_SINGLE_UNI
|
MXC_EHCI_INTERNAL_PHY
|
MXC_EHCI_IPPUE_DOWN
,
MXC_EHCI_IPPUE_DOWN
,
...
@@ -180,6 +157,7 @@ static void __init mxc_board_init(void)
...
@@ -180,6 +157,7 @@ static void __init mxc_board_init(void)
mxc_iomux_v3_setup_multiple_pads
(
eukrea_cpuimx35_pads
,
mxc_iomux_v3_setup_multiple_pads
(
eukrea_cpuimx35_pads
,
ARRAY_SIZE
(
eukrea_cpuimx35_pads
));
ARRAY_SIZE
(
eukrea_cpuimx35_pads
));
imx35_add_fec
(
NULL
);
platform_add_devices
(
devices
,
ARRAY_SIZE
(
devices
));
platform_add_devices
(
devices
,
ARRAY_SIZE
(
devices
));
imx35_add_imx_uart0
(
&
uart_pdata
);
imx35_add_imx_uart0
(
&
uart_pdata
);
...
...
arch/arm/mach-mx3/mach-mx31ads.c
View file @
c9ee46a9
...
@@ -517,7 +517,7 @@ static unsigned int ssi_pins[] = {
...
@@ -517,7 +517,7 @@ static unsigned int ssi_pins[] = {
static
void
mxc_init_audio
(
void
)
static
void
mxc_init_audio
(
void
)
{
{
mxc_register_device
(
&
imx_ssi_device
0
,
NULL
);
imx31_add_imx_ssi
(
0
,
NULL
);
mxc_iomux_setup_multiple_pins
(
ssi_pins
,
ARRAY_SIZE
(
ssi_pins
),
"ssi"
);
mxc_iomux_setup_multiple_pins
(
ssi_pins
,
ARRAY_SIZE
(
ssi_pins
),
"ssi"
);
}
}
...
...
arch/arm/mach-mx3/mach-mx35_3ds.c
View file @
c9ee46a9
/*
/*
* Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright (C) 2009 Marc Kleine-Budde, Pengutronix
*
*
* Author: Fabio Estevam <fabio.estevam@freescale.com>
* Author: Fabio Estevam <fabio.estevam@freescale.com>
*
*
...
@@ -27,6 +28,8 @@
...
@@ -27,6 +28,8 @@
#include <linux/gpio.h>
#include <linux/gpio.h>
#include <linux/fsl_devices.h>
#include <linux/fsl_devices.h>
#include <linux/mtd/physmap.h>
#include <asm/mach-types.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <asm/mach/time.h>
...
@@ -35,6 +38,7 @@
...
@@ -35,6 +38,7 @@
#include <mach/hardware.h>
#include <mach/hardware.h>
#include <mach/common.h>
#include <mach/common.h>
#include <mach/iomux-mx35.h>
#include <mach/iomux-mx35.h>
#include <mach/mxc_ehci.h>
#include "devices-imx35.h"
#include "devices-imx35.h"
#include "devices.h"
#include "devices.h"
...
@@ -43,8 +47,34 @@ static const struct imxuart_platform_data uart_pdata __initconst = {
...
@@ -43,8 +47,34 @@ static const struct imxuart_platform_data uart_pdata __initconst = {
.
flags
=
IMXUART_HAVE_RTSCTS
,
.
flags
=
IMXUART_HAVE_RTSCTS
,
};
};
static
struct
physmap_flash_data
mx35pdk_flash_data
=
{
.
width
=
2
,
};
static
struct
resource
mx35pdk_flash_resource
=
{
.
start
=
MX35_CS0_BASE_ADDR
,
.
end
=
MX35_CS0_BASE_ADDR
+
SZ_64M
-
1
,
.
flags
=
IORESOURCE_MEM
,
};
static
struct
platform_device
mx35pdk_flash
=
{
.
name
=
"physmap-flash"
,
.
id
=
0
,
.
dev
=
{
.
platform_data
=
&
mx35pdk_flash_data
,
},
.
resource
=
&
mx35pdk_flash_resource
,
.
num_resources
=
1
,
};
static
const
struct
mxc_nand_platform_data
mx35pdk_nand_board_info
__initconst
=
{
.
width
=
1
,
.
hw_ecc
=
1
,
.
flash_bbt
=
1
,
};
static
struct
platform_device
*
devices
[]
__initdata
=
{
static
struct
platform_device
*
devices
[]
__initdata
=
{
&
mx
c_fec_device
,
&
mx
35pdk_flash
,
};
};
static
struct
pad_desc
mx35pdk_pads
[]
=
{
static
struct
pad_desc
mx35pdk_pads
[]
=
{
...
@@ -75,14 +105,24 @@ static struct pad_desc mx35pdk_pads[] = {
...
@@ -75,14 +105,24 @@ static struct pad_desc mx35pdk_pads[] = {
/* USBOTG */
/* USBOTG */
MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR
,
MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR
,
MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC
,
MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC
,
/* USBH1 */
MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR
,
MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC
,
};
};
/* OTG config */
/* OTG config */
static
struct
fsl_usb2_platform_data
usb_pdata
=
{
static
struct
fsl_usb2_platform_data
usb_
otg_
pdata
=
{
.
operating_mode
=
FSL_USB2_DR_DEVICE
,
.
operating_mode
=
FSL_USB2_DR_DEVICE
,
.
phy_mode
=
FSL_USB2_PHY_UTMI_WIDE
,
.
phy_mode
=
FSL_USB2_PHY_UTMI_WIDE
,
};
};
/* USB HOST config */
static
struct
mxc_usbh_platform_data
usb_host_pdata
=
{
.
portsc
=
MXC_EHCI_MODE_SERIAL
,
.
flags
=
MXC_EHCI_INTERFACE_SINGLE_UNI
|
MXC_EHCI_INTERNAL_PHY
,
};
/*
/*
* Board specific initialization.
* Board specific initialization.
*/
*/
...
@@ -90,11 +130,16 @@ static void __init mxc_board_init(void)
...
@@ -90,11 +130,16 @@ static void __init mxc_board_init(void)
{
{
mxc_iomux_v3_setup_multiple_pads
(
mx35pdk_pads
,
ARRAY_SIZE
(
mx35pdk_pads
));
mxc_iomux_v3_setup_multiple_pads
(
mx35pdk_pads
,
ARRAY_SIZE
(
mx35pdk_pads
));
imx35_add_fec
(
NULL
);
platform_add_devices
(
devices
,
ARRAY_SIZE
(
devices
));
platform_add_devices
(
devices
,
ARRAY_SIZE
(
devices
));
imx35_add_imx_uart0
(
&
uart_pdata
);
imx35_add_imx_uart0
(
&
uart_pdata
);
mxc_register_device
(
&
mxc_otg_udc_device
,
&
usb_pdata
);
mxc_register_device
(
&
mxc_otg_udc_device
,
&
usb_otg_pdata
);
mxc_register_device
(
&
mxc_usbh1
,
&
usb_host_pdata
);
imx35_add_mxc_nand
(
&
mx35pdk_nand_board_info
);
}
}
static
void
__init
mx35pdk_timer_init
(
void
)
static
void
__init
mx35pdk_timer_init
(
void
)
...
...
arch/arm/mach-mx3/mach-pcm043.c
View file @
c9ee46a9
...
@@ -42,7 +42,6 @@
...
@@ -42,7 +42,6 @@
#include <mach/mxc_ehci.h>
#include <mach/mxc_ehci.h>
#include <mach/ulpi.h>
#include <mach/ulpi.h>
#include <mach/audmux.h>
#include <mach/audmux.h>
#include <mach/ssi.h>
#include "devices-imx35.h"
#include "devices-imx35.h"
#include "devices.h"
#include "devices.h"
...
@@ -141,7 +140,6 @@ static struct i2c_board_info pcm043_i2c_devices[] = {
...
@@ -141,7 +140,6 @@ static struct i2c_board_info pcm043_i2c_devices[] = {
static
struct
platform_device
*
devices
[]
__initdata
=
{
static
struct
platform_device
*
devices
[]
__initdata
=
{
&
pcm043_flash
,
&
pcm043_flash
,
&
mxc_fec_device
,
&
imx_wdt_device0
,
&
imx_wdt_device0
,
};
};
...
@@ -217,6 +215,13 @@ static struct pad_desc pcm043_pads[] = {
...
@@ -217,6 +215,13 @@ static struct pad_desc pcm043_pads[] = {
/* CAN2 */
/* CAN2 */
MX35_PAD_TX5_RX0__CAN2_TXCAN
,
MX35_PAD_TX5_RX0__CAN2_TXCAN
,
MX35_PAD_TX4_RX1__CAN2_RXCAN
,
MX35_PAD_TX4_RX1__CAN2_RXCAN
,
/* esdhc */
MX35_PAD_SD1_CMD__ESDHC1_CMD
,
MX35_PAD_SD1_CLK__ESDHC1_CLK
,
MX35_PAD_SD1_DATA0__ESDHC1_DAT0
,
MX35_PAD_SD1_DATA1__ESDHC1_DAT1
,
MX35_PAD_SD1_DATA2__ESDHC1_DAT2
,
MX35_PAD_SD1_DATA3__ESDHC1_DAT3
,
};
};
#define AC97_GPIO_TXFS (1 * 32 + 31)
#define AC97_GPIO_TXFS (1 * 32 + 31)
...
@@ -293,7 +298,7 @@ static void pcm043_ac97_cold_reset(struct snd_ac97 *ac97)
...
@@ -293,7 +298,7 @@ static void pcm043_ac97_cold_reset(struct snd_ac97 *ac97)
mdelay
(
1
);
mdelay
(
1
);
}
}
static
struct
imx_ssi_platform_data
pcm043_ssi_pdata
=
{
static
const
struct
imx_ssi_platform_data
pcm043_ssi_pdata
__initconst
=
{
.
ac97_reset
=
pcm043_ac97_cold_reset
,
.
ac97_reset
=
pcm043_ac97_cold_reset
,
.
ac97_warm_reset
=
pcm043_ac97_warm_reset
,
.
ac97_warm_reset
=
pcm043_ac97_warm_reset
,
.
flags
=
IMX_SSI_USE_AC97
,
.
flags
=
IMX_SSI_USE_AC97
,
...
@@ -357,11 +362,12 @@ static void __init mxc_board_init(void)
...
@@ -357,11 +362,12 @@ static void __init mxc_board_init(void)
MXC_AUDMUX_V2_PTCR_TCLKDIR
,
/* clock is output */
MXC_AUDMUX_V2_PTCR_TCLKDIR
,
/* clock is output */
MXC_AUDMUX_V2_PDCR_RXDSEL
(
3
));
MXC_AUDMUX_V2_PDCR_RXDSEL
(
3
));
imx35_add_fec
(
NULL
);
platform_add_devices
(
devices
,
ARRAY_SIZE
(
devices
));
platform_add_devices
(
devices
,
ARRAY_SIZE
(
devices
));
imx35_add_imx_uart0
(
&
uart_pdata
);
imx35_add_imx_uart0
(
&
uart_pdata
);
imx35_add_mxc_nand
(
&
pcm037_nand_board_info
);
imx35_add_mxc_nand
(
&
pcm037_nand_board_info
);
mxc_register_device
(
&
imx_ssi_device
0
,
&
pcm043_ssi_pdata
);
imx35_add_imx_ssi
(
0
,
&
pcm043_ssi_pdata
);
imx35_add_imx_uart1
(
&
uart_pdata
);
imx35_add_imx_uart1
(
&
uart_pdata
);
...
@@ -389,6 +395,7 @@ static void __init mxc_board_init(void)
...
@@ -389,6 +395,7 @@ static void __init mxc_board_init(void)
mxc_register_device
(
&
mxc_otg_udc_device
,
&
otg_device_pdata
);
mxc_register_device
(
&
mxc_otg_udc_device
,
&
otg_device_pdata
);
imx35_add_flexcan1
(
NULL
);
imx35_add_flexcan1
(
NULL
);
imx35_add_esdhc0
(
NULL
);
}
}
static
void
__init
pcm043_timer_init
(
void
)
static
void
__init
pcm043_timer_init
(
void
)
...
...
arch/arm/mach-mx3/mm.c
View file @
c9ee46a9
...
@@ -110,6 +110,24 @@ void __init mx35_init_irq(void)
...
@@ -110,6 +110,24 @@ void __init mx35_init_irq(void)
static
int
mxc_init_l2x0
(
void
)
static
int
mxc_init_l2x0
(
void
)
{
{
void
__iomem
*
l2x0_base
;
void
__iomem
*
l2x0_base
;
void
__iomem
*
clkctl_base
;
/*
* First of all, we must repair broken chip settings. There are some
* i.MX35 CPUs in the wild, comming with bogus L2 cache settings. These
* misconfigured CPUs will run amok immediately when the L2 cache gets enabled.
* Workaraound is to setup the correct register setting prior enabling the
* L2 cache. This should not hurt already working CPUs, as they are using the
* same value
*/
#define L2_MEM_VAL 0x10
clkctl_base
=
ioremap
(
MX35_CLKCTL_BASE_ADDR
,
4096
);
if
(
clkctl_base
!=
NULL
)
{
writel
(
0x00000515
,
clkctl_base
+
L2_MEM_VAL
);
iounmap
(
clkctl_base
);
}
else
{
pr_err
(
"L2 cache: Cannot fix timing. Trying to continue without
\n
"
);
}
l2x0_base
=
ioremap
(
L2CC_BASE_ADDR
,
4096
);
l2x0_base
=
ioremap
(
L2CC_BASE_ADDR
,
4096
);
if
(
IS_ERR
(
l2x0_base
))
{
if
(
IS_ERR
(
l2x0_base
))
{
...
...
arch/arm/mach-mx5/Kconfig
View file @
c9ee46a9
...
@@ -5,11 +5,14 @@ config ARCH_MX51
...
@@ -5,11 +5,14 @@ config ARCH_MX51
default y
default y
select MXC_TZIC
select MXC_TZIC
select ARCH_MXC_IOMUX_V3
select ARCH_MXC_IOMUX_V3
select ARCH_MXC_AUDMUX_V2
comment "MX5 platforms:"
comment "MX5 platforms:"
config MACH_MX51_BABBAGE
config MACH_MX51_BABBAGE
bool "Support MX51 BABBAGE platforms"
bool "Support MX51 BABBAGE platforms"
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
help
help
Include support for MX51 Babbage platform, also known as MX51EVK in
Include support for MX51 Babbage platform, also known as MX51EVK in
u-boot. This includes specific configurations for the board and its
u-boot. This includes specific configurations for the board and its
...
@@ -17,6 +20,8 @@ config MACH_MX51_BABBAGE
...
@@ -17,6 +20,8 @@ config MACH_MX51_BABBAGE
config MACH_MX51_3DS
config MACH_MX51_3DS
bool "Support MX51PDK (3DS)"
bool "Support MX51PDK (3DS)"
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_SPI_IMX
select MXC_DEBUG_BOARD
select MXC_DEBUG_BOARD
help
help
Include support for MX51PDK (3DS) platform. This includes specific
Include support for MX51PDK (3DS) platform. This includes specific
...
@@ -24,6 +29,8 @@ config MACH_MX51_3DS
...
@@ -24,6 +29,8 @@ config MACH_MX51_3DS
config MACH_EUKREA_CPUIMX51
config MACH_EUKREA_CPUIMX51
bool "Support Eukrea CPUIMX51 module"
bool "Support Eukrea CPUIMX51 module"
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
help
help
Include support for Eukrea CPUIMX51 platform. This includes
Include support for Eukrea CPUIMX51 platform. This includes
specific configurations for the module and its peripherals.
specific configurations for the module and its peripherals.
...
@@ -42,4 +49,11 @@ config MACH_EUKREA_MBIMX51_BASEBOARD
...
@@ -42,4 +49,11 @@ config MACH_EUKREA_MBIMX51_BASEBOARD
endchoice
endchoice
config MACH_MX51_EFIKAMX
bool "Support MX51 Genesi Efika MX nettop"
select IMX_HAVE_PLATFORM_IMX_UART
help
Include support for Genesi Efika MX nettop. This includes specific
configurations for the board and its peripherals.
endif
endif
arch/arm/mach-mx5/Makefile
View file @
c9ee46a9
...
@@ -9,3 +9,4 @@ obj-$(CONFIG_MACH_MX51_BABBAGE) += board-mx51_babbage.o
...
@@ -9,3 +9,4 @@ obj-$(CONFIG_MACH_MX51_BABBAGE) += board-mx51_babbage.o
obj-$(CONFIG_MACH_MX51_3DS)
+=
board-mx51_3ds.o
obj-$(CONFIG_MACH_MX51_3DS)
+=
board-mx51_3ds.o
obj-$(CONFIG_MACH_EUKREA_CPUIMX51)
+=
board-cpuimx51.o
obj-$(CONFIG_MACH_EUKREA_CPUIMX51)
+=
board-cpuimx51.o
obj-$(CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD)
+=
eukrea_mbimx51-baseboard.o
obj-$(CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD)
+=
eukrea_mbimx51-baseboard.o
obj-$(CONFIG_MACH_MX51_EFIKAMX)
+=
board-mx51_efikamx.o
arch/arm/mach-mx5/board-cpuimx51.c
View file @
c9ee46a9
...
@@ -28,9 +28,7 @@
...
@@ -28,9 +28,7 @@
#include <mach/eukrea-baseboards.h>
#include <mach/eukrea-baseboards.h>
#include <mach/common.h>
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/hardware.h>
#include <mach/imx-uart.h>
#include <mach/iomux-mx51.h>
#include <mach/iomux-mx51.h>
#include <mach/i2c.h>
#include <mach/mxc_ehci.h>
#include <mach/mxc_ehci.h>
#include <asm/irq.h>
#include <asm/irq.h>
...
@@ -39,6 +37,7 @@
...
@@ -39,6 +37,7 @@
#include <asm/mach/arch.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <asm/mach/time.h>
#include "devices-imx51.h"
#include "devices.h"
#include "devices.h"
#define CPUIMX51_USBH1_STP (0*32 + 27)
#define CPUIMX51_USBH1_STP (0*32 + 27)
...
@@ -109,7 +108,6 @@ static struct platform_device serial_device = {
...
@@ -109,7 +108,6 @@ static struct platform_device serial_device = {
#endif
#endif
static
struct
platform_device
*
devices
[]
__initdata
=
{
static
struct
platform_device
*
devices
[]
__initdata
=
{
&
mxc_fec_device
,
#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
&
serial_device
,
&
serial_device
,
#endif
#endif
...
@@ -148,11 +146,12 @@ static struct pad_desc eukrea_cpuimx51_pads[] = {
...
@@ -148,11 +146,12 @@ static struct pad_desc eukrea_cpuimx51_pads[] = {
MX51_PAD_USBH1_STP__USBH1_STP
,
MX51_PAD_USBH1_STP__USBH1_STP
,
};
};
static
struct
imxuart_platform_data
uart_pdata
=
{
static
const
struct
imxuart_platform_data
uart_pdata
__initconst
=
{
.
flags
=
IMXUART_HAVE_RTSCTS
,
.
flags
=
IMXUART_HAVE_RTSCTS
,
};
};
static
struct
imxi2c_platform_data
eukrea_cpuimx51_i2c_data
=
{
static
const
struct
imxi2c_platform_data
eukrea_cpuimx51_i2c_data
__initconst
=
{
.
bitrate
=
100000
,
.
bitrate
=
100000
,
};
};
...
@@ -239,7 +238,7 @@ static void __init eukrea_cpuimx51_init(void)
...
@@ -239,7 +238,7 @@ static void __init eukrea_cpuimx51_init(void)
mxc_iomux_v3_setup_multiple_pads
(
eukrea_cpuimx51_pads
,
mxc_iomux_v3_setup_multiple_pads
(
eukrea_cpuimx51_pads
,
ARRAY_SIZE
(
eukrea_cpuimx51_pads
));
ARRAY_SIZE
(
eukrea_cpuimx51_pads
));
mxc_register_device
(
&
mxc_uart_device
0
,
&
uart_pdata
);
imx51_add_imx_uart
(
0
,
&
uart_pdata
);
gpio_request
(
CPUIMX51_QUARTA_GPIO
,
"quarta_irq"
);
gpio_request
(
CPUIMX51_QUARTA_GPIO
,
"quarta_irq"
);
gpio_direction_input
(
CPUIMX51_QUARTA_GPIO
);
gpio_direction_input
(
CPUIMX51_QUARTA_GPIO
);
gpio_free
(
CPUIMX51_QUARTA_GPIO
);
gpio_free
(
CPUIMX51_QUARTA_GPIO
);
...
@@ -253,9 +252,10 @@ static void __init eukrea_cpuimx51_init(void)
...
@@ -253,9 +252,10 @@ static void __init eukrea_cpuimx51_init(void)
gpio_direction_input
(
CPUIMX51_QUARTD_GPIO
);
gpio_direction_input
(
CPUIMX51_QUARTD_GPIO
);
gpio_free
(
CPUIMX51_QUARTD_GPIO
);
gpio_free
(
CPUIMX51_QUARTD_GPIO
);
imx51_add_fec
(
NULL
);
platform_add_devices
(
devices
,
ARRAY_SIZE
(
devices
));
platform_add_devices
(
devices
,
ARRAY_SIZE
(
devices
));
mxc_register_device
(
&
mxc_i2c_device
1
,
&
eukrea_cpuimx51_i2c_data
);
imx51_add_imx_i2c
(
1
,
&
eukrea_cpuimx51_i2c_data
);
i2c_register_board_info
(
1
,
eukrea_cpuimx51_i2c_devices
,
i2c_register_board_info
(
1
,
eukrea_cpuimx51_i2c_devices
,
ARRAY_SIZE
(
eukrea_cpuimx51_i2c_devices
));
ARRAY_SIZE
(
eukrea_cpuimx51_i2c_devices
));
...
...
arch/arm/mach-mx5/board-mx51_3ds.c
View file @
c9ee46a9
...
@@ -13,6 +13,7 @@
...
@@ -13,6 +13,7 @@
#include <linux/irq.h>
#include <linux/irq.h>
#include <linux/platform_device.h>
#include <linux/platform_device.h>
#include <linux/input/matrix_keypad.h>
#include <linux/input/matrix_keypad.h>
#include <linux/spi/spi.h>
#include <asm/mach-types.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/arch.h>
...
@@ -21,12 +22,13 @@
...
@@ -21,12 +22,13 @@
#include <mach/hardware.h>
#include <mach/hardware.h>
#include <mach/common.h>
#include <mach/common.h>
#include <mach/iomux-mx51.h>
#include <mach/iomux-mx51.h>
#include <mach/imx-uart.h>
#include <mach/3ds_debugboard.h>
#include <mach/3ds_debugboard.h>
#include "devices-imx51.h"
#include "devices.h"
#include "devices.h"
#define EXPIO_PARENT_INT (MXC_INTERNAL_IRQS + GPIO_PORTA + 6)
#define EXPIO_PARENT_INT (MXC_INTERNAL_IRQS + GPIO_PORTA + 6)
#define MX51_3DS_ECSPI2_CS (GPIO_PORTC + 28)
static
struct
pad_desc
mx51_3ds_pads
[]
=
{
static
struct
pad_desc
mx51_3ds_pads
[]
=
{
/* UART1 */
/* UART1 */
...
@@ -61,19 +63,25 @@ static struct pad_desc mx51_3ds_pads[] = {
...
@@ -61,19 +63,25 @@ static struct pad_desc mx51_3ds_pads[] = {
MX51_PAD_KEY_COL3__KEY_COL3
,
MX51_PAD_KEY_COL3__KEY_COL3
,
MX51_PAD_KEY_COL4__KEY_COL4
,
MX51_PAD_KEY_COL4__KEY_COL4
,
MX51_PAD_KEY_COL5__KEY_COL5
,
MX51_PAD_KEY_COL5__KEY_COL5
,
/* eCSPI2 */
MX51_PAD_NANDF_RB2__ECSPI2_SCLK
,
MX51_PAD_NANDF_RB3__ECSPI2_MISO
,
MX51_PAD_NANDF_D15__ECSPI2_MOSI
,
MX51_PAD_NANDF_D12__GPIO_3_28
,
};
};
/* Serial ports */
/* Serial ports */
#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
static
struct
imxuart_platform_data
uart_pdata
=
{
static
const
struct
imxuart_platform_data
uart_pdata
__initconst
=
{
.
flags
=
IMXUART_HAVE_RTSCTS
,
.
flags
=
IMXUART_HAVE_RTSCTS
,
};
};
static
inline
void
mxc_init_imx_uart
(
void
)
static
inline
void
mxc_init_imx_uart
(
void
)
{
{
mxc_register_device
(
&
mxc_uart_device
0
,
&
uart_pdata
);
imx51_add_imx_uart
(
0
,
&
uart_pdata
);
mxc_register_device
(
&
mxc_uart_device
1
,
&
uart_pdata
);
imx51_add_imx_uart
(
1
,
&
uart_pdata
);
mxc_register_device
(
&
mxc_uart_device
2
,
&
uart_pdata
);
imx51_add_imx_uart
(
2
,
&
uart_pdata
);
}
}
#else
/* !SERIAL_IMX */
#else
/* !SERIAL_IMX */
static
inline
void
mxc_init_imx_uart
(
void
)
static
inline
void
mxc_init_imx_uart
(
void
)
...
@@ -127,6 +135,26 @@ static inline void mxc_init_keypad(void)
...
@@ -127,6 +135,26 @@ static inline void mxc_init_keypad(void)
}
}
#endif
#endif
static
int
mx51_3ds_spi2_cs
[]
=
{
MXC_SPI_CS
(
0
),
MX51_3DS_ECSPI2_CS
,
};
static
const
struct
spi_imx_master
mx51_3ds_ecspi2_pdata
__initconst
=
{
.
chipselect
=
mx51_3ds_spi2_cs
,
.
num_chipselect
=
ARRAY_SIZE
(
mx51_3ds_spi2_cs
),
};
static
struct
spi_board_info
mx51_3ds_spi_nor_device
[]
=
{
{
.
modalias
=
"m25p80"
,
.
max_speed_hz
=
25000000
,
/* max spi clock (SCK) speed in HZ */
.
bus_num
=
1
,
.
chip_select
=
1
,
.
mode
=
SPI_MODE_0
,
.
platform_data
=
NULL
,},
};
/*
/*
* Board specific initialization.
* Board specific initialization.
*/
*/
...
@@ -136,6 +164,10 @@ static void __init mxc_board_init(void)
...
@@ -136,6 +164,10 @@ static void __init mxc_board_init(void)
ARRAY_SIZE
(
mx51_3ds_pads
));
ARRAY_SIZE
(
mx51_3ds_pads
));
mxc_init_imx_uart
();
mxc_init_imx_uart
();
imx51_add_ecspi
(
1
,
&
mx51_3ds_ecspi2_pdata
);
spi_register_board_info
(
mx51_3ds_spi_nor_device
,
ARRAY_SIZE
(
mx51_3ds_spi_nor_device
));
if
(
mxc_expio_init
(
MX51_CS5_BASE_ADDR
,
EXPIO_PARENT_INT
))
if
(
mxc_expio_init
(
MX51_CS5_BASE_ADDR
,
EXPIO_PARENT_INT
))
printk
(
KERN_WARNING
"Init of the debugboard failed, all "
printk
(
KERN_WARNING
"Init of the debugboard failed, all "
"devices on the board are unusable.
\n
"
);
"devices on the board are unusable.
\n
"
);
...
...
arch/arm/mach-mx5/board-mx51_babbage.c
View file @
c9ee46a9
...
@@ -17,12 +17,11 @@
...
@@ -17,12 +17,11 @@
#include <linux/delay.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/io.h>
#include <linux/fsl_devices.h>
#include <linux/fsl_devices.h>
#include <linux/fec.h>
#include <mach/common.h>
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/hardware.h>
#include <mach/imx-uart.h>
#include <mach/iomux-mx51.h>
#include <mach/iomux-mx51.h>
#include <mach/i2c.h>
#include <mach/mxc_ehci.h>
#include <mach/mxc_ehci.h>
#include <asm/irq.h>
#include <asm/irq.h>
...
@@ -31,11 +30,13 @@
...
@@ -31,11 +30,13 @@
#include <asm/mach/arch.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <asm/mach/time.h>
#include "devices-imx51.h"
#include "devices.h"
#include "devices.h"
#define BABBAGE_USB_HUB_RESET (0*32 + 7)
/* GPIO_1_7 */
#define BABBAGE_USB_HUB_RESET (0*32 + 7)
/* GPIO_1_7 */
#define BABBAGE_USBH1_STP (0*32 + 27)
/* GPIO_1_27 */
#define BABBAGE_USBH1_STP (0*32 + 27)
/* GPIO_1_27 */
#define BABBAGE_PHY_RESET (1*32 +5)
/* GPIO_2_5 */
#define BABBAGE_PHY_RESET (1*32 + 5)
/* GPIO_2_5 */
#define BABBAGE_FEC_PHY_RESET (1*32 + 14)
/* GPIO_2_14 */
/* USB_CTRL_1 */
/* USB_CTRL_1 */
#define MX51_USB_CTRL_1_OFFSET 0x10
#define MX51_USB_CTRL_1_OFFSET 0x10
...
@@ -45,10 +46,6 @@
...
@@ -45,10 +46,6 @@
#define MX51_USB_PLL_DIV_19_2_MHZ 0x01
#define MX51_USB_PLL_DIV_19_2_MHZ 0x01
#define MX51_USB_PLL_DIV_24_MHZ 0x02
#define MX51_USB_PLL_DIV_24_MHZ 0x02
static
struct
platform_device
*
devices
[]
__initdata
=
{
&
mxc_fec_device
,
};
static
struct
pad_desc
mx51babbage_pads
[]
=
{
static
struct
pad_desc
mx51babbage_pads
[]
=
{
/* UART1 */
/* UART1 */
MX51_PAD_UART1_RXD__UART1_RXD
,
MX51_PAD_UART1_RXD__UART1_RXD
,
...
@@ -93,19 +90,41 @@ static struct pad_desc mx51babbage_pads[] = {
...
@@ -93,19 +90,41 @@ static struct pad_desc mx51babbage_pads[] = {
/* USB HUB reset line*/
/* USB HUB reset line*/
MX51_PAD_GPIO_1_7__GPIO_1_7
,
MX51_PAD_GPIO_1_7__GPIO_1_7
,
/* FEC */
MX51_PAD_EIM_EB2__FEC_MDIO
,
MX51_PAD_EIM_EB3__FEC_RDAT1
,
MX51_PAD_EIM_CS2__FEC_RDAT2
,
MX51_PAD_EIM_CS3__FEC_RDAT3
,
MX51_PAD_EIM_CS4__FEC_RX_ER
,
MX51_PAD_EIM_CS5__FEC_CRS
,
MX51_PAD_NANDF_RB2__FEC_COL
,
MX51_PAD_NANDF_RB3__FEC_RXCLK
,
MX51_PAD_NANDF_RB6__FEC_RDAT0
,
MX51_PAD_NANDF_RB7__FEC_TDAT0
,
MX51_PAD_NANDF_CS2__FEC_TX_ER
,
MX51_PAD_NANDF_CS3__FEC_MDC
,
MX51_PAD_NANDF_CS4__FEC_TDAT1
,
MX51_PAD_NANDF_CS5__FEC_TDAT2
,
MX51_PAD_NANDF_CS6__FEC_TDAT3
,
MX51_PAD_NANDF_CS7__FEC_TX_EN
,
MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK
,
/* FEC PHY reset line */
MX51_PAD_EIM_A20__GPIO_2_14
,
};
};
/* Serial ports */
/* Serial ports */
#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
static
struct
imxuart_platform_data
uart_pdata
=
{
static
const
struct
imxuart_platform_data
uart_pdata
__initconst
=
{
.
flags
=
IMXUART_HAVE_RTSCTS
,
.
flags
=
IMXUART_HAVE_RTSCTS
,
};
};
static
inline
void
mxc_init_imx_uart
(
void
)
static
inline
void
mxc_init_imx_uart
(
void
)
{
{
mxc_register_device
(
&
mxc_uart_device
0
,
&
uart_pdata
);
imx51_add_imx_uart
(
0
,
&
uart_pdata
);
mxc_register_device
(
&
mxc_uart_device
1
,
&
uart_pdata
);
imx51_add_imx_uart
(
1
,
&
uart_pdata
);
mxc_register_device
(
&
mxc_uart_device
2
,
&
uart_pdata
);
imx51_add_imx_uart
(
2
,
&
uart_pdata
);
}
}
#else
/* !SERIAL_IMX */
#else
/* !SERIAL_IMX */
static
inline
void
mxc_init_imx_uart
(
void
)
static
inline
void
mxc_init_imx_uart
(
void
)
...
@@ -113,7 +132,7 @@ static inline void mxc_init_imx_uart(void)
...
@@ -113,7 +132,7 @@ static inline void mxc_init_imx_uart(void)
}
}
#endif
/* SERIAL_IMX */
#endif
/* SERIAL_IMX */
static
struct
imxi2c_platform_data
babbage_i2c_data
=
{
static
const
struct
imxi2c_platform_data
babbage_i2c_data
__initconst
=
{
.
bitrate
=
100000
,
.
bitrate
=
100000
,
};
};
...
@@ -171,6 +190,22 @@ static inline void babbage_usbhub_reset(void)
...
@@ -171,6 +190,22 @@ static inline void babbage_usbhub_reset(void)
gpio_set_value
(
BABBAGE_USB_HUB_RESET
,
1
);
gpio_set_value
(
BABBAGE_USB_HUB_RESET
,
1
);
}
}
static
inline
void
babbage_fec_reset
(
void
)
{
int
ret
;
/* reset FEC PHY */
ret
=
gpio_request
(
BABBAGE_FEC_PHY_RESET
,
"fec-phy-reset"
);
if
(
ret
)
{
printk
(
KERN_ERR
"failed to get GPIO_FEC_PHY_RESET: %d
\n
"
,
ret
);
return
;
}
gpio_direction_output
(
BABBAGE_FEC_PHY_RESET
,
0
);
gpio_set_value
(
BABBAGE_FEC_PHY_RESET
,
0
);
msleep
(
1
);
gpio_set_value
(
BABBAGE_FEC_PHY_RESET
,
1
);
}
/* This function is board specific as the bit mask for the plldiv will also
/* This function is board specific as the bit mask for the plldiv will also
be different for other Freescale SoCs, thus a common bitmask is not
be different for other Freescale SoCs, thus a common bitmask is not
possible and cannot get place in /plat-mxc/ehci.c.*/
possible and cannot get place in /plat-mxc/ehci.c.*/
...
@@ -178,7 +213,7 @@ static int initialize_otg_port(struct platform_device *pdev)
...
@@ -178,7 +213,7 @@ static int initialize_otg_port(struct platform_device *pdev)
{
{
u32
v
;
u32
v
;
void
__iomem
*
usb_base
;
void
__iomem
*
usb_base
;
u32
usbother_base
;
void
__iomem
*
usbother_base
;
usb_base
=
ioremap
(
MX51_OTG_BASE_ADDR
,
SZ_4K
);
usb_base
=
ioremap
(
MX51_OTG_BASE_ADDR
,
SZ_4K
);
usbother_base
=
usb_base
+
MX5_USBOTHER_REGS_OFFSET
;
usbother_base
=
usb_base
+
MX5_USBOTHER_REGS_OFFSET
;
...
@@ -196,7 +231,7 @@ static int initialize_usbh1_port(struct platform_device *pdev)
...
@@ -196,7 +231,7 @@ static int initialize_usbh1_port(struct platform_device *pdev)
{
{
u32
v
;
u32
v
;
void
__iomem
*
usb_base
;
void
__iomem
*
usb_base
;
u32
usbother_base
;
void
__iomem
*
usbother_base
;
usb_base
=
ioremap
(
MX51_OTG_BASE_ADDR
,
SZ_4K
);
usb_base
=
ioremap
(
MX51_OTG_BASE_ADDR
,
SZ_4K
);
usbother_base
=
usb_base
+
MX5_USBOTHER_REGS_OFFSET
;
usbother_base
=
usb_base
+
MX5_USBOTHER_REGS_OFFSET
;
...
@@ -250,10 +285,11 @@ static void __init mxc_board_init(void)
...
@@ -250,10 +285,11 @@ static void __init mxc_board_init(void)
mxc_iomux_v3_setup_multiple_pads
(
mx51babbage_pads
,
mxc_iomux_v3_setup_multiple_pads
(
mx51babbage_pads
,
ARRAY_SIZE
(
mx51babbage_pads
));
ARRAY_SIZE
(
mx51babbage_pads
));
mxc_init_imx_uart
();
mxc_init_imx_uart
();
platform_add_devices
(
devices
,
ARRAY_SIZE
(
devices
));
babbage_fec_reset
();
imx51_add_fec
(
NULL
);
mxc_register_device
(
&
mxc_i2c_device
0
,
&
babbage_i2c_data
);
imx51_add_imx_i2c
(
0
,
&
babbage_i2c_data
);
mxc_register_device
(
&
mxc_i2c_device
1
,
&
babbage_i2c_data
);
imx51_add_imx_i2c
(
1
,
&
babbage_i2c_data
);
mxc_register_device
(
&
mxc_hsi2c_device
,
&
babbage_hsi2c_data
);
mxc_register_device
(
&
mxc_hsi2c_device
,
&
babbage_hsi2c_data
);
if
(
otg_mode_host
)
if
(
otg_mode_host
)
...
@@ -283,7 +319,7 @@ MACHINE_START(MX51_BABBAGE, "Freescale MX51 Babbage Board")
...
@@ -283,7 +319,7 @@ MACHINE_START(MX51_BABBAGE, "Freescale MX51 Babbage Board")
/* Maintainer: Amit Kucheria <amit.kucheria@canonical.com> */
/* Maintainer: Amit Kucheria <amit.kucheria@canonical.com> */
.
phys_io
=
MX51_AIPS1_BASE_ADDR
,
.
phys_io
=
MX51_AIPS1_BASE_ADDR
,
.
io_pg_offst
=
((
MX51_AIPS1_BASE_ADDR_VIRT
)
>>
18
)
&
0xfffc
,
.
io_pg_offst
=
((
MX51_AIPS1_BASE_ADDR_VIRT
)
>>
18
)
&
0xfffc
,
.
boot_params
=
PHYS_OFFSET
+
0x100
,
.
boot_params
=
MX51_
PHYS_OFFSET
+
0x100
,
.
map_io
=
mx51_map_io
,
.
map_io
=
mx51_map_io
,
.
init_irq
=
mx51_init_irq
,
.
init_irq
=
mx51_init_irq
,
.
init_machine
=
mxc_board_init
,
.
init_machine
=
mxc_board_init
,
...
...
arch/arm/mach-mx5/board-mx51_efikamx.c
0 → 100644
View file @
c9ee46a9
/*
* Copyright (C) 2010 Linaro Limited
*
* based on code from the following
* Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2009-2010 Pegatron Corporation. All Rights Reserved.
* Copyright 2009-2010 Genesi USA, Inc. All Rights Reserved.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/i2c.h>
#include <linux/gpio.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/fsl_devices.h>
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/iomux-mx51.h>
#include <mach/i2c.h>
#include <mach/mxc_ehci.h>
#include <asm/irq.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include "devices-imx51.h"
#include "devices.h"
#define MX51_USB_PLL_DIV_24_MHZ 0x01
static
struct
pad_desc
mx51efikamx_pads
[]
=
{
/* UART1 */
MX51_PAD_UART1_RXD__UART1_RXD
,
MX51_PAD_UART1_TXD__UART1_TXD
,
MX51_PAD_UART1_RTS__UART1_RTS
,
MX51_PAD_UART1_CTS__UART1_CTS
,
};
/* Serial ports */
#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
static
const
struct
imxuart_platform_data
uart_pdata
=
{
.
flags
=
IMXUART_HAVE_RTSCTS
,
};
static
inline
void
mxc_init_imx_uart
(
void
)
{
imx51_add_imx_uart
(
0
,
&
uart_pdata
);
imx51_add_imx_uart
(
1
,
&
uart_pdata
);
imx51_add_imx_uart
(
2
,
&
uart_pdata
);
}
#else
/* !SERIAL_IMX */
static
inline
void
mxc_init_imx_uart
(
void
)
{
}
#endif
/* SERIAL_IMX */
/* This function is board specific as the bit mask for the plldiv will also
* be different for other Freescale SoCs, thus a common bitmask is not
* possible and cannot get place in /plat-mxc/ehci.c.
*/
static
int
initialize_otg_port
(
struct
platform_device
*
pdev
)
{
u32
v
;
void
__iomem
*
usb_base
;
void
__iomem
*
usbother_base
;
usb_base
=
ioremap
(
MX51_OTG_BASE_ADDR
,
SZ_4K
);
usbother_base
=
(
void
__iomem
*
)(
usb_base
+
MX5_USBOTHER_REGS_OFFSET
);
/* Set the PHY clock to 19.2MHz */
v
=
__raw_readl
(
usbother_base
+
MXC_USB_PHY_CTR_FUNC2_OFFSET
);
v
&=
~
MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK
;
v
|=
MX51_USB_PLL_DIV_24_MHZ
;
__raw_writel
(
v
,
usbother_base
+
MXC_USB_PHY_CTR_FUNC2_OFFSET
);
iounmap
(
usb_base
);
return
0
;
}
static
struct
mxc_usbh_platform_data
dr_utmi_config
=
{
.
init
=
initialize_otg_port
,
.
portsc
=
MXC_EHCI_UTMI_16BIT
,
.
flags
=
MXC_EHCI_INTERNAL_PHY
,
};
static
void
__init
mxc_board_init
(
void
)
{
mxc_iomux_v3_setup_multiple_pads
(
mx51efikamx_pads
,
ARRAY_SIZE
(
mx51efikamx_pads
));
mxc_register_device
(
&
mxc_usbdr_host_device
,
&
dr_utmi_config
);
mxc_init_imx_uart
();
}
static
void
__init
mx51_efikamx_timer_init
(
void
)
{
mx51_clocks_init
(
32768
,
24000000
,
22579200
,
24576000
);
}
static
struct
sys_timer
mxc_timer
=
{
.
init
=
mx51_efikamx_timer_init
,
};
MACHINE_START
(
MX51_EFIKAMX
,
"Genesi EfikaMX nettop"
)
/* Maintainer: Amit Kucheria <amit.kucheria@linaro.org> */
.
phys_io
=
MX51_AIPS1_BASE_ADDR
,
.
io_pg_offst
=
((
MX51_AIPS1_BASE_ADDR_VIRT
)
>>
18
)
&
0xfffc
,
.
boot_params
=
MX51_PHYS_OFFSET
+
0x100
,
.
map_io
=
mx51_map_io
,
.
init_irq
=
mx51_init_irq
,
.
init_machine
=
mxc_board_init
,
.
timer
=
&
mxc_timer
,
MACHINE_END
arch/arm/mach-mx5/clock-mx51.c
View file @
c9ee46a9
...
@@ -41,34 +41,36 @@ static struct clk usboh3_clk;
...
@@ -41,34 +41,36 @@ static struct clk usboh3_clk;
#define MAX_DPLL_WAIT_TRIES 1000
/* 1000 * udelay(1) = 1ms */
#define MAX_DPLL_WAIT_TRIES 1000
/* 1000 * udelay(1) = 1ms */
static
int
_clk_ccgr_enable
(
struct
clk
*
clk
)
static
void
_clk_ccgr_setclk
(
struct
clk
*
clk
,
unsigned
mode
)
{
{
u32
reg
;
u32
reg
=
__raw_readl
(
clk
->
enable_reg
);
reg
&=
~
(
MXC_CCM_CCGRx_CG_MASK
<<
clk
->
enable_shift
);
reg
|=
mode
<<
clk
->
enable_shift
;
reg
=
__raw_readl
(
clk
->
enable_reg
);
reg
|=
MXC_CCM_CCGRx_MOD_ON
<<
clk
->
enable_shift
;
__raw_writel
(
reg
,
clk
->
enable_reg
);
__raw_writel
(
reg
,
clk
->
enable_reg
);
}
static
int
_clk_ccgr_enable
(
struct
clk
*
clk
)
{
_clk_ccgr_setclk
(
clk
,
MXC_CCM_CCGRx_MOD_ON
);
return
0
;
return
0
;
}
}
static
void
_clk_ccgr_disable
(
struct
clk
*
clk
)
static
void
_clk_ccgr_disable
(
struct
clk
*
clk
)
{
{
u32
reg
;
_clk_ccgr_setclk
(
clk
,
MXC_CCM_CCGRx_MOD_OFF
);
reg
=
__raw_readl
(
clk
->
enable_reg
);
}
reg
&=
~
(
MXC_CCM_CCGRx_CG_MASK
<<
clk
->
enable_shift
);
__raw_writel
(
reg
,
clk
->
enable_reg
);
static
int
_clk_ccgr_enable_inrun
(
struct
clk
*
clk
)
{
_clk_ccgr_setclk
(
clk
,
MXC_CCM_CCGRx_MOD_IDLE
);
return
0
;
}
}
static
void
_clk_ccgr_disable_inwait
(
struct
clk
*
clk
)
static
void
_clk_ccgr_disable_inwait
(
struct
clk
*
clk
)
{
{
u32
reg
;
_clk_ccgr_setclk
(
clk
,
MXC_CCM_CCGRx_MOD_IDLE
);
reg
=
__raw_readl
(
clk
->
enable_reg
);
reg
&=
~
(
MXC_CCM_CCGRx_CG_MASK
<<
clk
->
enable_shift
);
reg
|=
MXC_CCM_CCGRx_MOD_IDLE
<<
clk
->
enable_shift
;
__raw_writel
(
reg
,
clk
->
enable_reg
);
}
}
/*
/*
...
@@ -571,6 +573,64 @@ static int _clk_uart_set_parent(struct clk *clk, struct clk *parent)
...
@@ -571,6 +573,64 @@ static int _clk_uart_set_parent(struct clk *clk, struct clk *parent)
return
0
;
return
0
;
}
}
#define clk_nfc_set_parent NULL
static
unsigned
long
clk_nfc_get_rate
(
struct
clk
*
clk
)
{
unsigned
long
rate
;
u32
reg
,
div
;
reg
=
__raw_readl
(
MXC_CCM_CBCDR
);
div
=
((
reg
&
MXC_CCM_CBCDR_NFC_PODF_MASK
)
>>
MXC_CCM_CBCDR_NFC_PODF_OFFSET
)
+
1
;
rate
=
clk_get_rate
(
clk
->
parent
)
/
div
;
WARN_ON
(
rate
==
0
);
return
rate
;
}
static
unsigned
long
clk_nfc_round_rate
(
struct
clk
*
clk
,
unsigned
long
rate
)
{
u32
div
;
unsigned
long
parent_rate
=
clk_get_rate
(
clk
->
parent
);
if
(
!
rate
)
return
-
EINVAL
;
div
=
parent_rate
/
rate
;
if
(
parent_rate
%
rate
)
div
++
;
if
(
div
>
8
)
return
-
EINVAL
;
return
parent_rate
/
div
;
}
static
int
clk_nfc_set_rate
(
struct
clk
*
clk
,
unsigned
long
rate
)
{
u32
reg
,
div
;
div
=
clk_get_rate
(
clk
->
parent
)
/
rate
;
if
(
div
==
0
)
div
++
;
if
(((
clk_get_rate
(
clk
->
parent
)
/
div
)
!=
rate
)
||
(
div
>
8
))
return
-
EINVAL
;
reg
=
__raw_readl
(
MXC_CCM_CBCDR
);
reg
&=
~
MXC_CCM_CBCDR_NFC_PODF_MASK
;
reg
|=
(
div
-
1
)
<<
MXC_CCM_CBCDR_NFC_PODF_OFFSET
;
__raw_writel
(
reg
,
MXC_CCM_CBCDR
);
while
(
__raw_readl
(
MXC_CCM_CDHIPR
)
&
MXC_CCM_CDHIPR_NFC_IPG_INT_MEM_PODF_BUSY
){
}
return
0
;
}
static
unsigned
long
clk_usboh3_get_rate
(
struct
clk
*
clk
)
static
unsigned
long
clk_usboh3_get_rate
(
struct
clk
*
clk
)
{
{
u32
reg
,
prediv
,
podf
;
u32
reg
,
prediv
,
podf
;
...
@@ -620,6 +680,17 @@ static unsigned long get_ckih2_reference_clock_rate(struct clk *clk)
...
@@ -620,6 +680,17 @@ static unsigned long get_ckih2_reference_clock_rate(struct clk *clk)
return
ckih2_reference
;
return
ckih2_reference
;
}
}
static
unsigned
long
clk_emi_slow_get_rate
(
struct
clk
*
clk
)
{
u32
reg
,
div
;
reg
=
__raw_readl
(
MXC_CCM_CBCDR
);
div
=
((
reg
&
MXC_CCM_CBCDR_EMI_PODF_MASK
)
>>
MXC_CCM_CBCDR_EMI_PODF_OFFSET
)
+
1
;
return
clk_get_rate
(
clk
->
parent
)
/
div
;
}
/* External high frequency clock */
/* External high frequency clock */
static
struct
clk
ckih_clk
=
{
static
struct
clk
ckih_clk
=
{
.
get_rate
=
get_high_reference_clock_rate
,
.
get_rate
=
get_high_reference_clock_rate
,
...
@@ -762,45 +833,105 @@ static struct clk kpp_clk = {
...
@@ -762,45 +833,105 @@ static struct clk kpp_clk = {
.
id
=
0
,
.
id
=
0
,
};
};
#define DEFINE_CLOCK(name, i, er, es, gr, sr, p, s) \
static
struct
clk
emi_slow_clk
=
{
.
parent
=
&
pll2_sw_clk
,
.
enable_reg
=
MXC_CCM_CCGR5
,
.
enable_shift
=
MXC_CCM_CCGRx_CG8_OFFSET
,
.
enable
=
_clk_ccgr_enable
,
.
disable
=
_clk_ccgr_disable_inwait
,
.
get_rate
=
clk_emi_slow_get_rate
,
};
#define DEFINE_CLOCK1(name, i, er, es, pfx, p, s) \
static struct clk name = { \
static struct clk name = { \
.id = i, \
.id = i, \
.enable_reg = er, \
.enable_reg = er, \
.enable_shift = es, \
.enable_shift = es, \
.get_rate = gr, \
.get_rate = pfx##_get_rate, \
.set_rate = sr, \
.set_rate = pfx##_set_rate, \
.round_rate = pfx##_round_rate, \
.set_parent = pfx##_set_parent, \
.enable = _clk_ccgr_enable, \
.enable = _clk_ccgr_enable, \
.disable = _clk_ccgr_disable, \
.disable = _clk_ccgr_disable, \
.parent = p, \
.parent = p, \
.secondary = s, \
.secondary = s, \
}
}
/* DEFINE_CLOCK(name, id, enable_reg, enable_shift,
/* eCSPI */
get_rate, set_rate, parent, secondary); */
static
unsigned
long
clk_ecspi_get_rate
(
struct
clk
*
clk
)
{
u32
reg
,
pred
,
podf
;
reg
=
__raw_readl
(
MXC_CCM_CSCDR2
);
pred
=
(
reg
&
MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK
)
>>
MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET
;
podf
=
(
reg
&
MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK
)
>>
MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET
;
return
DIV_ROUND_CLOSEST
(
clk_get_rate
(
clk
->
parent
),
(
pred
+
1
)
*
(
podf
+
1
));
}
static
int
clk_ecspi_set_parent
(
struct
clk
*
clk
,
struct
clk
*
parent
)
{
u32
reg
,
mux
;
mux
=
_get_mux
(
parent
,
&
pll1_sw_clk
,
&
pll2_sw_clk
,
&
pll3_sw_clk
,
&
lp_apm_clk
);
reg
=
__raw_readl
(
MXC_CCM_CSCMR1
)
&
~
MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK
;
reg
|=
mux
<<
MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET
;
__raw_writel
(
reg
,
MXC_CCM_CSCMR1
);
return
0
;
}
static
struct
clk
ecspi_main_clk
=
{
.
parent
=
&
pll3_sw_clk
,
.
get_rate
=
clk_ecspi_get_rate
,
.
set_parent
=
clk_ecspi_set_parent
,
};
#define DEFINE_CLOCK_FULL(name, i, er, es, gr, sr, e, d, p, s) \
static struct clk name = { \
.id = i, \
.enable_reg = er, \
.enable_shift = es, \
.get_rate = gr, \
.set_rate = sr, \
.enable = e, \
.disable = d, \
.parent = p, \
.secondary = s, \
}
#define DEFINE_CLOCK(name, i, er, es, gr, sr, p, s) \
DEFINE_CLOCK_FULL(name, i, er, es, gr, sr, _clk_ccgr_enable, _clk_ccgr_disable, p, s)
/* Shared peripheral bus arbiter */
/* Shared peripheral bus arbiter */
DEFINE_CLOCK
(
spba_clk
,
0
,
MXC_CCM_CCGR5
,
MXC_CCM_CCGRx_CG0_OFFSET
,
DEFINE_CLOCK
(
spba_clk
,
0
,
MXC_CCM_CCGR5
,
MXC_CCM_CCGRx_CG0_OFFSET
,
NULL
,
NULL
,
&
ipg_clk
,
NULL
);
NULL
,
NULL
,
&
ipg_clk
,
NULL
);
/* UART */
/* UART */
DEFINE_CLOCK
(
uart1_clk
,
0
,
MXC_CCM_CCGR1
,
MXC_CCM_CCGRx_CG4_OFFSET
,
NULL
,
NULL
,
&
uart_root_clk
,
NULL
);
DEFINE_CLOCK
(
uart2_clk
,
1
,
MXC_CCM_CCGR1
,
MXC_CCM_CCGRx_CG6_OFFSET
,
NULL
,
NULL
,
&
uart_root_clk
,
NULL
);
DEFINE_CLOCK
(
uart3_clk
,
2
,
MXC_CCM_CCGR1
,
MXC_CCM_CCGRx_CG8_OFFSET
,
NULL
,
NULL
,
&
uart_root_clk
,
NULL
);
DEFINE_CLOCK
(
uart1_ipg_clk
,
0
,
MXC_CCM_CCGR1
,
MXC_CCM_CCGRx_CG3_OFFSET
,
DEFINE_CLOCK
(
uart1_ipg_clk
,
0
,
MXC_CCM_CCGR1
,
MXC_CCM_CCGRx_CG3_OFFSET
,
NULL
,
NULL
,
&
ipg_clk
,
&
aips_tz1_clk
);
NULL
,
NULL
,
&
ipg_clk
,
&
aips_tz1_clk
);
DEFINE_CLOCK
(
uart2_ipg_clk
,
1
,
MXC_CCM_CCGR1
,
MXC_CCM_CCGRx_CG5_OFFSET
,
DEFINE_CLOCK
(
uart2_ipg_clk
,
1
,
MXC_CCM_CCGR1
,
MXC_CCM_CCGRx_CG5_OFFSET
,
NULL
,
NULL
,
&
ipg_clk
,
&
aips_tz1_clk
);
NULL
,
NULL
,
&
ipg_clk
,
&
aips_tz1_clk
);
DEFINE_CLOCK
(
uart3_ipg_clk
,
2
,
MXC_CCM_CCGR1
,
MXC_CCM_CCGRx_CG7_OFFSET
,
DEFINE_CLOCK
(
uart3_ipg_clk
,
2
,
MXC_CCM_CCGR1
,
MXC_CCM_CCGRx_CG7_OFFSET
,
NULL
,
NULL
,
&
ipg_clk
,
&
spba_clk
);
NULL
,
NULL
,
&
ipg_clk
,
&
spba_clk
);
DEFINE_CLOCK
(
uart1_clk
,
0
,
MXC_CCM_CCGR1
,
MXC_CCM_CCGRx_CG4_OFFSET
,
NULL
,
NULL
,
&
uart_root_clk
,
&
uart1_ipg_clk
);
DEFINE_CLOCK
(
uart2_clk
,
1
,
MXC_CCM_CCGR1
,
MXC_CCM_CCGRx_CG6_OFFSET
,
NULL
,
NULL
,
&
uart_root_clk
,
&
uart2_ipg_clk
);
DEFINE_CLOCK
(
uart3_clk
,
2
,
MXC_CCM_CCGR1
,
MXC_CCM_CCGRx_CG8_OFFSET
,
NULL
,
NULL
,
&
uart_root_clk
,
&
uart3_ipg_clk
);
/* GPT */
/* GPT */
DEFINE_CLOCK
(
gpt_clk
,
0
,
MXC_CCM_CCGR2
,
MXC_CCM_CCGRx_CG9_OFFSET
,
NULL
,
NULL
,
&
ipg_clk
,
NULL
);
DEFINE_CLOCK
(
gpt_ipg_clk
,
0
,
MXC_CCM_CCGR2
,
MXC_CCM_CCGRx_CG10_OFFSET
,
DEFINE_CLOCK
(
gpt_ipg_clk
,
0
,
MXC_CCM_CCGR2
,
MXC_CCM_CCGRx_CG10_OFFSET
,
NULL
,
NULL
,
&
ipg_clk
,
NULL
);
NULL
,
NULL
,
&
ipg_clk
,
NULL
);
DEFINE_CLOCK
(
gpt_clk
,
0
,
MXC_CCM_CCGR2
,
MXC_CCM_CCGRx_CG9_OFFSET
,
NULL
,
NULL
,
&
ipg_clk
,
&
gpt_ipg_clk
);
/* I2C */
/* I2C */
DEFINE_CLOCK
(
i2c1_clk
,
0
,
MXC_CCM_CCGR1
,
MXC_CCM_CCGRx_CG9_OFFSET
,
DEFINE_CLOCK
(
i2c1_clk
,
0
,
MXC_CCM_CCGR1
,
MXC_CCM_CCGRx_CG9_OFFSET
,
...
@@ -814,6 +945,42 @@ DEFINE_CLOCK(hsi2c_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG11_OFFSET,
...
@@ -814,6 +945,42 @@ DEFINE_CLOCK(hsi2c_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG11_OFFSET,
DEFINE_CLOCK
(
fec_clk
,
0
,
MXC_CCM_CCGR2
,
MXC_CCM_CCGRx_CG12_OFFSET
,
DEFINE_CLOCK
(
fec_clk
,
0
,
MXC_CCM_CCGR2
,
MXC_CCM_CCGRx_CG12_OFFSET
,
NULL
,
NULL
,
&
ipg_clk
,
NULL
);
NULL
,
NULL
,
&
ipg_clk
,
NULL
);
/* NFC */
DEFINE_CLOCK1
(
nfc_clk
,
0
,
MXC_CCM_CCGR5
,
MXC_CCM_CCGRx_CG10_OFFSET
,
clk_nfc
,
&
emi_slow_clk
,
NULL
);
/* SSI */
DEFINE_CLOCK
(
ssi1_ipg_clk
,
0
,
MXC_CCM_CCGR3
,
MXC_CCM_CCGRx_CG8_OFFSET
,
NULL
,
NULL
,
&
ipg_clk
,
NULL
);
DEFINE_CLOCK
(
ssi1_clk
,
0
,
MXC_CCM_CCGR3
,
MXC_CCM_CCGRx_CG9_OFFSET
,
NULL
,
NULL
,
&
pll3_sw_clk
,
&
ssi1_ipg_clk
);
DEFINE_CLOCK
(
ssi2_ipg_clk
,
1
,
MXC_CCM_CCGR3
,
MXC_CCM_CCGRx_CG10_OFFSET
,
NULL
,
NULL
,
&
ipg_clk
,
NULL
);
DEFINE_CLOCK
(
ssi2_clk
,
1
,
MXC_CCM_CCGR3
,
MXC_CCM_CCGRx_CG11_OFFSET
,
NULL
,
NULL
,
&
pll3_sw_clk
,
&
ssi2_ipg_clk
);
/* eCSPI */
DEFINE_CLOCK_FULL
(
ecspi1_ipg_clk
,
0
,
MXC_CCM_CCGR4
,
MXC_CCM_CCGRx_CG9_OFFSET
,
NULL
,
NULL
,
_clk_ccgr_enable_inrun
,
_clk_ccgr_disable
,
&
ipg_clk
,
&
spba_clk
);
DEFINE_CLOCK
(
ecspi1_clk
,
0
,
MXC_CCM_CCGR4
,
MXC_CCM_CCGRx_CG10_OFFSET
,
NULL
,
NULL
,
&
ecspi_main_clk
,
&
ecspi1_ipg_clk
);
DEFINE_CLOCK_FULL
(
ecspi2_ipg_clk
,
0
,
MXC_CCM_CCGR4
,
MXC_CCM_CCGRx_CG11_OFFSET
,
NULL
,
NULL
,
_clk_ccgr_enable_inrun
,
_clk_ccgr_disable
,
&
ipg_clk
,
&
aips_tz2_clk
);
DEFINE_CLOCK
(
ecspi2_clk
,
0
,
MXC_CCM_CCGR4
,
MXC_CCM_CCGRx_CG12_OFFSET
,
NULL
,
NULL
,
&
ecspi_main_clk
,
&
ecspi2_ipg_clk
);
/* CSPI */
DEFINE_CLOCK
(
cspi_ipg_clk
,
0
,
MXC_CCM_CCGR4
,
MXC_CCM_CCGRx_CG9_OFFSET
,
NULL
,
NULL
,
&
ipg_clk
,
&
aips_tz2_clk
);
DEFINE_CLOCK
(
cspi_clk
,
0
,
MXC_CCM_CCGR4
,
MXC_CCM_CCGRx_CG13_OFFSET
,
NULL
,
NULL
,
&
ipg_clk
,
&
cspi_ipg_clk
);
/* SDMA */
DEFINE_CLOCK
(
sdma_clk
,
1
,
MXC_CCM_CCGR4
,
MXC_CCM_CCGRx_CG15_OFFSET
,
NULL
,
NULL
,
&
ahb_clk
,
NULL
);
#define _REGISTER_CLOCK(d, n, c) \
#define _REGISTER_CLOCK(d, n, c) \
{ \
{ \
.dev_id = d, \
.dev_id = d, \
...
@@ -837,6 +1004,16 @@ static struct clk_lookup lookups[] = {
...
@@ -837,6 +1004,16 @@ static struct clk_lookup lookups[] = {
_REGISTER_CLOCK
(
"fsl-usb2-udc"
,
"usb"
,
usboh3_clk
)
_REGISTER_CLOCK
(
"fsl-usb2-udc"
,
"usb"
,
usboh3_clk
)
_REGISTER_CLOCK
(
"fsl-usb2-udc"
,
"usb_ahb"
,
ahb_clk
)
_REGISTER_CLOCK
(
"fsl-usb2-udc"
,
"usb_ahb"
,
ahb_clk
)
_REGISTER_CLOCK
(
"imx-keypad.0"
,
NULL
,
kpp_clk
)
_REGISTER_CLOCK
(
"imx-keypad.0"
,
NULL
,
kpp_clk
)
_REGISTER_CLOCK
(
"mxc_nand"
,
NULL
,
nfc_clk
)
_REGISTER_CLOCK
(
"imx-ssi.0"
,
NULL
,
ssi1_clk
)
_REGISTER_CLOCK
(
"imx-ssi.1"
,
NULL
,
ssi2_clk
)
_REGISTER_CLOCK
(
"imx-sdma"
,
NULL
,
sdma_clk
)
_REGISTER_CLOCK
(
NULL
,
"ckih"
,
ckih_clk
)
_REGISTER_CLOCK
(
NULL
,
"ckih2"
,
ckih2_clk
)
_REGISTER_CLOCK
(
NULL
,
"gpt_32k"
,
gpt_32k_clk
)
_REGISTER_CLOCK
(
"imx51-ecspi.0"
,
NULL
,
ecspi1_clk
)
_REGISTER_CLOCK
(
"imx51-ecspi.1"
,
NULL
,
ecspi2_clk
)
_REGISTER_CLOCK
(
"imx51-cspi.0"
,
NULL
,
cspi_clk
)
};
};
static
void
clk_tree_init
(
void
)
static
void
clk_tree_init
(
void
)
...
...
arch/arm/mach-mx5/devices-imx51.h
0 → 100644
View file @
c9ee46a9
/*
* Copyright (C) 2010 Pengutronix
* Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
*
* This program is free software; you can redistribute it and/or modify it under
* the terms of the GNU General Public License version 2 as published by the
* Free Software Foundation.
*/
#include <mach/mx51.h>
#include <mach/devices-common.h>
extern
const
struct
imx_fec_data
imx51_fec_data
__initconst
;
#define imx51_add_fec(pdata) \
imx_add_fec(&imx51_fec_data, pdata)
extern
const
struct
imx_imx_i2c_data
imx51_imx_i2c_data
[]
__initconst
;
#define imx51_add_imx_i2c(id, pdata) \
imx_add_imx_i2c(&imx51_imx_i2c_data[id], pdata)
extern
const
struct
imx_imx_ssi_data
imx51_imx_ssi_data
[]
__initconst
;
#define imx51_add_imx_ssi(id, pdata) \
imx_add_imx_ssi(&imx51_imx_ssi_data[id], pdata)
extern
const
struct
imx_imx_uart_1irq_data
imx51_imx_uart_data
[]
__initconst
;
#define imx51_add_imx_uart(id, pdata) \
imx_add_imx_uart_1irq(&imx51_imx_uart_data[id], pdata)
extern
const
struct
imx_mxc_nand_data
imx51_mxc_nand_data
__initconst
;
#define imx51_add_mxc_nand(pdata) \
imx_add_mxc_nand(&imx51_mxc_nand_data, pdata)
extern
const
struct
imx_spi_imx_data
imx51_cspi_data
__initconst
;
#define imx51_add_cspi(pdata) \
imx_add_spi_imx(&imx51_cspi_data, pdata)
extern
const
struct
imx_spi_imx_data
imx51_ecspi_data
[]
__initconst
;
#define imx51_add_ecspi(id, pdata) \
imx_add_spi_imx(&imx51_ecspi_data[id], pdata)
arch/arm/mach-mx5/devices.c
View file @
c9ee46a9
...
@@ -17,120 +17,6 @@
...
@@ -17,120 +17,6 @@
#include <mach/imx-uart.h>
#include <mach/imx-uart.h>
#include <mach/irqs.h>
#include <mach/irqs.h>
static
struct
resource
uart0
[]
=
{
{
.
start
=
MX51_UART1_BASE_ADDR
,
.
end
=
MX51_UART1_BASE_ADDR
+
0xfff
,
.
flags
=
IORESOURCE_MEM
,
},
{
.
start
=
MX51_MXC_INT_UART1
,
.
end
=
MX51_MXC_INT_UART1
,
.
flags
=
IORESOURCE_IRQ
,
},
};
struct
platform_device
mxc_uart_device0
=
{
.
name
=
"imx-uart"
,
.
id
=
0
,
.
resource
=
uart0
,
.
num_resources
=
ARRAY_SIZE
(
uart0
),
};
static
struct
resource
uart1
[]
=
{
{
.
start
=
MX51_UART2_BASE_ADDR
,
.
end
=
MX51_UART2_BASE_ADDR
+
0xfff
,
.
flags
=
IORESOURCE_MEM
,
},
{
.
start
=
MX51_MXC_INT_UART2
,
.
end
=
MX51_MXC_INT_UART2
,
.
flags
=
IORESOURCE_IRQ
,
},
};
struct
platform_device
mxc_uart_device1
=
{
.
name
=
"imx-uart"
,
.
id
=
1
,
.
resource
=
uart1
,
.
num_resources
=
ARRAY_SIZE
(
uart1
),
};
static
struct
resource
uart2
[]
=
{
{
.
start
=
MX51_UART3_BASE_ADDR
,
.
end
=
MX51_UART3_BASE_ADDR
+
0xfff
,
.
flags
=
IORESOURCE_MEM
,
},
{
.
start
=
MX51_MXC_INT_UART3
,
.
end
=
MX51_MXC_INT_UART3
,
.
flags
=
IORESOURCE_IRQ
,
},
};
struct
platform_device
mxc_uart_device2
=
{
.
name
=
"imx-uart"
,
.
id
=
2
,
.
resource
=
uart2
,
.
num_resources
=
ARRAY_SIZE
(
uart2
),
};
static
struct
resource
mxc_fec_resources
[]
=
{
{
.
start
=
MX51_MXC_FEC_BASE_ADDR
,
.
end
=
MX51_MXC_FEC_BASE_ADDR
+
0xfff
,
.
flags
=
IORESOURCE_MEM
,
},
{
.
start
=
MX51_MXC_INT_FEC
,
.
end
=
MX51_MXC_INT_FEC
,
.
flags
=
IORESOURCE_IRQ
,
},
};
struct
platform_device
mxc_fec_device
=
{
.
name
=
"fec"
,
.
id
=
0
,
.
num_resources
=
ARRAY_SIZE
(
mxc_fec_resources
),
.
resource
=
mxc_fec_resources
,
};
static
struct
resource
mxc_i2c0_resources
[]
=
{
{
.
start
=
MX51_I2C1_BASE_ADDR
,
.
end
=
MX51_I2C1_BASE_ADDR
+
SZ_4K
-
1
,
.
flags
=
IORESOURCE_MEM
,
},
{
.
start
=
MX51_MXC_INT_I2C1
,
.
end
=
MX51_MXC_INT_I2C1
,
.
flags
=
IORESOURCE_IRQ
,
},
};
struct
platform_device
mxc_i2c_device0
=
{
.
name
=
"imx-i2c"
,
.
id
=
0
,
.
num_resources
=
ARRAY_SIZE
(
mxc_i2c0_resources
),
.
resource
=
mxc_i2c0_resources
,
};
static
struct
resource
mxc_i2c1_resources
[]
=
{
{
.
start
=
MX51_I2C2_BASE_ADDR
,
.
end
=
MX51_I2C2_BASE_ADDR
+
SZ_4K
-
1
,
.
flags
=
IORESOURCE_MEM
,
},
{
.
start
=
MX51_MXC_INT_I2C2
,
.
end
=
MX51_MXC_INT_I2C2
,
.
flags
=
IORESOURCE_IRQ
,
},
};
struct
platform_device
mxc_i2c_device1
=
{
.
name
=
"imx-i2c"
,
.
id
=
1
,
.
num_resources
=
ARRAY_SIZE
(
mxc_i2c1_resources
),
.
resource
=
mxc_i2c1_resources
,
};
static
struct
resource
mxc_hsi2c_resources
[]
=
{
static
struct
resource
mxc_hsi2c_resources
[]
=
{
{
{
.
start
=
MX51_HSI2C_DMA_BASE_ADDR
,
.
start
=
MX51_HSI2C_DMA_BASE_ADDR
,
...
...
arch/arm/mach-mx5/devices.h
View file @
c9ee46a9
extern
struct
platform_device
mxc_uart_device0
;
extern
struct
platform_device
mxc_uart_device1
;
extern
struct
platform_device
mxc_uart_device2
;
extern
struct
platform_device
mxc_fec_device
;
extern
struct
platform_device
mxc_usbdr_host_device
;
extern
struct
platform_device
mxc_usbdr_host_device
;
extern
struct
platform_device
mxc_usbh1_device
;
extern
struct
platform_device
mxc_usbh1_device
;
extern
struct
platform_device
mxc_usbdr_udc_device
;
extern
struct
platform_device
mxc_usbdr_udc_device
;
extern
struct
platform_device
mxc_wdt
;
extern
struct
platform_device
mxc_wdt
;
extern
struct
platform_device
mxc_i2c_device0
;
extern
struct
platform_device
mxc_i2c_device1
;
extern
struct
platform_device
mxc_hsi2c_device
;
extern
struct
platform_device
mxc_hsi2c_device
;
extern
struct
platform_device
mxc_keypad_device
;
extern
struct
platform_device
mxc_keypad_device
;
arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c
View file @
c9ee46a9
...
@@ -30,6 +30,7 @@
...
@@ -30,6 +30,7 @@
#include <asm/mach/arch.h>
#include <asm/mach/arch.h>
#include "devices-imx51.h"
#include "devices.h"
#include "devices.h"
#define MBIMX51_TSC2007_GPIO (2*32 + 30)
#define MBIMX51_TSC2007_GPIO (2*32 + 30)
...
@@ -114,7 +115,7 @@ static struct pad_desc mbimx51_pads[] = {
...
@@ -114,7 +115,7 @@ static struct pad_desc mbimx51_pads[] = {
MX51_PAD_KEY_COL3__KEY_COL3
,
MX51_PAD_KEY_COL3__KEY_COL3
,
};
};
static
struct
imxuart_platform_data
uart_pdata
=
{
static
const
struct
imxuart_platform_data
uart_pdata
__initconst
=
{
.
flags
=
IMXUART_HAVE_RTSCTS
,
.
flags
=
IMXUART_HAVE_RTSCTS
,
};
};
...
@@ -172,8 +173,8 @@ void __init eukrea_mbimx51_baseboard_init(void)
...
@@ -172,8 +173,8 @@ void __init eukrea_mbimx51_baseboard_init(void)
mxc_iomux_v3_setup_multiple_pads
(
mbimx51_pads
,
mxc_iomux_v3_setup_multiple_pads
(
mbimx51_pads
,
ARRAY_SIZE
(
mbimx51_pads
));
ARRAY_SIZE
(
mbimx51_pads
));
mxc_register_device
(
&
mxc_uart_device
1
,
NULL
);
imx51_add_imx_uart
(
1
,
NULL
);
mxc_register_device
(
&
mxc_uart_device
2
,
&
uart_pdata
);
imx51_add_imx_uart
(
2
,
&
uart_pdata
);
gpio_request
(
MBIMX51_LED0
,
"LED0"
);
gpio_request
(
MBIMX51_LED0
,
"LED0"
);
gpio_direction_output
(
MBIMX51_LED0
,
1
);
gpio_direction_output
(
MBIMX51_LED0
,
1
);
...
...
arch/arm/plat-mxc/Kconfig
View file @
c9ee46a9
...
@@ -92,6 +92,18 @@ config MXC_DEBUG_BOARD
...
@@ -92,6 +92,18 @@ config MXC_DEBUG_BOARD
data/address de-multiplexing and decode, signal level shift,
data/address de-multiplexing and decode, signal level shift,
interrupt control and various board functions.
interrupt control and various board functions.
config HAVE_EPIT
bool
config MXC_USE_EPIT
bool "Use EPIT instead of GPT"
depends on HAVE_EPIT
help
Use EPIT as the system timer on systems that have it. Normally you
don't have a reason to do so as the EPIT has the same features and
uses the same clocks as the GPT. Anyway, on some systems the GPT
may be in use for other purposes.
config MXC_ULPI
config MXC_ULPI
bool
bool
...
...
arch/arm/plat-mxc/Makefile
View file @
c9ee46a9
...
@@ -13,6 +13,7 @@ obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o
...
@@ -13,6 +13,7 @@ obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o
obj-$(CONFIG_MXC_PWM)
+=
pwm.o
obj-$(CONFIG_MXC_PWM)
+=
pwm.o
obj-$(CONFIG_USB_EHCI_MXC)
+=
ehci.o
obj-$(CONFIG_USB_EHCI_MXC)
+=
ehci.o
obj-$(CONFIG_MXC_ULPI)
+=
ulpi.o
obj-$(CONFIG_MXC_ULPI)
+=
ulpi.o
obj-$(CONFIG_MXC_USE_EPIT)
+=
epit.o
obj-$(CONFIG_ARCH_MXC_AUDMUX_V1)
+=
audmux-v1.o
obj-$(CONFIG_ARCH_MXC_AUDMUX_V1)
+=
audmux-v1.o
obj-$(CONFIG_ARCH_MXC_AUDMUX_V2)
+=
audmux-v2.o
obj-$(CONFIG_ARCH_MXC_AUDMUX_V2)
+=
audmux-v2.o
obj-$(CONFIG_MXC_DEBUG_BOARD)
+=
3ds_debugboard.o
obj-$(CONFIG_MXC_DEBUG_BOARD)
+=
3ds_debugboard.o
...
...
arch/arm/plat-mxc/audmux-v2.c
View file @
c9ee46a9
...
@@ -186,7 +186,13 @@ EXPORT_SYMBOL_GPL(mxc_audmux_v2_configure_port);
...
@@ -186,7 +186,13 @@ EXPORT_SYMBOL_GPL(mxc_audmux_v2_configure_port);
static
int
mxc_audmux_v2_init
(
void
)
static
int
mxc_audmux_v2_init
(
void
)
{
{
int
ret
;
int
ret
;
#if defined(CONFIG_ARCH_MX5)
if
(
cpu_is_mx51
())
{
audmux_base
=
MX51_IO_ADDRESS
(
MX51_AUDMUX_BASE_ADDR
);
ret
=
0
;
return
ret
;
}
#endif
#if defined(CONFIG_ARCH_MX3)
#if defined(CONFIG_ARCH_MX3)
if
(
cpu_is_mx31
())
if
(
cpu_is_mx31
())
audmux_base
=
MX31_IO_ADDRESS
(
MX31_AUDMUX_BASE_ADDR
);
audmux_base
=
MX31_IO_ADDRESS
(
MX31_AUDMUX_BASE_ADDR
);
...
...
arch/arm/plat-mxc/devices/Kconfig
View file @
c9ee46a9
config IMX_HAVE_PLATFORM_ESDHC
bool
config IMX_HAVE_PLATFORM_FEC
bool
default y if ARCH_MX25 || SOC_IMX27 || ARCH_MX35 || ARCH_MX51
config IMX_HAVE_PLATFORM_FLEXCAN
config IMX_HAVE_PLATFORM_FLEXCAN
select HAVE_CAN_FLEXCAN
select HAVE_CAN_FLEXCAN
bool
bool
...
@@ -5,6 +12,9 @@ config IMX_HAVE_PLATFORM_FLEXCAN
...
@@ -5,6 +12,9 @@ config IMX_HAVE_PLATFORM_FLEXCAN
config IMX_HAVE_PLATFORM_IMX_I2C
config IMX_HAVE_PLATFORM_IMX_I2C
bool
bool
config IMX_HAVE_PLATFORM_IMX_SSI
bool
config IMX_HAVE_PLATFORM_IMX_UART
config IMX_HAVE_PLATFORM_IMX_UART
bool
bool
...
...
arch/arm/plat-mxc/devices/Makefile
View file @
c9ee46a9
ifdef
CONFIG_CAN_FLEXCAN
obj-$(CONFIG_IMX_HAVE_PLATFORM_ESDHC)
+=
platform-esdhc.o
# the ifdef can be removed once the flexcan driver has been merged
obj-$(CONFIG_IMX_HAVE_PLATFORM_FEC)
+=
platform-fec.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_FLEXCAN)
+=
platform-flexcan.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_FLEXCAN)
+=
platform-flexcan.o
endif
obj-y
+=
platform-imx-dma.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_I2C)
+=
platform-imx-i2c.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_I2C)
+=
platform-imx-i2c.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_SSI)
+=
platform-imx-ssi.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UART)
+=
platform-imx-uart.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UART)
+=
platform-imx-uart.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_NAND)
+=
platform-mxc_nand.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_NAND)
+=
platform-mxc_nand.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_SPI_IMX)
+=
platform-spi_imx.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_SPI_IMX)
+=
platform-spi_imx.o
arch/arm/plat-mxc/devices/platform-esdhc.c
0 → 100644
View file @
c9ee46a9
/*
* Copyright (C) 2010 Pengutronix, Wolfram Sang <w.sang@pengutronix.de>
*
* This program is free software; you can redistribute it and/or modify it under
* the terms of the GNU General Public License version 2 as published by the
* Free Software Foundation.
*/
#include <mach/devices-common.h>
#include <mach/esdhc.h>
struct
platform_device
*
__init
imx_add_esdhc
(
int
id
,
resource_size_t
iobase
,
resource_size_t
iosize
,
resource_size_t
irq
,
const
struct
esdhc_platform_data
*
pdata
)
{
struct
resource
res
[]
=
{
{
.
start
=
iobase
,
.
end
=
iobase
+
iosize
-
1
,
.
flags
=
IORESOURCE_MEM
,
},
{
.
start
=
irq
,
.
end
=
irq
,
.
flags
=
IORESOURCE_IRQ
,
},
};
return
imx_add_platform_device
(
"sdhci-esdhc-imx"
,
id
,
res
,
ARRAY_SIZE
(
res
),
pdata
,
sizeof
(
*
pdata
));
}
arch/arm/plat-mxc/devices/platform-fec.c
0 → 100644
View file @
c9ee46a9
/*
* Copyright (C) 2010 Pengutronix
* Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
*
* This program is free software; you can redistribute it and/or modify it under
* the terms of the GNU General Public License version 2 as published by the
* Free Software Foundation.
*/
#include <asm/sizes.h>
#include <mach/hardware.h>
#include <mach/devices-common.h>
#define imx_fec_data_entry_single(soc) \
{ \
.iobase = soc ## _FEC_BASE_ADDR, \
.irq = soc ## _INT_FEC, \
}
#ifdef CONFIG_ARCH_MX25
const
struct
imx_fec_data
imx25_fec_data
__initconst
=
imx_fec_data_entry_single
(
MX25
);
#endif
/* ifdef CONFIG_ARCH_MX25 */
#ifdef CONFIG_SOC_IMX27
const
struct
imx_fec_data
imx27_fec_data
__initconst
=
imx_fec_data_entry_single
(
MX27
);
#endif
/* ifdef CONFIG_SOC_IMX27 */
#ifdef CONFIG_ARCH_MX35
const
struct
imx_fec_data
imx35_fec_data
__initconst
=
imx_fec_data_entry_single
(
MX35
);
#endif
#ifdef CONFIG_ARCH_MX51
const
struct
imx_fec_data
imx51_fec_data
__initconst
=
imx_fec_data_entry_single
(
MX51
);
#endif
struct
platform_device
*
__init
imx_add_fec
(
const
struct
imx_fec_data
*
data
,
const
struct
fec_platform_data
*
pdata
)
{
struct
resource
res
[]
=
{
{
.
start
=
data
->
iobase
,
.
end
=
data
->
iobase
+
SZ_4K
,
.
flags
=
IORESOURCE_MEM
,
},
{
.
start
=
data
->
irq
,
.
end
=
data
->
irq
,
.
flags
=
IORESOURCE_IRQ
,
},
};
return
imx_add_platform_device
(
"fec"
,
0
/* -1? */
,
res
,
ARRAY_SIZE
(
res
),
pdata
,
sizeof
(
*
pdata
));
}
arch/arm/plat-mxc/devices/platform-imx-dma.c
0 → 100644
View file @
c9ee46a9
/*
* Copyright (C) 2010 Pengutronix
* Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
*
* This program is free software; you can redistribute it and/or modify it under
* the terms of the GNU General Public License version 2 as published by the
* Free Software Foundation.
*/
#include <linux/compiler.h>
#include <linux/err.h>
#include <linux/init.h>
#include <mach/hardware.h>
#include <mach/devices-common.h>
#ifdef SDMA_IS_MERGED
#include <mach/sdma.h>
#else
struct
sdma_platform_data
{
int
sdma_version
;
char
*
cpu_name
;
int
to_version
;
};
#endif
struct
imx_imx_sdma_data
{
resource_size_t
iobase
;
resource_size_t
irq
;
struct
sdma_platform_data
pdata
;
};
#define imx_imx_sdma_data_entry_single(soc, _sdma_version, _cpu_name, _to_version)\
{ \
.iobase = soc ## _SDMA ## _BASE_ADDR, \
.irq = soc ## _INT_SDMA, \
.pdata = { \
.sdma_version = _sdma_version, \
.cpu_name = _cpu_name, \
.to_version = _to_version, \
}, \
}
#ifdef CONFIG_ARCH_MX25
const
struct
imx_imx_sdma_data
imx25_imx_sdma_data
__initconst
=
imx_imx_sdma_data_entry_single
(
MX25
,
1
,
"imx25"
,
0
);
#endif
/* ifdef CONFIG_ARCH_MX25 */
#ifdef CONFIG_ARCH_MX31
struct
imx_imx_sdma_data
imx31_imx_sdma_data
__initdata
=
imx_imx_sdma_data_entry_single
(
MX31
,
1
,
"imx31"
,
0
);
#endif
/* ifdef CONFIG_ARCH_MX31 */
#ifdef CONFIG_ARCH_MX35
struct
imx_imx_sdma_data
imx35_imx_sdma_data
__initdata
=
imx_imx_sdma_data_entry_single
(
MX35
,
2
,
"imx35"
,
0
);
#endif
/* ifdef CONFIG_ARCH_MX35 */
#ifdef CONFIG_ARCH_MX51
const
struct
imx_imx_sdma_data
imx51_imx_sdma_data
__initconst
=
imx_imx_sdma_data_entry_single
(
MX51
,
2
,
"imx51"
,
0
);
#endif
/* ifdef CONFIG_ARCH_MX51 */
static
struct
platform_device
__init
__maybe_unused
*
imx_add_imx_sdma
(
const
struct
imx_imx_sdma_data
*
data
)
{
struct
resource
res
[]
=
{
{
.
start
=
data
->
iobase
,
.
end
=
data
->
iobase
+
SZ_4K
-
1
,
.
flags
=
IORESOURCE_MEM
,
},
{
.
start
=
data
->
irq
,
.
end
=
data
->
irq
,
.
flags
=
IORESOURCE_IRQ
,
},
};
return
imx_add_platform_device
(
"imx-sdma"
,
-
1
,
res
,
ARRAY_SIZE
(
res
),
&
data
->
pdata
,
sizeof
(
data
->
pdata
));
}
static
struct
platform_device
__init
__maybe_unused
*
imx_add_imx_dma
(
void
)
{
return
imx_add_platform_device
(
"imx-dma"
,
-
1
,
NULL
,
0
,
NULL
,
0
);
}
static
int
__init
imxXX_add_imx_dma
(
void
)
{
struct
platform_device
*
ret
;
#if defined(CONFIG_SOC_IMX21) || defined(CONFIG_SOC_IMX27)
if
(
cpu_is_mx21
()
||
cpu_is_mx27
())
ret
=
imx_add_imx_dma
();
else
#endif
#if defined(CONFIG_ARCH_MX25)
if
(
cpu_is_mx25
())
ret
=
imx_add_imx_sdma
(
&
imx25_imx_sdma_data
);
else
#endif
#if defined(CONFIG_ARCH_MX31)
if
(
cpu_is_mx31
())
{
imx31_imx_sdma_data
.
pdata
.
to_version
=
mx31_revision
()
>>
4
;
ret
=
imx_add_imx_sdma
(
&
imx31_imx_sdma_data
);
}
else
#endif
#if defined(CONFIG_ARCH_MX35)
if
(
cpu_is_mx35
())
{
imx35_imx_sdma_data
.
pdata
.
to_version
=
mx35_revision
()
>>
4
;
ret
=
imx_add_imx_sdma
(
&
imx35_imx_sdma_data
);
}
else
#endif
#if defined(CONFIG_ARCH_MX51)
if
(
cpu_is_mx51
())
ret
=
imx_add_imx_sdma
(
&
imx51_imx_sdma_data
);
else
#endif
ret
=
ERR_PTR
(
-
ENODEV
);
if
(
IS_ERR
(
ret
))
return
PTR_ERR
(
ret
);
return
0
;
}
arch_initcall
(
imxXX_add_imx_dma
);
arch/arm/plat-mxc/devices/platform-imx-i2c.c
View file @
c9ee46a9
...
@@ -6,24 +6,94 @@
...
@@ -6,24 +6,94 @@
* the terms of the GNU General Public License version 2 as published by the
* the terms of the GNU General Public License version 2 as published by the
* Free Software Foundation.
* Free Software Foundation.
*/
*/
#include <mach/hardware.h>
#include <mach/devices-common.h>
#include <mach/devices-common.h>
struct
platform_device
*
__init
imx_add_imx_i2c
(
int
id
,
#define imx_imx_i2c_data_entry_single(soc, _id, _hwid, _size) \
resource_size_t
iobase
,
resource_size_t
iosize
,
int
irq
,
{ \
.id = _id, \
.iobase = soc ## _I2C ## _hwid ## _BASE_ADDR, \
.iosize = _size, \
.irq = soc ## _INT_I2C ## _hwid, \
}
#define imx_imx_i2c_data_entry(soc, _id, _hwid, _size) \
[_id] = imx_imx_i2c_data_entry_single(soc, _id, _hwid, _size)
#ifdef CONFIG_SOC_IMX1
const
struct
imx_imx_i2c_data
imx1_imx_i2c_data
__initconst
=
imx_imx_i2c_data_entry_single
(
MX1
,
0
,
,
SZ_4K
);
#endif
/* ifdef CONFIG_SOC_IMX1 */
#ifdef CONFIG_SOC_IMX21
const
struct
imx_imx_i2c_data
imx21_imx_i2c_data
__initconst
=
imx_imx_i2c_data_entry_single
(
MX21
,
0
,
,
SZ_4K
);
#endif
/* ifdef CONFIG_SOC_IMX21 */
#ifdef CONFIG_ARCH_MX25
const
struct
imx_imx_i2c_data
imx25_imx_i2c_data
[]
__initconst
=
{
#define imx25_imx_i2c_data_entry(_id, _hwid) \
imx_imx_i2c_data_entry(MX25, _id, _hwid, SZ_16K)
imx25_imx_i2c_data_entry
(
0
,
1
),
imx25_imx_i2c_data_entry
(
1
,
2
),
imx25_imx_i2c_data_entry
(
2
,
3
),
};
#endif
/* ifdef CONFIG_ARCH_MX25 */
#ifdef CONFIG_SOC_IMX27
const
struct
imx_imx_i2c_data
imx27_imx_i2c_data
[]
__initconst
=
{
#define imx27_imx_i2c_data_entry(_id, _hwid) \
imx_imx_i2c_data_entry(MX27, _id, _hwid, SZ_4K)
imx27_imx_i2c_data_entry
(
0
,
1
),
imx27_imx_i2c_data_entry
(
1
,
2
),
};
#endif
/* ifdef CONFIG_SOC_IMX27 */
#ifdef CONFIG_ARCH_MX31
const
struct
imx_imx_i2c_data
imx31_imx_i2c_data
[]
__initconst
=
{
#define imx31_imx_i2c_data_entry(_id, _hwid) \
imx_imx_i2c_data_entry(MX31, _id, _hwid, SZ_4K)
imx31_imx_i2c_data_entry
(
0
,
1
),
imx31_imx_i2c_data_entry
(
1
,
2
),
imx31_imx_i2c_data_entry
(
2
,
3
),
};
#endif
/* ifdef CONFIG_ARCH_MX31 */
#ifdef CONFIG_ARCH_MX35
const
struct
imx_imx_i2c_data
imx35_imx_i2c_data
[]
__initconst
=
{
#define imx35_imx_i2c_data_entry(_id, _hwid) \
imx_imx_i2c_data_entry(MX35, _id, _hwid, SZ_4K)
imx35_imx_i2c_data_entry
(
0
,
1
),
imx35_imx_i2c_data_entry
(
1
,
2
),
};
#endif
/* ifdef CONFIG_ARCH_MX35 */
#ifdef CONFIG_ARCH_MX51
const
struct
imx_imx_i2c_data
imx51_imx_i2c_data
[]
__initconst
=
{
#define imx51_imx_i2c_data_entry(_id, _hwid) \
imx_imx_i2c_data_entry(MX51, _id, _hwid, SZ_4K)
imx51_imx_i2c_data_entry
(
0
,
1
),
imx51_imx_i2c_data_entry
(
1
,
2
),
};
#endif
/* ifdef CONFIG_ARCH_MX51 */
struct
platform_device
*
__init
imx_add_imx_i2c
(
const
struct
imx_imx_i2c_data
*
data
,
const
struct
imxi2c_platform_data
*
pdata
)
const
struct
imxi2c_platform_data
*
pdata
)
{
{
struct
resource
res
[]
=
{
struct
resource
res
[]
=
{
{
{
.
start
=
iobase
,
.
start
=
data
->
iobase
,
.
end
=
iobase
+
iosize
-
1
,
.
end
=
data
->
iobase
+
data
->
iosize
-
1
,
.
flags
=
IORESOURCE_MEM
,
.
flags
=
IORESOURCE_MEM
,
},
{
},
{
.
start
=
irq
,
.
start
=
data
->
irq
,
.
end
=
irq
,
.
end
=
data
->
irq
,
.
flags
=
IORESOURCE_IRQ
,
.
flags
=
IORESOURCE_IRQ
,
},
},
};
};
return
imx_add_platform_device
(
"imx-i2c"
,
id
,
res
,
ARRAY_SIZE
(
res
),
return
imx_add_platform_device
(
"imx-i2c"
,
data
->
id
,
res
,
ARRAY_SIZE
(
res
),
pdata
,
sizeof
(
*
pdata
));
pdata
,
sizeof
(
*
pdata
));
}
}
arch/arm/plat-mxc/devices/platform-imx-ssi.c
0 → 100644
View file @
c9ee46a9
/*
* Copyright (C) 2010 Pengutronix
* Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
*
* This program is free software; you can redistribute it and/or modify it under
* the terms of the GNU General Public License version 2 as published by the
* Free Software Foundation.
*/
#include <mach/hardware.h>
#include <mach/devices-common.h>
#define imx_imx_ssi_data_entry(soc, _id, _hwid, _size) \
[_id] = { \
.id = _id, \
.iobase = soc ## _SSI ## _hwid ## _BASE_ADDR, \
.iosize = _size, \
.irq = soc ## _INT_SSI ## _hwid, \
.dmatx0 = soc ## _DMA_REQ_SSI ## _hwid ## _TX0, \
.dmarx0 = soc ## _DMA_REQ_SSI ## _hwid ## _RX0, \
.dmatx1 = soc ## _DMA_REQ_SSI ## _hwid ## _TX1, \
.dmarx1 = soc ## _DMA_REQ_SSI ## _hwid ## _RX1, \
}
#ifdef CONFIG_SOC_IMX21
const
struct
imx_imx_ssi_data
imx21_imx_ssi_data
[]
__initconst
=
{
#define imx21_imx_ssi_data_entry(_id, _hwid) \
imx_imx_ssi_data_entry(MX21, _id, _hwid, SZ_4K)
imx21_imx_ssi_data_entry
(
0
,
1
),
imx21_imx_ssi_data_entry
(
1
,
2
),
};
#endif
/* ifdef CONFIG_SOC_IMX21 */
#ifdef CONFIG_ARCH_MX25
const
struct
imx_imx_ssi_data
imx25_imx_ssi_data
[]
__initconst
=
{
#define imx25_imx_ssi_data_entry(_id, _hwid) \
imx_imx_ssi_data_entry(MX25, _id, _hwid, SZ_4K)
imx25_imx_ssi_data_entry
(
0
,
1
),
imx25_imx_ssi_data_entry
(
1
,
2
),
};
#endif
/* ifdef CONFIG_ARCH_MX25 */
#ifdef CONFIG_SOC_IMX27
const
struct
imx_imx_ssi_data
imx27_imx_ssi_data
[]
__initconst
=
{
#define imx27_imx_ssi_data_entry(_id, _hwid) \
imx_imx_ssi_data_entry(MX27, _id, _hwid, SZ_4K)
imx27_imx_ssi_data_entry
(
0
,
1
),
imx27_imx_ssi_data_entry
(
1
,
2
),
};
#endif
/* ifdef CONFIG_SOC_IMX27 */
#ifdef CONFIG_ARCH_MX31
const
struct
imx_imx_ssi_data
imx31_imx_ssi_data
[]
__initconst
=
{
#define imx31_imx_ssi_data_entry(_id, _hwid) \
imx_imx_ssi_data_entry(MX31, _id, _hwid, SZ_4K)
imx31_imx_ssi_data_entry
(
0
,
1
),
imx31_imx_ssi_data_entry
(
1
,
2
),
};
#endif
/* ifdef CONFIG_ARCH_MX31 */
#ifdef CONFIG_ARCH_MX35
const
struct
imx_imx_ssi_data
imx35_imx_ssi_data
[]
__initconst
=
{
#define imx35_imx_ssi_data_entry(_id, _hwid) \
imx_imx_ssi_data_entry(MX35, _id, _hwid, SZ_4K)
imx35_imx_ssi_data_entry
(
0
,
1
),
imx35_imx_ssi_data_entry
(
1
,
2
),
};
#endif
/* ifdef CONFIG_ARCH_MX35 */
#ifdef CONFIG_ARCH_MX51
const
struct
imx_imx_ssi_data
imx51_imx_ssi_data
[]
__initconst
=
{
#define imx51_imx_ssi_data_entry(_id, _hwid) \
imx_imx_ssi_data_entry(MX51, _id, _hwid, SZ_4K)
imx51_imx_ssi_data_entry
(
0
,
1
),
imx51_imx_ssi_data_entry
(
1
,
2
),
};
#endif
/* ifdef CONFIG_ARCH_MX51 */
struct
platform_device
*
__init
imx_add_imx_ssi
(
const
struct
imx_imx_ssi_data
*
data
,
const
struct
imx_ssi_platform_data
*
pdata
)
{
struct
resource
res
[]
=
{
{
.
start
=
data
->
iobase
,
.
end
=
data
->
iobase
+
data
->
iosize
-
1
,
.
flags
=
IORESOURCE_MEM
,
},
{
.
start
=
data
->
irq
,
.
end
=
data
->
irq
,
.
flags
=
IORESOURCE_IRQ
,
},
#define DMARES(_name) { \
.name = #_name, \
.start = data->dma ## _name, \
.end = data->dma ## _name, \
.flags = IORESOURCE_DMA, \
}
DMARES
(
tx0
),
DMARES
(
rx0
),
DMARES
(
tx1
),
DMARES
(
rx1
),
};
return
imx_add_platform_device
(
"imx-ssi"
,
data
->
id
,
res
,
ARRAY_SIZE
(
res
),
pdata
,
sizeof
(
*
pdata
));
}
arch/arm/plat-mxc/devices/platform-imx-uart.c
View file @
c9ee46a9
...
@@ -6,55 +6,148 @@
...
@@ -6,55 +6,148 @@
* the terms of the GNU General Public License version 2 as published by the
* the terms of the GNU General Public License version 2 as published by the
* Free Software Foundation.
* Free Software Foundation.
*/
*/
#include <mach/hardware.h>
#include <mach/devices-common.h>
#include <mach/devices-common.h>
struct
platform_device
*
__init
imx_add_imx_uart_3irq
(
int
id
,
#define imx_imx_uart_3irq_data_entry(soc, _id, _hwid, _size) \
resource_size_t
iobase
,
resource_size_t
iosize
,
[_id] = { \
resource_size_t
irqrx
,
resource_size_t
irqtx
,
.id = _id, \
resource_size_t
irqrts
,
.iobase = soc ## _UART ## _hwid ## _BASE_ADDR, \
.iosize = _size, \
.irqrx = soc ## _INT_UART ## _hwid ## RX, \
.irqtx = soc ## _INT_UART ## _hwid ## TX, \
.irqrts = soc ## _INT_UART ## _hwid ## RTS, \
}
#define imx_imx_uart_1irq_data_entry(soc, _id, _hwid, _size) \
[_id] = { \
.id = _id, \
.iobase = soc ## _UART ## _hwid ## _BASE_ADDR, \
.iosize = _size, \
.irq = soc ## _INT_UART ## _hwid, \
}
#ifdef CONFIG_SOC_IMX1
const
struct
imx_imx_uart_3irq_data
imx1_imx_uart_data
[]
__initconst
=
{
#define imx1_imx_uart_data_entry(_id, _hwid) \
imx_imx_uart_3irq_data_entry(MX1, _id, _hwid, 0xd0)
imx1_imx_uart_data_entry
(
0
,
1
),
imx1_imx_uart_data_entry
(
1
,
2
),
};
#endif
/* ifdef CONFIG_SOC_IMX1 */
#ifdef CONFIG_SOC_IMX21
const
struct
imx_imx_uart_1irq_data
imx21_imx_uart_data
[]
__initconst
=
{
#define imx21_imx_uart_data_entry(_id, _hwid) \
imx_imx_uart_1irq_data_entry(MX21, _id, _hwid, SZ_4K)
imx21_imx_uart_data_entry
(
0
,
1
),
imx21_imx_uart_data_entry
(
1
,
2
),
imx21_imx_uart_data_entry
(
2
,
3
),
imx21_imx_uart_data_entry
(
3
,
4
),
};
#endif
#ifdef CONFIG_ARCH_MX25
const
struct
imx_imx_uart_1irq_data
imx25_imx_uart_data
[]
__initconst
=
{
#define imx25_imx_uart_data_entry(_id, _hwid) \
imx_imx_uart_1irq_data_entry(MX25, _id, _hwid, SZ_16K)
imx25_imx_uart_data_entry
(
0
,
1
),
imx25_imx_uart_data_entry
(
1
,
2
),
imx25_imx_uart_data_entry
(
2
,
3
),
imx25_imx_uart_data_entry
(
3
,
4
),
imx25_imx_uart_data_entry
(
4
,
5
),
};
#endif
/* ifdef CONFIG_ARCH_MX25 */
#ifdef CONFIG_SOC_IMX27
const
struct
imx_imx_uart_1irq_data
imx27_imx_uart_data
[]
__initconst
=
{
#define imx27_imx_uart_data_entry(_id, _hwid) \
imx_imx_uart_1irq_data_entry(MX27, _id, _hwid, SZ_4K)
imx27_imx_uart_data_entry
(
0
,
1
),
imx27_imx_uart_data_entry
(
1
,
2
),
imx27_imx_uart_data_entry
(
2
,
3
),
imx27_imx_uart_data_entry
(
3
,
4
),
imx27_imx_uart_data_entry
(
4
,
5
),
imx27_imx_uart_data_entry
(
5
,
6
),
};
#endif
/* ifdef CONFIG_SOC_IMX27 */
#ifdef CONFIG_ARCH_MX31
const
struct
imx_imx_uart_1irq_data
imx31_imx_uart_data
[]
__initconst
=
{
#define imx31_imx_uart_data_entry(_id, _hwid) \
imx_imx_uart_1irq_data_entry(MX31, _id, _hwid, SZ_4K)
imx31_imx_uart_data_entry
(
0
,
1
),
imx31_imx_uart_data_entry
(
1
,
2
),
imx31_imx_uart_data_entry
(
2
,
3
),
imx31_imx_uart_data_entry
(
3
,
4
),
imx31_imx_uart_data_entry
(
4
,
5
),
};
#endif
/* ifdef CONFIG_ARCH_MX31 */
#ifdef CONFIG_ARCH_MX35
const
struct
imx_imx_uart_1irq_data
imx35_imx_uart_data
[]
__initconst
=
{
#define imx35_imx_uart_data_entry(_id, _hwid) \
imx_imx_uart_1irq_data_entry(MX31, _id, _hwid, SZ_16K)
imx35_imx_uart_data_entry
(
0
,
1
),
imx35_imx_uart_data_entry
(
1
,
2
),
imx35_imx_uart_data_entry
(
2
,
3
),
};
#endif
/* ifdef CONFIG_ARCH_MX35 */
#ifdef CONFIG_ARCH_MX51
const
struct
imx_imx_uart_1irq_data
imx51_imx_uart_data
[]
__initconst
=
{
#define imx51_imx_uart_data_entry(_id, _hwid) \
imx_imx_uart_1irq_data_entry(MX51, _id, _hwid, SZ_4K)
imx51_imx_uart_data_entry
(
0
,
1
),
imx51_imx_uart_data_entry
(
1
,
2
),
imx51_imx_uart_data_entry
(
2
,
3
),
};
#endif
/* ifdef CONFIG_ARCH_MX51 */
struct
platform_device
*
__init
imx_add_imx_uart_3irq
(
const
struct
imx_imx_uart_3irq_data
*
data
,
const
struct
imxuart_platform_data
*
pdata
)
const
struct
imxuart_platform_data
*
pdata
)
{
{
struct
resource
res
[]
=
{
struct
resource
res
[]
=
{
{
{
.
start
=
iobase
,
.
start
=
data
->
iobase
,
.
end
=
iobase
+
iosize
-
1
,
.
end
=
data
->
iobase
+
data
->
iosize
-
1
,
.
flags
=
IORESOURCE_MEM
,
.
flags
=
IORESOURCE_MEM
,
},
{
},
{
.
start
=
irqrx
,
.
start
=
data
->
irqrx
,
.
end
=
irqrx
,
.
end
=
data
->
irqrx
,
.
flags
=
IORESOURCE_IRQ
,
.
flags
=
IORESOURCE_IRQ
,
},
{
},
{
.
start
=
irqtx
,
.
start
=
data
->
irqtx
,
.
end
=
irqtx
,
.
end
=
data
->
irqtx
,
.
flags
=
IORESOURCE_IRQ
,
.
flags
=
IORESOURCE_IRQ
,
},
{
},
{
.
start
=
irqrts
,
.
start
=
data
->
irqrts
,
.
end
=
irqrx
,
.
end
=
data
->
irqrx
,
.
flags
=
IORESOURCE_IRQ
,
.
flags
=
IORESOURCE_IRQ
,
},
},
};
};
return
imx_add_platform_device
(
"imx-uart"
,
id
,
res
,
ARRAY_SIZE
(
res
)
,
return
imx_add_platform_device
(
"imx-uart"
,
data
->
id
,
res
,
pdata
,
sizeof
(
*
pdata
));
ARRAY_SIZE
(
res
),
pdata
,
sizeof
(
*
pdata
));
}
}
struct
platform_device
*
__init
imx_add_imx_uart_1irq
(
int
id
,
struct
platform_device
*
__init
imx_add_imx_uart_1irq
(
resource_size_t
iobase
,
resource_size_t
iosize
,
const
struct
imx_imx_uart_1irq_data
*
data
,
resource_size_t
irq
,
const
struct
imxuart_platform_data
*
pdata
)
const
struct
imxuart_platform_data
*
pdata
)
{
{
struct
resource
res
[]
=
{
struct
resource
res
[]
=
{
{
{
.
start
=
iobase
,
.
start
=
data
->
iobase
,
.
end
=
iobase
+
iosize
-
1
,
.
end
=
data
->
iobase
+
data
->
iosize
-
1
,
.
flags
=
IORESOURCE_MEM
,
.
flags
=
IORESOURCE_MEM
,
},
{
},
{
.
start
=
irq
,
.
start
=
data
->
irq
,
.
end
=
irq
,
.
end
=
data
->
irq
,
.
flags
=
IORESOURCE_IRQ
,
.
flags
=
IORESOURCE_IRQ
,
},
},
};
};
return
imx_add_platform_device
(
"imx-uart"
,
id
,
res
,
ARRAY_SIZE
(
res
),
return
imx_add_platform_device
(
"imx-uart"
,
data
->
id
,
res
,
ARRAY_SIZE
(
res
),
pdata
,
sizeof
(
*
pdata
));
pdata
,
sizeof
(
*
pdata
));
}
}
arch/arm/plat-mxc/devices/platform-mxc_nand.c
View file @
c9ee46a9
...
@@ -7,38 +7,77 @@
...
@@ -7,38 +7,77 @@
* Free Software Foundation.
* Free Software Foundation.
*/
*/
#include <asm/sizes.h>
#include <asm/sizes.h>
#include <mach/hardware.h>
#include <mach/devices-common.h>
#include <mach/devices-common.h>
static
struct
platform_device
*
__init
imx_add_mxc_nand
(
resource_size_t
iobase
,
#define imx_mxc_nand_data_entry_single(soc, _size) \
int
irq
,
const
struct
mxc_nand_platform_data
*
pdata
,
{ \
resource_size_t
iosize
)
.iobase = soc ## _NFC_BASE_ADDR, \
.iosize = _size, \
.irq = soc ## _INT_NFC \
}
#define imx_mxc_nandv3_data_entry_single(soc, _size) \
{ \
.id = -1, \
.iobase = soc ## _NFC_BASE_ADDR, \
.iosize = _size, \
.axibase = soc ## _NFC_AXI_BASE_ADDR, \
.irq = soc ## _INT_NFC \
}
#ifdef CONFIG_SOC_IMX21
const
struct
imx_mxc_nand_data
imx21_mxc_nand_data
__initconst
=
imx_mxc_nand_data_entry_single
(
MX21
,
SZ_4K
);
#endif
/* ifdef CONFIG_SOC_IMX21 */
#ifdef CONFIG_ARCH_MX25
const
struct
imx_mxc_nand_data
imx25_mxc_nand_data
__initconst
=
imx_mxc_nand_data_entry_single
(
MX25
,
SZ_8K
);
#endif
/* ifdef CONFIG_ARCH_MX25 */
#ifdef CONFIG_SOC_IMX27
const
struct
imx_mxc_nand_data
imx27_mxc_nand_data
__initconst
=
imx_mxc_nand_data_entry_single
(
MX27
,
SZ_4K
);
#endif
/* ifdef CONFIG_SOC_IMX27 */
#ifdef CONFIG_ARCH_MX31
const
struct
imx_mxc_nand_data
imx31_mxc_nand_data
__initconst
=
imx_mxc_nand_data_entry_single
(
MX31
,
SZ_4K
);
#endif
#ifdef CONFIG_ARCH_MX35
const
struct
imx_mxc_nand_data
imx35_mxc_nand_data
__initconst
=
imx_mxc_nand_data_entry_single
(
MX35
,
SZ_8K
);
#endif
#ifdef CONFIG_ARCH_MX51
const
struct
imx_mxc_nand_data
imx51_mxc_nand_data
__initconst
=
imx_mxc_nandv3_data_entry_single
(
MX51
,
SZ_16K
);
#endif
struct
platform_device
*
__init
imx_add_mxc_nand
(
const
struct
imx_mxc_nand_data
*
data
,
const
struct
mxc_nand_platform_data
*
pdata
)
{
{
static
int
id
=
0
;
/* AXI has to come first, that's how the mxc_nand driver expect it */
struct
resource
res
[]
=
{
struct
resource
res
[]
=
{
{
{
.
start
=
io
base
,
.
start
=
data
->
axi
base
,
.
end
=
iobase
+
iosize
-
1
,
.
end
=
data
->
axibase
+
SZ_16K
-
1
,
.
flags
=
IORESOURCE_MEM
,
.
flags
=
IORESOURCE_MEM
,
},
{
},
{
.
start
=
irq
,
.
start
=
data
->
iobase
,
.
end
=
irq
,
.
end
=
data
->
iobase
+
data
->
iosize
-
1
,
.
flags
=
IORESOURCE_MEM
,
},
{
.
start
=
data
->
irq
,
.
end
=
data
->
irq
,
.
flags
=
IORESOURCE_IRQ
,
.
flags
=
IORESOURCE_IRQ
,
},
},
};
};
return
imx_add_platform_device
(
"mxc_nand"
,
data
->
id
,
return
imx_add_platform_device
(
"mxc_nand"
,
id
++
,
res
,
ARRAY_SIZE
(
res
),
res
+
!
data
->
axibase
,
ARRAY_SIZE
(
res
)
-
!
data
->
axibase
,
pdata
,
sizeof
(
*
pdata
));
pdata
,
sizeof
(
*
pdata
));
}
}
struct
platform_device
*
__init
imx_add_mxc_nand_v1
(
resource_size_t
iobase
,
int
irq
,
const
struct
mxc_nand_platform_data
*
pdata
)
{
return
imx_add_mxc_nand
(
iobase
,
irq
,
pdata
,
SZ_4K
);
}
struct
platform_device
*
__init
imx_add_mxc_nand_v21
(
resource_size_t
iobase
,
int
irq
,
const
struct
mxc_nand_platform_data
*
pdata
)
{
return
imx_add_mxc_nand
(
iobase
,
irq
,
pdata
,
SZ_8K
);
}
arch/arm/plat-mxc/devices/platform-spi_imx.c
View file @
c9ee46a9
...
@@ -6,25 +6,96 @@
...
@@ -6,25 +6,96 @@
* the terms of the GNU General Public License version 2 as published by the
* the terms of the GNU General Public License version 2 as published by the
* Free Software Foundation.
* Free Software Foundation.
*/
*/
#include <
asm/sizes
.h>
#include <
mach/hardware
.h>
#include <mach/devices-common.h>
#include <mach/devices-common.h>
struct
platform_device
*
__init
imx_add_spi_imx
(
int
id
,
#define imx_spi_imx_data_entry_single(soc, type, _devid, _id, hwid, _size) \
resource_size_t
iobase
,
resource_size_t
iosize
,
int
irq
,
{ \
.devid = _devid, \
.id = _id, \
.iobase = soc ## _ ## type ## hwid ## _BASE_ADDR, \
.iosize = _size, \
.irq = soc ## _INT_ ## type ## hwid, \
}
#define imx_spi_imx_data_entry(soc, type, devid, id, hwid, size) \
[id] = imx_spi_imx_data_entry_single(soc, type, devid, id, hwid, size)
#ifdef CONFIG_SOC_IMX21
const
struct
imx_spi_imx_data
imx21_cspi_data
[]
__initconst
=
{
#define imx21_cspi_data_entry(_id, _hwid) \
imx_spi_imx_data_entry(MX21, CSPI, "imx21-cspi", _id, _hwid, SZ_4K)
imx21_cspi_data_entry
(
0
,
1
),
imx21_cspi_data_entry
(
1
,
2
),
#endif
#ifdef CONFIG_ARCH_MX25
const
struct
imx_spi_imx_data
imx25_cspi_data
[]
__initconst
=
{
#define imx25_cspi_data_entry(_id, _hwid) \
imx_spi_imx_data_entry(MX25, CSPI, "imx25-cspi", _id, _hwid, SZ_16K)
imx25_cspi_data_entry
(
0
,
1
),
imx25_cspi_data_entry
(
1
,
2
),
imx25_cspi_data_entry
(
2
,
3
),
};
#endif
/* ifdef CONFIG_ARCH_MX25 */
#ifdef CONFIG_SOC_IMX27
const
struct
imx_spi_imx_data
imx27_cspi_data
[]
__initconst
=
{
#define imx27_cspi_data_entry(_id, _hwid) \
imx_spi_imx_data_entry(MX27, CSPI, "imx27-cspi", _id, _hwid, SZ_4K)
imx27_cspi_data_entry
(
0
,
1
),
imx27_cspi_data_entry
(
1
,
2
),
imx27_cspi_data_entry
(
2
,
3
),
};
#endif
/* ifdef CONFIG_SOC_IMX27 */
#ifdef CONFIG_ARCH_MX31
const
struct
imx_spi_imx_data
imx31_cspi_data
[]
__initconst
=
{
#define imx31_cspi_data_entry(_id, _hwid) \
imx_spi_imx_data_entry(MX31, CSPI, "imx31-cspi", _id, _hwid, SZ_4K)
imx31_cspi_data_entry
(
0
,
1
),
imx31_cspi_data_entry
(
1
,
2
),
imx31_cspi_data_entry
(
2
,
3
),
};
#endif
/* ifdef CONFIG_ARCH_MX31 */
#ifdef CONFIG_ARCH_MX35
const
struct
imx_spi_imx_data
imx35_cspi_data
[]
__initconst
=
{
#define imx35_cspi_data_entry(_id, _hwid) \
imx_spi_imx_data_entry(MX35, CSPI, "imx35-cspi", _id, _hwid, SZ_4K)
imx35_cspi_data_entry
(
0
,
1
),
imx35_cspi_data_entry
(
1
,
2
),
};
#endif
/* ifdef CONFIG_ARCH_MX35 */
#ifdef CONFIG_ARCH_MX51
const
struct
imx_spi_imx_data
imx51_cspi_data
__initconst
=
imx_spi_imx_data_entry_single
(
MX51
,
CSPI
,
"imx51-cspi"
,
0
,
,
SZ_4K
);
const
struct
imx_spi_imx_data
imx51_ecspi_data
[]
__initconst
=
{
#define imx51_ecspi_data_entry(_id, _hwid) \
imx_spi_imx_data_entry(MX51, ECSPI, "imx51-ecspi", _id, _hwid, SZ_4K)
imx51_ecspi_data_entry
(
0
,
1
),
imx51_ecspi_data_entry
(
1
,
2
),
};
#endif
/* ifdef CONFIG_ARCH_MX51 */
struct
platform_device
*
__init
imx_add_spi_imx
(
const
struct
imx_spi_imx_data
*
data
,
const
struct
spi_imx_master
*
pdata
)
const
struct
spi_imx_master
*
pdata
)
{
{
struct
resource
res
[]
=
{
struct
resource
res
[]
=
{
{
{
.
start
=
iobase
,
.
start
=
data
->
iobase
,
.
end
=
iobase
+
iosize
-
1
,
.
end
=
data
->
iobase
+
data
->
iosize
-
1
,
.
flags
=
IORESOURCE_MEM
,
.
flags
=
IORESOURCE_MEM
,
},
{
},
{
.
start
=
irq
,
.
start
=
data
->
irq
,
.
end
=
irq
,
.
end
=
data
->
irq
,
.
flags
=
IORESOURCE_IRQ
,
.
flags
=
IORESOURCE_IRQ
,
},
},
};
};
return
imx_add_platform_device
(
"spi_imx"
,
id
,
res
,
ARRAY_SIZE
(
res
)
,
return
imx_add_platform_device
(
data
->
devid
,
data
->
id
,
pdata
,
sizeof
(
*
pdata
));
res
,
ARRAY_SIZE
(
res
),
pdata
,
sizeof
(
*
pdata
));
}
}
arch/arm/plat-mxc/ehci.c
View file @
c9ee46a9
...
@@ -249,8 +249,8 @@ int mxc_initialize_usb_hw(int port, unsigned int flags)
...
@@ -249,8 +249,8 @@ int mxc_initialize_usb_hw(int port, unsigned int flags)
#ifdef CONFIG_ARCH_MX51
#ifdef CONFIG_ARCH_MX51
if
(
cpu_is_mx51
())
{
if
(
cpu_is_mx51
())
{
void
__iomem
*
usb_base
;
void
__iomem
*
usb_base
;
u32
usbotg_base
;
void
__iomem
*
usbotg_base
;
u32
usbother_base
;
void
__iomem
*
usbother_base
;
int
ret
=
0
;
int
ret
=
0
;
usb_base
=
ioremap
(
MX51_OTG_BASE_ADDR
,
SZ_4K
);
usb_base
=
ioremap
(
MX51_OTG_BASE_ADDR
,
SZ_4K
);
...
...
arch/arm/plat-mxc/epit.c
0 → 100644
View file @
c9ee46a9
/*
* linux/arch/arm/plat-mxc/epit.c
*
* Copyright (C) 2010 Sascha Hauer <s.hauer@pengutronix.de>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
*/
#define EPITCR 0x00
#define EPITSR 0x04
#define EPITLR 0x08
#define EPITCMPR 0x0c
#define EPITCNR 0x10
#define EPITCR_EN (1 << 0)
#define EPITCR_ENMOD (1 << 1)
#define EPITCR_OCIEN (1 << 2)
#define EPITCR_RLD (1 << 3)
#define EPITCR_PRESC(x) (((x) & 0xfff) << 4)
#define EPITCR_SWR (1 << 16)
#define EPITCR_IOVW (1 << 17)
#define EPITCR_DBGEN (1 << 18)
#define EPITCR_WAITEN (1 << 19)
#define EPITCR_RES (1 << 20)
#define EPITCR_STOPEN (1 << 21)
#define EPITCR_OM_DISCON (0 << 22)
#define EPITCR_OM_TOGGLE (1 << 22)
#define EPITCR_OM_CLEAR (2 << 22)
#define EPITCR_OM_SET (3 << 22)
#define EPITCR_CLKSRC_OFF (0 << 24)
#define EPITCR_CLKSRC_PERIPHERAL (1 << 24)
#define EPITCR_CLKSRC_REF_HIGH (1 << 24)
#define EPITCR_CLKSRC_REF_LOW (3 << 24)
#define EPITSR_OCIF (1 << 0)
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/clockchips.h>
#include <linux/clk.h>
#include <mach/hardware.h>
#include <asm/mach/time.h>
#include <mach/common.h>
static
struct
clock_event_device
clockevent_epit
;
static
enum
clock_event_mode
clockevent_mode
=
CLOCK_EVT_MODE_UNUSED
;
static
void
__iomem
*
timer_base
;
static
inline
void
epit_irq_disable
(
void
)
{
u32
val
;
val
=
__raw_readl
(
timer_base
+
EPITCR
);
val
&=
~
EPITCR_OCIEN
;
__raw_writel
(
val
,
timer_base
+
EPITCR
);
}
static
inline
void
epit_irq_enable
(
void
)
{
u32
val
;
val
=
__raw_readl
(
timer_base
+
EPITCR
);
val
|=
EPITCR_OCIEN
;
__raw_writel
(
val
,
timer_base
+
EPITCR
);
}
static
void
epit_irq_acknowledge
(
void
)
{
__raw_writel
(
EPITSR_OCIF
,
timer_base
+
EPITSR
);
}
static
cycle_t
epit_read
(
struct
clocksource
*
cs
)
{
return
0
-
__raw_readl
(
timer_base
+
EPITCNR
);
}
static
struct
clocksource
clocksource_epit
=
{
.
name
=
"epit"
,
.
rating
=
200
,
.
read
=
epit_read
,
.
mask
=
CLOCKSOURCE_MASK
(
32
),
.
shift
=
20
,
.
flags
=
CLOCK_SOURCE_IS_CONTINUOUS
,
};
static
int
__init
epit_clocksource_init
(
struct
clk
*
timer_clk
)
{
unsigned
int
c
=
clk_get_rate
(
timer_clk
);
clocksource_epit
.
mult
=
clocksource_hz2mult
(
c
,
clocksource_epit
.
shift
);
clocksource_register
(
&
clocksource_epit
);
return
0
;
}
/* clock event */
static
int
epit_set_next_event
(
unsigned
long
evt
,
struct
clock_event_device
*
unused
)
{
unsigned
long
tcmp
;
tcmp
=
__raw_readl
(
timer_base
+
EPITCNR
);
__raw_writel
(
tcmp
-
evt
,
timer_base
+
EPITCMPR
);
return
0
;
}
static
void
epit_set_mode
(
enum
clock_event_mode
mode
,
struct
clock_event_device
*
evt
)
{
unsigned
long
flags
;
/*
* The timer interrupt generation is disabled at least
* for enough time to call epit_set_next_event()
*/
local_irq_save
(
flags
);
/* Disable interrupt in GPT module */
epit_irq_disable
();
if
(
mode
!=
clockevent_mode
)
{
/* Set event time into far-far future */
/* Clear pending interrupt */
epit_irq_acknowledge
();
}
/* Remember timer mode */
clockevent_mode
=
mode
;
local_irq_restore
(
flags
);
switch
(
mode
)
{
case
CLOCK_EVT_MODE_PERIODIC
:
printk
(
KERN_ERR
"epit_set_mode: Periodic mode is not "
"supported for i.MX EPIT
\n
"
);
break
;
case
CLOCK_EVT_MODE_ONESHOT
:
/*
* Do not put overhead of interrupt enable/disable into
* epit_set_next_event(), the core has about 4 minutes
* to call epit_set_next_event() or shutdown clock after
* mode switching
*/
local_irq_save
(
flags
);
epit_irq_enable
();
local_irq_restore
(
flags
);
break
;
case
CLOCK_EVT_MODE_SHUTDOWN
:
case
CLOCK_EVT_MODE_UNUSED
:
case
CLOCK_EVT_MODE_RESUME
:
/* Left event sources disabled, no more interrupts appear */
break
;
}
}
/*
* IRQ handler for the timer
*/
static
irqreturn_t
epit_timer_interrupt
(
int
irq
,
void
*
dev_id
)
{
struct
clock_event_device
*
evt
=
&
clockevent_epit
;
epit_irq_acknowledge
();
evt
->
event_handler
(
evt
);
return
IRQ_HANDLED
;
}
static
struct
irqaction
epit_timer_irq
=
{
.
name
=
"i.MX EPIT Timer Tick"
,
.
flags
=
IRQF_DISABLED
|
IRQF_TIMER
|
IRQF_IRQPOLL
,
.
handler
=
epit_timer_interrupt
,
};
static
struct
clock_event_device
clockevent_epit
=
{
.
name
=
"epit"
,
.
features
=
CLOCK_EVT_FEAT_ONESHOT
,
.
shift
=
32
,
.
set_mode
=
epit_set_mode
,
.
set_next_event
=
epit_set_next_event
,
.
rating
=
200
,
};
static
int
__init
epit_clockevent_init
(
struct
clk
*
timer_clk
)
{
unsigned
int
c
=
clk_get_rate
(
timer_clk
);
clockevent_epit
.
mult
=
div_sc
(
c
,
NSEC_PER_SEC
,
clockevent_epit
.
shift
);
clockevent_epit
.
max_delta_ns
=
clockevent_delta2ns
(
0xfffffffe
,
&
clockevent_epit
);
clockevent_epit
.
min_delta_ns
=
clockevent_delta2ns
(
0x800
,
&
clockevent_epit
);
clockevent_epit
.
cpumask
=
cpumask_of
(
0
);
clockevents_register_device
(
&
clockevent_epit
);
return
0
;
}
void
__init
epit_timer_init
(
struct
clk
*
timer_clk
,
void
__iomem
*
base
,
int
irq
)
{
clk_enable
(
timer_clk
);
timer_base
=
base
;
/*
* Initialise to a known state (all timers off, and timing reset)
*/
__raw_writel
(
0x0
,
timer_base
+
EPITCR
);
__raw_writel
(
0xffffffff
,
timer_base
+
EPITLR
);
__raw_writel
(
EPITCR_EN
|
EPITCR_CLKSRC_REF_HIGH
|
EPITCR_WAITEN
,
timer_base
+
EPITCR
);
/* init and register the timer to the framework */
epit_clocksource_init
(
timer_clk
);
epit_clockevent_init
(
timer_clk
);
/* Make irqs happen */
setup_irq
(
irq
,
&
epit_timer_irq
);
}
arch/arm/plat-mxc/gpio.c
View file @
c9ee46a9
...
@@ -235,7 +235,7 @@ static void mxc_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
...
@@ -235,7 +235,7 @@ static void mxc_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
unsigned
long
flags
;
unsigned
long
flags
;
spin_lock_irqsave
(
&
port
->
lock
,
flags
);
spin_lock_irqsave
(
&
port
->
lock
,
flags
);
l
=
(
__raw_readl
(
reg
)
&
(
~
(
1
<<
offset
)))
|
(
value
<<
offset
);
l
=
(
__raw_readl
(
reg
)
&
(
~
(
1
<<
offset
)))
|
(
!!
value
<<
offset
);
__raw_writel
(
l
,
reg
);
__raw_writel
(
l
,
reg
);
spin_unlock_irqrestore
(
&
port
->
lock
,
flags
);
spin_unlock_irqrestore
(
&
port
->
lock
,
flags
);
}
}
...
...
arch/arm/plat-mxc/include/mach/common.h
View file @
c9ee46a9
...
@@ -32,6 +32,7 @@ extern void mx31_init_irq(void);
...
@@ -32,6 +32,7 @@ extern void mx31_init_irq(void);
extern
void
mx35_init_irq
(
void
);
extern
void
mx35_init_irq
(
void
);
extern
void
mx51_init_irq
(
void
);
extern
void
mx51_init_irq
(
void
);
extern
void
mxc91231_init_irq
(
void
);
extern
void
mxc91231_init_irq
(
void
);
extern
void
epit_timer_init
(
struct
clk
*
timer_clk
,
void
__iomem
*
base
,
int
irq
);
extern
void
mxc_timer_init
(
struct
clk
*
timer_clk
,
void
__iomem
*
,
int
);
extern
void
mxc_timer_init
(
struct
clk
*
timer_clk
,
void
__iomem
*
,
int
);
extern
int
mx1_clocks_init
(
unsigned
long
fref
);
extern
int
mx1_clocks_init
(
unsigned
long
fref
);
extern
int
mx21_clocks_init
(
unsigned
long
lref
,
unsigned
long
fref
);
extern
int
mx21_clocks_init
(
unsigned
long
lref
,
unsigned
long
fref
);
...
...
arch/arm/plat-mxc/include/mach/devices-common.h
View file @
c9ee46a9
...
@@ -14,47 +14,101 @@ struct platform_device *imx_add_platform_device(const char *name, int id,
...
@@ -14,47 +14,101 @@ struct platform_device *imx_add_platform_device(const char *name, int id,
const
struct
resource
*
res
,
unsigned
int
num_resources
,
const
struct
resource
*
res
,
unsigned
int
num_resources
,
const
void
*
data
,
size_t
size_data
);
const
void
*
data
,
size_t
size_data
);
#if defined (CONFIG_CAN_FLEXCAN) || defined (CONFIG_CAN_FLEXCAN_MODULE)
#include <linux/fec.h>
struct
imx_fec_data
{
resource_size_t
iobase
;
resource_size_t
irq
;
};
struct
platform_device
*
__init
imx_add_fec
(
const
struct
imx_fec_data
*
data
,
const
struct
fec_platform_data
*
pdata
);
#include <linux/can/platform/flexcan.h>
#include <linux/can/platform/flexcan.h>
struct
platform_device
*
__init
imx_add_flexcan
(
int
id
,
struct
platform_device
*
__init
imx_add_flexcan
(
int
id
,
resource_size_t
iobase
,
resource_size_t
iosize
,
resource_size_t
iobase
,
resource_size_t
iosize
,
resource_size_t
irq
,
resource_size_t
irq
,
const
struct
flexcan_platform_data
*
pdata
);
const
struct
flexcan_platform_data
*
pdata
);
#else
/* the ifdef can be removed once the flexcan driver has been merged */
struct
flexcan_platform_data
;
static
inline
struct
platform_device
*
__init
imx_add_flexcan
(
int
id
,
resource_size_t
iobase
,
resource_size_t
iosize
,
resource_size_t
irq
,
const
struct
flexcan_platform_data
*
pdata
)
{
return
NULL
;
}
#endif
#include <mach/i2c.h>
#include <mach/i2c.h>
struct
platform_device
*
__init
imx_add_imx_i2c
(
int
id
,
struct
imx_imx_i2c_data
{
resource_size_t
iobase
,
resource_size_t
iosize
,
int
irq
,
int
id
;
resource_size_t
iobase
;
resource_size_t
iosize
;
resource_size_t
irq
;
};
struct
platform_device
*
__init
imx_add_imx_i2c
(
const
struct
imx_imx_i2c_data
*
data
,
const
struct
imxi2c_platform_data
*
pdata
);
const
struct
imxi2c_platform_data
*
pdata
);
#include <mach/ssi.h>
struct
imx_imx_ssi_data
{
int
id
;
resource_size_t
iobase
;
resource_size_t
iosize
;
resource_size_t
irq
;
resource_size_t
dmatx0
;
resource_size_t
dmarx0
;
resource_size_t
dmatx1
;
resource_size_t
dmarx1
;
};
struct
platform_device
*
__init
imx_add_imx_ssi
(
const
struct
imx_imx_ssi_data
*
data
,
const
struct
imx_ssi_platform_data
*
pdata
);
#include <mach/imx-uart.h>
#include <mach/imx-uart.h>
struct
platform_device
*
__init
imx_add_imx_uart_3irq
(
int
id
,
struct
imx_imx_uart_3irq_data
{
resource_size_t
iobase
,
resource_size_t
iosize
,
int
id
;
resource_size_t
irqrx
,
resource_size_t
irqtx
,
resource_size_t
iobase
;
resource_size_t
irqrts
,
resource_size_t
iosize
;
resource_size_t
irqrx
;
resource_size_t
irqtx
;
resource_size_t
irqrts
;
};
struct
platform_device
*
__init
imx_add_imx_uart_3irq
(
const
struct
imx_imx_uart_3irq_data
*
data
,
const
struct
imxuart_platform_data
*
pdata
);
const
struct
imxuart_platform_data
*
pdata
);
struct
platform_device
*
__init
imx_add_imx_uart_1irq
(
int
id
,
resource_size_t
iobase
,
resource_size_t
iosize
,
struct
imx_imx_uart_1irq_data
{
resource_size_t
irq
,
int
id
;
resource_size_t
iobase
;
resource_size_t
iosize
;
resource_size_t
irq
;
};
struct
platform_device
*
__init
imx_add_imx_uart_1irq
(
const
struct
imx_imx_uart_1irq_data
*
data
,
const
struct
imxuart_platform_data
*
pdata
);
const
struct
imxuart_platform_data
*
pdata
);
#include <mach/mxc_nand.h>
#include <mach/mxc_nand.h>
struct
platform_device
*
__init
imx_add_mxc_nand_v1
(
resource_size_t
iobase
,
struct
imx_mxc_nand_data
{
int
irq
,
const
struct
mxc_nand_platform_data
*
pdata
);
/*
struct
platform_device
*
__init
imx_add_mxc_nand_v21
(
resource_size_t
iobase
,
* id is traditionally 0, but -1 is more appropriate. We use -1 for new
int
irq
,
const
struct
mxc_nand_platform_data
*
pdata
);
* machines but don't change existing devices as the nand device usually
* appears in the kernel command line to pass its partitioning.
*/
int
id
;
resource_size_t
iobase
;
resource_size_t
iosize
;
resource_size_t
axibase
;
resource_size_t
irq
;
};
struct
platform_device
*
__init
imx_add_mxc_nand
(
const
struct
imx_mxc_nand_data
*
data
,
const
struct
mxc_nand_platform_data
*
pdata
);
#include <mach/spi.h>
#include <mach/spi.h>
struct
platform_device
*
__init
imx_add_spi_imx
(
int
id
,
struct
imx_spi_imx_data
{
resource_size_t
iobase
,
resource_size_t
iosize
,
int
irq
,
const
char
*
devid
;
int
id
;
resource_size_t
iobase
;
resource_size_t
iosize
;
int
irq
;
};
struct
platform_device
*
__init
imx_add_spi_imx
(
const
struct
imx_spi_imx_data
*
data
,
const
struct
spi_imx_master
*
pdata
);
const
struct
spi_imx_master
*
pdata
);
#include <mach/esdhc.h>
struct
platform_device
*
__init
imx_add_esdhc
(
int
id
,
resource_size_t
iobase
,
resource_size_t
iosize
,
resource_size_t
irq
,
const
struct
esdhc_platform_data
*
pdata
);
arch/arm/plat-mxc/include/mach/esdhc.h
0 → 100644
View file @
c9ee46a9
/*
* Copyright 2010 Wolfram Sang <w.sang@pengutronix.de>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; version 2
* of the License.
*/
#ifndef __ASM_ARCH_IMX_ESDHC_H
#define __ASM_ARCH_IMX_ESDHC_H
struct
esdhc_platform_data
{
unsigned
int
wp_gpio
;
/* write protect pin */
};
#endif
/* __ASM_ARCH_IMX_ESDHC_H */
arch/arm/plat-mxc/include/mach/iomux-mx51.h
View file @
c9ee46a9
...
@@ -45,6 +45,15 @@ typedef enum iomux_config {
...
@@ -45,6 +45,15 @@ typedef enum iomux_config {
PAD_CTL_PKE | PAD_CTL_HYS)
PAD_CTL_PKE | PAD_CTL_HYS)
#define MX51_GPIO_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_PKE | \
#define MX51_GPIO_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_PKE | \
PAD_CTL_SRE_FAST)
PAD_CTL_SRE_FAST)
#define MX51_ECSPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \
PAD_CTL_SRE_FAST)
#define MX51_PAD_CTRL_1 (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_HYS)
#define MX51_PAD_CTRL_2 (PAD_CTL_HYS | PAD_CTL_PKE)
#define MX51_PAD_CTRL_3 (PAD_CTL_PKE | PAD_CTL_PUS_100K_UP)
#define MX51_PAD_CTRL_4 (PAD_CTL_DVS | PAD_CTL_HYS | PAD_CTL_PKE)
#define MX51_PAD_CTRL_5 (PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
/*
/*
* The naming convention for the pad modes is MX51_PAD_<padname>__<padmode>
* The naming convention for the pad modes is MX51_PAD_<padname>__<padmode>
...
@@ -106,14 +115,20 @@ typedef enum iomux_config {
...
@@ -106,14 +115,20 @@ typedef enum iomux_config {
#define MX51_PAD_EIM_EB0__EIM_EB0 IOMUX_PAD(0x460, 0x0cc, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_EB0__EIM_EB0 IOMUX_PAD(0x460, 0x0cc, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_EB1__EIM_EB1 IOMUX_PAD(0x464, 0x0d0, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_EB1__EIM_EB1 IOMUX_PAD(0x464, 0x0d0, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_EB2__GPIO_2_22 IOMUX_PAD(0x468, 0x0d4, 1, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_EB2__GPIO_2_22 IOMUX_PAD(0x468, 0x0d4, 1, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_EB2__FEC_MDIO IOMUX_PAD(0x468, 0x0d4, 3, 0x0, 0, MX51_PAD_CTRL_1 | PAD_CTL_PUS_22K_UP)
#define MX51_PAD_EIM_EB3__GPIO_2_23 IOMUX_PAD(0x46c, 0x0d8, 1, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_EB3__GPIO_2_23 IOMUX_PAD(0x46c, 0x0d8, 1, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_EB3__FEC_RDAT1 IOMUX_PAD(0x46c, 0x0d8, 3, 0x0, 0, MX51_PAD_CTRL_2)
#define MX51_PAD_EIM_OE__GPIO_2_24 IOMUX_PAD(0x470, 0x0dc, 1, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_OE__GPIO_2_24 IOMUX_PAD(0x470, 0x0dc, 1, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_CS0__GPIO_2_25 IOMUX_PAD(0x474, 0x0e0, 1, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_CS0__GPIO_2_25 IOMUX_PAD(0x474, 0x0e0, 1, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_CS1__GPIO_2_26 IOMUX_PAD(0x478, 0x0e4, 1, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_CS1__GPIO_2_26 IOMUX_PAD(0x478, 0x0e4, 1, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_CS2__GPIO_2_27 IOMUX_PAD(0x47c, 0x0e8, 1, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_CS2__GPIO_2_27 IOMUX_PAD(0x47c, 0x0e8, 1, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_CS2__FEC_RDAT2 IOMUX_PAD(0x47c, 0x0e8, 3, 0x0, 0, MX51_PAD_CTRL_2)
#define MX51_PAD_EIM_CS3__GPIO_2_28 IOMUX_PAD(0x480, 0x0ec, 1, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_CS3__GPIO_2_28 IOMUX_PAD(0x480, 0x0ec, 1, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_CS3__FEC_RDAT3 IOMUX_PAD(0x480, 0x0ec, 3, 0x0, 0, MX51_PAD_CTRL_2)
#define MX51_PAD_EIM_CS4__GPIO_2_29 IOMUX_PAD(0x484, 0x0f0, 1, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_CS4__GPIO_2_29 IOMUX_PAD(0x484, 0x0f0, 1, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_CS4__FEC_RX_ER IOMUX_PAD(0x484, 0x0f0, 3, 0x0, 0, MX51_PAD_CTRL_2)
#define MX51_PAD_EIM_CS5__GPIO_2_30 IOMUX_PAD(0x488, 0x0f4, 1, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_CS5__GPIO_2_30 IOMUX_PAD(0x488, 0x0f4, 1, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_CS5__FEC_CRS IOMUX_PAD(0x488, 0x0f4, 3, 0x0, 0, MX51_PAD_CTRL_2)
#define MX51_PAD_EIM_DTACK__GPIO_2_31 IOMUX_PAD(0x48c, 0x0f8, 1, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_DTACK__GPIO_2_31 IOMUX_PAD(0x48c, 0x0f8, 1, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_LBA__GPIO_3_1 IOMUX_PAD(0x494, 0x0FC, 1, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_LBA__GPIO_3_1 IOMUX_PAD(0x494, 0x0FC, 1, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_CRE__GPIO_3_2 IOMUX_PAD(0x4A0, 0x100, 1, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_CRE__GPIO_3_2 IOMUX_PAD(0x4A0, 0x100, 1, 0x0, 0, NO_PAD_CTRL)
...
@@ -126,18 +141,32 @@ typedef enum iomux_config {
...
@@ -126,18 +141,32 @@ typedef enum iomux_config {
#define MX51_PAD_NANDF_RB0__GPIO_3_8 IOMUX_PAD(0x4F8, 0x11C, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_RB0__GPIO_3_8 IOMUX_PAD(0x4F8, 0x11C, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_RB1__GPIO_3_9 IOMUX_PAD(0x4FC, 0x120, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_RB1__GPIO_3_9 IOMUX_PAD(0x4FC, 0x120, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_RB2__GPIO_3_10 IOMUX_PAD(0x500, 0x124, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_RB2__GPIO_3_10 IOMUX_PAD(0x500, 0x124, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_RB2__ECSPI2_SCLK IOMUX_PAD(0x500, 0x124, 2, 0x0, 0, MX51_ECSPI_PAD_CTRL)
#define MX51_PAD_NANDF_RB2__FEC_COL IOMUX_PAD(0x500, 0x124, 1, 0x0, 0, MX51_PAD_CTRL_2)
#define MX51_PAD_NANDF_RB3__GPIO_3_11 IOMUX_PAD(0x504, 0x128, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_RB3__GPIO_3_11 IOMUX_PAD(0x504, 0x128, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_RB3__ECSPI2_MISO IOMUX_PAD(0x504, 0x128, 2, 0x0, 0, MX51_ECSPI_PAD_CTRL)
#define MX51_PAD_NANDF_RB3__FEC_RXCLK IOMUX_PAD(0x504, 0x128, 1, 0x0, 0, MX51_PAD_CTRL_2)
#define MX51_PAD_NANDF_RB6__FEC_RDAT0 IOMUX_PAD(0x5DC, 0x134, 1, 0x0, 0, MX51_PAD_CTRL_4)
#define MX51_PAD_NANDF_RB7__FEC_TDAT0 IOMUX_PAD(0x5E0, 0x138, 1, 0x0, 0, MX51_PAD_CTRL_5)
#define MX51_PAD_GPIO_NAND__GPIO_3_12 IOMUX_PAD(0x514, 0x12C, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_NAND__GPIO_3_12 IOMUX_PAD(0x514, 0x12C, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_CS0__GPIO_3_16 IOMUX_PAD(0x518, 0x130, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_CS0__GPIO_3_16 IOMUX_PAD(0x518, 0x130, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_CS1__GPIO_3_17 IOMUX_PAD(0x51C, 0x134, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_CS1__GPIO_3_17 IOMUX_PAD(0x51C, 0x134, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_CS2__GPIO_3_18 IOMUX_PAD(0x520, 0x138, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_CS2__GPIO_3_18 IOMUX_PAD(0x520, 0x138, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_CS2__FEC_TX_ER IOMUX_PAD(0x520, 0x138, 2, 0x0, 0, MX51_PAD_CTRL_5)
#define MX51_PAD_NANDF_CS3__GPIO_3_19 IOMUX_PAD(0x524, 0x13C, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_CS3__GPIO_3_19 IOMUX_PAD(0x524, 0x13C, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_CS3__FEC_MDC IOMUX_PAD(0x524, 0x13C, 2, 0x0, 0, MX51_PAD_CTRL_5)
#define MX51_PAD_NANDF_CS4__GPIO_3_20 IOMUX_PAD(0x528, 0x140, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_CS4__GPIO_3_20 IOMUX_PAD(0x528, 0x140, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_CS4__FEC_TDAT1 IOMUX_PAD(0x528, 0x140, 2, 0x0, 0, MX51_PAD_CTRL_5)
#define MX51_PAD_NANDF_CS5__GPIO_3_21 IOMUX_PAD(0x52C, 0x144, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_CS5__GPIO_3_21 IOMUX_PAD(0x52C, 0x144, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_CS5__FEC_TDAT2 IOMUX_PAD(0x52C, 0x144, 2, 0x0, 0, MX51_PAD_CTRL_5)
#define MX51_PAD_NANDF_CS6__GPIO_3_22 IOMUX_PAD(0x530, 0x148, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_CS6__GPIO_3_22 IOMUX_PAD(0x530, 0x148, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_CS6__FEC_TDAT3 IOMUX_PAD(0x530, 0x148, 2, 0x0, 0, MX51_PAD_CTRL_5)
#define MX51_PAD_NANDF_CS7__GPIO_3_23 IOMUX_PAD(0x534, 0x14C, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_CS7__GPIO_3_23 IOMUX_PAD(0x534, 0x14C, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_CS7__FEC_TX_EN IOMUX_PAD(0x534, 0x14C, 1, 0x0, 0, MX51_PAD_CTRL_5)
#define MX51_PAD_NANDF_RDY_INT__GPIO_3_24 IOMUX_PAD(0x538, 0x150, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_RDY_INT__GPIO_3_24 IOMUX_PAD(0x538, 0x150, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK IOMUX_PAD(0x538, 0x150, 1, 0x0, 0, MX51_PAD_CTRL_4)
#define MX51_PAD_NANDF_D15__GPIO_3_25 IOMUX_PAD(0x53C, 0x154, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_D15__GPIO_3_25 IOMUX_PAD(0x53C, 0x154, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_D15__ECSPI2_MOSI IOMUX_PAD(0x53C, 0x154, 2, 0x0, 0, MX51_ECSPI_PAD_CTRL)
#define MX51_PAD_NANDF_D14__GPIO_3_26 IOMUX_PAD(0x540, 0x158, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_D14__GPIO_3_26 IOMUX_PAD(0x540, 0x158, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_D13__GPIO_3_27 IOMUX_PAD(0x544, 0x15C, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_D13__GPIO_3_27 IOMUX_PAD(0x544, 0x15C, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_D12__GPIO_3_28 IOMUX_PAD(0x548, 0x160, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_D12__GPIO_3_28 IOMUX_PAD(0x548, 0x160, 3, 0x0, 0, NO_PAD_CTRL)
...
@@ -185,15 +214,25 @@ typedef enum iomux_config {
...
@@ -185,15 +214,25 @@ typedef enum iomux_config {
#define MX51_PAD_I2C1_CLK__HSI2C_CLK IOMUX_PAD(0x5E8, 0x1F8, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_I2C1_CLK__HSI2C_CLK IOMUX_PAD(0x5E8, 0x1F8, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_I2C1_DAT__GPIO_4_17 IOMUX_PAD(0x5EC, 0x1FC, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_I2C1_DAT__GPIO_4_17 IOMUX_PAD(0x5EC, 0x1FC, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_I2C1_DAT__HSI2C_DAT IOMUX_PAD(0x5EC, 0x1FC, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_I2C1_DAT__HSI2C_DAT IOMUX_PAD(0x5EC, 0x1FC, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_AUD3_BB_TXD__AUD3_BB_TXD IOMUX_PAD(0x5F0, 0x200, IOMUX_CONFIG_SION, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_AUD3_BB_TXD__GPIO_4_18 IOMUX_PAD(0x5F0, 0x200, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_AUD3_BB_TXD__GPIO_4_18 IOMUX_PAD(0x5F0, 0x200, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_AUD3_BB_RXD__AUD3_BB_RXD IOMUX_PAD(0x5F4, 0x204, IOMUX_CONFIG_SION, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_AUD3_BB_RXD__GPIO_4_19 IOMUX_PAD(0x5F4, 0x204, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_AUD3_BB_RXD__GPIO_4_19 IOMUX_PAD(0x5F4, 0x204, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_AUD3_BB_CK__AUD3_BB_CK IOMUX_PAD(0x5F8, 0x208, IOMUX_CONFIG_SION, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_AUD3_BB_CK__GPIO_4_20 IOMUX_PAD(0x5F8, 0x208, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_AUD3_BB_CK__GPIO_4_20 IOMUX_PAD(0x5F8, 0x208, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_AUD3_BB_FS__AUD3_BB_FS IOMUX_PAD(0x5FC, 0x20C, IOMUX_CONFIG_SION, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_AUD3_BB_FS__GPIO_4_21 IOMUX_PAD(0x5FC, 0x20C, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_AUD3_BB_FS__GPIO_4_21 IOMUX_PAD(0x5FC, 0x20C, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI IOMUX_PAD(0x600, 0x210, 0, 0x0, 0, MX51_ECSPI_PAD_CTRL)
#define MX51_PAD_CSPI1_MOSI__GPIO_4_22 IOMUX_PAD(0x600, 0x210, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_CSPI1_MOSI__GPIO_4_22 IOMUX_PAD(0x600, 0x210, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_CSPI1_MISO__ECSPI1_MISO IOMUX_PAD(0x604, 0x214, 0, 0x0, 0, MX51_ECSPI_PAD_CTRL)
#define MX51_PAD_CSPI1_MISO__GPIO_4_23 IOMUX_PAD(0x604, 0x214, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_CSPI1_MISO__GPIO_4_23 IOMUX_PAD(0x604, 0x214, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_CSPI1_SS0__ECSPI1_SS0 IOMUX_PAD(0x608, 0x218, 0, 0x0, 0, MX51_ECSPI_PAD_CTRL)
#define MX51_PAD_CSPI1_SS0__GPIO_4_24 IOMUX_PAD(0x608, 0x218, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_CSPI1_SS0__GPIO_4_24 IOMUX_PAD(0x608, 0x218, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_CSPI1_SS1__ECSPI1_SS1 IOMUX_PAD(0x60C, 0x21C, 0, 0x0, 0, MX51_ECSPI_PAD_CTRL)
#define MX51_PAD_CSPI1_SS1__GPIO_4_25 IOMUX_PAD(0x60C, 0x21C, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_CSPI1_SS1__GPIO_4_25 IOMUX_PAD(0x60C, 0x21C, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_CSPI1_RDY__ECSPI1_RDY IOMUX_PAD(0x610, 0x220, 0, 0x0, 0, MX51_ECSPI_PAD_CTRL)
#define MX51_PAD_CSPI1_RDY__GPIO_4_26 IOMUX_PAD(0x610, 0x220, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_CSPI1_RDY__GPIO_4_26 IOMUX_PAD(0x610, 0x220, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK IOMUX_PAD(0x614, 0x224, 0, 0x0, 0, MX51_ECSPI_PAD_CTRL)
#define MX51_PAD_CSPI1_SCLK__GPIO_4_27 IOMUX_PAD(0x614, 0x224, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_CSPI1_SCLK__GPIO_4_27 IOMUX_PAD(0x614, 0x224, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_UART1_RXD__UART1_RXD IOMUX_PAD(0x618, 0x228, 0, 0x9e4, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST)
#define MX51_PAD_UART1_RXD__UART1_RXD IOMUX_PAD(0x618, 0x228, 0, 0x9e4, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST)
#define MX51_PAD_UART1_TXD__UART1_TXD IOMUX_PAD(0x61C, 0x22C, 0, 0x0, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST)
#define MX51_PAD_UART1_TXD__UART1_TXD IOMUX_PAD(0x61C, 0x22C, 0, 0x0, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST)
...
@@ -236,14 +275,14 @@ typedef enum iomux_config {
...
@@ -236,14 +275,14 @@ typedef enum iomux_config {
#define MX51_PAD_USBH1_DATA6__USBH1_DATA6 IOMUX_PAD(0x6A0, 0x2A0, 0, 0x0, 0, MX51_USBH1_PAD_CTRL)
#define MX51_PAD_USBH1_DATA6__USBH1_DATA6 IOMUX_PAD(0x6A0, 0x2A0, 0, 0x0, 0, MX51_USBH1_PAD_CTRL)
#define MX51_PAD_USBH1_DATA7__USBH1_DATA7 IOMUX_PAD(0x6A4, 0x2A4, 0, 0x0, 0, MX51_USBH1_PAD_CTRL)
#define MX51_PAD_USBH1_DATA7__USBH1_DATA7 IOMUX_PAD(0x6A4, 0x2A4, 0, 0x0, 0, MX51_USBH1_PAD_CTRL)
#define MX51_PAD_DI1_PIN11__GPIO_3_0 IOMUX_PAD(0x6A8, 0x2A8, 4, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DI1_PIN11__GPIO_3_0 IOMUX_PAD(0x6A8, 0x2A8, 4, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DI1_PIN12__GPIO_3_1 IOMUX_PAD(0x6AC, 0x2AC, 4, 0x
0, 0
, NO_PAD_CTRL)
#define MX51_PAD_DI1_PIN12__GPIO_3_1 IOMUX_PAD(0x6AC, 0x2AC, 4, 0x
978, 1
, NO_PAD_CTRL)
#define MX51_PAD_DI1_PIN13__GPIO_3_2 IOMUX_PAD(0x6B0, 0x2B0, 4, 0x
0, 0
, NO_PAD_CTRL)
#define MX51_PAD_DI1_PIN13__GPIO_3_2 IOMUX_PAD(0x6B0, 0x2B0, 4, 0x
97c, 1
, NO_PAD_CTRL)
#define MX51_PAD_DI1_D0_CS__GPIO_3_3 IOMUX_PAD(0x6B4, 0x2B4, 4, 0x
0, 0
, NO_PAD_CTRL)
#define MX51_PAD_DI1_D0_CS__GPIO_3_3 IOMUX_PAD(0x6B4, 0x2B4, 4, 0x
980, 1
, NO_PAD_CTRL)
#define MX51_PAD_DI1_D1_CS__GPIO_3_4 IOMUX_PAD(0x6B8, 0x2B8, 4, 0x
0, 0
, NO_PAD_CTRL)
#define MX51_PAD_DI1_D1_CS__GPIO_3_4 IOMUX_PAD(0x6B8, 0x2B8, 4, 0x
984, 1
, NO_PAD_CTRL)
#define MX51_PAD_DISPB2_SER_DIN__GPIO_3_5 IOMUX_PAD(0x6BC, 0x2BC, 4, 0x
0, 0
, NO_PAD_CTRL)
#define MX51_PAD_DISPB2_SER_DIN__GPIO_3_5 IOMUX_PAD(0x6BC, 0x2BC, 4, 0x
988, 1
, NO_PAD_CTRL)
#define MX51_PAD_DISPB2_SER_DIO__GPIO_3_6 IOMUX_PAD(0x6C0, 0x2C0, 4, 0x
0, 0
, NO_PAD_CTRL)
#define MX51_PAD_DISPB2_SER_DIO__GPIO_3_6 IOMUX_PAD(0x6C0, 0x2C0, 4, 0x
98c, 1
, NO_PAD_CTRL)
#define MX51_PAD_DISPB2_SER_CLK__GPIO_3_7 IOMUX_PAD(0x6C4, 0x2C4, 4, 0x
0, 0
, NO_PAD_CTRL)
#define MX51_PAD_DISPB2_SER_CLK__GPIO_3_7 IOMUX_PAD(0x6C4, 0x2C4, 4, 0x
990, 1
, NO_PAD_CTRL)
#define MX51_PAD_DISPB2_SER_RS__GPIO_3_8 IOMUX_PAD(0x6C8, 0x2C8, 4, 0x
0, 0
, NO_PAD_CTRL)
#define MX51_PAD_DISPB2_SER_RS__GPIO_3_8 IOMUX_PAD(0x6C8, 0x2C8, 4, 0x
994, 1
, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT0__DISP1_DAT0 IOMUX_PAD(0x6CC, 0x2CC, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT0__DISP1_DAT0 IOMUX_PAD(0x6CC, 0x2CC, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT1__DISP1_DAT1 IOMUX_PAD(0x6D0, 0x2D0, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT1__DISP1_DAT1 IOMUX_PAD(0x6D0, 0x2D0, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT2__DISP1_DAT2 IOMUX_PAD(0x6D4, 0x2D4, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT2__DISP1_DAT2 IOMUX_PAD(0x6D4, 0x2D4, 0, 0x0, 0, NO_PAD_CTRL)
...
@@ -295,11 +334,17 @@ typedef enum iomux_config {
...
@@ -295,11 +334,17 @@ typedef enum iomux_config {
#define MX51_PAD_DISP2_DAT14__DISP2_DAT14 IOMUX_PAD(0x794, 0x38C, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP2_DAT14__DISP2_DAT14 IOMUX_PAD(0x794, 0x38C, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP2_DAT15__DISP2_DAT15 IOMUX_PAD(0x798, 0x390, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP2_DAT15__DISP2_DAT15 IOMUX_PAD(0x798, 0x390, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x79C, 0x394, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x79C, 0x394, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_SD1_CMD__AUD5_RXFS IOMUX_PAD(0x79C, 0x394, 1, 0x8e0, 1, NO_PAD_CTRL)
#define MX51_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x7A0, 0x398, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x7A0, 0x398, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_SD1_CLK__AUD5_RXC IOMUX_PAD(0x7A0, 0x398, 1, 0x8dc, 1, NO_PAD_CTRL)
#define MX51_PAD_SD1_DATA0__SD1_DATA0 IOMUX_PAD(0x7A4, 0x39C, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_SD1_DATA0__SD1_DATA0 IOMUX_PAD(0x7A4, 0x39C, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_SD1_DATA0__AUD5_TXD IOMUX_PAD(0x7A4, 0x39C, 1, 0x8d8, 2, NO_PAD_CTRL)
#define MX51_PAD_SD1_DATA1__SD1_DATA1 IOMUX_PAD(0x7A8, 0x3A0, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_SD1_DATA1__SD1_DATA1 IOMUX_PAD(0x7A8, 0x3A0, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_SD1_DATA1__AUD5_RXD IOMUX_PAD(0x7A8, 0x3A0, 1, 0x8d4, 2, NO_PAD_CTRL)
#define MX51_PAD_SD1_DATA2__SD1_DATA2 IOMUX_PAD(0x7AC, 0x3A4, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_SD1_DATA2__SD1_DATA2 IOMUX_PAD(0x7AC, 0x3A4, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_SD1_DATA2__AUD5_TXC IOMUX_PAD(0x7AC, 0x3A4, 1, 0x8e4, 2, NO_PAD_CTRL)
#define MX51_PAD_SD1_DATA3__SD1_DATA3 IOMUX_PAD(0x7B0, 0x3A8, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_SD1_DATA3__SD1_DATA3 IOMUX_PAD(0x7B0, 0x3A8, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_SD1_DATA3__AUD5_TXFS IOMUX_PAD(0x7B0, 0x3A8, 1, 0x8e8, 2, NO_PAD_CTRL)
#define MX51_PAD_GPIO_1_0__GPIO_1_0 IOMUX_PAD(0x7B4, 0x3AC, 1, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_1_0__GPIO_1_0 IOMUX_PAD(0x7B4, 0x3AC, 1, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_1_1__GPIO_1_1 IOMUX_PAD(0x7B8, 0x3B0, 1, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_1_1__GPIO_1_1 IOMUX_PAD(0x7B8, 0x3B0, 1, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_SD2_CMD__SD2_CMD IOMUX_PAD(0x7BC, 0x3B4, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_SD2_CMD__SD2_CMD IOMUX_PAD(0x7BC, 0x3B4, 0, 0x0, 0, NO_PAD_CTRL)
...
...
arch/arm/plat-mxc/include/mach/mx21.h
View file @
c9ee46a9
...
@@ -120,7 +120,7 @@
...
@@ -120,7 +120,7 @@
#define MX21_INT_GPT1 26
#define MX21_INT_GPT1 26
#define MX21_INT_WDOG 27
#define MX21_INT_WDOG 27
#define MX21_INT_PCMCIA 28
#define MX21_INT_PCMCIA 28
#define MX21_INT_N
AND
FC 29
#define MX21_INT_NFC 29
#define MX21_INT_BMI 30
#define MX21_INT_BMI 30
#define MX21_INT_CSI 31
#define MX21_INT_CSI 31
#define MX21_INT_DMACH0 32
#define MX21_INT_DMACH0 32
...
...
arch/arm/plat-mxc/include/mach/mx25.h
View file @
c9ee46a9
...
@@ -50,6 +50,8 @@
...
@@ -50,6 +50,8 @@
#define MX25_SSI1_BASE_ADDR 0x50034000
#define MX25_SSI1_BASE_ADDR 0x50034000
#define MX25_NFC_BASE_ADDR 0xbb000000
#define MX25_NFC_BASE_ADDR 0xbb000000
#define MX25_DRYICE_BASE_ADDR 0x53ffc000
#define MX25_DRYICE_BASE_ADDR 0x53ffc000
#define MX25_ESDHC1_BASE_ADDR 0x53fb4000
#define MX25_ESDHC2_BASE_ADDR 0x53fb8000
#define MX25_LCDC_BASE_ADDR 0x53fbc000
#define MX25_LCDC_BASE_ADDR 0x53fbc000
#define MX25_KPP_BASE_ADDR 0x43fa8000
#define MX25_KPP_BASE_ADDR 0x43fa8000
#define MX25_OTG_BASE_ADDR 0x53ff4000
#define MX25_OTG_BASE_ADDR 0x53ff4000
...
@@ -59,6 +61,8 @@
...
@@ -59,6 +61,8 @@
#define MX25_INT_I2C1 3
#define MX25_INT_I2C1 3
#define MX25_INT_I2C2 4
#define MX25_INT_I2C2 4
#define MX25_INT_UART4 5
#define MX25_INT_UART4 5
#define MX25_INT_MMC_SDHC2 8
#define MX25_INT_MMC_SDHC1 9
#define MX25_INT_I2C3 10
#define MX25_INT_I2C3 10
#define MX25_INT_SSI2 11
#define MX25_INT_SSI2 11
#define MX25_INT_SSI1 12
#define MX25_INT_SSI1 12
...
@@ -69,7 +73,7 @@
...
@@ -69,7 +73,7 @@
#define MX25_INT_KPP 24
#define MX25_INT_KPP 24
#define MX25_INT_DRYICE 25
#define MX25_INT_DRYICE 25
#define MX25_INT_UART2 32
#define MX25_INT_UART2 32
#define MX25_INT_N
AND
FC 33
#define MX25_INT_NFC 33
#define MX25_INT_LCDC 39
#define MX25_INT_LCDC 39
#define MX25_INT_UART5 40
#define MX25_INT_UART5 40
#define MX25_INT_CAN1 43
#define MX25_INT_CAN1 43
...
@@ -77,4 +81,13 @@
...
@@ -77,4 +81,13 @@
#define MX25_INT_UART1 45
#define MX25_INT_UART1 45
#define MX25_INT_FEC 57
#define MX25_INT_FEC 57
#define MX25_DMA_REQ_SSI2_RX1 22
#define MX25_DMA_REQ_SSI2_TX1 23
#define MX25_DMA_REQ_SSI2_RX0 24
#define MX25_DMA_REQ_SSI2_TX0 25
#define MX25_DMA_REQ_SSI1_RX1 26
#define MX25_DMA_REQ_SSI1_TX1 27
#define MX25_DMA_REQ_SSI1_RX0 28
#define MX25_DMA_REQ_SSI1_TX0 29
#endif
/* ifndef __MACH_MX25_H__ */
#endif
/* ifndef __MACH_MX25_H__ */
arch/arm/plat-mxc/include/mach/mx27.h
View file @
c9ee46a9
...
@@ -167,7 +167,7 @@ static inline void mx27_setup_weimcs(size_t cs,
...
@@ -167,7 +167,7 @@ static inline void mx27_setup_weimcs(size_t cs,
#define MX27_INT_GPT1 26
#define MX27_INT_GPT1 26
#define MX27_INT_WDOG 27
#define MX27_INT_WDOG 27
#define MX27_INT_PCMCIA 28
#define MX27_INT_PCMCIA 28
#define MX27_INT_N
AND
FC 29
#define MX27_INT_NFC 29
#define MX27_INT_ATA 30
#define MX27_INT_ATA 30
#define MX27_INT_CSI 31
#define MX27_INT_CSI 31
#define MX27_INT_DMACH0 32
#define MX27_INT_DMACH0 32
...
...
arch/arm/plat-mxc/include/mach/mx31.h
View file @
c9ee46a9
...
@@ -168,7 +168,7 @@ static inline void mx31_setup_weimcs(size_t cs,
...
@@ -168,7 +168,7 @@ static inline void mx31_setup_weimcs(size_t cs,
#define MX31_INT_POWER_FAIL 30
#define MX31_INT_POWER_FAIL 30
#define MX31_INT_CCM_DVFS 31
#define MX31_INT_CCM_DVFS 31
#define MX31_INT_UART2 32
#define MX31_INT_UART2 32
#define MX31_INT_N
AND
FC 33
#define MX31_INT_NFC 33
#define MX31_INT_SDMA 34
#define MX31_INT_SDMA 34
#define MX31_INT_USB1 35
#define MX31_INT_USB1 35
#define MX31_INT_USB2 36
#define MX31_INT_USB2 36
...
@@ -197,6 +197,15 @@ static inline void mx31_setup_weimcs(size_t cs,
...
@@ -197,6 +197,15 @@ static inline void mx31_setup_weimcs(size_t cs,
#define MX31_INT_EXT_WDOG 62
#define MX31_INT_EXT_WDOG 62
#define MX31_INT_EXT_TV 63
#define MX31_INT_EXT_TV 63
#define MX31_DMA_REQ_SSI2_RX1 22
#define MX31_DMA_REQ_SSI2_TX1 23
#define MX31_DMA_REQ_SSI2_RX0 24
#define MX31_DMA_REQ_SSI2_TX0 25
#define MX31_DMA_REQ_SSI1_RX1 26
#define MX31_DMA_REQ_SSI1_TX1 27
#define MX31_DMA_REQ_SSI1_RX0 28
#define MX31_DMA_REQ_SSI1_TX0 29
#define MX31_PROD_SIGNATURE 0x1
/* For MX31 */
#define MX31_PROD_SIGNATURE 0x1
/* For MX31 */
/* silicon revisions specific to i.MX31 */
/* silicon revisions specific to i.MX31 */
...
...
arch/arm/plat-mxc/include/mach/mx35.h
View file @
c9ee46a9
#ifndef __MACH_MX35_H__
#ifndef __MACH_MX35_H__
#define __MACH_MX35_H__
#define __MACH_MX35_H__
/*
/*
* IRAM
* IRAM
*/
*/
...
@@ -52,6 +53,9 @@
...
@@ -52,6 +53,9 @@
#define MX35_GPIO3_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xa4000)
#define MX35_GPIO3_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xa4000)
#define MX35_SCC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xac000)
#define MX35_SCC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xac000)
#define MX35_RNGA_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xb0000)
#define MX35_RNGA_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xb0000)
#define MX35_ESDHC1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xb4000)
#define MX35_ESDHC2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xb8000)
#define MX35_ESDHC3_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xbc000)
#define MX35_IPU_CTRL_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xc0000)
#define MX35_IPU_CTRL_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xc0000)
#define MX35_AUDMUX_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xc4000)
#define MX35_AUDMUX_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xc4000)
#define MX35_GPIO1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xcc000)
#define MX35_GPIO1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xcc000)
...
@@ -63,6 +67,8 @@
...
@@ -63,6 +67,8 @@
#define MX35_CAN1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe4000)
#define MX35_CAN1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe4000)
#define MX35_CAN2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe8000)
#define MX35_CAN2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe8000)
#define MX35_RTIC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xec000)
#define MX35_RTIC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xec000)
#define MX35_IIM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xf0000)
#define MX35_OTG_BASE_ADDR 0x53ff4000
#define MX35_OTG_BASE_ADDR 0x53ff4000
#define MX35_ROMP_BASE_ADDR 0x60000000
#define MX35_ROMP_BASE_ADDR 0x60000000
...
@@ -145,7 +151,7 @@
...
@@ -145,7 +151,7 @@
#define MX35_INT_GPT 29
#define MX35_INT_GPT 29
#define MX35_INT_POWER_FAIL 30
#define MX35_INT_POWER_FAIL 30
#define MX35_INT_UART2 32
#define MX35_INT_UART2 32
#define MX35_INT_N
AND
FC 33
#define MX35_INT_NFC 33
#define MX35_INT_SDMA 34
#define MX35_INT_SDMA 34
#define MX35_INT_USBHS 35
#define MX35_INT_USBHS 35
#define MX35_INT_USBOTG 37
#define MX35_INT_USBOTG 37
...
@@ -173,22 +179,18 @@
...
@@ -173,22 +179,18 @@
#define MX35_INT_EXT_WDOG 62
#define MX35_INT_EXT_WDOG 62
#define MX35_INT_EXT_TV 63
#define MX35_INT_EXT_TV 63
#define MX35_DMA_REQ_SSI2_RX1 22
#define MX35_DMA_REQ_SSI2_TX1 23
#define MX35_DMA_REQ_SSI2_RX0 24
#define MX35_DMA_REQ_SSI2_TX0 25
#define MX35_DMA_REQ_SSI1_RX1 26
#define MX35_DMA_REQ_SSI1_TX1 27
#define MX35_DMA_REQ_SSI1_RX0 28
#define MX35_DMA_REQ_SSI1_TX0 29
#define MX35_PROD_SIGNATURE 0x1
/* For MX31 */
#define MX35_PROD_SIGNATURE 0x1
/* For MX31 */
/* silicon revisions specific to i.MX31 */
#define MX35_SYSTEM_REV_MIN MX3x_CHIP_REV_1_0
#define MX35_CHIP_REV_1_0 0x10
#define MX35_CHIP_REV_1_1 0x11
#define MX35_CHIP_REV_1_2 0x12
#define MX35_CHIP_REV_1_3 0x13
#define MX35_CHIP_REV_2_0 0x20
#define MX35_CHIP_REV_2_1 0x21
#define MX35_CHIP_REV_2_2 0x22
#define MX35_CHIP_REV_2_3 0x23
#define MX35_CHIP_REV_3_0 0x30
#define MX35_CHIP_REV_3_1 0x31
#define MX35_CHIP_REV_3_2 0x32
#define MX35_SYSTEM_REV_MIN MX35_CHIP_REV_1_0
#define MX35_SYSTEM_REV_NUM 3
#define MX35_SYSTEM_REV_NUM 3
#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
...
...
arch/arm/plat-mxc/include/mach/mx3x.h
View file @
c9ee46a9
...
@@ -240,7 +240,7 @@
...
@@ -240,7 +240,7 @@
#define MX3x_PROD_SIGNATURE 0x1
/* For MX31 */
#define MX3x_PROD_SIGNATURE 0x1
/* For MX31 */
/* silicon revisions specific to i.MX31 */
/* silicon revisions specific to i.MX31
and i.MX35
*/
#define MX3x_CHIP_REV_1_0 0x10
#define MX3x_CHIP_REV_1_0 0x10
#define MX3x_CHIP_REV_1_1 0x11
#define MX3x_CHIP_REV_1_1 0x11
#define MX3x_CHIP_REV_1_2 0x12
#define MX3x_CHIP_REV_1_2 0x12
...
@@ -267,6 +267,14 @@ static inline int mx31_revision(void)
...
@@ -267,6 +267,14 @@ static inline int mx31_revision(void)
{
{
return
mx31_cpu_rev
;
return
mx31_cpu_rev
;
}
}
extern
unsigned
int
mx35_cpu_rev
;
extern
void
mx35_read_cpu_rev
(
void
);
static
inline
int
mx35_revision
(
void
)
{
return
mx35_cpu_rev
;
}
#endif
#endif
#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
...
@@ -389,19 +397,6 @@ static inline int mx31_revision(void)
...
@@ -389,19 +397,6 @@ static inline int mx31_revision(void)
#define MXC_INT_EXT_WDOG MX3x_INT_EXT_WDOG
#define MXC_INT_EXT_WDOG MX3x_INT_EXT_WDOG
#define MXC_INT_EXT_TV MX3x_INT_EXT_TV
#define MXC_INT_EXT_TV MX3x_INT_EXT_TV
#define PROD_SIGNATURE MX3x_PROD_SIGNATURE
#define PROD_SIGNATURE MX3x_PROD_SIGNATURE
#define CHIP_REV_1_0 MX3x_CHIP_REV_1_0
#define CHIP_REV_1_1 MX3x_CHIP_REV_1_1
#define CHIP_REV_1_2 MX3x_CHIP_REV_1_2
#define CHIP_REV_1_3 MX3x_CHIP_REV_1_3
#define CHIP_REV_2_0 MX3x_CHIP_REV_2_0
#define CHIP_REV_2_1 MX3x_CHIP_REV_2_1
#define CHIP_REV_2_2 MX3x_CHIP_REV_2_2
#define CHIP_REV_2_3 MX3x_CHIP_REV_2_3
#define CHIP_REV_3_0 MX3x_CHIP_REV_3_0
#define CHIP_REV_3_1 MX3x_CHIP_REV_3_1
#define CHIP_REV_3_2 MX3x_CHIP_REV_3_2
#define SYSTEM_REV_MIN MX3x_SYSTEM_REV_MIN
#define SYSTEM_REV_NUM MX3x_SYSTEM_REV_NUM
#endif
#endif
#endif
/* ifndef __MACH_MX3x_H__ */
#endif
/* ifndef __MACH_MX3x_H__ */
arch/arm/plat-mxc/include/mach/mx51.h
View file @
c9ee46a9
#ifndef __
ASM_ARCH_MXC
_MX51_H__
#ifndef __
MACH
_MX51_H__
#define __
ASM_ARCH_MXC
_MX51_H__
#define __
MACH
_MX51_H__
/*
/*
* MX51 memory map:
* MX51 memory map:
...
@@ -7,24 +7,23 @@
...
@@ -7,24 +7,23 @@
*
*
* Virt Phys Size What
* Virt Phys Size What
* ---------------------------------------------------------------------------
* ---------------------------------------------------------------------------
*
FA3E0000 1FFE
0000 128K IRAM (SCCv2 RAM)
*
fa3e0000 1ffe
0000 128K IRAM (SCCv2 RAM)
* 30000000 256M GPU
* 30000000 256M GPU
* 40000000 512M IPU
* 40000000 512M IPU
*
FA
200000 60000000 1M DEBUG
*
fa
200000 60000000 1M DEBUG
*
FB
100000 70000000 1M SPBA 0
*
fb
100000 70000000 1M SPBA 0
*
FB000000 73F
00000 1M AIPS 1
*
fb000000 73f
00000 1M AIPS 1
*
FB200000 83F
00000 1M AIPS 2
*
fb200000 83f
00000 1M AIPS 2
* 8
FFFC
000 16K TZIC (interrupt controller)
* 8
fffc
000 16K TZIC (interrupt controller)
* 90000000 256M CSD0 SDRAM/DDR
* 90000000 256M CSD0 SDRAM/DDR
* A0000000 256M CSD1 SDRAM/DDR
* a0000000 256M CSD1 SDRAM/DDR
* B0000000 128M CS0 Flash
* b0000000 128M CS0 Flash
* B8000000 128M CS1 Flash
* b8000000 128M CS1 Flash
* C0000000 128M CS2 Flash
* c0000000 128M CS2 Flash
* C8000000 64M CS3 Flash
* c8000000 64M CS3 Flash
* CC000000 32M CS4 SRAM
* cc000000 32M CS4 SRAM
* CE000000 32M CS5 SRAM
* ce000000 32M CS5 SRAM
* CFFF0000 64K NFC (NAND Flash AXI)
* cfff0000 64K NFC (NAND Flash AXI)
*
*/
*/
/*
/*
...
@@ -36,65 +35,151 @@
...
@@ -36,65 +35,151 @@
/*
/*
* IRAM
* IRAM
*/
*/
#define MX51_IRAM_BASE_ADDR 0x1
FFE
0000
/* internal ram */
#define MX51_IRAM_BASE_ADDR 0x1
ffe
0000
/* internal ram */
#define MX51_IRAM_BASE_ADDR_VIRT 0x
FA3E
0000
#define MX51_IRAM_BASE_ADDR_VIRT 0x
fa3e
0000
#define MX51_IRAM_PARTITIONS 16
#define MX51_IRAM_PARTITIONS 16
#define MX51_IRAM_PARTITIONS_TO1 12
#define MX51_IRAM_SIZE (MX51_IRAM_PARTITIONS * SZ_8K)
/* 128KB */
#define MX51_IRAM_SIZE (MX51_IRAM_PARTITIONS * SZ_8K)
/* 128KB */
#define MX51_GPU_BASE_ADDR 0x20000000
#define MX51_GPU_CTRL_BASE_ADDR 0x30000000
#define MX51_IPU_CTRL_BASE_ADDR 0x40000000
#define MX51_DEBUG_BASE_ADDR 0x60000000
#define MX51_DEBUG_BASE_ADDR_VIRT 0xfa200000
#define MX51_DEBUG_SIZE SZ_1M
#define MX51_ETB_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x01000)
#define MX51_ETM_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x02000)
#define MX51_TPIU_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x03000)
#define MX51_CTI0_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x04000)
#define MX51_CTI1_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x05000)
#define MX51_CTI2_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x06000)
#define MX51_CTI3_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x07000)
#define MX51_CORTEX_DBG_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x08000)
/*
/*
*
NFC
*
SPBA global module enabled #0
*/
*/
#define MX51_NFC_AXI_BASE_ADDR 0xCFFF0000
/* NAND flash AXI */
#define MX51_SPBA0_BASE_ADDR 0x70000000
#define MX51_NFC_AXI_SIZE SZ_64K
#define MX51_SPBA0_BASE_ADDR_VIRT 0xfb100000
#define MX51_SPBA0_SIZE SZ_1M
#define MX51_MMC_SDHC1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x04000)
#define MX51_MMC_SDHC2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x08000)
#define MX51_UART3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x0c000)
#define MX51_ECSPI1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x10000)
#define MX51_SSI2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x14000)
#define MX51_MMC_SDHC3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x20000)
#define MX51_MMC_SDHC4_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x24000)
#define MX51_SPDIF_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x28000)
#define MX51_ATA_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x30000)
#define MX51_SLIM_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x34000)
#define MX51_HSI2C_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x38000)
#define MX51_SPBA_CTRL_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x3c000)
/*
/*
*
Graphics Memory of GPU
*
AIPS 1
*/
*/
#define MX51_GPU_BASE_ADDR 0x20000000
#define MX51_AIPS1_BASE_ADDR 0x73f00000
#define MX51_GPU2D_BASE_ADDR 0xD0000000
#define MX51_AIPS1_BASE_ADDR_VIRT 0xfb000000
#define MX51_AIPS1_SIZE SZ_1M
#define MX51_OTG_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x80000)
#define MX51_GPIO1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x84000)
#define MX51_GPIO2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x88000)
#define MX51_GPIO3_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x8c000)
#define MX51_GPIO4_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x90000)
#define MX51_KPP_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x94000)
#define MX51_WDOG_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x98000)
#define MX51_WDOG2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x9c000)
#define MX51_GPT1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xa0000)
#define MX51_SRTC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xa4000)
#define MX51_IOMUXC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xa8000)
#define MX51_EPIT1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xac000)
#define MX51_EPIT2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xb0000)
#define MX51_PWM1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xb4000)
#define MX51_PWM2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xb8000)
#define MX51_UART1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xbc000)
#define MX51_UART2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xc0000)
#define MX51_SRC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xd0000)
#define MX51_CCM_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xd4000)
#define MX51_GPC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xd8000)
#define MX51_TZIC_BASE_ADDR_TO1 0x8FFFC000
/*
#define MX51_TZIC_BASE_ADDR 0xE0000000
* AIPS 2
*/
#define MX51_AIPS2_BASE_ADDR 0x83f00000
#define MX51_AIPS2_BASE_ADDR_VIRT 0xfb200000
#define MX51_AIPS2_SIZE SZ_1M
#define MX51_DEBUG_BASE_ADDR 0x60000000
#define MX51_PLL1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x80000)
#define MX51_DEBUG_BASE_ADDR_VIRT 0xFA200000
#define MX51_PLL2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x84000)
#define MX51_DEBUG_SIZE SZ_1M
#define MX51_PLL3_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x88000)
#define MX51_ETB_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00001000)
#define MX51_AHBMAX_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x94000)
#define MX51_ETM_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00002000)
#define MX51_IIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x98000)
#define MX51_TPIU_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00003000)
#define MX51_CSU_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x9c000)
#define MX51_CTI0_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00004000)
#define MX51_ARM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xa0000)
#define MX51_CTI1_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00005000)
#define MX51_OWIRE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xa4000)
#define MX51_CTI2_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00006000)
#define MX51_FIRI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xa8000)
#define MX51_CTI3_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00007000)
#define MX51_ECSPI2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xac000)
#define MX51_CORTEX_DBG_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00008000)
#define MX51_SDMA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xb0000)
#define MX51_SCC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xb4000)
#define MX51_ROMCP_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xb8000)
#define MX51_RTIC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xbc000)
#define MX51_CSPI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xc0000)
#define MX51_I2C2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xc4000)
#define MX51_I2C1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xc8000)
#define MX51_SSI1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xcc000)
#define MX51_AUDMUX_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xd0000)
#define MX51_M4IF_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xd8000)
#define MX51_ESDCTL_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xd9000)
#define MX51_WEIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xda000)
#define MX51_NFC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xdb000)
#define MX51_EMI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xdbf00)
#define MX51_MIPI_HSC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xdc000)
#define MX51_ATA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe0000)
#define MX51_SIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe4000)
#define MX51_SSI3BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe8000)
#define MX51_FEC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xec000)
#define MX51_TVE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xf0000)
#define MX51_VPU_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xf4000)
#define MX51_SAHARA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xf8000)
#define MX51_CSD0_BASE_ADDR 0x90000000
#define MX51_CSD1_BASE_ADDR 0xa0000000
#define MX51_CS0_BASE_ADDR 0xb0000000
#define MX51_CS1_BASE_ADDR 0xb8000000
#define MX51_CS2_BASE_ADDR 0xc0000000
#define MX51_CS3_BASE_ADDR 0xc8000000
#define MX51_CS4_BASE_ADDR 0xcc000000
#define MX51_CS5_BASE_ADDR 0xce000000
/*
/*
*
SPBA global module enabled #0
*
NFC
*/
*/
#define MX51_SPBA0_BASE_ADDR 0x70000000
#define MX51_NFC_AXI_BASE_ADDR 0xcfff0000
/* NAND flash AXI */
#define MX51_SPBA0_BASE_ADDR_VIRT 0xFB100000
#define MX51_NFC_AXI_SIZE SZ_64K
#define MX51_SPBA0_SIZE SZ_1M
#define MX51_GPU2D_BASE_ADDR 0xd0000000
#define MX51_TZIC_BASE_ADDR 0xe0000000
#define MX51_MMC_SDHC1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00004000)
#define MX51_IO_ADDRESS(x) ( \
#define MX51_MMC_SDHC2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00008000)
IMX_IO_ADDRESS(x, MX51_IRAM) ?: \
#define MX51_UART3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x0000C000)
IMX_IO_ADDRESS(x, MX51_DEBUG) ?: \
#define MX51_CSPI1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00010000)
IMX_IO_ADDRESS(x, MX51_SPBA0) ?: \
#define MX51_SSI2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00014000)
IMX_IO_ADDRESS(x, MX51_AIPS1) ?: \
#define MX51_MMC_SDHC3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00020000)
IMX_IO_ADDRESS(x, MX51_AIPS2))
#define MX51_MMC_SDHC4_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00024000)
#define MX51_SPDIF_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00028000)
/* This is currently used in <mach/debug-macro.S>, but should go away */
#define MX51_ATA_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00030000)
#define MX51_AIPS1_IO_ADDRESS(x) \
#define MX51_SLIM_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00034000)
(((x) - MX51_AIPS1_BASE_ADDR) + MX51_AIPS1_BASE_ADDR_VIRT)
#define MX51_HSI2C_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00038000)
#define MX51_SPBA_CTRL_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x0003C000)
/*
/*
* defines for SPBA modules
* defines for SPBA modules
*/
*/
#define MX51_SPBA_SDHC1 0x04
#define MX51_SPBA_SDHC1 0x04
#define MX51_SPBA_SDHC2 0x08
#define MX51_SPBA_SDHC2 0x08
#define MX51_SPBA_UART3 0x0
C
#define MX51_SPBA_UART3 0x0
c
#define MX51_SPBA_CSPI1 0x10
#define MX51_SPBA_CSPI1 0x10
#define MX51_SPBA_SSI2 0x14
#define MX51_SPBA_SSI2 0x14
#define MX51_SPBA_SDHC3 0x20
#define MX51_SPBA_SDHC3 0x20
...
@@ -103,35 +188,7 @@
...
@@ -103,35 +188,7 @@
#define MX51_SPBA_ATA 0x30
#define MX51_SPBA_ATA 0x30
#define MX51_SPBA_SLIM 0x34
#define MX51_SPBA_SLIM 0x34
#define MX51_SPBA_HSI2C 0x38
#define MX51_SPBA_HSI2C 0x38
#define MX51_SPBA_CTRL 0x3C
#define MX51_SPBA_CTRL 0x3c
/*
* AIPS 1
*/
#define MX51_AIPS1_BASE_ADDR 0x73F00000
#define MX51_AIPS1_BASE_ADDR_VIRT 0xFB000000
#define MX51_AIPS1_SIZE SZ_1M
#define MX51_OTG_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00080000)
#define MX51_GPIO1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00084000)
#define MX51_GPIO2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00088000)
#define MX51_GPIO3_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x0008C000)
#define MX51_GPIO4_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00090000)
#define MX51_KPP_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00094000)
#define MX51_WDOG_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00098000)
#define MX51_WDOG2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x0009C000)
#define MX51_GPT1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000A0000)
#define MX51_SRTC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000A4000)
#define MX51_IOMUXC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000A8000)
#define MX51_EPIT1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000AC000)
#define MX51_EPIT2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000B0000)
#define MX51_PWM1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000B4000)
#define MX51_PWM2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000B8000)
#define MX51_UART1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000BC000)
#define MX51_UART2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000C0000)
#define MX51_SRC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000D0000)
#define MX51_CCM_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000D4000)
#define MX51_GPC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000D8000)
/*
/*
* Defines for modules using static and dynamic DMA channels
* Defines for modules using static and dynamic DMA channels
...
@@ -164,282 +221,186 @@
...
@@ -164,282 +221,186 @@
#define MX51_MXC_DMA_CHANNEL_ATA_TX MXC_DMA_DYNAMIC_CHANNEL
#define MX51_MXC_DMA_CHANNEL_ATA_TX MXC_DMA_DYNAMIC_CHANNEL
#define MX51_MXC_DMA_CHANNEL_MEMORY MXC_DMA_DYNAMIC_CHANNEL
#define MX51_MXC_DMA_CHANNEL_MEMORY MXC_DMA_DYNAMIC_CHANNEL
/*
* AIPS 2
*/
#define MX51_AIPS2_BASE_ADDR 0x83F00000
#define MX51_AIPS2_BASE_ADDR_VIRT 0xFB200000
#define MX51_AIPS2_SIZE SZ_1M
#define MX51_PLL1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00080000)
#define MX51_PLL2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00084000)
#define MX51_PLL3_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00088000)
#define MX51_AHBMAX_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00094000)
#define MX51_IIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00098000)
#define MX51_CSU_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x0009C000)
#define MX51_ARM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000A0000)
#define MX51_OWIRE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000A4000)
#define MX51_FIRI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000A8000)
#define MX51_CSPI2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000AC000)
#define MX51_SDMA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000B0000)
#define MX51_SCC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000B4000)
#define MX51_ROMCP_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000B8000)
#define MX51_RTIC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000BC000)
#define MX51_CSPI3_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000C0000)
#define MX51_I2C2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000C4000)
#define MX51_I2C1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000C8000)
#define MX51_SSI1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000CC000)
#define MX51_AUDMUX_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000D0000)
#define MX51_M4IF_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000D8000)
#define MX51_ESDCTL_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000D9000)
#define MX51_WEIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000DA000)
#define MX51_NFC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000DB000)
#define MX51_EMI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000DBF00)
#define MX51_MIPI_HSC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000DC000)
#define MX51_ATA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000E0000)
#define MX51_SIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000E4000)
#define MX51_SSI3BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000E8000)
#define MX51_MXC_FEC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000EC000)
#define MX51_TVE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000F0000)
#define MX51_VPU_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000F4000)
#define MX51_SAHARA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000F8000)
/*
* Memory regions and CS
*/
#define MX51_GPU_CTRL_BASE_ADDR 0x30000000
#define MX51_IPU_CTRL_BASE_ADDR 0x40000000
#define MX51_CSD0_BASE_ADDR 0x90000000
#define MX51_CSD1_BASE_ADDR 0xA0000000
#define MX51_CS0_BASE_ADDR 0xB0000000
#define MX51_CS1_BASE_ADDR 0xB8000000
#define MX51_CS2_BASE_ADDR 0xC0000000
#define MX51_CS3_BASE_ADDR 0xC8000000
#define MX51_CS4_BASE_ADDR 0xCC000000
#define MX51_CS5_BASE_ADDR 0xCE000000
/* Does given address belongs to the specified memory region? */
#define ADDRESS_IN_REGION(addr, start, size) \
(((addr) >= (start)) && ((addr) < (start)+(size)))
/* Does given address belongs to the specified named `module'? */
#define MX51_IS_MODULE(addr, module) \
ADDRESS_IN_REGION(addr, MX51_ ## module ## _BASE_ADDR, \
MX51_ ## module ## _SIZE)
/*
* This macro defines the physical to virtual address mapping for all the
* peripheral modules. It is used by passing in the physical address as x
* and returning the virtual address. If the physical address is not mapped,
* it returns 0xDEADBEEF
*/
#define MX51_IO_ADDRESS(x) \
(void __iomem *) \
(MX51_IS_MODULE(x, IRAM) ? MX51_IRAM_IO_ADDRESS(x) : \
MX51_IS_MODULE(x, DEBUG) ? MX51_DEBUG_IO_ADDRESS(x) : \
MX51_IS_MODULE(x, SPBA0) ? MX51_SPBA0_IO_ADDRESS(x) : \
MX51_IS_MODULE(x, AIPS1) ? MX51_AIPS1_IO_ADDRESS(x) : \
MX51_IS_MODULE(x, AIPS2) ? MX51_AIPS2_IO_ADDRESS(x) : \
0xDEADBEEF)
/*
* define the address mapping macros: in physical address order
*/
#define MX51_IRAM_IO_ADDRESS(x) \
(((x) - MX51_IRAM_BASE_ADDR) + MX51_IRAM_BASE_ADDR_VIRT)
#define MX51_DEBUG_IO_ADDRESS(x) \
(((x) - MX51_DEBUG_BASE_ADDR) + MX51_DEBUG_BASE_ADDR_VIRT)
#define MX51_SPBA0_IO_ADDRESS(x) \
(((x) - MX51_SPBA0_BASE_ADDR) + MX51_SPBA0_BASE_ADDR_VIRT)
#define MX51_AIPS1_IO_ADDRESS(x) \
(((x) - MX51_AIPS1_BASE_ADDR) + MX51_AIPS1_BASE_ADDR_VIRT)
#define MX51_AIPS2_IO_ADDRESS(x) \
(((x) - MX51_AIPS2_BASE_ADDR) + MX51_AIPS2_BASE_ADDR_VIRT)
#define MX51_IS_MEM_DEVICE_NONSHARED(x) 0
#define MX51_IS_MEM_DEVICE_NONSHARED(x) 0
/*
/*
* DMA request assignments
* DMA request assignments
*/
*/
#define MX51_DMA_REQ_
SSI3_TX1 47
#define MX51_DMA_REQ_
VPU 0
#define MX51_DMA_REQ_
SSI3_RX1 46
#define MX51_DMA_REQ_
GPC 1
#define MX51_DMA_REQ_
SPDIF 45
#define MX51_DMA_REQ_
ATA_RX 2
#define MX51_DMA_REQ_
UART3_TX 44
#define MX51_DMA_REQ_
ATA_TX 3
#define MX51_DMA_REQ_
UART3_RX 43
#define MX51_DMA_REQ_
ATA_TX_END 4
#define MX51_DMA_REQ_SLIM_B
_TX 42
#define MX51_DMA_REQ_SLIM_B
5
#define MX51_DMA_REQ_
SDHC4 41
#define MX51_DMA_REQ_
CSPI1_RX 6
#define MX51_DMA_REQ_
SDHC3 40
#define MX51_DMA_REQ_
CSPI1_TX 7
#define MX51_DMA_REQ_CSPI
_TX 39
#define MX51_DMA_REQ_CSPI
2_RX 8
#define MX51_DMA_REQ_CSPI
_RX 38
#define MX51_DMA_REQ_CSPI
2_TX 9
#define MX51_DMA_REQ_
SSI3_TX2 37
#define MX51_DMA_REQ_
HS_I2C_TX 10
#define MX51_DMA_REQ_
IPU 36
#define MX51_DMA_REQ_
HS_I2C_RX 11
#define MX51_DMA_REQ_
SSI3_RX2 35
#define MX51_DMA_REQ_
FIRI_RX 12
#define MX51_DMA_REQ_
EPIT2 34
#define MX51_DMA_REQ_
FIRI_TX 13
#define MX51_DMA_REQ_
CTI2_1 33
#define MX51_DMA_REQ_
EXTREQ1 14
#define MX51_DMA_REQ_
EMI_WR 32
#define MX51_DMA_REQ_
GPU 15
#define MX51_DMA_REQ_
CTI2_0 31
#define MX51_DMA_REQ_
UART2_RX 16
#define MX51_DMA_REQ_
EMI_RD 30
#define MX51_DMA_REQ_
UART2_TX 17
#define MX51_DMA_REQ_
SSI1_TX1 29
#define MX51_DMA_REQ_
UART1_RX 18
#define MX51_DMA_REQ_
SSI1_RX1 28
#define MX51_DMA_REQ_
UART1_TX 19
#define MX51_DMA_REQ_S
SI1_TX2 27
#define MX51_DMA_REQ_S
DHC1 20
#define MX51_DMA_REQ_S
SI1_RX2 26
#define MX51_DMA_REQ_S
DHC2 21
#define MX51_DMA_REQ_SSI2_
TX1 25
#define MX51_DMA_REQ_SSI2_
RX1 22
#define MX51_DMA_REQ_SSI2_
RX1 24
#define MX51_DMA_REQ_SSI2_
TX1 23
#define MX51_DMA_REQ_SSI2_
TX2 23
#define MX51_DMA_REQ_SSI2_
RX0 24
#define MX51_DMA_REQ_SSI2_
RX2 22
#define MX51_DMA_REQ_SSI2_
TX0 25
#define MX51_DMA_REQ_S
DHC2 21
#define MX51_DMA_REQ_S
SI1_RX1 26
#define MX51_DMA_REQ_S
DHC1 20
#define MX51_DMA_REQ_S
SI1_TX1 27
#define MX51_DMA_REQ_
UART1_TX 19
#define MX51_DMA_REQ_
SSI1_RX0 28
#define MX51_DMA_REQ_
UART1_RX 18
#define MX51_DMA_REQ_
SSI1_TX0 29
#define MX51_DMA_REQ_
UART2_TX 17
#define MX51_DMA_REQ_
EMI_RD 30
#define MX51_DMA_REQ_
UART2_RX 16
#define MX51_DMA_REQ_
CTI2_0 31
#define MX51_DMA_REQ_
GPU 15
#define MX51_DMA_REQ_
EMI_WR 32
#define MX51_DMA_REQ_
EXTREQ1 14
#define MX51_DMA_REQ_
CTI2_1 33
#define MX51_DMA_REQ_
FIRI_TX 13
#define MX51_DMA_REQ_
EPIT2 34
#define MX51_DMA_REQ_
FIRI_RX 12
#define MX51_DMA_REQ_
SSI3_RX2 35
#define MX51_DMA_REQ_
HS_I2C_RX 11
#define MX51_DMA_REQ_
IPU 36
#define MX51_DMA_REQ_
HS_I2C_TX 10
#define MX51_DMA_REQ_
SSI3_TX2 37
#define MX51_DMA_REQ_CSPI
2_TX 9
#define MX51_DMA_REQ_CSPI
_RX 38
#define MX51_DMA_REQ_CSPI
2_RX 8
#define MX51_DMA_REQ_CSPI
_TX 39
#define MX51_DMA_REQ_
CSPI1_TX 7
#define MX51_DMA_REQ_
SDHC3 40
#define MX51_DMA_REQ_
CSPI1_RX 6
#define MX51_DMA_REQ_
SDHC4 41
#define MX51_DMA_REQ_SLIM_B
5
#define MX51_DMA_REQ_SLIM_B
_TX 42
#define MX51_DMA_REQ_
ATA_TX_END 4
#define MX51_DMA_REQ_
UART3_RX 43
#define MX51_DMA_REQ_
ATA_TX 3
#define MX51_DMA_REQ_
UART3_TX 44
#define MX51_DMA_REQ_
ATA_RX 2
#define MX51_DMA_REQ_
SPDIF 45
#define MX51_DMA_REQ_
GPC 1
#define MX51_DMA_REQ_
SSI3_RX1 46
#define MX51_DMA_REQ_
VPU 0
#define MX51_DMA_REQ_
SSI3_TX1 47
/*
/*
* Interrupt numbers
* Interrupt numbers
*/
*/
#define MX51_MXC_INT_BASE 0
#define MX51_MXC_INT_BASE
0
#define MX51_MXC_INT_RESV0 0
#define MX51_MXC_INT_RESV0
0
#define MX51_MXC_INT_MMC_SDHC1 1
#define MX51_MXC_INT_MMC_SDHC1
1
#define MX51_MXC_INT_MMC_SDHC2 2
#define MX51_MXC_INT_MMC_SDHC2
2
#define MX51_MXC_INT_MMC_SDHC3 3
#define MX51_MXC_INT_MMC_SDHC3
3
#define MX51_MXC_INT_MMC_SDHC4 4
#define MX51_MXC_INT_MMC_SDHC4
4
#define MX51_MXC_INT_RESV5 5
#define MX51_MXC_INT_RESV5
5
#define MX51_
MXC_INT_SDMA
6
#define MX51_
INT_SDMA
6
#define MX51_MXC_INT_IOMUX 7
#define MX51_MXC_INT_IOMUX
7
#define MX51_
MXC_INT_NFC
8
#define MX51_
INT_NFC
8
#define MX51_MXC_INT_VPU 9
#define MX51_MXC_INT_VPU
9
#define MX51_MXC_INT_IPU_ERR 10
#define MX51_MXC_INT_IPU_ERR
10
#define MX51_MXC_INT_IPU_SYN 11
#define MX51_MXC_INT_IPU_SYN
11
#define MX51_MXC_INT_GPU 12
#define MX51_MXC_INT_GPU
12
#define MX51_MXC_INT_RESV13 13
#define MX51_MXC_INT_RESV13
13
#define MX51_MXC_INT_USB_H1 14
#define MX51_MXC_INT_USB_H1
14
#define MX51_MXC_INT_EMI 15
#define MX51_MXC_INT_EMI
15
#define MX51_MXC_INT_USB_H2 16
#define MX51_MXC_INT_USB_H2
16
#define MX51_MXC_INT_USB_H3 17
#define MX51_MXC_INT_USB_H3
17
#define MX51_MXC_INT_USB_OTG 18
#define MX51_MXC_INT_USB_OTG
18
#define MX51_MXC_INT_SAHARA_H0 19
#define MX51_MXC_INT_SAHARA_H0
19
#define MX51_MXC_INT_SAHARA_H1 20
#define MX51_MXC_INT_SAHARA_H1
20
#define MX51_MXC_INT_SCC_SMN 21
#define MX51_MXC_INT_SCC_SMN
21
#define MX51_MXC_INT_SCC_STZ 22
#define MX51_MXC_INT_SCC_STZ
22
#define MX51_MXC_INT_SCC_SCM 23
#define MX51_MXC_INT_SCC_SCM
23
#define MX51_MXC_INT_SRTC_NTZ 24
#define MX51_MXC_INT_SRTC_NTZ
24
#define MX51_MXC_INT_SRTC_TZ 25
#define MX51_MXC_INT_SRTC_TZ
25
#define MX51_MXC_INT_RTIC 26
#define MX51_MXC_INT_RTIC
26
#define MX51_MXC_INT_CSU 27
#define MX51_MXC_INT_CSU
27
#define MX51_MXC_INT_SLIM_B 28
#define MX51_MXC_INT_SLIM_B
28
#define MX51_
MXC_INT_SSI1
29
#define MX51_
INT_SSI1
29
#define MX51_
MXC_INT_SSI2
30
#define MX51_
INT_SSI2
30
#define MX51_
MXC_INT_UART1
31
#define MX51_
INT_UART1
31
#define MX51_
MXC_INT_UART2
32
#define MX51_
INT_UART2
32
#define MX51_
MXC_INT_UART3
33
#define MX51_
INT_UART3
33
#define MX51_MXC_INT_RESV34 34
#define MX51_MXC_INT_RESV34
34
#define MX51_MXC_INT_RESV35 35
#define MX51_MXC_INT_RESV35
35
#define MX51_
MXC_INT_CSPI1
36
#define MX51_
INT_ECSPI1
36
#define MX51_
MXC_INT_CSPI2
37
#define MX51_
INT_ECSPI2
37
#define MX51_
MXC_INT_CSPI
38
#define MX51_
INT_CSPI
38
#define MX51_MXC_INT_GPT 39
#define MX51_MXC_INT_GPT
39
#define MX51_MXC_INT_EPIT1 40
#define MX51_MXC_INT_EPIT1
40
#define MX51_MXC_INT_EPIT2 41
#define MX51_MXC_INT_EPIT2
41
#define MX51_MXC_INT_GPIO1_INT7 42
#define MX51_MXC_INT_GPIO1_INT7
42
#define MX51_MXC_INT_GPIO1_INT6 43
#define MX51_MXC_INT_GPIO1_INT6
43
#define MX51_MXC_INT_GPIO1_INT5 44
#define MX51_MXC_INT_GPIO1_INT5
44
#define MX51_MXC_INT_GPIO1_INT4 45
#define MX51_MXC_INT_GPIO1_INT4
45
#define MX51_MXC_INT_GPIO1_INT3 46
#define MX51_MXC_INT_GPIO1_INT3
46
#define MX51_MXC_INT_GPIO1_INT2 47
#define MX51_MXC_INT_GPIO1_INT2
47
#define MX51_MXC_INT_GPIO1_INT1 48
#define MX51_MXC_INT_GPIO1_INT1
48
#define MX51_MXC_INT_GPIO1_INT0 49
#define MX51_MXC_INT_GPIO1_INT0
49
#define MX51_MXC_INT_GPIO1_LOW 50
#define MX51_MXC_INT_GPIO1_LOW
50
#define MX51_MXC_INT_GPIO1_HIGH 51
#define MX51_MXC_INT_GPIO1_HIGH
51
#define MX51_MXC_INT_GPIO2_LOW 52
#define MX51_MXC_INT_GPIO2_LOW
52
#define MX51_MXC_INT_GPIO2_HIGH 53
#define MX51_MXC_INT_GPIO2_HIGH
53
#define MX51_MXC_INT_GPIO3_LOW 54
#define MX51_MXC_INT_GPIO3_LOW
54
#define MX51_MXC_INT_GPIO3_HIGH 55
#define MX51_MXC_INT_GPIO3_HIGH
55
#define MX51_MXC_INT_GPIO4_LOW 56
#define MX51_MXC_INT_GPIO4_LOW
56
#define MX51_MXC_INT_GPIO4_HIGH 57
#define MX51_MXC_INT_GPIO4_HIGH
57
#define MX51_MXC_INT_WDOG1 58
#define MX51_MXC_INT_WDOG1
58
#define MX51_MXC_INT_WDOG2 59
#define MX51_MXC_INT_WDOG2
59
#define MX51_MXC_INT_KPP 60
#define MX51_MXC_INT_KPP
60
#define MX51_MXC_INT_PWM1 61
#define MX51_MXC_INT_PWM1
61
#define MX51_
MXC_INT_I2C1
62
#define MX51_
INT_I2C1
62
#define MX51_
MXC_INT_I2C2
63
#define MX51_
INT_I2C2
63
#define MX51_MXC_INT_HS_I2C 64
#define MX51_MXC_INT_HS_I2C
64
#define MX51_MXC_INT_RESV65 65
#define MX51_MXC_INT_RESV65
65
#define MX51_MXC_INT_RESV66 66
#define MX51_MXC_INT_RESV66
66
#define MX51_MXC_INT_SIM_IPB 67
#define MX51_MXC_INT_SIM_IPB
67
#define MX51_MXC_INT_SIM_DAT 68
#define MX51_MXC_INT_SIM_DAT
68
#define MX51_MXC_INT_IIM 69
#define MX51_MXC_INT_IIM
69
#define MX51_MXC_INT_ATA 70
#define MX51_MXC_INT_ATA
70
#define MX51_MXC_INT_CCM1 71
#define MX51_MXC_INT_CCM1
71
#define MX51_MXC_INT_CCM2 72
#define MX51_MXC_INT_CCM2
72
#define MX51_MXC_INT_GPC1 73
#define MX51_MXC_INT_GPC1
73
#define MX51_MXC_INT_GPC2 74
#define MX51_MXC_INT_GPC2
74
#define MX51_MXC_INT_SRC 75
#define MX51_MXC_INT_SRC
75
#define MX51_MXC_INT_NM 76
#define MX51_MXC_INT_NM
76
#define MX51_MXC_INT_PMU 77
#define MX51_MXC_INT_PMU
77
#define MX51_MXC_INT_CTI_IRQ 78
#define MX51_MXC_INT_CTI_IRQ
78
#define MX51_MXC_INT_CTI1_TG0 79
#define MX51_MXC_INT_CTI1_TG0
79
#define MX51_MXC_INT_CTI1_TG1 80
#define MX51_MXC_INT_CTI1_TG1
80
#define MX51_MXC_INT_MCG_ERR 81
#define MX51_MXC_INT_MCG_ERR
81
#define MX51_MXC_INT_MCG_TMR 82
#define MX51_MXC_INT_MCG_TMR
82
#define MX51_MXC_INT_MCG_FUNC 83
#define MX51_MXC_INT_MCG_FUNC
83
#define MX51_MXC_INT_GPU2_IRQ 84
#define MX51_MXC_INT_GPU2_IRQ
84
#define MX51_MXC_INT_GPU2_BUSY 85
#define MX51_MXC_INT_GPU2_BUSY
85
#define MX51_MXC_INT_RESV86 86
#define MX51_MXC_INT_RESV86
86
#define MX51_
MXC_INT_FEC
87
#define MX51_
INT_FEC
87
#define MX51_MXC_INT_OWIRE 88
#define MX51_MXC_INT_OWIRE
88
#define MX51_MXC_INT_CTI1_TG2 89
#define MX51_MXC_INT_CTI1_TG2
89
#define MX51_MXC_INT_SJC 90
#define MX51_MXC_INT_SJC
90
#define MX51_MXC_INT_SPDIF 91
#define MX51_MXC_INT_SPDIF
91
#define MX51_MXC_INT_TVE 92
#define MX51_MXC_INT_TVE
92
#define MX51_MXC_INT_FIRI 93
#define MX51_MXC_INT_FIRI
93
#define MX51_MXC_INT_PWM2 94
#define MX51_MXC_INT_PWM2
94
#define MX51_MXC_INT_SLIM_EXP 95
#define MX51_MXC_INT_SLIM_EXP
95
#define MX51_MXC_INT_SSI3 96
#define MX51_MXC_INT_SSI3
96
#define MX51_MXC_INT_EMI_BOOT 97
#define MX51_MXC_INT_EMI_BOOT
97
#define MX51_MXC_INT_CTI1_TG3 98
#define MX51_MXC_INT_CTI1_TG3
98
#define MX51_MXC_INT_SMC_RX 99
#define MX51_MXC_INT_SMC_RX
99
#define MX51_MXC_INT_VPU_IDLE 100
#define MX51_MXC_INT_VPU_IDLE
100
#define MX51_MXC_INT_EMI_NFC 101
#define MX51_MXC_INT_EMI_NFC
101
#define MX51_MXC_INT_GPU_IDLE 102
#define MX51_MXC_INT_GPU_IDLE
102
/* silicon revisions specific to i.MX51 */
/* silicon revisions specific to i.MX51 */
#define MX51_CHIP_REV_1_0 0x10
#define MX51_CHIP_REV_1_0 0x10
#define MX51_CHIP_REV_1_1 0x11
#define MX51_CHIP_REV_1_1 0x11
#define MX51_CHIP_REV_1_2 0x12
#define MX51_CHIP_REV_1_2 0x12
#define MX51_CHIP_REV_1_3 0x13
#define MX51_CHIP_REV_1_3 0x13
#define MX51_CHIP_REV_2_0 0x20
#define MX51_CHIP_REV_2_0 0x20
#define MX51_CHIP_REV_2_1 0x21
#define MX51_CHIP_REV_2_1 0x21
#define MX51_CHIP_REV_2_2 0x22
#define MX51_CHIP_REV_2_2 0x22
#define MX51_CHIP_REV_2_3 0x23
#define MX51_CHIP_REV_2_3 0x23
#define MX51_CHIP_REV_3_0 0x30
#define MX51_CHIP_REV_3_0 0x30
#define MX51_CHIP_REV_3_1 0x31
#define MX51_CHIP_REV_3_1 0x31
#define MX51_CHIP_REV_3_2 0x32
#define MX51_CHIP_REV_3_2 0x32
/* Mandatory defines used globally */
#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
extern
int
mx51_revision
(
void
);
extern
int
mx51_revision
(
void
);
#endif
#endif
#endif
/* __ASM_ARCH_MXC_MX51_H__ */
/* tape-out 1 defines */
#define MX51_TZIC_BASE_ADDR_TO1 0x8fffc000
#endif
/* ifndef __MACH_MX51_H__ */
drivers/spi/Kconfig
View file @
c9ee46a9
...
@@ -143,10 +143,26 @@ config SPI_GPIO
...
@@ -143,10 +143,26 @@ config SPI_GPIO
GPIO operations, you should be able to leverage that for better
GPIO operations, you should be able to leverage that for better
speed with a custom version of this driver; see the source code.
speed with a custom version of this driver; see the source code.
config SPI_IMX_VER_IMX1
def_bool y if SOC_IMX1
config SPI_IMX_VER_0_0
def_bool y if SOC_IMX21 || SOC_IMX27
config SPI_IMX_VER_0_4
def_bool y if ARCH_MX31
config SPI_IMX_VER_0_7
def_bool y if ARCH_MX25 || ARCH_MX35 || ARCH_MX51
config SPI_IMX_VER_2_3
def_bool y if ARCH_MX51
config SPI_IMX
config SPI_IMX
tristate "Freescale i.MX SPI controllers"
tristate "Freescale i.MX SPI controllers"
depends on ARCH_MXC
depends on ARCH_MXC
select SPI_BITBANG
select SPI_BITBANG
default m if IMX_HAVE_PLATFORM_SPI_IMX
help
help
This enables using the Freescale i.MX SPI controllers in master
This enables using the Freescale i.MX SPI controllers in master
mode.
mode.
...
...
drivers/spi/spi_imx.c
View file @
c9ee46a9
...
@@ -56,7 +56,28 @@ struct spi_imx_config {
...
@@ -56,7 +56,28 @@ struct spi_imx_config {
unsigned
int
speed_hz
;
unsigned
int
speed_hz
;
unsigned
int
bpw
;
unsigned
int
bpw
;
unsigned
int
mode
;
unsigned
int
mode
;
int
cs
;
u8
cs
;
};
enum
spi_imx_devtype
{
SPI_IMX_VER_IMX1
,
SPI_IMX_VER_0_0
,
SPI_IMX_VER_0_4
,
SPI_IMX_VER_0_5
,
SPI_IMX_VER_0_7
,
SPI_IMX_VER_2_3
,
SPI_IMX_VER_AUTODETECT
,
};
struct
spi_imx_data
;
struct
spi_imx_devtype_data
{
void
(
*
intctrl
)(
struct
spi_imx_data
*
,
int
);
int
(
*
config
)(
struct
spi_imx_data
*
,
struct
spi_imx_config
*
);
void
(
*
trigger
)(
struct
spi_imx_data
*
);
int
(
*
rx_available
)(
struct
spi_imx_data
*
);
void
(
*
reset
)(
struct
spi_imx_data
*
);
unsigned
int
fifosize
;
};
};
struct
spi_imx_data
{
struct
spi_imx_data
{
...
@@ -76,11 +97,7 @@ struct spi_imx_data {
...
@@ -76,11 +97,7 @@ struct spi_imx_data {
const
void
*
tx_buf
;
const
void
*
tx_buf
;
unsigned
int
txfifo
;
/* number of words pushed in tx FIFO */
unsigned
int
txfifo
;
/* number of words pushed in tx FIFO */
/* SoC specific functions */
struct
spi_imx_devtype_data
devtype_data
;
void
(
*
intctrl
)(
struct
spi_imx_data
*
,
int
);
int
(
*
config
)(
struct
spi_imx_data
*
,
struct
spi_imx_config
*
);
void
(
*
trigger
)(
struct
spi_imx_data
*
);
int
(
*
rx_available
)(
struct
spi_imx_data
*
);
};
};
#define MXC_SPI_BUF_RX(type) \
#define MXC_SPI_BUF_RX(type) \
...
@@ -140,7 +157,7 @@ static unsigned int spi_imx_clkdiv_1(unsigned int fin,
...
@@ -140,7 +157,7 @@ static unsigned int spi_imx_clkdiv_1(unsigned int fin,
return
max
;
return
max
;
}
}
/* MX1, MX31, MX35 */
/* MX1, MX31, MX35
, MX51 CSPI
*/
static
unsigned
int
spi_imx_clkdiv_2
(
unsigned
int
fin
,
static
unsigned
int
spi_imx_clkdiv_2
(
unsigned
int
fin
,
unsigned
int
fspi
)
unsigned
int
fspi
)
{
{
...
@@ -155,6 +172,128 @@ static unsigned int spi_imx_clkdiv_2(unsigned int fin,
...
@@ -155,6 +172,128 @@ static unsigned int spi_imx_clkdiv_2(unsigned int fin,
return
7
;
return
7
;
}
}
#define SPI_IMX2_3_CTRL 0x08
#define SPI_IMX2_3_CTRL_ENABLE (1 << 0)
#define SPI_IMX2_3_CTRL_XCH (1 << 2)
#define SPI_IMX2_3_CTRL_MODE(cs) (1 << ((cs) + 4))
#define SPI_IMX2_3_CTRL_POSTDIV_OFFSET 8
#define SPI_IMX2_3_CTRL_PREDIV_OFFSET 12
#define SPI_IMX2_3_CTRL_CS(cs) ((cs) << 18)
#define SPI_IMX2_3_CTRL_BL_OFFSET 20
#define SPI_IMX2_3_CONFIG 0x0c
#define SPI_IMX2_3_CONFIG_SCLKPHA(cs) (1 << ((cs) + 0))
#define SPI_IMX2_3_CONFIG_SCLKPOL(cs) (1 << ((cs) + 4))
#define SPI_IMX2_3_CONFIG_SBBCTRL(cs) (1 << ((cs) + 8))
#define SPI_IMX2_3_CONFIG_SSBPOL(cs) (1 << ((cs) + 12))
#define SPI_IMX2_3_INT 0x10
#define SPI_IMX2_3_INT_TEEN (1 << 0)
#define SPI_IMX2_3_INT_RREN (1 << 3)
#define SPI_IMX2_3_STAT 0x18
#define SPI_IMX2_3_STAT_RR (1 << 3)
/* MX51 eCSPI */
static
unsigned
int
spi_imx2_3_clkdiv
(
unsigned
int
fin
,
unsigned
int
fspi
)
{
/*
* there are two 4-bit dividers, the pre-divider divides by
* $pre, the post-divider by 2^$post
*/
unsigned
int
pre
,
post
;
if
(
unlikely
(
fspi
>
fin
))
return
0
;
post
=
fls
(
fin
)
-
fls
(
fspi
);
if
(
fin
>
fspi
<<
post
)
post
++
;
/* now we have: (fin <= fspi << post) with post being minimal */
post
=
max
(
4U
,
post
)
-
4
;
if
(
unlikely
(
post
>
0xf
))
{
pr_err
(
"%s: cannot set clock freq: %u (base freq: %u)
\n
"
,
__func__
,
fspi
,
fin
);
return
0xff
;
}
pre
=
DIV_ROUND_UP
(
fin
,
fspi
<<
post
)
-
1
;
pr_debug
(
"%s: fin: %u, fspi: %u, post: %u, pre: %u
\n
"
,
__func__
,
fin
,
fspi
,
post
,
pre
);
return
(
pre
<<
SPI_IMX2_3_CTRL_PREDIV_OFFSET
)
|
(
post
<<
SPI_IMX2_3_CTRL_POSTDIV_OFFSET
);
}
static
void
__maybe_unused
spi_imx2_3_intctrl
(
struct
spi_imx_data
*
spi_imx
,
int
enable
)
{
unsigned
val
=
0
;
if
(
enable
&
MXC_INT_TE
)
val
|=
SPI_IMX2_3_INT_TEEN
;
if
(
enable
&
MXC_INT_RR
)
val
|=
SPI_IMX2_3_INT_RREN
;
writel
(
val
,
spi_imx
->
base
+
SPI_IMX2_3_INT
);
}
static
void
__maybe_unused
spi_imx2_3_trigger
(
struct
spi_imx_data
*
spi_imx
)
{
u32
reg
;
reg
=
readl
(
spi_imx
->
base
+
SPI_IMX2_3_CTRL
);
reg
|=
SPI_IMX2_3_CTRL_XCH
;
writel
(
reg
,
spi_imx
->
base
+
SPI_IMX2_3_CTRL
);
}
static
int
__maybe_unused
spi_imx2_3_config
(
struct
spi_imx_data
*
spi_imx
,
struct
spi_imx_config
*
config
)
{
u32
ctrl
=
SPI_IMX2_3_CTRL_ENABLE
,
cfg
=
0
;
/* set master mode */
ctrl
|=
SPI_IMX2_3_CTRL_MODE
(
config
->
cs
);
/* set clock speed */
ctrl
|=
spi_imx2_3_clkdiv
(
spi_imx
->
spi_clk
,
config
->
speed_hz
);
/* set chip select to use */
ctrl
|=
SPI_IMX2_3_CTRL_CS
(
config
->
cs
);
ctrl
|=
(
config
->
bpw
-
1
)
<<
SPI_IMX2_3_CTRL_BL_OFFSET
;
cfg
|=
SPI_IMX2_3_CONFIG_SBBCTRL
(
config
->
cs
);
if
(
config
->
mode
&
SPI_CPHA
)
cfg
|=
SPI_IMX2_3_CONFIG_SCLKPHA
(
config
->
cs
);
if
(
config
->
mode
&
SPI_CPOL
)
cfg
|=
SPI_IMX2_3_CONFIG_SCLKPOL
(
config
->
cs
);
if
(
config
->
mode
&
SPI_CS_HIGH
)
cfg
|=
SPI_IMX2_3_CONFIG_SSBPOL
(
config
->
cs
);
writel
(
ctrl
,
spi_imx
->
base
+
SPI_IMX2_3_CTRL
);
writel
(
cfg
,
spi_imx
->
base
+
SPI_IMX2_3_CONFIG
);
return
0
;
}
static
int
__maybe_unused
spi_imx2_3_rx_available
(
struct
spi_imx_data
*
spi_imx
)
{
return
readl
(
spi_imx
->
base
+
SPI_IMX2_3_STAT
)
&
SPI_IMX2_3_STAT_RR
;
}
static
void
__maybe_unused
spi_imx2_3_reset
(
struct
spi_imx_data
*
spi_imx
)
{
/* drain receive buffer */
while
(
spi_imx2_3_rx_available
(
spi_imx
))
readl
(
spi_imx
->
base
+
MXC_CSPIRXDATA
);
}
#define MX31_INTREG_TEEN (1 << 0)
#define MX31_INTREG_TEEN (1 << 0)
#define MX31_INTREG_RREN (1 << 3)
#define MX31_INTREG_RREN (1 << 3)
...
@@ -178,7 +317,7 @@ static unsigned int spi_imx_clkdiv_2(unsigned int fin,
...
@@ -178,7 +317,7 @@ static unsigned int spi_imx_clkdiv_2(unsigned int fin,
* the i.MX35 has a slightly different register layout for bits
* the i.MX35 has a slightly different register layout for bits
* we do not use here.
* we do not use here.
*/
*/
static
void
mx31_intctrl
(
struct
spi_imx_data
*
spi_imx
,
int
enable
)
static
void
__maybe_unused
mx31_intctrl
(
struct
spi_imx_data
*
spi_imx
,
int
enable
)
{
{
unsigned
int
val
=
0
;
unsigned
int
val
=
0
;
...
@@ -190,7 +329,7 @@ static void mx31_intctrl(struct spi_imx_data *spi_imx, int enable)
...
@@ -190,7 +329,7 @@ static void mx31_intctrl(struct spi_imx_data *spi_imx, int enable)
writel
(
val
,
spi_imx
->
base
+
MXC_CSPIINT
);
writel
(
val
,
spi_imx
->
base
+
MXC_CSPIINT
);
}
}
static
void
mx31_trigger
(
struct
spi_imx_data
*
spi_imx
)
static
void
__maybe_unused
mx31_trigger
(
struct
spi_imx_data
*
spi_imx
)
{
{
unsigned
int
reg
;
unsigned
int
reg
;
...
@@ -199,20 +338,16 @@ static void mx31_trigger(struct spi_imx_data *spi_imx)
...
@@ -199,20 +338,16 @@ static void mx31_trigger(struct spi_imx_data *spi_imx)
writel
(
reg
,
spi_imx
->
base
+
MXC_CSPICTRL
);
writel
(
reg
,
spi_imx
->
base
+
MXC_CSPICTRL
);
}
}
static
int
mx31
_config
(
struct
spi_imx_data
*
spi_imx
,
static
int
__maybe_unused
spi_imx0_4
_config
(
struct
spi_imx_data
*
spi_imx
,
struct
spi_imx_config
*
config
)
struct
spi_imx_config
*
config
)
{
{
unsigned
int
reg
=
MX31_CSPICTRL_ENABLE
|
MX31_CSPICTRL_MASTER
;
unsigned
int
reg
=
MX31_CSPICTRL_ENABLE
|
MX31_CSPICTRL_MASTER
;
int
cs
=
spi_imx
->
chipselect
[
config
->
cs
];
reg
|=
spi_imx_clkdiv_2
(
spi_imx
->
spi_clk
,
config
->
speed_hz
)
<<
reg
|=
spi_imx_clkdiv_2
(
spi_imx
->
spi_clk
,
config
->
speed_hz
)
<<
MX31_CSPICTRL_DR_SHIFT
;
MX31_CSPICTRL_DR_SHIFT
;
if
(
cpu_is_mx31
())
reg
|=
(
config
->
bpw
-
1
)
<<
MX31_CSPICTRL_BC_SHIFT
;
reg
|=
(
config
->
bpw
-
1
)
<<
MX31_CSPICTRL_BC_SHIFT
;
else
if
(
cpu_is_mx25
()
||
cpu_is_mx35
())
{
reg
|=
(
config
->
bpw
-
1
)
<<
MX35_CSPICTRL_BL_SHIFT
;
reg
|=
MX31_CSPICTRL_SSCTL
;
}
if
(
config
->
mode
&
SPI_CPHA
)
if
(
config
->
mode
&
SPI_CPHA
)
reg
|=
MX31_CSPICTRL_PHA
;
reg
|=
MX31_CSPICTRL_PHA
;
...
@@ -220,23 +355,52 @@ static int mx31_config(struct spi_imx_data *spi_imx,
...
@@ -220,23 +355,52 @@ static int mx31_config(struct spi_imx_data *spi_imx,
reg
|=
MX31_CSPICTRL_POL
;
reg
|=
MX31_CSPICTRL_POL
;
if
(
config
->
mode
&
SPI_CS_HIGH
)
if
(
config
->
mode
&
SPI_CS_HIGH
)
reg
|=
MX31_CSPICTRL_SSPOL
;
reg
|=
MX31_CSPICTRL_SSPOL
;
if
(
config
->
cs
<
0
)
{
if
(
cs
<
0
)
if
(
cpu_is_mx31
())
reg
|=
(
cs
+
32
)
<<
MX31_CSPICTRL_CS_SHIFT
;
reg
|=
(
config
->
cs
+
32
)
<<
MX31_CSPICTRL_CS_SHIFT
;
else
if
(
cpu_is_mx25
()
||
cpu_is_mx35
())
writel
(
reg
,
spi_imx
->
base
+
MXC_CSPICTRL
);
reg
|=
(
config
->
cs
+
32
)
<<
MX35_CSPICTRL_CS_SHIFT
;
}
return
0
;
}
static
int
__maybe_unused
spi_imx0_7_config
(
struct
spi_imx_data
*
spi_imx
,
struct
spi_imx_config
*
config
)
{
unsigned
int
reg
=
MX31_CSPICTRL_ENABLE
|
MX31_CSPICTRL_MASTER
;
int
cs
=
spi_imx
->
chipselect
[
config
->
cs
];
reg
|=
spi_imx_clkdiv_2
(
spi_imx
->
spi_clk
,
config
->
speed_hz
)
<<
MX31_CSPICTRL_DR_SHIFT
;
reg
|=
(
config
->
bpw
-
1
)
<<
MX35_CSPICTRL_BL_SHIFT
;
reg
|=
MX31_CSPICTRL_SSCTL
;
if
(
config
->
mode
&
SPI_CPHA
)
reg
|=
MX31_CSPICTRL_PHA
;
if
(
config
->
mode
&
SPI_CPOL
)
reg
|=
MX31_CSPICTRL_POL
;
if
(
config
->
mode
&
SPI_CS_HIGH
)
reg
|=
MX31_CSPICTRL_SSPOL
;
if
(
cs
<
0
)
reg
|=
(
cs
+
32
)
<<
MX35_CSPICTRL_CS_SHIFT
;
writel
(
reg
,
spi_imx
->
base
+
MXC_CSPICTRL
);
writel
(
reg
,
spi_imx
->
base
+
MXC_CSPICTRL
);
return
0
;
return
0
;
}
}
static
int
mx31_rx_available
(
struct
spi_imx_data
*
spi_imx
)
static
int
__maybe_unused
mx31_rx_available
(
struct
spi_imx_data
*
spi_imx
)
{
{
return
readl
(
spi_imx
->
base
+
MX31_CSPISTATUS
)
&
MX31_STATUS_RR
;
return
readl
(
spi_imx
->
base
+
MX31_CSPISTATUS
)
&
MX31_STATUS_RR
;
}
}
static
void
__maybe_unused
spi_imx0_4_reset
(
struct
spi_imx_data
*
spi_imx
)
{
/* drain receive buffer */
while
(
readl
(
spi_imx
->
base
+
MX3_CSPISTAT
)
&
MX3_CSPISTAT_RR
)
readl
(
spi_imx
->
base
+
MXC_CSPIRXDATA
);
}
#define MX27_INTREG_RR (1 << 4)
#define MX27_INTREG_RR (1 << 4)
#define MX27_INTREG_TEEN (1 << 9)
#define MX27_INTREG_TEEN (1 << 9)
#define MX27_INTREG_RREN (1 << 13)
#define MX27_INTREG_RREN (1 << 13)
...
@@ -250,7 +414,7 @@ static int mx31_rx_available(struct spi_imx_data *spi_imx)
...
@@ -250,7 +414,7 @@ static int mx31_rx_available(struct spi_imx_data *spi_imx)
#define MX27_CSPICTRL_DR_SHIFT 14
#define MX27_CSPICTRL_DR_SHIFT 14
#define MX27_CSPICTRL_CS_SHIFT 19
#define MX27_CSPICTRL_CS_SHIFT 19
static
void
mx27_intctrl
(
struct
spi_imx_data
*
spi_imx
,
int
enable
)
static
void
__maybe_unused
mx27_intctrl
(
struct
spi_imx_data
*
spi_imx
,
int
enable
)
{
{
unsigned
int
val
=
0
;
unsigned
int
val
=
0
;
...
@@ -262,7 +426,7 @@ static void mx27_intctrl(struct spi_imx_data *spi_imx, int enable)
...
@@ -262,7 +426,7 @@ static void mx27_intctrl(struct spi_imx_data *spi_imx, int enable)
writel
(
val
,
spi_imx
->
base
+
MXC_CSPIINT
);
writel
(
val
,
spi_imx
->
base
+
MXC_CSPIINT
);
}
}
static
void
mx27_trigger
(
struct
spi_imx_data
*
spi_imx
)
static
void
__maybe_unused
mx27_trigger
(
struct
spi_imx_data
*
spi_imx
)
{
{
unsigned
int
reg
;
unsigned
int
reg
;
...
@@ -271,10 +435,11 @@ static void mx27_trigger(struct spi_imx_data *spi_imx)
...
@@ -271,10 +435,11 @@ static void mx27_trigger(struct spi_imx_data *spi_imx)
writel
(
reg
,
spi_imx
->
base
+
MXC_CSPICTRL
);
writel
(
reg
,
spi_imx
->
base
+
MXC_CSPICTRL
);
}
}
static
int
mx27_config
(
struct
spi_imx_data
*
spi_imx
,
static
int
__maybe_unused
mx27_config
(
struct
spi_imx_data
*
spi_imx
,
struct
spi_imx_config
*
config
)
struct
spi_imx_config
*
config
)
{
{
unsigned
int
reg
=
MX27_CSPICTRL_ENABLE
|
MX27_CSPICTRL_MASTER
;
unsigned
int
reg
=
MX27_CSPICTRL_ENABLE
|
MX27_CSPICTRL_MASTER
;
int
cs
=
spi_imx
->
chipselect
[
config
->
cs
];
reg
|=
spi_imx_clkdiv_1
(
spi_imx
->
spi_clk
,
config
->
speed_hz
)
<<
reg
|=
spi_imx_clkdiv_1
(
spi_imx
->
spi_clk
,
config
->
speed_hz
)
<<
MX27_CSPICTRL_DR_SHIFT
;
MX27_CSPICTRL_DR_SHIFT
;
...
@@ -286,19 +451,24 @@ static int mx27_config(struct spi_imx_data *spi_imx,
...
@@ -286,19 +451,24 @@ static int mx27_config(struct spi_imx_data *spi_imx,
reg
|=
MX27_CSPICTRL_POL
;
reg
|=
MX27_CSPICTRL_POL
;
if
(
config
->
mode
&
SPI_CS_HIGH
)
if
(
config
->
mode
&
SPI_CS_HIGH
)
reg
|=
MX27_CSPICTRL_SSPOL
;
reg
|=
MX27_CSPICTRL_SSPOL
;
if
(
c
onfig
->
c
s
<
0
)
if
(
cs
<
0
)
reg
|=
(
c
onfig
->
c
s
+
32
)
<<
MX27_CSPICTRL_CS_SHIFT
;
reg
|=
(
cs
+
32
)
<<
MX27_CSPICTRL_CS_SHIFT
;
writel
(
reg
,
spi_imx
->
base
+
MXC_CSPICTRL
);
writel
(
reg
,
spi_imx
->
base
+
MXC_CSPICTRL
);
return
0
;
return
0
;
}
}
static
int
mx27_rx_available
(
struct
spi_imx_data
*
spi_imx
)
static
int
__maybe_unused
mx27_rx_available
(
struct
spi_imx_data
*
spi_imx
)
{
{
return
readl
(
spi_imx
->
base
+
MXC_CSPIINT
)
&
MX27_INTREG_RR
;
return
readl
(
spi_imx
->
base
+
MXC_CSPIINT
)
&
MX27_INTREG_RR
;
}
}
static
void
__maybe_unused
spi_imx0_0_reset
(
struct
spi_imx_data
*
spi_imx
)
{
writel
(
1
,
spi_imx
->
base
+
MXC_RESET
);
}
#define MX1_INTREG_RR (1 << 3)
#define MX1_INTREG_RR (1 << 3)
#define MX1_INTREG_TEEN (1 << 8)
#define MX1_INTREG_TEEN (1 << 8)
#define MX1_INTREG_RREN (1 << 11)
#define MX1_INTREG_RREN (1 << 11)
...
@@ -310,7 +480,7 @@ static int mx27_rx_available(struct spi_imx_data *spi_imx)
...
@@ -310,7 +480,7 @@ static int mx27_rx_available(struct spi_imx_data *spi_imx)
#define MX1_CSPICTRL_MASTER (1 << 10)
#define MX1_CSPICTRL_MASTER (1 << 10)
#define MX1_CSPICTRL_DR_SHIFT 13
#define MX1_CSPICTRL_DR_SHIFT 13
static
void
mx1_intctrl
(
struct
spi_imx_data
*
spi_imx
,
int
enable
)
static
void
__maybe_unused
mx1_intctrl
(
struct
spi_imx_data
*
spi_imx
,
int
enable
)
{
{
unsigned
int
val
=
0
;
unsigned
int
val
=
0
;
...
@@ -322,7 +492,7 @@ static void mx1_intctrl(struct spi_imx_data *spi_imx, int enable)
...
@@ -322,7 +492,7 @@ static void mx1_intctrl(struct spi_imx_data *spi_imx, int enable)
writel
(
val
,
spi_imx
->
base
+
MXC_CSPIINT
);
writel
(
val
,
spi_imx
->
base
+
MXC_CSPIINT
);
}
}
static
void
mx1_trigger
(
struct
spi_imx_data
*
spi_imx
)
static
void
__maybe_unused
mx1_trigger
(
struct
spi_imx_data
*
spi_imx
)
{
{
unsigned
int
reg
;
unsigned
int
reg
;
...
@@ -331,7 +501,7 @@ static void mx1_trigger(struct spi_imx_data *spi_imx)
...
@@ -331,7 +501,7 @@ static void mx1_trigger(struct spi_imx_data *spi_imx)
writel
(
reg
,
spi_imx
->
base
+
MXC_CSPICTRL
);
writel
(
reg
,
spi_imx
->
base
+
MXC_CSPICTRL
);
}
}
static
int
mx1_config
(
struct
spi_imx_data
*
spi_imx
,
static
int
__maybe_unused
mx1_config
(
struct
spi_imx_data
*
spi_imx
,
struct
spi_imx_config
*
config
)
struct
spi_imx_config
*
config
)
{
{
unsigned
int
reg
=
MX1_CSPICTRL_ENABLE
|
MX1_CSPICTRL_MASTER
;
unsigned
int
reg
=
MX1_CSPICTRL_ENABLE
|
MX1_CSPICTRL_MASTER
;
...
@@ -350,11 +520,73 @@ static int mx1_config(struct spi_imx_data *spi_imx,
...
@@ -350,11 +520,73 @@ static int mx1_config(struct spi_imx_data *spi_imx,
return
0
;
return
0
;
}
}
static
int
mx1_rx_available
(
struct
spi_imx_data
*
spi_imx
)
static
int
__maybe_unused
mx1_rx_available
(
struct
spi_imx_data
*
spi_imx
)
{
{
return
readl
(
spi_imx
->
base
+
MXC_CSPIINT
)
&
MX1_INTREG_RR
;
return
readl
(
spi_imx
->
base
+
MXC_CSPIINT
)
&
MX1_INTREG_RR
;
}
}
static
void
__maybe_unused
mx1_reset
(
struct
spi_imx_data
*
spi_imx
)
{
writel
(
1
,
spi_imx
->
base
+
MXC_RESET
);
}
/*
* These version numbers are taken from the Freescale driver. Unfortunately it
* doesn't support i.MX1, so this entry doesn't match the scheme. :-(
*/
static
struct
spi_imx_devtype_data
spi_imx_devtype_data
[]
__devinitdata
=
{
#ifdef CONFIG_SPI_IMX_VER_IMX1
[
SPI_IMX_VER_IMX1
]
=
{
.
intctrl
=
mx1_intctrl
,
.
config
=
mx1_config
,
.
trigger
=
mx1_trigger
,
.
rx_available
=
mx1_rx_available
,
.
reset
=
mx1_reset
,
.
fifosize
=
8
,
},
#endif
#ifdef CONFIG_SPI_IMX_VER_0_0
[
SPI_IMX_VER_0_0
]
=
{
.
intctrl
=
mx27_intctrl
,
.
config
=
mx27_config
,
.
trigger
=
mx27_trigger
,
.
rx_available
=
mx27_rx_available
,
.
reset
=
spi_imx0_0_reset
,
.
fifosize
=
8
,
},
#endif
#ifdef CONFIG_SPI_IMX_VER_0_4
[
SPI_IMX_VER_0_4
]
=
{
.
intctrl
=
mx31_intctrl
,
.
config
=
spi_imx0_4_config
,
.
trigger
=
mx31_trigger
,
.
rx_available
=
mx31_rx_available
,
.
reset
=
spi_imx0_4_reset
,
.
fifosize
=
8
,
},
#endif
#ifdef CONFIG_SPI_IMX_VER_0_7
[
SPI_IMX_VER_0_7
]
=
{
.
intctrl
=
mx31_intctrl
,
.
config
=
spi_imx0_7_config
,
.
trigger
=
mx31_trigger
,
.
rx_available
=
mx31_rx_available
,
.
reset
=
spi_imx0_4_reset
,
.
fifosize
=
8
,
},
#endif
#ifdef CONFIG_SPI_IMX_VER_2_3
[
SPI_IMX_VER_2_3
]
=
{
.
intctrl
=
spi_imx2_3_intctrl
,
.
config
=
spi_imx2_3_config
,
.
trigger
=
spi_imx2_3_trigger
,
.
rx_available
=
spi_imx2_3_rx_available
,
.
reset
=
spi_imx2_3_reset
,
.
fifosize
=
64
,
},
#endif
};
static
void
spi_imx_chipselect
(
struct
spi_device
*
spi
,
int
is_active
)
static
void
spi_imx_chipselect
(
struct
spi_device
*
spi
,
int
is_active
)
{
{
struct
spi_imx_data
*
spi_imx
=
spi_master_get_devdata
(
spi
->
master
);
struct
spi_imx_data
*
spi_imx
=
spi_master_get_devdata
(
spi
->
master
);
...
@@ -370,21 +602,21 @@ static void spi_imx_chipselect(struct spi_device *spi, int is_active)
...
@@ -370,21 +602,21 @@ static void spi_imx_chipselect(struct spi_device *spi, int is_active)
static
void
spi_imx_push
(
struct
spi_imx_data
*
spi_imx
)
static
void
spi_imx_push
(
struct
spi_imx_data
*
spi_imx
)
{
{
while
(
spi_imx
->
txfifo
<
8
)
{
while
(
spi_imx
->
txfifo
<
spi_imx
->
devtype_data
.
fifosize
)
{
if
(
!
spi_imx
->
count
)
if
(
!
spi_imx
->
count
)
break
;
break
;
spi_imx
->
tx
(
spi_imx
);
spi_imx
->
tx
(
spi_imx
);
spi_imx
->
txfifo
++
;
spi_imx
->
txfifo
++
;
}
}
spi_imx
->
trigger
(
spi_imx
);
spi_imx
->
devtype_data
.
trigger
(
spi_imx
);
}
}
static
irqreturn_t
spi_imx_isr
(
int
irq
,
void
*
dev_id
)
static
irqreturn_t
spi_imx_isr
(
int
irq
,
void
*
dev_id
)
{
{
struct
spi_imx_data
*
spi_imx
=
dev_id
;
struct
spi_imx_data
*
spi_imx
=
dev_id
;
while
(
spi_imx
->
rx_available
(
spi_imx
))
{
while
(
spi_imx
->
devtype_data
.
rx_available
(
spi_imx
))
{
spi_imx
->
rx
(
spi_imx
);
spi_imx
->
rx
(
spi_imx
);
spi_imx
->
txfifo
--
;
spi_imx
->
txfifo
--
;
}
}
...
@@ -398,11 +630,12 @@ static irqreturn_t spi_imx_isr(int irq, void *dev_id)
...
@@ -398,11 +630,12 @@ static irqreturn_t spi_imx_isr(int irq, void *dev_id)
/* No data left to push, but still waiting for rx data,
/* No data left to push, but still waiting for rx data,
* enable receive data available interrupt.
* enable receive data available interrupt.
*/
*/
spi_imx
->
intctrl
(
spi_imx
,
MXC_INT_RR
);
spi_imx
->
devtype_data
.
intctrl
(
spi_imx
,
MXC_INT_RR
);
return
IRQ_HANDLED
;
return
IRQ_HANDLED
;
}
}
spi_imx
->
intctrl
(
spi_imx
,
0
);
spi_imx
->
devtype_data
.
intctrl
(
spi_imx
,
0
);
complete
(
&
spi_imx
->
xfer_done
);
complete
(
&
spi_imx
->
xfer_done
);
return
IRQ_HANDLED
;
return
IRQ_HANDLED
;
...
@@ -417,7 +650,7 @@ static int spi_imx_setupxfer(struct spi_device *spi,
...
@@ -417,7 +650,7 @@ static int spi_imx_setupxfer(struct spi_device *spi,
config
.
bpw
=
t
?
t
->
bits_per_word
:
spi
->
bits_per_word
;
config
.
bpw
=
t
?
t
->
bits_per_word
:
spi
->
bits_per_word
;
config
.
speed_hz
=
t
?
t
->
speed_hz
:
spi
->
max_speed_hz
;
config
.
speed_hz
=
t
?
t
->
speed_hz
:
spi
->
max_speed_hz
;
config
.
mode
=
spi
->
mode
;
config
.
mode
=
spi
->
mode
;
config
.
cs
=
spi
_imx
->
chipselect
[
spi
->
chip_select
]
;
config
.
cs
=
spi
->
chip_select
;
if
(
!
config
.
speed_hz
)
if
(
!
config
.
speed_hz
)
config
.
speed_hz
=
spi
->
max_speed_hz
;
config
.
speed_hz
=
spi
->
max_speed_hz
;
...
@@ -439,7 +672,7 @@ static int spi_imx_setupxfer(struct spi_device *spi,
...
@@ -439,7 +672,7 @@ static int spi_imx_setupxfer(struct spi_device *spi,
}
else
}
else
BUG
();
BUG
();
spi_imx
->
config
(
spi_imx
,
&
config
);
spi_imx
->
devtype_data
.
config
(
spi_imx
,
&
config
);
return
0
;
return
0
;
}
}
...
@@ -458,7 +691,7 @@ static int spi_imx_transfer(struct spi_device *spi,
...
@@ -458,7 +691,7 @@ static int spi_imx_transfer(struct spi_device *spi,
spi_imx_push
(
spi_imx
);
spi_imx_push
(
spi_imx
);
spi_imx
->
intctrl
(
spi_imx
,
MXC_INT_TE
);
spi_imx
->
devtype_data
.
intctrl
(
spi_imx
,
MXC_INT_TE
);
wait_for_completion
(
&
spi_imx
->
xfer_done
);
wait_for_completion
(
&
spi_imx
->
xfer_done
);
...
@@ -485,6 +718,39 @@ static void spi_imx_cleanup(struct spi_device *spi)
...
@@ -485,6 +718,39 @@ static void spi_imx_cleanup(struct spi_device *spi)
{
{
}
}
static
struct
platform_device_id
spi_imx_devtype
[]
=
{
{
.
name
=
DRIVER_NAME
,
.
driver_data
=
SPI_IMX_VER_AUTODETECT
,
},
{
.
name
=
"imx1-cspi"
,
.
driver_data
=
SPI_IMX_VER_IMX1
,
},
{
.
name
=
"imx21-cspi"
,
.
driver_data
=
SPI_IMX_VER_0_0
,
},
{
.
name
=
"imx25-cspi"
,
.
driver_data
=
SPI_IMX_VER_0_7
,
},
{
.
name
=
"imx27-cspi"
,
.
driver_data
=
SPI_IMX_VER_0_0
,
},
{
.
name
=
"imx31-cspi"
,
.
driver_data
=
SPI_IMX_VER_0_4
,
},
{
.
name
=
"imx35-cspi"
,
.
driver_data
=
SPI_IMX_VER_0_7
,
},
{
.
name
=
"imx51-cspi"
,
.
driver_data
=
SPI_IMX_VER_0_7
,
},
{
.
name
=
"imx51-ecspi"
,
.
driver_data
=
SPI_IMX_VER_2_3
,
},
{
/* sentinel */
}
};
static
int
__devinit
spi_imx_probe
(
struct
platform_device
*
pdev
)
static
int
__devinit
spi_imx_probe
(
struct
platform_device
*
pdev
)
{
{
struct
spi_imx_master
*
mxc_platform_info
;
struct
spi_imx_master
*
mxc_platform_info
;
...
@@ -536,6 +802,31 @@ static int __devinit spi_imx_probe(struct platform_device *pdev)
...
@@ -536,6 +802,31 @@ static int __devinit spi_imx_probe(struct platform_device *pdev)
init_completion
(
&
spi_imx
->
xfer_done
);
init_completion
(
&
spi_imx
->
xfer_done
);
if
(
pdev
->
id_entry
->
driver_data
==
SPI_IMX_VER_AUTODETECT
)
{
if
(
cpu_is_mx25
()
||
cpu_is_mx35
())
spi_imx
->
devtype_data
=
spi_imx_devtype_data
[
SPI_IMX_VER_0_7
];
else
if
(
cpu_is_mx25
()
||
cpu_is_mx31
()
||
cpu_is_mx35
())
spi_imx
->
devtype_data
=
spi_imx_devtype_data
[
SPI_IMX_VER_0_4
];
else
if
(
cpu_is_mx27
()
||
cpu_is_mx21
())
spi_imx
->
devtype_data
=
spi_imx_devtype_data
[
SPI_IMX_VER_0_0
];
else
if
(
cpu_is_mx1
())
spi_imx
->
devtype_data
=
spi_imx_devtype_data
[
SPI_IMX_VER_IMX1
];
else
BUG
();
}
else
spi_imx
->
devtype_data
=
spi_imx_devtype_data
[
pdev
->
id_entry
->
driver_data
];
if
(
!
spi_imx
->
devtype_data
.
intctrl
)
{
dev_err
(
&
pdev
->
dev
,
"no support for this device compiled in
\n
"
);
ret
=
-
ENODEV
;
goto
out_gpio_free
;
}
res
=
platform_get_resource
(
pdev
,
IORESOURCE_MEM
,
0
);
res
=
platform_get_resource
(
pdev
,
IORESOURCE_MEM
,
0
);
if
(
!
res
)
{
if
(
!
res
)
{
dev_err
(
&
pdev
->
dev
,
"can't get platform resource
\n
"
);
dev_err
(
&
pdev
->
dev
,
"can't get platform resource
\n
"
);
...
@@ -567,24 +858,6 @@ static int __devinit spi_imx_probe(struct platform_device *pdev)
...
@@ -567,24 +858,6 @@ static int __devinit spi_imx_probe(struct platform_device *pdev)
goto
out_iounmap
;
goto
out_iounmap
;
}
}
if
(
cpu_is_mx25
()
||
cpu_is_mx31
()
||
cpu_is_mx35
())
{
spi_imx
->
intctrl
=
mx31_intctrl
;
spi_imx
->
config
=
mx31_config
;
spi_imx
->
trigger
=
mx31_trigger
;
spi_imx
->
rx_available
=
mx31_rx_available
;
}
else
if
(
cpu_is_mx27
()
||
cpu_is_mx21
())
{
spi_imx
->
intctrl
=
mx27_intctrl
;
spi_imx
->
config
=
mx27_config
;
spi_imx
->
trigger
=
mx27_trigger
;
spi_imx
->
rx_available
=
mx27_rx_available
;
}
else
if
(
cpu_is_mx1
())
{
spi_imx
->
intctrl
=
mx1_intctrl
;
spi_imx
->
config
=
mx1_config
;
spi_imx
->
trigger
=
mx1_trigger
;
spi_imx
->
rx_available
=
mx1_rx_available
;
}
else
BUG
();
spi_imx
->
clk
=
clk_get
(
&
pdev
->
dev
,
NULL
);
spi_imx
->
clk
=
clk_get
(
&
pdev
->
dev
,
NULL
);
if
(
IS_ERR
(
spi_imx
->
clk
))
{
if
(
IS_ERR
(
spi_imx
->
clk
))
{
dev_err
(
&
pdev
->
dev
,
"unable to get clock
\n
"
);
dev_err
(
&
pdev
->
dev
,
"unable to get clock
\n
"
);
...
@@ -595,15 +868,9 @@ static int __devinit spi_imx_probe(struct platform_device *pdev)
...
@@ -595,15 +868,9 @@ static int __devinit spi_imx_probe(struct platform_device *pdev)
clk_enable
(
spi_imx
->
clk
);
clk_enable
(
spi_imx
->
clk
);
spi_imx
->
spi_clk
=
clk_get_rate
(
spi_imx
->
clk
);
spi_imx
->
spi_clk
=
clk_get_rate
(
spi_imx
->
clk
);
if
(
cpu_is_mx1
()
||
cpu_is_mx21
()
||
cpu_is_mx27
())
spi_imx
->
devtype_data
.
reset
(
spi_imx
);
writel
(
1
,
spi_imx
->
base
+
MXC_RESET
);
/* drain receive buffer */
if
(
cpu_is_mx25
()
||
cpu_is_mx31
()
||
cpu_is_mx35
())
while
(
readl
(
spi_imx
->
base
+
MX3_CSPISTAT
)
&
MX3_CSPISTAT_RR
)
readl
(
spi_imx
->
base
+
MXC_CSPIRXDATA
);
spi_imx
->
intctrl
(
spi_imx
,
0
);
spi_imx
->
devtype_data
.
intctrl
(
spi_imx
,
0
);
ret
=
spi_bitbang_start
(
&
spi_imx
->
bitbang
);
ret
=
spi_bitbang_start
(
&
spi_imx
->
bitbang
);
if
(
ret
)
{
if
(
ret
)
{
...
@@ -668,6 +935,7 @@ static struct platform_driver spi_imx_driver = {
...
@@ -668,6 +935,7 @@ static struct platform_driver spi_imx_driver = {
.
name
=
DRIVER_NAME
,
.
name
=
DRIVER_NAME
,
.
owner
=
THIS_MODULE
,
.
owner
=
THIS_MODULE
,
},
},
.
id_table
=
spi_imx_devtype
,
.
probe
=
spi_imx_probe
,
.
probe
=
spi_imx_probe
,
.
remove
=
__devexit_p
(
spi_imx_remove
),
.
remove
=
__devexit_p
(
spi_imx_remove
),
};
};
...
...
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