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Commit ca247341 authored by Jeff Garzik's avatar Jeff Garzik
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[netdrvr ixgb] Lindent, then fix up obvious indent uglies by hand

parent d2f797b0
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Showing with 2121 additions and 2184 deletions
drivers/net/ixgb/ixgb.h
View file @ ca247341
......@@ -68,12 +68,10 @@ struct ixgb_adapter;
#define PCI_DMA_64BIT 0xffffffffffffffffULL
#define PCI_DMA_32BIT 0x00000000ffffffffULL
#include "ixgb_hw.h"
#include "ixgb_ee.h"
#include "ixgb_ids.h"
#if _DEBUG_DRIVER_
#define IXGB_DBG(args...) printk(KERN_DEBUG "ixgb: " args)
#else
......
drivers/net/ixgb/ixgb_ee.c
View file @ ca247341
......@@ -25,15 +25,13 @@
Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
*******************************************************************************/
#include "ixgb_hw.h"
#include "ixgb_ee.h"
/* Local prototypes */
static uint16_t ixgb_shift_in_bits(struct ixgb_hw *hw);
static void ixgb_shift_out_bits(struct ixgb_hw *hw,
uint16_t data,
uint16_t count);
uint16_t data, uint16_t count);
static void ixgb_standby_eeprom(struct ixgb_hw *hw);
static boolean_t ixgb_wait_eeprom_command(struct ixgb_hw *hw);
......@@ -47,8 +45,7 @@ static void ixgb_cleanup_eeprom(struct ixgb_hw *hw);
* eecd_reg - EECD's current value
*****************************************************************************/
static void
ixgb_raise_clock(struct ixgb_hw *hw,
uint32_t *eecd_reg)
ixgb_raise_clock(struct ixgb_hw *hw, uint32_t * eecd_reg)
{
/* Raise the clock input to the EEPROM (by setting the SK bit), and then
* wait 50 microseconds.
......@@ -66,8 +63,7 @@ ixgb_raise_clock(struct ixgb_hw *hw,
* eecd_reg - EECD's current value
*****************************************************************************/
static void
ixgb_lower_clock(struct ixgb_hw *hw,
uint32_t *eecd_reg)
ixgb_lower_clock(struct ixgb_hw *hw, uint32_t * eecd_reg)
{
/* Lower the clock input to the EEPROM (by clearing the SK bit), and then
* wait 50 microseconds.
......@@ -86,9 +82,7 @@ ixgb_lower_clock(struct ixgb_hw *hw,
* count - number of bits to shift out
*****************************************************************************/
static void
ixgb_shift_out_bits(struct ixgb_hw *hw,
uint16_t data,
uint16_t count)
ixgb_shift_out_bits(struct ixgb_hw *hw, uint16_t data, uint16_t count)
{
uint32_t eecd_reg;
uint32_t mask;
......@@ -108,7 +102,7 @@ ixgb_shift_out_bits(struct ixgb_hw *hw,
*/
eecd_reg &= ~IXGB_EECD_DI;
if(data & mask)
if (data & mask)
eecd_reg |= IXGB_EECD_DI;
IXGB_WRITE_REG(hw, EECD, eecd_reg);
......@@ -120,7 +114,7 @@ ixgb_shift_out_bits(struct ixgb_hw *hw,
mask = mask >> 1;
} while(mask);
} while (mask);
/* We leave the "DI" bit set to "0" when we leave this routine. */
eecd_reg &= ~IXGB_EECD_DI;
......@@ -152,14 +146,14 @@ ixgb_shift_in_bits(struct ixgb_hw *hw)
eecd_reg &= ~(IXGB_EECD_DO | IXGB_EECD_DI);
data = 0;
for(i = 0; i < 16; i++) {
for (i = 0; i < 16; i++) {
data = data << 1;
ixgb_raise_clock(hw, &eecd_reg);
eecd_reg = IXGB_READ_REG(hw, EECD);
eecd_reg &= ~(IXGB_EECD_DI);
if(eecd_reg & IXGB_EECD_DO)
if (eecd_reg & IXGB_EECD_DO)
data |= 1;
ixgb_lower_clock(hw, &eecd_reg);
......@@ -288,7 +282,6 @@ ixgb_wait_eeprom_command(struct ixgb_hw *hw)
uint32_t eecd_reg;
uint32_t i;
/* Toggle the CS line. This in effect tells to EEPROM to actually execute
* the command in question.
*/
......@@ -298,10 +291,10 @@ ixgb_wait_eeprom_command(struct ixgb_hw *hw)
* signal that the command has been completed by raising the DO signal.
* If DO does not go high in 10 milliseconds, then error out.
*/
for(i = 0; i < 200; i++) {
for (i = 0; i < 200; i++) {
eecd_reg = IXGB_READ_REG(hw, EECD);
if(eecd_reg & IXGB_EECD_DO)
if (eecd_reg & IXGB_EECD_DO)
return (TRUE);
usec_delay(50);
......@@ -310,7 +303,6 @@ ixgb_wait_eeprom_command(struct ixgb_hw *hw)
return (FALSE);
}
/******************************************************************************
* Verifies that the EEPROM has a valid checksum
*
......@@ -325,15 +317,15 @@ ixgb_wait_eeprom_command(struct ixgb_hw *hw)
* FALSE: Checksum is not valid.
*****************************************************************************/
boolean_t
ixgb_validate_eeprom_checksum(struct ixgb_hw *hw)
ixgb_validate_eeprom_checksum(struct ixgb_hw * hw)
{
uint16_t checksum = 0;
uint16_t i;
for(i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++)
for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++)
checksum += ixgb_read_eeprom(hw, i);
if(checksum == (uint16_t) EEPROM_SUM)
if (checksum == (uint16_t) EEPROM_SUM)
return (TRUE);
else
return (FALSE);
......@@ -353,7 +345,7 @@ ixgb_update_eeprom_checksum(struct ixgb_hw *hw)
uint16_t checksum = 0;
uint16_t i;
for(i = 0; i < EEPROM_CHECKSUM_REG; i++)
for (i = 0; i < EEPROM_CHECKSUM_REG; i++)
checksum += ixgb_read_eeprom(hw, i);
checksum = (uint16_t) EEPROM_SUM - checksum;
......@@ -374,9 +366,7 @@ ixgb_update_eeprom_checksum(struct ixgb_hw *hw)
*
*****************************************************************************/
void
ixgb_write_eeprom(struct ixgb_hw *hw,
uint16_t offset,
uint16_t data)
ixgb_write_eeprom(struct ixgb_hw *hw, uint16_t offset, uint16_t data)
{
/* Prepare the EEPROM for writing */
ixgb_setup_eeprom(hw);
......@@ -425,8 +415,7 @@ ixgb_write_eeprom(struct ixgb_hw *hw,
* The 16-bit value read from the eeprom
*****************************************************************************/
uint16_t
ixgb_read_eeprom(struct ixgb_hw *hw,
uint16_t offset)
ixgb_read_eeprom(struct ixgb_hw * hw, uint16_t offset)
{
uint16_t data;
......@@ -460,7 +449,7 @@ ixgb_read_eeprom(struct ixgb_hw *hw,
* FALSE: otherwise.
*****************************************************************************/
boolean_t
ixgb_get_eeprom_data(struct ixgb_hw *hw)
ixgb_get_eeprom_data(struct ixgb_hw * hw)
{
uint16_t i;
uint16_t checksum = 0;
......@@ -471,11 +460,11 @@ ixgb_get_eeprom_data(struct ixgb_hw *hw)
ee_map = (struct ixgb_ee_map_type *) hw->eeprom;
DEBUGOUT("ixgb_ee: Reading eeprom data\n");
for (i=0; i < IXGB_EEPROM_SIZE ; i++) {
for (i = 0; i < IXGB_EEPROM_SIZE; i++) {
uint16_t ee_data;
ee_data = ixgb_read_eeprom(hw, i);
checksum += ee_data;
hw->eeprom[i] = le16_to_cpu (ee_data);
hw->eeprom[i] = le16_to_cpu(ee_data);
}
if (checksum != (uint16_t) EEPROM_SUM) {
......@@ -486,13 +475,12 @@ ixgb_get_eeprom_data(struct ixgb_hw *hw)
if ((ee_map->init_ctrl_reg_1 & le16_to_cpu(EEPROM_ICW1_SIGNATURE_MASK))
!= le16_to_cpu(EEPROM_ICW1_SIGNATURE_VALID)) {
DEBUGOUT("ixgb_ee: Signature invalid.\n");
return(FALSE);
return (FALSE);
}
return(TRUE);
return (TRUE);
}
/******************************************************************************
* Local function to check if the eeprom signature is good
* If the eeprom signature is good, calls ixgb)get_eeprom_data.
......@@ -504,10 +492,10 @@ ixgb_get_eeprom_data(struct ixgb_hw *hw)
* FALSE: otherwise.
******************************************************************************/
static boolean_t
ixgb_check_and_get_eeprom_data (struct ixgb_hw* hw)
ixgb_check_and_get_eeprom_data(struct ixgb_hw *hw)
{
struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *) hw->eeprom;
struct ixgb_ee_map_type *ee_map =
(struct ixgb_ee_map_type *) hw->eeprom;
if ((ee_map->init_ctrl_reg_1 & le16_to_cpu(EEPROM_ICW1_SIGNATURE_MASK))
== le16_to_cpu(EEPROM_ICW1_SIGNATURE_VALID)) {
......@@ -526,15 +514,15 @@ ixgb_check_and_get_eeprom_data (struct ixgb_hw* hw)
* Returns: None.
******************************************************************************/
void
ixgb_get_ee_mac_addr(struct ixgb_hw *hw,
uint8_t *mac_addr)
ixgb_get_ee_mac_addr(struct ixgb_hw *hw, uint8_t * mac_addr)
{
int i;
struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *) hw->eeprom;
struct ixgb_ee_map_type *ee_map =
(struct ixgb_ee_map_type *) hw->eeprom;
DEBUGFUNC("ixgb_get_ee_mac_addr");
if (ixgb_check_and_get_eeprom_data (hw) == TRUE) {
if (ixgb_check_and_get_eeprom_data(hw) == TRUE) {
for (i = 0; i < IXGB_ETH_LENGTH_OF_ADDRESS; i++) {
mac_addr[i] = ee_map->mac_addr[i];
DEBUGOUT2("mac(%d) = %.2X\n", i, mac_addr[i]);
......@@ -553,12 +541,13 @@ ixgb_get_ee_mac_addr(struct ixgb_hw *hw,
uint16_t
ixgb_get_ee_compatibility(struct ixgb_hw *hw)
{
struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *) hw->eeprom;
struct ixgb_ee_map_type *ee_map =
(struct ixgb_ee_map_type *) hw->eeprom;
if (ixgb_check_and_get_eeprom_data (hw) == TRUE)
return(ee_map->compatibility);
if (ixgb_check_and_get_eeprom_data(hw) == TRUE)
return (ee_map->compatibility);
return(0);
return (0);
}
/******************************************************************************
......@@ -570,13 +559,13 @@ ixgb_get_ee_compatibility(struct ixgb_hw *hw)
* PBA number if EEPROM contents are valid, 0 otherwise
******************************************************************************/
uint32_t
ixgb_get_ee_pba_number(struct ixgb_hw *hw)
ixgb_get_ee_pba_number(struct ixgb_hw * hw)
{
if (ixgb_check_and_get_eeprom_data (hw) == TRUE)
return ( le16_to_cpu(hw->eeprom[EEPROM_PBA_1_2_REG])
| (le16_to_cpu(hw->eeprom[EEPROM_PBA_3_4_REG])<<16));
if (ixgb_check_and_get_eeprom_data(hw) == TRUE)
return (le16_to_cpu(hw->eeprom[EEPROM_PBA_1_2_REG])
| (le16_to_cpu(hw->eeprom[EEPROM_PBA_3_4_REG]) << 16));
return(0);
return (0);
}
/******************************************************************************
......@@ -588,14 +577,15 @@ ixgb_get_ee_pba_number(struct ixgb_hw *hw)
* Initialization Control Word 1 if EEPROM contents are valid, 0 otherwise
******************************************************************************/
uint16_t
ixgb_get_ee_init_ctrl_reg_1(struct ixgb_hw *hw)
ixgb_get_ee_init_ctrl_reg_1(struct ixgb_hw * hw)
{
struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *) hw->eeprom;
struct ixgb_ee_map_type *ee_map =
(struct ixgb_ee_map_type *) hw->eeprom;
if (ixgb_check_and_get_eeprom_data (hw) == TRUE)
return(ee_map->init_ctrl_reg_1);
if (ixgb_check_and_get_eeprom_data(hw) == TRUE)
return (ee_map->init_ctrl_reg_1);
return(0);
return (0);
}
/******************************************************************************
......@@ -607,14 +597,15 @@ ixgb_get_ee_init_ctrl_reg_1(struct ixgb_hw *hw)
* Initialization Control Word 2 if EEPROM contents are valid, 0 otherwise
******************************************************************************/
uint16_t
ixgb_get_ee_init_ctrl_reg_2(struct ixgb_hw *hw)
ixgb_get_ee_init_ctrl_reg_2(struct ixgb_hw * hw)
{
struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *) hw->eeprom;
struct ixgb_ee_map_type *ee_map =
(struct ixgb_ee_map_type *) hw->eeprom;
if (ixgb_check_and_get_eeprom_data (hw) == TRUE)
return(ee_map->init_ctrl_reg_2);
if (ixgb_check_and_get_eeprom_data(hw) == TRUE)
return (ee_map->init_ctrl_reg_2);
return(0);
return (0);
}
/******************************************************************************
......@@ -626,14 +617,15 @@ ixgb_get_ee_init_ctrl_reg_2(struct ixgb_hw *hw)
* Subsystem Id if EEPROM contents are valid, 0 otherwise
******************************************************************************/
uint16_t
ixgb_get_ee_subsystem_id(struct ixgb_hw *hw)
ixgb_get_ee_subsystem_id(struct ixgb_hw * hw)
{
struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *) hw->eeprom;
struct ixgb_ee_map_type *ee_map =
(struct ixgb_ee_map_type *) hw->eeprom;
if (ixgb_check_and_get_eeprom_data (hw) == TRUE)
return(ee_map->subsystem_id);
if (ixgb_check_and_get_eeprom_data(hw) == TRUE)
return (ee_map->subsystem_id);
return(0);
return (0);
}
/******************************************************************************
......@@ -645,14 +637,15 @@ ixgb_get_ee_subsystem_id(struct ixgb_hw *hw)
* Sub Vendor Id if EEPROM contents are valid, 0 otherwise
******************************************************************************/
uint16_t
ixgb_get_ee_subvendor_id(struct ixgb_hw *hw)
ixgb_get_ee_subvendor_id(struct ixgb_hw * hw)
{
struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *) hw->eeprom;
struct ixgb_ee_map_type *ee_map =
(struct ixgb_ee_map_type *) hw->eeprom;
if (ixgb_check_and_get_eeprom_data (hw) == TRUE)
return(ee_map->subvendor_id);
if (ixgb_check_and_get_eeprom_data(hw) == TRUE)
return (ee_map->subvendor_id);
return(0);
return (0);
}
/******************************************************************************
......@@ -664,14 +657,15 @@ ixgb_get_ee_subvendor_id(struct ixgb_hw *hw)
* Device Id if EEPROM contents are valid, 0 otherwise
******************************************************************************/
uint16_t
ixgb_get_ee_device_id(struct ixgb_hw *hw)
ixgb_get_ee_device_id(struct ixgb_hw * hw)
{
struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *) hw->eeprom;
struct ixgb_ee_map_type *ee_map =
(struct ixgb_ee_map_type *) hw->eeprom;
if (ixgb_check_and_get_eeprom_data (hw) == TRUE)
return(ee_map->device_id);
if (ixgb_check_and_get_eeprom_data(hw) == TRUE)
return (ee_map->device_id);
return(0);
return (0);
}
/******************************************************************************
......@@ -683,14 +677,15 @@ ixgb_get_ee_device_id(struct ixgb_hw *hw)
* Device Id if EEPROM contents are valid, 0 otherwise
******************************************************************************/
uint16_t
ixgb_get_ee_vendor_id(struct ixgb_hw *hw)
ixgb_get_ee_vendor_id(struct ixgb_hw * hw)
{
struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *) hw->eeprom;
struct ixgb_ee_map_type *ee_map =
(struct ixgb_ee_map_type *) hw->eeprom;
if (ixgb_check_and_get_eeprom_data (hw) == TRUE)
return(ee_map->vendor_id);
if (ixgb_check_and_get_eeprom_data(hw) == TRUE)
return (ee_map->vendor_id);
return(0);
return (0);
}
/******************************************************************************
......@@ -702,14 +697,15 @@ ixgb_get_ee_vendor_id(struct ixgb_hw *hw)
* SDP Register if EEPROM contents are valid, 0 otherwise
******************************************************************************/
uint16_t
ixgb_get_ee_swdpins_reg(struct ixgb_hw *hw)
ixgb_get_ee_swdpins_reg(struct ixgb_hw * hw)
{
struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *) hw->eeprom;
struct ixgb_ee_map_type *ee_map =
(struct ixgb_ee_map_type *) hw->eeprom;
if (ixgb_check_and_get_eeprom_data (hw) == TRUE)
return(ee_map->swdpins_reg);
if (ixgb_check_and_get_eeprom_data(hw) == TRUE)
return (ee_map->swdpins_reg);
return(0);
return (0);
}
/******************************************************************************
......@@ -721,14 +717,15 @@ ixgb_get_ee_swdpins_reg(struct ixgb_hw *hw)
* D3 Power Management Bits if EEPROM contents are valid, 0 otherwise
******************************************************************************/
uint8_t
ixgb_get_ee_d3_power(struct ixgb_hw *hw)
ixgb_get_ee_d3_power(struct ixgb_hw * hw)
{
struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *) hw->eeprom;
struct ixgb_ee_map_type *ee_map =
(struct ixgb_ee_map_type *) hw->eeprom;
if (ixgb_check_and_get_eeprom_data (hw) == TRUE)
return(ee_map->d3_power);
if (ixgb_check_and_get_eeprom_data(hw) == TRUE)
return (ee_map->d3_power);
return(0);
return (0);
}
/******************************************************************************
......@@ -740,12 +737,13 @@ ixgb_get_ee_d3_power(struct ixgb_hw *hw)
* D0 Power Management Bits if EEPROM contents are valid, 0 otherwise
******************************************************************************/
uint8_t
ixgb_get_ee_d0_power(struct ixgb_hw *hw)
ixgb_get_ee_d0_power(struct ixgb_hw * hw)
{
struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *) hw->eeprom;
struct ixgb_ee_map_type *ee_map =
(struct ixgb_ee_map_type *) hw->eeprom;
if (ixgb_check_and_get_eeprom_data (hw) == TRUE)
return(ee_map->d0_power);
if (ixgb_check_and_get_eeprom_data(hw) == TRUE)
return (ee_map->d0_power);
return(0);
return (0);
}
drivers/net/ixgb/ixgb_ee.h
View file @ ca247341
......@@ -28,12 +28,10 @@
#ifndef _IXGB_EE_H_
#define _IXGB_EE_H_
#define IXGB_EEPROM_SIZE 64 /* Size in words */
#define IXGB_ETH_LENGTH_OF_ADDRESS 6
/* EEPROM Commands */
#define EEPROM_READ_OPCODE 0x6 /* EERPOM read opcode */
#define EEPROM_WRITE_OPCODE 0x5 /* EERPOM write opcode */
......@@ -74,7 +72,7 @@
/* EEPROM Map defines (WORD OFFSETS)*/
/* EEPROM structure */
struct ixgb_ee_map_type{
struct ixgb_ee_map_type {
uint8_t mac_addr[IXGB_ETH_LENGTH_OF_ADDRESS];
uint16_t compatibility;
uint16_t reserved1[4];
......@@ -92,19 +90,15 @@ struct ixgb_ee_map_type{
uint8_t d0_power;
uint16_t reserved2[28];
uint16_t checksum;
};
};
/* EEPROM Functions */
uint16_t ixgb_read_eeprom(struct ixgb_hw *hw,
uint16_t reg);
uint16_t ixgb_read_eeprom(struct ixgb_hw *hw, uint16_t reg);
boolean_t ixgb_validate_eeprom_checksum(struct ixgb_hw *hw);
void ixgb_update_eeprom_checksum(struct ixgb_hw *hw);
void ixgb_write_eeprom(struct ixgb_hw *hw,
uint16_t reg,
uint16_t data);
void ixgb_write_eeprom(struct ixgb_hw *hw, uint16_t reg, uint16_t data);
#endif /* IXGB_EE_H */
drivers/net/ixgb/ixgb_ethtool.c
View file @ ca247341
......@@ -25,7 +25,6 @@
Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
*******************************************************************************/
/* ethtool support for ixgb */
#include "ixgb.h"
......@@ -55,15 +54,14 @@ ixgb_eeprom_size(struct ixgb_hw *hw)
#define SPEED_10000 10000
static void
ixgb_ethtool_gset(struct ixgb_adapter *adapter,
struct ethtool_cmd *ecmd)
ixgb_ethtool_gset(struct ixgb_adapter *adapter, struct ethtool_cmd *ecmd)
{
ecmd->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
ecmd->advertising = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
ecmd->port = PORT_FIBRE;
ecmd->transceiver = XCVR_EXTERNAL;
if(netif_carrier_ok(adapter->netdev)) {
if (netif_carrier_ok(adapter->netdev)) {
ecmd->speed = 10000;
ecmd->duplex = DUPLEX_FULL;
} else {
......@@ -75,10 +73,9 @@ ixgb_ethtool_gset(struct ixgb_adapter *adapter,
}
static int
ixgb_ethtool_sset(struct ixgb_adapter *adapter,
struct ethtool_cmd *ecmd)
ixgb_ethtool_sset(struct ixgb_adapter *adapter, struct ethtool_cmd *ecmd)
{
if(ecmd->autoneg == AUTONEG_ENABLE ||
if (ecmd->autoneg == AUTONEG_ENABLE ||
ecmd->speed + ecmd->duplex != SPEED_10000 + DUPLEX_FULL)
return -EINVAL;
else {
......@@ -97,12 +94,12 @@ ixgb_ethtool_promiscuous(struct ixgb_adapter *adapter,
uint32_t rctl = IXGB_READ_REG(&adapter->hw, RCTL);
pmode->rctl_old = rctl;
if(pmode->upe)
if (pmode->upe)
rctl |= IXGB_RCTL_UPE;
else
rctl &= ~IXGB_RCTL_UPE;
if(pmode->mpe)
if (pmode->mpe)
rctl |= IXGB_RCTL_MPE;
else
rctl &= ~IXGB_RCTL_MPE;
......@@ -134,8 +131,7 @@ ixgb_ethtool_gdrvinfo(struct ixgb_adapter *adapter,
#define IXGB_GET_STAT(_A_, _R_) _A_->stats._R_
static void
ixgb_ethtool_gregs(struct ixgb_adapter *adapter,
struct ethtool_regs *regs,
uint8_t *regs_buff)
struct ethtool_regs *regs, uint8_t * regs_buff)
{
struct ixgb_hw *hw = &adapter->hw;
uint32_t *reg = (uint32_t *) regs_buff;
......@@ -172,7 +168,7 @@ ixgb_ethtool_gregs(struct ixgb_adapter *adapter,
*reg++ = IXGB_READ_REG(hw, RAIDC); /* 19 */
*reg++ = IXGB_READ_REG(hw, RXCSUM); /* 20 */
for(i = 0; i < IXGB_RAR_ENTRIES; i++) {
for (i = 0; i < IXGB_RAR_ENTRIES; i++) {
*reg++ = IXGB_READ_REG_ARRAY(hw, RAL, (i << 1)); /*21,...,51 */
*reg++ = IXGB_READ_REG_ARRAY(hw, RAH, (i << 1)); /*22,...,52 */
}
......@@ -277,14 +273,13 @@ ixgb_ethtool_gregs(struct ixgb_adapter *adapter,
#if 0
#endif
regs->len = (reg - reg_start) * sizeof(uint32_t);
regs->len = (reg - reg_start) * sizeof (uint32_t);
}
#endif /* ETHTOOL_GREGS */
static int
ixgb_ethtool_geeprom(struct ixgb_adapter *adapter,
struct ethtool_eeprom *eeprom,
uint16_t *eeprom_buff)
struct ethtool_eeprom *eeprom, uint16_t * eeprom_buff)
{
struct ixgb_hw *hw = &adapter->hw;
int i, max_len, first_word, last_word;
......@@ -300,16 +295,16 @@ ixgb_ethtool_geeprom(struct ixgb_adapter *adapter,
/* use our function to read the eeprom and update our cache */
ixgb_get_eeprom_data(hw);
if(eeprom->offset > eeprom->offset + eeprom->len)
if (eeprom->offset > eeprom->offset + eeprom->len)
return -EINVAL;
if((eeprom->offset + eeprom->len) > max_len)
if ((eeprom->offset + eeprom->len) > max_len)
eeprom->len = (max_len - eeprom->offset);
first_word = eeprom->offset >> 1;
last_word = (eeprom->offset + eeprom->len - 1) >> 1;
for(i = 0; i <= (last_word - first_word); i++) {
for (i = 0; i <= (last_word - first_word); i++) {
eeprom_buff[i] = hw->eeprom[first_word + i];
}
......@@ -324,44 +319,44 @@ ixgb_ethtool_seeprom(struct ixgb_adapter *adapter,
int i, max_len, first_word, last_word;
void *ptr;
if(eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
return -EFAULT;
if(eeprom->len == 0)
if (eeprom->len == 0)
return -EINVAL;
max_len = ixgb_eeprom_size(hw);
if(eeprom->offset > eeprom->offset + eeprom->len)
if (eeprom->offset > eeprom->offset + eeprom->len)
return -EINVAL;
if((eeprom->offset + eeprom->len) > max_len)
if ((eeprom->offset + eeprom->len) > max_len)
eeprom->len = (max_len - eeprom->offset);
first_word = eeprom->offset >> 1;
last_word = (eeprom->offset + eeprom->len - 1) >> 1;
ptr = (void *)eeprom_buff;
ptr = (void *) eeprom_buff;
if(eeprom->offset & 1) {
if (eeprom->offset & 1) {
/* need read/modify/write of first changed EEPROM word */
/* only the second byte of the word is being modified */
eeprom_buff[0] = ixgb_read_eeprom(hw, first_word);
ptr++;
}
if((eeprom->offset + eeprom->len) & 1) {
if ((eeprom->offset + eeprom->len) & 1) {
/* need read/modify/write of last changed EEPROM word */
/* only the first byte of the word is being modified */
eeprom_buff[last_word - first_word]
= ixgb_read_eeprom(hw, last_word);
}
if(copy_from_user(ptr, user_data, eeprom->len))
if (copy_from_user(ptr, user_data, eeprom->len))
return -EFAULT;
for(i = 0; i <= (last_word - first_word); i++)
for (i = 0; i <= (last_word - first_word); i++)
ixgb_write_eeprom(hw, first_word + i, eeprom_buff[i]);
/* Update the checksum over the first part of the EEPROM if needed */
if(first_word <= EEPROM_CHECKSUM_REG)
if (first_word <= EEPROM_CHECKSUM_REG)
ixgb_update_eeprom_checksum(hw);
return 0;
......@@ -380,7 +375,7 @@ ixgb_led_blink_callback(unsigned long data)
{
struct ixgb_adapter *adapter = (struct ixgb_adapter *) data;
if(test_and_change_bit(IXGB_LED_ON, &adapter->led_status))
if (test_and_change_bit(IXGB_LED_ON, &adapter->led_status))
ixgb_led_off(&adapter->hw);
else
ixgb_led_on(&adapter->hw);
......@@ -389,10 +384,9 @@ ixgb_led_blink_callback(unsigned long data)
}
static int
ixgb_ethtool_led_blink(struct ixgb_adapter *adapter,
struct ethtool_value *id)
ixgb_ethtool_led_blink(struct ixgb_adapter *adapter, struct ethtool_value *id)
{
if(!adapter->blink_timer.function) {
if (!adapter->blink_timer.function) {
init_timer(&adapter->blink_timer);
adapter->blink_timer.function = ixgb_led_blink_callback;
adapter->blink_timer.data = (unsigned long) adapter;
......@@ -401,7 +395,7 @@ ixgb_ethtool_led_blink(struct ixgb_adapter *adapter,
mod_timer(&adapter->blink_timer, jiffies);
set_current_state(TASK_INTERRUPTIBLE);
if(id->data)
if (id->data)
schedule_timeout(id->data * HZ);
else
schedule_timeout(MAX_SCHEDULE_TIMEOUT);
......@@ -415,27 +409,26 @@ ixgb_ethtool_led_blink(struct ixgb_adapter *adapter,
#endif /* ETHTOOL_PHYS_ID */
int
ixgb_ethtool_ioctl(struct net_device *netdev,
struct ifreq *ifr)
ixgb_ethtool_ioctl(struct net_device *netdev, struct ifreq *ifr)
{
struct ixgb_adapter *adapter = netdev->priv;
void *addr = ifr->ifr_data;
uint32_t cmd;
if(get_user(cmd, (uint32_t *) addr))
if (get_user(cmd, (uint32_t *) addr))
return -EFAULT;
switch (cmd) {
#if 0
case ETHTOOL_PROMISCUOUS: {
case ETHTOOL_PROMISCUOUS:{
struct ethtool_pmode pmode;
if(copy_from_user(&pmode, addr, sizeof(pmode)))
if (copy_from_user(&pmode, addr, sizeof (pmode)))
return -EFAULT;
ixgb_ethtool_promiscuous(adapter, &pmode);
if(copy_to_user(addr, &pmode, sizeof(pmode)))
if (copy_to_user(addr, &pmode, sizeof (pmode)))
return -EFAULT;
return 0;
......@@ -445,20 +438,20 @@ ixgb_ethtool_ioctl(struct net_device *netdev,
ixgb_up(netdev->priv);
return 0;
#endif
case ETHTOOL_GSET: {
case ETHTOOL_GSET:{
struct ethtool_cmd ecmd = { ETHTOOL_GSET };
ixgb_ethtool_gset(adapter, &ecmd);
if(copy_to_user(addr, &ecmd, sizeof(ecmd)))
if (copy_to_user(addr, &ecmd, sizeof (ecmd)))
return -EFAULT;
return 0;
}
case ETHTOOL_SSET: {
case ETHTOOL_SSET:{
struct ethtool_cmd ecmd;
if(!capable(CAP_NET_ADMIN))
if (!capable(CAP_NET_ADMIN))
return -EPERM;
if(copy_from_user(&ecmd, addr, sizeof(ecmd)))
if (copy_from_user(&ecmd, addr, sizeof (ecmd)))
return -EFAULT;
return ixgb_ethtool_sset(adapter, &ecmd);
}
......@@ -467,30 +460,30 @@ ixgb_ethtool_ioctl(struct net_device *netdev,
struct ethtool_drvinfo drvinfo = { ETHTOOL_GDRVINFO };
ixgb_ethtool_gdrvinfo(adapter, &drvinfo);
if(copy_to_user(addr, &drvinfo, sizeof(drvinfo)))
if (copy_to_user(addr, &drvinfo, sizeof (drvinfo)))
return -EFAULT;
return 0;
}
#if defined(ETHTOOL_GREGS) && defined(ETHTOOL_GEEPROM)
case ETHTOOL_GREGS: {
case ETHTOOL_GREGS:{
struct ethtool_regs regs = { ETHTOOL_GREGS };
uint8_t regs_buff[IXGB_REG_DUMP_LEN];
ixgb_ethtool_gregs(adapter, &regs, regs_buff);
if(copy_to_user(addr, &regs, sizeof(regs)))
if (copy_to_user(addr, &regs, sizeof (regs)))
return -EFAULT;
addr += offsetof(struct ethtool_regs, data);
if(copy_to_user(addr, regs_buff, regs.len))
if (copy_to_user(addr, regs_buff, regs.len))
return -EFAULT;
return 0;
}
#endif /* ETHTOOL_GREGS */
case ETHTOOL_NWAY_RST: {
case ETHTOOL_NWAY_RST:{
IXGB_DBG("ETHTOOL_NWAY_RST\n");
if(!capable(CAP_NET_ADMIN))
if (!capable(CAP_NET_ADMIN))
return -EPERM;
ixgb_down(adapter);
......@@ -499,56 +492,58 @@ ixgb_ethtool_ioctl(struct net_device *netdev,
return 0;
}
#ifdef ETHTOOL_PHYS_ID
case ETHTOOL_PHYS_ID: {
case ETHTOOL_PHYS_ID:{
struct ethtool_value id;
IXGB_DBG("ETHTOOL_PHYS_ID\n");
if(copy_from_user(&id, addr, sizeof(id)))
if (copy_from_user(&id, addr, sizeof (id)))
return -EFAULT;
return ixgb_ethtool_led_blink(adapter, &id);
}
#endif /* ETHTOOL_PHYS_ID */
case ETHTOOL_GLINK: {
case ETHTOOL_GLINK:{
struct ethtool_value link = { ETHTOOL_GLINK };
IXGB_DBG("ETHTOOL_GLINK\n");
link.data = netif_carrier_ok(netdev);
if(copy_to_user(addr, &link, sizeof(link)))
if (copy_to_user(addr, &link, sizeof (link)))
return -EFAULT;
return 0;
}
case ETHTOOL_GEEPROM: {
case ETHTOOL_GEEPROM:{
struct ethtool_eeprom eeprom = { ETHTOOL_GEEPROM };
uint16_t eeprom_buff[IXGB_EEPROM_SIZE];
void *ptr;
int err;
IXGB_DBG("ETHTOOL_GEEPROM\n");
if(copy_from_user(&eeprom, addr, sizeof(eeprom)))
if (copy_from_user(&eeprom, addr, sizeof (eeprom)))
return -EFAULT;
if ((err = ixgb_ethtool_geeprom(adapter, &eeprom, eeprom_buff))<0)
if ((err =
ixgb_ethtool_geeprom(adapter, &eeprom,
eeprom_buff)) < 0)
return err;
if(copy_to_user(addr, &eeprom, sizeof(eeprom)))
if (copy_to_user(addr, &eeprom, sizeof (eeprom)))
return -EFAULT;
addr += offsetof(struct ethtool_eeprom, data);
ptr = ((void *)eeprom_buff) + (eeprom.offset & 1);
if(copy_to_user(addr, ptr, eeprom.len))
ptr = ((void *) eeprom_buff) + (eeprom.offset & 1);
if (copy_to_user(addr, ptr, eeprom.len))
return -EFAULT;
return 0;
}
case ETHTOOL_SEEPROM: {
case ETHTOOL_SEEPROM:{
struct ethtool_eeprom eeprom;
IXGB_DBG("ETHTOOL_SEEPROM\n");
if(!capable(CAP_NET_ADMIN))
if (!capable(CAP_NET_ADMIN))
return -EPERM;
if(copy_from_user(&eeprom, addr, sizeof(eeprom)))
if (copy_from_user(&eeprom, addr, sizeof (eeprom)))
return -EFAULT;
addr += offsetof(struct ethtool_eeprom, data);
......@@ -558,4 +553,3 @@ ixgb_ethtool_ioctl(struct net_device *netdev,
return -EOPNOTSUPP;
}
}
drivers/net/ixgb/ixgb_hw.c
View file @ ca247341
......@@ -25,7 +25,6 @@
Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
*******************************************************************************/
/* ixgb_hw.c
* Shared functions for accessing and configuring the adapter
*/
......@@ -35,35 +34,29 @@
/* Local function prototypes */
static uint32_t ixgb_hash_mc_addr(struct ixgb_hw *hw,
uint8_t *mc_addr);
static uint32_t ixgb_hash_mc_addr(struct ixgb_hw *hw, uint8_t * mc_addr);
static void ixgb_mta_set(struct ixgb_hw *hw,
uint32_t hash_value);
static void ixgb_mta_set(struct ixgb_hw *hw, uint32_t hash_value);
static void ixgb_get_bus_info(struct ixgb_hw *hw);
boolean_t mac_addr_valid(uint8_t *mac_addr);
boolean_t mac_addr_valid(uint8_t * mac_addr);
static boolean_t ixgb_link_reset(struct ixgb_hw *hw);
static void ixgb_optics_reset(struct ixgb_hw *hw);
uint32_t ixgb_mac_reset (struct ixgb_hw* hw);
uint32_t ixgb_mac_reset(struct ixgb_hw *hw);
uint32_t ixgb_mac_reset (struct ixgb_hw* hw)
uint32_t
ixgb_mac_reset(struct ixgb_hw *hw)
{
uint32_t ctrl_reg;
/* Setup up hardware to known state with RESET. */
ctrl_reg = IXGB_CTRL0_RST |
IXGB_CTRL0_SDP3_DIR | /* All pins are Output=1 */
IXGB_CTRL0_SDP2_DIR |
IXGB_CTRL0_SDP1_DIR |
IXGB_CTRL0_SDP0_DIR |
IXGB_CTRL0_SDP3 | /* Initial value 1101 */
IXGB_CTRL0_SDP2 |
IXGB_CTRL0_SDP0;
ctrl_reg = IXGB_CTRL0_RST | IXGB_CTRL0_SDP3_DIR | /* All pins are Output=1 */
IXGB_CTRL0_SDP2_DIR | IXGB_CTRL0_SDP1_DIR | IXGB_CTRL0_SDP0_DIR | IXGB_CTRL0_SDP3 | /* Initial value 1101 */
IXGB_CTRL0_SDP2 | IXGB_CTRL0_SDP0;
#ifdef HP_ZX1
outl(IXGB_CTRL0, hw->io_base);
outl(ctrl_reg, hw->io_base + 4);
......@@ -89,7 +82,7 @@ uint32_t ixgb_mac_reset (struct ixgb_hw* hw)
* hw - Struct containing variables accessed by shared code
*****************************************************************************/
boolean_t
ixgb_adapter_stop(struct ixgb_hw *hw)
ixgb_adapter_stop(struct ixgb_hw * hw)
{
uint32_t ctrl_reg;
uint32_t icr_reg;
......@@ -99,7 +92,7 @@ ixgb_adapter_stop(struct ixgb_hw *hw)
/* If we are stopped or resetting exit gracefully and wait to be
* started again before accessing the hardware.
*/
if(hw->adapter_stopped) {
if (hw->adapter_stopped) {
DEBUGOUT("Exiting because the adapter is already stopped!!!\n");
return FALSE;
}
......@@ -158,7 +151,7 @@ ixgb_adapter_stop(struct ixgb_hw *hw)
* FALSE if unrecoverable problems were encountered.
*****************************************************************************/
boolean_t
ixgb_init_hw(struct ixgb_hw *hw)
ixgb_init_hw(struct ixgb_hw * hw)
{
uint32_t i;
uint32_t ctrl_reg;
......@@ -187,10 +180,9 @@ ixgb_init_hw(struct ixgb_hw *hw)
msec_delay(IXGB_DELAY_AFTER_EE_RESET);
if (ixgb_get_eeprom_data(hw) == FALSE) {
return(FALSE);
return (FALSE);
}
/* Setup the receive addresses.
* Receive Address Registers (RARs 0 - 15).
*/
......@@ -202,7 +194,7 @@ ixgb_init_hw(struct ixgb_hw *hw)
*/
if (!mac_addr_valid(hw->curr_mac_addr)) {
DEBUGOUT("MAC address invalid after ixgb_init_rx_addrs\n");
return(FALSE);
return (FALSE);
}
/* tell the routines in this file they can access hardware again */
......@@ -213,7 +205,7 @@ ixgb_init_hw(struct ixgb_hw *hw)
/* Zero out the Multicast HASH table */
DEBUGOUT("Zeroing the MTA\n");
for(i = 0; i < IXGB_MC_TBL_SIZE; i++)
for (i = 0; i < IXGB_MC_TBL_SIZE; i++)
IXGB_WRITE_REG_ARRAY(hw, MTA, i, 0);
/* Zero out the VLAN Filter Table Array */
......@@ -259,32 +251,27 @@ ixgb_init_rx_addrs(struct ixgb_hw *hw)
DEBUGOUT3(" Keeping Permanent MAC Addr =%.2X %.2X %.2X ",
hw->curr_mac_addr[0],
hw->curr_mac_addr[1],
hw->curr_mac_addr[2]);
hw->curr_mac_addr[1], hw->curr_mac_addr[2]);
DEBUGOUT3("%.2X %.2X %.2X\n",
hw->curr_mac_addr[3],
hw->curr_mac_addr[4],
hw->curr_mac_addr[5]);
hw->curr_mac_addr[4], hw->curr_mac_addr[5]);
} else {
/* Setup the receive address. */
DEBUGOUT("Overriding MAC Address in RAR[0]\n");
DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ",
hw->curr_mac_addr[0],
hw->curr_mac_addr[1],
hw->curr_mac_addr[2]);
hw->curr_mac_addr[1], hw->curr_mac_addr[2]);
DEBUGOUT3("%.2X %.2X %.2X\n",
hw->curr_mac_addr[3],
hw->curr_mac_addr[4],
hw->curr_mac_addr[5]);
hw->curr_mac_addr[4], hw->curr_mac_addr[5]);
ixgb_rar_set(hw, hw->curr_mac_addr, 0);
}
/* Zero out the other 15 receive addresses. */
DEBUGOUT("Clearing RAR[1-15]\n");
for(i = 1; i < IXGB_RAR_ENTRIES; i++) {
for (i = 1; i < IXGB_RAR_ENTRIES; i++) {
IXGB_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
IXGB_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
}
......@@ -307,9 +294,8 @@ ixgb_init_rx_addrs(struct ixgb_hw *hw)
*****************************************************************************/
void
ixgb_mc_addr_list_update(struct ixgb_hw *hw,
uint8_t *mc_addr_list,
uint32_t mc_addr_count,
uint32_t pad)
uint8_t * mc_addr_list,
uint32_t mc_addr_count, uint32_t pad)
{
uint32_t hash_value;
uint32_t i;
......@@ -322,41 +308,49 @@ ixgb_mc_addr_list_update(struct ixgb_hw *hw,
/* Clear RAR[1-15] */
DEBUGOUT(" Clearing RAR[1-15]\n");
for(i = rar_used_count; i < IXGB_RAR_ENTRIES; i++) {
for (i = rar_used_count; i < IXGB_RAR_ENTRIES; i++) {
IXGB_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
IXGB_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
}
/* Clear the MTA */
DEBUGOUT(" Clearing MTA\n");
for(i = 0; i < IXGB_MC_TBL_SIZE; i++) {
for (i = 0; i < IXGB_MC_TBL_SIZE; i++) {
IXGB_WRITE_REG_ARRAY(hw, MTA, i, 0);
}
/* Add the new addresses */
for(i = 0; i < mc_addr_count; i++) {
for (i = 0; i < mc_addr_count; i++) {
DEBUGOUT(" Adding the multicast addresses:\n");
DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i,
mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad)],
mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) + 1],
mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) + 2],
mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) + 3],
mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) + 4],
mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) + 5]);
mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) +
1],
mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) +
2],
mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) +
3],
mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) +
4],
mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) +
5]);
/* Place this multicast address in the RAR if there is room, *
* else put it in the MTA
*/
if(rar_used_count < IXGB_RAR_ENTRIES) {
if (rar_used_count < IXGB_RAR_ENTRIES) {
ixgb_rar_set(hw,
mc_addr_list + (i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad)),
mc_addr_list +
(i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad)),
rar_used_count);
DEBUGOUT1("Added a multicast address to RAR[%d]\n", i);
rar_used_count++;
} else {
hash_value = ixgb_hash_mc_addr(hw,
mc_addr_list +
(i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad)));
(i *
(IXGB_ETH_LENGTH_OF_ADDRESS
+ pad)));
DEBUGOUT1(" Hash value = 0x%03X\n", hash_value);
......@@ -378,8 +372,7 @@ ixgb_mc_addr_list_update(struct ixgb_hw *hw,
* The hash value
*****************************************************************************/
static uint32_t
ixgb_hash_mc_addr(struct ixgb_hw *hw,
uint8_t *mc_addr)
ixgb_hash_mc_addr(struct ixgb_hw *hw, uint8_t * mc_addr)
{
uint32_t hash_value = 0;
......@@ -394,13 +387,16 @@ ixgb_hash_mc_addr(struct ixgb_hw *hw,
* LSB MSB - According to H/W docs */
case 0:
/* [47:36] i.e. 0x563 for above example address */
hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4));
hash_value =
((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4));
break;
case 1: /* [46:35] i.e. 0xAC6 for above example address */
hash_value = ((mc_addr[4] >> 3) | (((uint16_t) mc_addr[5]) << 5));
hash_value =
((mc_addr[4] >> 3) | (((uint16_t) mc_addr[5]) << 5));
break;
case 2: /* [45:34] i.e. 0x5D8 for above example address */
hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6));
hash_value =
((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6));
break;
case 3: /* [43:32] i.e. 0x634 for above example address */
hash_value = ((mc_addr[4]) | (((uint16_t) mc_addr[5]) << 8));
......@@ -423,8 +419,7 @@ ixgb_hash_mc_addr(struct ixgb_hw *hw,
* hash_value - Multicast address hash value
*****************************************************************************/
static void
ixgb_mta_set(struct ixgb_hw *hw,
uint32_t hash_value)
ixgb_mta_set(struct ixgb_hw *hw, uint32_t hash_value)
{
uint32_t hash_bit, hash_reg;
uint32_t mta_reg;
......@@ -457,9 +452,7 @@ ixgb_mta_set(struct ixgb_hw *hw,
* index - Receive address register to write
*****************************************************************************/
void
ixgb_rar_set(struct ixgb_hw *hw,
uint8_t *addr,
uint32_t index)
ixgb_rar_set(struct ixgb_hw *hw, uint8_t * addr, uint32_t index)
{
uint32_t rar_low, rar_high;
......@@ -470,12 +463,10 @@ ixgb_rar_set(struct ixgb_hw *hw,
*/
rar_low = ((uint32_t) addr[0] |
((uint32_t) addr[1] << 8) |
((uint32_t) addr[2] << 16) |
((uint32_t) addr[3] << 24));
((uint32_t) addr[2] << 16) | ((uint32_t) addr[3] << 24));
rar_high = ((uint32_t) addr[4] |
((uint32_t) addr[5] << 8) |
IXGB_RAH_AV);
((uint32_t) addr[5] << 8) | IXGB_RAH_AV);
IXGB_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
IXGB_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
......@@ -490,9 +481,7 @@ ixgb_rar_set(struct ixgb_hw *hw,
* value - Value to write into VLAN filter table
*****************************************************************************/
void
ixgb_write_vfta(struct ixgb_hw *hw,
uint32_t offset,
uint32_t value)
ixgb_write_vfta(struct ixgb_hw *hw, uint32_t offset, uint32_t value)
{
IXGB_WRITE_REG_ARRAY(hw, VFTA, offset, value);
return;
......@@ -508,7 +497,7 @@ ixgb_clear_vfta(struct ixgb_hw *hw)
{
uint32_t offset;
for(offset = 0; offset < IXGB_VLAN_FILTER_TBL_SIZE; offset++)
for (offset = 0; offset < IXGB_VLAN_FILTER_TBL_SIZE; offset++)
IXGB_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
return;
}
......@@ -520,7 +509,7 @@ ixgb_clear_vfta(struct ixgb_hw *hw)
*****************************************************************************/
boolean_t
ixgb_setup_fc(struct ixgb_hw *hw)
ixgb_setup_fc(struct ixgb_hw * hw)
{
uint32_t ctrl_reg;
uint32_t pap_reg = 0; /* by default, assume no pause time */
......@@ -586,14 +575,14 @@ ixgb_setup_fc(struct ixgb_hw *hw)
* ability to transmit pause frames in not enabled, then these
* registers will be set to 0.
*/
if(!(hw->fc.type & ixgb_fc_tx_pause)) {
if (!(hw->fc.type & ixgb_fc_tx_pause)) {
IXGB_WRITE_REG(hw, FCRTL, 0);
IXGB_WRITE_REG(hw, FCRTH, 0);
} else {
/* We need to set up the Receive Threshold high and low water
* marks as well as (optionally) enabling the transmission of XON frames.
*/
if(hw->fc.send_xon) {
if (hw->fc.send_xon) {
IXGB_WRITE_REG(hw, FCRTL,
(hw->fc.low_water | IXGB_FCRTL_XONE));
} else {
......@@ -619,10 +608,9 @@ ixgb_setup_fc(struct ixgb_hw *hw)
* read command.
*****************************************************************************/
uint16_t
ixgb_read_phy_reg(struct ixgb_hw *hw,
ixgb_read_phy_reg(struct ixgb_hw * hw,
uint32_t reg_address,
uint32_t phy_address,
uint32_t device_type)
uint32_t phy_address, uint32_t device_type)
{
uint32_t i;
uint32_t data;
......@@ -647,8 +635,7 @@ ixgb_read_phy_reg(struct ixgb_hw *hw,
** from the CPU Write to the Ready bit assertion.
**************************************************************/
for (i = 0; i < 10; i++)
{
for (i = 0; i < 10; i++) {
usec_delay(10);
command = IXGB_READ_REG(hw, MSCA);
......@@ -674,8 +661,7 @@ ixgb_read_phy_reg(struct ixgb_hw *hw,
** from the CPU Write to the Ready bit assertion.
**************************************************************/
for (i = 0; i < 10; i++)
{
for (i = 0; i < 10; i++) {
usec_delay(10);
command = IXGB_READ_REG(hw, MSCA);
......@@ -691,7 +677,7 @@ ixgb_read_phy_reg(struct ixgb_hw *hw,
*/
data = IXGB_READ_REG(hw, MSRWD);
data >>= IXGB_MSRWD_READ_DATA_SHIFT;
return((uint16_t) data);
return ((uint16_t) data);
}
/******************************************************************************
......@@ -713,9 +699,7 @@ ixgb_read_phy_reg(struct ixgb_hw *hw,
void
ixgb_write_phy_reg(struct ixgb_hw *hw,
uint32_t reg_address,
uint32_t phy_address,
uint32_t device_type,
uint16_t data)
uint32_t phy_address, uint32_t device_type, uint16_t data)
{
uint32_t i;
uint32_t command = 0;
......@@ -725,7 +709,7 @@ ixgb_write_phy_reg(struct ixgb_hw *hw,
ASSERT(device_type <= IXGB_MAX_PHY_DEV_TYPE);
/* Put the data in the MDIO Read/Write Data register */
IXGB_WRITE_REG(hw, MSRWD, (uint32_t)data);
IXGB_WRITE_REG(hw, MSRWD, (uint32_t) data);
/* Setup and write the address cycle command */
command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT) |
......@@ -742,8 +726,7 @@ ixgb_write_phy_reg(struct ixgb_hw *hw,
** from the CPU Write to the Ready bit assertion.
**************************************************************/
for (i = 0; i < 10; i++)
{
for (i = 0; i < 10; i++) {
usec_delay(10);
command = IXGB_READ_REG(hw, MSCA);
......@@ -769,8 +752,7 @@ ixgb_write_phy_reg(struct ixgb_hw *hw,
** from the CPU Write to the Ready bit assertion.
**************************************************************/
for (i = 0; i < 10; i++)
{
for (i = 0; i < 10; i++) {
usec_delay(10);
command = IXGB_READ_REG(hw, MSCA);
......@@ -784,7 +766,6 @@ ixgb_write_phy_reg(struct ixgb_hw *hw,
/* Operation is complete, return. */
}
/******************************************************************************
* Checks to see if the link status of the hardware has changed.
*
......@@ -817,7 +798,8 @@ ixgb_check_for_link(struct ixgb_hw *hw)
/* Anything else for 10 Gig?? */
}
boolean_t ixgb_check_for_bad_link(struct ixgb_hw *hw)
boolean_t
ixgb_check_for_bad_link(struct ixgb_hw *hw)
{
uint32_t newLFC, newRFC;
boolean_t bad_link_returncode = FALSE;
......@@ -836,6 +818,7 @@ boolean_t ixgb_check_for_bad_link(struct ixgb_hw *hw)
hw->lastRFC = newRFC;
return bad_link_returncode;
}
/******************************************************************************
* Clears all hardware statistics counters.
*
......@@ -849,7 +832,7 @@ ixgb_clear_hw_cntrs(struct ixgb_hw *hw)
DEBUGFUNC("ixgb_clear_hw_cntrs");
/* if we are stopped or resetting exit gracefully */
if(hw->adapter_stopped) {
if (hw->adapter_stopped) {
DEBUGOUT("Exiting because the adapter is stopped!!!\n");
return;
}
......@@ -917,7 +900,6 @@ ixgb_clear_hw_cntrs(struct ixgb_hw *hw)
return;
}
/******************************************************************************
* Turns on the software controllable LED
*
......@@ -950,7 +932,6 @@ ixgb_led_off(struct ixgb_hw *hw)
return;
}
/******************************************************************************
* Gets the current PCI bus type, speed, and width of the hardware
*
......@@ -992,8 +973,6 @@ ixgb_get_bus_info(struct ixgb_hw *hw)
return;
}
/******************************************************************************
* Tests a MAC address to ensure it is a valid Individual Address
*
......@@ -1001,12 +980,11 @@ ixgb_get_bus_info(struct ixgb_hw *hw)
*
*****************************************************************************/
boolean_t
mac_addr_valid(uint8_t *mac_addr)
mac_addr_valid(uint8_t * mac_addr)
{
boolean_t is_valid = TRUE;
DEBUGFUNC("mac_addr_valid");
/* Make sure it is not a multicast address */
if (IS_MULTICAST(mac_addr)) {
DEBUGOUT("MAC address is multicast\n");
......@@ -1021,11 +999,7 @@ mac_addr_valid(uint8_t *mac_addr)
else if (mac_addr[0] == 0 &&
mac_addr[1] == 0 &&
mac_addr[2] == 0 &&
mac_addr[3] == 0 &&
mac_addr[4] == 0 &&
mac_addr[5] == 0
)
{
mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) {
DEBUGOUT("MAC address is all zeros\n");
is_valid = FALSE;
}
......@@ -1039,28 +1013,28 @@ mac_addr_valid(uint8_t *mac_addr)
* hw - Struct containing variables accessed by shared code
*****************************************************************************/
boolean_t
ixgb_link_reset(struct ixgb_hw *hw)
ixgb_link_reset(struct ixgb_hw * hw)
{
boolean_t link_status = FALSE;
uint8_t wait_retries = MAX_RESET_ITERATIONS;
uint8_t lrst_retries = MAX_RESET_ITERATIONS;
do {
IXGB_WRITE_REG(hw, CTRL0, IXGB_READ_REG(hw, CTRL0) | IXGB_CTRL0_LRST);
IXGB_WRITE_REG(hw, CTRL0,
IXGB_READ_REG(hw, CTRL0) | IXGB_CTRL0_LRST);
do {
usec_delay(IXGB_DELAY_USECS_AFTER_LINK_RESET);
link_status = ((IXGB_READ_REG(hw, STATUS) & IXGB_STATUS_LU) &&
(IXGB_READ_REG(hw, XPCSS) & IXGB_XPCSS_ALIGN_STATUS)) ?
TRUE : FALSE;
} while (!link_status && -- wait_retries);
link_status =
((IXGB_READ_REG(hw, STATUS) & IXGB_STATUS_LU)
&& (IXGB_READ_REG(hw, XPCSS) &
IXGB_XPCSS_ALIGN_STATUS)) ? TRUE : FALSE;
} while (!link_status && --wait_retries);
} while (!link_status && --lrst_retries);
return link_status;
}
/******************************************************************************
* Resets the 10GbE optics module.
*
......@@ -1071,13 +1045,11 @@ ixgb_optics_reset(struct ixgb_hw *hw)
{
uint16_t mdio_reg;
ixgb_write_phy_reg( hw,
ixgb_write_phy_reg(hw,
TXN17401_PMA_PMD_CR1,
IXGB_PHY_ADDRESS,
TXN17401_PMA_PMD_DID,
TXN17401_PMA_PMD_CR1_RESET);
mdio_reg = ixgb_read_phy_reg( hw,
TXN17401_PMA_PMD_DID, TXN17401_PMA_PMD_CR1_RESET);
mdio_reg = ixgb_read_phy_reg(hw,
TXN17401_PMA_PMD_CR1,
IXGB_PHY_ADDRESS,
TXN17401_PMA_PMD_DID);
IXGB_PHY_ADDRESS, TXN17401_PMA_PMD_DID);
}
drivers/net/ixgb/ixgb_hw.h
View file @ ca247341
......@@ -77,7 +77,6 @@ typedef enum {
ixgb_bus_width_64
} ixgb_bus_width;
#define IXGB_ETH_LENGTH_OF_ADDRESS 6
#define IXGB_EEPROM_SIZE 64 /* Size in words */
......@@ -85,7 +84,6 @@ typedef enum {
#define SPEED_10000 10000
#define FULL_DUPLEX 2
#define IXGB_DELAY_BEFORE_RESET 10 /* allow 10ms after idling rx/tx units */
#define IXGB_DELAY_AFTER_RESET 1 /* allow 1ms after the reset */
#define IXGB_DELAY_AFTER_EE_RESET 10 /* allow 10ms after the EEPROM reset */
......@@ -224,7 +222,6 @@ typedef enum {
#define IXGB_XOFFTXC 0x021D0 /* XOFF Transmitted Count */
#define IXGB_RJC 0x021D8 /* Receive Jabber Count */
/* CTRL0 Bit Masks */
#define IXGB_CTRL0_LRST 0x00000008
#define IXGB_CTRL0_JFE 0x00000010
......@@ -245,14 +242,11 @@ typedef enum {
#define IXGB_CTRL1_EE_RST 0x00002000
/* STATUS Bit Masks */
#define IXGB_STATUS_LU 0x00000002
#define IXGB_STATUS_TXOFF 0x00000010
#define IXGB_STATUS_PCI_SPD 0x00000800
#define IXGB_STATUS_BUS64 0x00001000
#define IXGB_STATUS_PCIX_MODE 0x00002000
......@@ -261,14 +255,12 @@ typedef enum {
#define IXGB_STATUS_PCIX_SPD_100 0x00004000
#define IXGB_STATUS_PCIX_SPD_133 0x00008000
/* EECD Bit Masks */
#define IXGB_EECD_SK 0x00000001
#define IXGB_EECD_CS 0x00000002
#define IXGB_EECD_DI 0x00000004
#define IXGB_EECD_DO 0x00000008
/* MFS */
#define IXGB_MFS_SHIFT 16
......@@ -297,7 +289,6 @@ typedef enum {
#define IXGB_RCTL_CFF 0x00800000
#define IXGB_RCTL_SECRC 0x04000000
/* FCRTL Bit Masks */
#define IXGB_FCRTL_XONE 0x80000000
......@@ -323,7 +314,6 @@ typedef enum {
#define IXGB_TCTL_TXEN 0x00000002
#define IXGB_TCTL_TPDE 0x00000004
/* TXDCTL Bit Masks */
#define IXGB_TXDCTL_HTHRESH_SHIFT 8
......@@ -440,7 +430,6 @@ struct ixgb_context_desc {
#define IXGB_CONTEXT_DESC_TYPE 0x00000000
/* Filters */
#define IXGB_RAR_ENTRIES 16 /* Number of entries in Rx Address array */
#define IXGB_MC_TBL_SIZE 128 /* Multicast Filter Table (4096 bits) */
......@@ -461,7 +450,6 @@ struct ixgb_context_desc {
#define IS_MULTICAST(Address) \
(boolean_t)(((uint8_t *)(Address))[0] & ((uint8_t)0x01))
/*
* Check whether an address is broadcast.
*/
......@@ -501,7 +489,7 @@ struct ixgb_hw {
ixgb_mac_type mac_type; /* Identifier for MAC controller */
uint32_t max_frame_size; /* Maximum frame size supported */
uint32_t mc_filter_type; /* Multicast filter hash type */
uint32_t num_mc_addrs; /* Number of current Multicast addrs*/
uint32_t num_mc_addrs; /* Number of current Multicast addrs */
uint8_t curr_mac_addr[IXGB_ETH_LENGTH_OF_ADDRESS]; /* Individual address currently programmed in MAC */
uint32_t num_tx_desc; /* Number of Transmit descriptors */
uint32_t num_rx_desc; /* Number of Receive descriptors */
......@@ -511,7 +499,7 @@ struct ixgb_hw {
uint16_t device_id; /* device id from PCI configuration space */
uint16_t vendor_id; /* vendor id from PCI configuration space */
uint8_t revision_id; /* revision id from PCI configuration space */
uint16_t subsystem_vendor_id;/* subsystem vendor id from PCI configuration space */
uint16_t subsystem_vendor_id; /* subsystem vendor id from PCI configuration space */
uint16_t subsystem_id; /* subsystem id from PCI configuration space */
uint16_t pci_cmd_word; /* PCI command register id from PCI configuration space */
uint16_t eeprom[IXGB_EEPROM_SIZE]; /* EEPROM contents read at init time */
......@@ -592,40 +580,32 @@ extern void ixgb_check_for_link(struct ixgb_hw *hw);
extern boolean_t ixgb_check_for_bad_link(struct ixgb_hw *hw);
extern boolean_t ixgb_setup_fc(struct ixgb_hw *hw);
extern void ixgb_clear_hw_cntrs(struct ixgb_hw *hw);
extern boolean_t mac_addr_valid(uint8_t *mac_addr);
extern boolean_t mac_addr_valid(uint8_t * mac_addr);
extern uint16_t ixgb_read_phy_reg(struct ixgb_hw *hw,
uint32_t reg_addr,
uint32_t phy_addr,
uint32_t device_type);
uint32_t phy_addr, uint32_t device_type);
extern void ixgb_write_phy_reg(struct ixgb_hw *hw,
uint32_t reg_addr,
uint32_t phy_addr,
uint32_t device_type,
uint16_t data);
extern void ixgb_rar_set(struct ixgb_hw *hw,
uint8_t *addr,
uint32_t index);
uint32_t device_type, uint16_t data);
extern void ixgb_rar_set(struct ixgb_hw *hw, uint8_t * addr, uint32_t index);
/* Filters (multicast, vlan, receive) */
extern void ixgb_mc_addr_list_update(struct ixgb_hw *hw,
uint8_t * mc_addr_list,
uint32_t mc_addr_count,
uint32_t pad);
uint32_t mc_addr_count, uint32_t pad);
/* Vfta functions */
extern void ixgb_write_vfta(struct ixgb_hw *hw,
uint32_t offset,
uint32_t value);
uint32_t offset, uint32_t value);
extern void ixgb_clear_vfta(struct ixgb_hw *hw);
/* Access functions to eeprom data */
void ixgb_get_ee_mac_addr(struct ixgb_hw *hw, uint8_t *mac_addr);
void ixgb_get_ee_mac_addr(struct ixgb_hw *hw, uint8_t * mac_addr);
uint16_t ixgb_get_ee_compatibility(struct ixgb_hw *hw);
uint32_t ixgb_get_ee_pba_number(struct ixgb_hw *hw);
uint16_t ixgb_get_ee_init_ctrl_reg_1(struct ixgb_hw *hw);
......@@ -642,9 +622,6 @@ boolean_t ixgb_get_eeprom_data(struct ixgb_hw *hw);
/* Everything else */
void ixgb_led_on(struct ixgb_hw *hw);
void ixgb_led_off(struct ixgb_hw *hw);
void ixgb_write_pci_cfg(struct ixgb_hw *hw,
uint32_t reg,
uint16_t * value);
void ixgb_write_pci_cfg(struct ixgb_hw *hw, uint32_t reg, uint16_t * value);
#endif /* _IXGB_HW_H_ */
drivers/net/ixgb/ixgb_ids.h
View file @ ca247341
......@@ -25,7 +25,6 @@
Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
*******************************************************************************/
#ifndef _IXGB_IDS_H_
#define _IXGB_IDS_H_
......
drivers/net/ixgb/ixgb_main.c
View file @ ca247341
......@@ -93,7 +93,8 @@ static inline boolean_t ixgb_tso(struct ixgb_adapter *adapter,
static int ixgb_xmit_frame(struct sk_buff *skb, struct net_device *netdev);
static void ixgb_tx_timeout(struct net_device *netdev);
static void ixgb_tx_timeout_task(struct net_device *netdev);
static void ixgb_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp);
static void ixgb_vlan_rx_register(struct net_device *netdev,
struct vlan_group *grp);
static void ixgb_vlan_rx_add_vid(struct net_device *netdev, uint16_t vid);
static void ixgb_vlan_rx_kill_vid(struct net_device *netdev, uint16_t vid);
static void ixgb_restore_vlan(struct ixgb_adapter *adapter);
......@@ -115,7 +116,8 @@ static int ixgb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd);
static inline void ixgb_rx_checksum(struct ixgb_adapter *adapter,
struct ixgb_rx_desc *rx_desc,
struct sk_buff *skb);
static int ixgb_notify_reboot(struct notifier_block *, unsigned long event, void *ptr);
static int ixgb_notify_reboot(struct notifier_block *, unsigned long event,
void *ptr);
static int ixgb_suspend(struct pci_dev *pdev, uint32_t state);
struct notifier_block ixgb_notifier_reboot = {
......@@ -124,13 +126,11 @@ struct notifier_block ixgb_notifier_reboot = {
.priority = 0
};
/* Exported from other modules */
extern void ixgb_check_options(struct ixgb_adapter *adapter);
extern int ixgb_ethtool_ioctl(struct net_device *netdev, struct ifreq *ifr);
static struct pci_driver ixgb_driver = {
.name = ixgb_driver_name,
.id_table = ixgb_pci_tbl,
......@@ -171,7 +171,7 @@ ixgb_init_module(void)
printk(KERN_INFO "NAPI Enabled\n");
#endif
ret = pci_module_init(&ixgb_driver);
if(ret >= 0) {
if (ret >= 0) {
register_reboot_notifier(&ixgb_notifier_reboot);
}
return ret;
......@@ -211,7 +211,7 @@ ixgb_up(struct ixgb_adapter *adapter)
IXGB_DBG("ixgb_up\n");
if(request_irq(netdev->irq, &ixgb_intr, SA_SHIRQ | SA_SAMPLE_RANDOM,
if (request_irq(netdev->irq, &ixgb_intr, SA_SHIRQ | SA_SAMPLE_RANDOM,
netdev->name, netdev)) {
IXGB_DBG("%s: request_irq failed\n", netdev->name);
return -1;
......@@ -253,7 +253,7 @@ ixgb_down(struct ixgb_adapter *adapter, boolean_t kill_watchdog)
ixgb_irq_disable(adapter);
free_irq(netdev->irq, netdev);
if(kill_watchdog)
if (kill_watchdog)
del_timer_sync(&adapter->watchdog_timer);
adapter->link_speed = 0;
adapter->link_duplex = 0;
......@@ -278,7 +278,7 @@ ixgb_reset(struct ixgb_adapter *adapter)
IXGB_DBG("ixgb_reset\n");
ixgb_adapter_stop(&adapter->hw);
if(!ixgb_init_hw(&adapter->hw))
if (!ixgb_init_hw(&adapter->hw))
IXGB_DBG("ixgb_init_hw failed.\n");
}
......@@ -303,22 +303,22 @@ ixgb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
IXGB_DBG("ixgb_probe\n");
if((i = pci_enable_device(pdev))) {
if ((i = pci_enable_device(pdev))) {
IXGB_ERR("pci_enable_device failed\n");
return i;
}
if(!(i = pci_set_dma_mask(pdev, PCI_DMA_64BIT))) {
if (!(i = pci_set_dma_mask(pdev, PCI_DMA_64BIT))) {
pci_using_dac = 1;
} else {
if((i = pci_set_dma_mask(pdev, PCI_DMA_32BIT))) {
if ((i = pci_set_dma_mask(pdev, PCI_DMA_32BIT))) {
IXGB_ERR("No usable DMA configuration, aborting\n");
return i;
}
pci_using_dac = 0;
}
if((i = pci_request_regions(pdev, ixgb_driver_name))) {
if ((i = pci_request_regions(pdev, ixgb_driver_name))) {
IXGB_ERR("Failed to reserve PCI I/O and Memory resources.\n");
return i;
}
......@@ -326,8 +326,8 @@ ixgb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
pci_set_master(pdev);
/* alloc_etherdev clears the memory for us */
netdev = alloc_etherdev(sizeof(struct ixgb_adapter));
if(!netdev) {
netdev = alloc_etherdev(sizeof (struct ixgb_adapter));
if (!netdev) {
IXGB_ERR("Unable to allocate net_device struct\n");
goto err_alloc_etherdev;
}
......@@ -344,13 +344,13 @@ ixgb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
mmio_len = pci_resource_len(pdev, BAR_0);
adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
if(!adapter->hw.hw_addr)
if (!adapter->hw.hw_addr)
goto err_ioremap;
for(i = BAR_1; i <= BAR_5; i++) {
if(pci_resource_len(pdev, i) == 0)
for (i = BAR_1; i <= BAR_5; i++) {
if (pci_resource_len(pdev, i) == 0)
continue;
if(pci_resource_flags(pdev, i) & IORESOURCE_IO) {
if (pci_resource_flags(pdev, i) & IORESOURCE_IO) {
adapter->hw.io_base = pci_resource_start(pdev, i);
break;
}
......@@ -391,26 +391,24 @@ ixgb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
netdev->features = NETIF_F_SG |
NETIF_F_HW_CSUM |
NETIF_F_HW_VLAN_TX |
NETIF_F_HW_VLAN_RX |
NETIF_F_HW_VLAN_FILTER;
NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_FILTER;
#ifdef NETIF_F_TSO
netdev->features |= NETIF_F_TSO;
#endif
if(pci_using_dac)
if (pci_using_dac)
netdev->features |= NETIF_F_HIGHDMA;
/* make sure the EEPROM is good */
if(!ixgb_validate_eeprom_checksum(&adapter->hw)) {
if (!ixgb_validate_eeprom_checksum(&adapter->hw)) {
IXGB_DBG("Invalid EEPROM checksum.\n");
goto err_eeprom;
}
ixgb_get_ee_mac_addr(&adapter->hw, netdev->dev_addr);
if(!is_valid_ether_addr(netdev->dev_addr)) {
if (!is_valid_ether_addr(netdev->dev_addr)) {
IXGB_DBG("Invalid MAC address in EEPROM.\n");
goto err_eeprom;
}
......@@ -418,17 +416,16 @@ ixgb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
adapter->max_data_per_txd = IXGB_MAX_JUMBO_FRAME_SIZE;
adapter->part_num = ixgb_get_ee_pba_number(&adapter->hw);
init_timer(&adapter->watchdog_timer);
adapter->watchdog_timer.function = &ixgb_watchdog;
adapter->watchdog_timer.data = (unsigned long) adapter;
INIT_WORK(&adapter->tx_timeout_task,
(void (*)(void *))ixgb_tx_timeout_task, netdev);
(void (*)(void *)) ixgb_tx_timeout_task, netdev);
register_netdev(netdev);
memcpy(adapter->ifname, netdev->name, IFNAMSIZ);
adapter->ifname[IFNAMSIZ-1] = 0;
adapter->ifname[IFNAMSIZ - 1] = 0;
/* we're going to reset, so assume we have no link for now */
......@@ -444,12 +441,12 @@ ixgb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
cards_found++;
return 0;
err_eeprom:
err_eeprom:
iounmap(adapter->hw.hw_addr);
err_ioremap:
err_ioremap:
pci_release_regions(pdev);
kfree(netdev);
err_alloc_etherdev:
err_alloc_etherdev:
return -ENOMEM;
}
......@@ -477,7 +474,6 @@ ixgb_remove(struct pci_dev *pdev)
ixgb_identify_stop(adapter);
#endif
iounmap((void *) adapter->hw.hw_addr);
pci_release_regions(pdev);
......@@ -516,7 +512,7 @@ ixgb_sw_init(struct ixgb_adapter *adapter)
hw->max_frame_size = netdev->mtu + ENET_HEADER_SIZE + ENET_FCS_LENGTH;
if(hw->device_id == IXGB_DEVICE_ID_82597EX)
if (hw->device_id == IXGB_DEVICE_ID_82597EX)
hw->mac_type = ixgb_82597;
else {
/* should never have loaded on this device */
......@@ -551,27 +547,27 @@ ixgb_open(struct net_device *netdev)
/* allocate transmit descriptors */
if(ixgb_setup_tx_resources(adapter)) {
if (ixgb_setup_tx_resources(adapter)) {
IXGB_DBG("ixgb_open: failed ixgb_setup_tx_resources.\n");
goto err_setup_tx;
}
/* allocate receive descriptors and buffers */
if(ixgb_setup_rx_resources(adapter)) {
if (ixgb_setup_rx_resources(adapter)) {
IXGB_DBG("ixgb_open: failed ixgb_setup_rx_resources.\n");
goto err_setup_rx;
}
if(ixgb_up(adapter))
if (ixgb_up(adapter))
goto err_up;
return 0;
err_up:
err_up:
ixgb_free_rx_resources(adapter);
err_setup_rx:
err_setup_rx:
ixgb_free_tx_resources(adapter);
err_setup_tx:
err_setup_tx:
ixgb_reset(adapter);
return -EBUSY;
}
......@@ -619,19 +615,19 @@ ixgb_setup_tx_resources(struct ixgb_adapter *adapter)
IXGB_DBG("ixgb_setup_tx_resources\n");
size = sizeof(struct ixgb_buffer) * txdr->count;
size = sizeof (struct ixgb_buffer) * txdr->count;
txdr->buffer_info = kmalloc(size, GFP_KERNEL);
if(!txdr->buffer_info) {
if (!txdr->buffer_info) {
return -ENOMEM;
}
memset(txdr->buffer_info, 0, size);
/* round up to nearest 4K */
txdr->size = txdr->count * sizeof(struct ixgb_tx_desc);
txdr->size = txdr->count * sizeof (struct ixgb_tx_desc);
IXGB_ROUNDUP(txdr->size, 4096);
txdr->desc = pci_alloc_consistent(pdev, txdr->size, &txdr->dma);
if(!txdr->desc) {
if (!txdr->desc) {
kfree(txdr->buffer_info);
return -ENOMEM;
}
......@@ -658,7 +654,7 @@ static void
ixgb_configure_tx(struct ixgb_adapter *adapter)
{
uint32_t tctl;
uint32_t tdlen = adapter->tx_ring.count * sizeof(struct ixgb_tx_desc);
uint32_t tdlen = adapter->tx_ring.count * sizeof (struct ixgb_tx_desc);
uint64_t tdba = adapter->tx_ring.dma;
struct ixgb_hw *hw = &adapter->hw;
......@@ -717,20 +713,20 @@ ixgb_setup_rx_resources(struct ixgb_adapter *adapter)
IXGB_DBG("ixgb_setup_rx_resources.\n");
size = sizeof(struct ixgb_buffer) * rxdr->count;
size = sizeof (struct ixgb_buffer) * rxdr->count;
rxdr->buffer_info = kmalloc(size, GFP_KERNEL);
if(!rxdr->buffer_info) {
if (!rxdr->buffer_info) {
return -ENOMEM;
}
memset(rxdr->buffer_info, 0, size);
/* Round up to nearest 4K */
rxdr->size = rxdr->count * sizeof(struct ixgb_rx_desc);
rxdr->size = rxdr->count * sizeof (struct ixgb_rx_desc);
IXGB_ROUNDUP(rxdr->size, 4096);
rxdr->desc = pci_alloc_consistent(pdev, rxdr->size, &rxdr->dma);
if(!rxdr->desc) {
if (!rxdr->desc) {
IXGB_DBG("pci_alloc_consistent failed.\n");
kfree(rxdr->buffer_info);
return -ENOMEM;
......@@ -799,7 +795,7 @@ static void
ixgb_configure_rx(struct ixgb_adapter *adapter)
{
uint64_t rdba = adapter->rx_ring.dma;
uint32_t rdlen = adapter->rx_ring.count * sizeof(struct ixgb_rx_desc);
uint32_t rdlen = adapter->rx_ring.count * sizeof (struct ixgb_rx_desc);
struct ixgb_hw *hw = &adapter->hw;
uint32_t rctl;
uint32_t rxcsum;
......@@ -823,14 +819,14 @@ ixgb_configure_rx(struct ixgb_adapter *adapter)
IXGB_WRITE_REG(hw, RDH, 0);
IXGB_WRITE_REG(hw, RDT, 0);
{
{
uint32_t rxdctl;
/* burst 16 or burst when RXT0*/
/* burst 16 or burst when RXT0 */
rxdctl = RXDCTL_WTHRESH_DEFAULT << IXGB_RXDCTL_WTHRESH_SHIFT
| RXDCTL_HTHRESH_DEFAULT << IXGB_RXDCTL_HTHRESH_SHIFT
| RXDCTL_PTHRESH_DEFAULT << IXGB_RXDCTL_PTHRESH_SHIFT;
IXGB_WRITE_REG(hw, RXDCTL, rxdctl);
}
}
if (adapter->raidc) {
uint32_t raidc;
......@@ -852,26 +848,25 @@ ixgb_configure_rx(struct ixgb_adapter *adapter)
also known as 10000 interrupts / sec */
/* divide this by 2^3 (8) to get a register size count */
poll_threshold = ((adapter->rx_ring.count-1) >> 3);
poll_threshold = ((adapter->rx_ring.count - 1) >> 3);
/* poll at half of that size */
poll_threshold >>= 1;
/* make sure its not bigger than our max */
poll_threshold &= 0x3F;
raidc =
IXGB_RAIDC_EN | /* turn on raidc style moderation */
raidc = IXGB_RAIDC_EN | /* turn on raidc style moderation */
IXGB_RAIDC_RXT_GATE | /* don't interrupt with rxt0 while
in RBD mode (polling) */
(IXGB_RAIDC_POLL_DEFAULT << IXGB_RAIDC_POLL_SHIFT) |
/* this sets the regular "min interrupt delay" */
(adapter-> rx_int_delay << IXGB_RAIDC_DELAY_SHIFT) |
(adapter->rx_int_delay << IXGB_RAIDC_DELAY_SHIFT) |
poll_threshold;
IXGB_WRITE_REG(hw, RAIDC, raidc);
}
/* Enable Receive Checksum Offload for TCP and UDP */
if(adapter->rx_csum == TRUE) {
if (adapter->rx_csum == TRUE) {
rxcsum = IXGB_READ_REG(hw, RXCSUM);
rxcsum |= IXGB_RXCSUM_TUOFL;
IXGB_WRITE_REG(hw, RXCSUM, rxcsum);
......@@ -923,8 +918,8 @@ ixgb_clean_tx_ring(struct ixgb_adapter *adapter)
/* Free all the Tx ring sk_buffs */
for(i = 0; i < adapter->tx_ring.count; i++) {
if(adapter->tx_ring.buffer_info[i].skb) {
for (i = 0; i < adapter->tx_ring.count; i++) {
if (adapter->tx_ring.buffer_info[i].skb) {
pci_unmap_page(pdev,
adapter->tx_ring.buffer_info[i].dma,
......@@ -937,7 +932,7 @@ ixgb_clean_tx_ring(struct ixgb_adapter *adapter)
}
}
size = sizeof(struct ixgb_buffer) * adapter->tx_ring.count;
size = sizeof (struct ixgb_buffer) * adapter->tx_ring.count;
memset(adapter->tx_ring.buffer_info, 0, size);
/* Zero out the descriptor ring */
......@@ -992,8 +987,8 @@ ixgb_clean_rx_ring(struct ixgb_adapter *adapter)
/* Free all the Rx ring sk_buffs */
for(i = 0; i < adapter->rx_ring.count; i++) {
if(adapter->rx_ring.buffer_info[i].skb) {
for (i = 0; i < adapter->rx_ring.count; i++) {
if (adapter->rx_ring.buffer_info[i].skb) {
pci_unmap_single(pdev,
adapter->rx_ring.buffer_info[i].dma,
......@@ -1006,7 +1001,7 @@ ixgb_clean_rx_ring(struct ixgb_adapter *adapter)
}
}
size = sizeof(struct ixgb_buffer) * adapter->rx_ring.count;
size = sizeof (struct ixgb_buffer) * adapter->rx_ring.count;
memset(adapter->rx_ring.buffer_info, 0, size);
/* Zero out the descriptor ring */
......@@ -1045,16 +1040,16 @@ ixgb_set_multi(struct net_device *netdev)
rctl = IXGB_READ_REG(&adapter->hw, RCTL);
if(netdev->flags & IFF_PROMISC) {
if (netdev->flags & IFF_PROMISC) {
rctl |= (IXGB_RCTL_UPE | IXGB_RCTL_MPE);
} else if(netdev->flags & IFF_ALLMULTI) {
} else if (netdev->flags & IFF_ALLMULTI) {
rctl |= IXGB_RCTL_MPE;
rctl &= ~IXGB_RCTL_UPE;
} else {
rctl &= ~(IXGB_RCTL_UPE | IXGB_RCTL_MPE);
}
if(netdev->mc_count > IXGB_MAX_NUM_MULTICAST_ADDRESSES) {
if (netdev->mc_count > IXGB_MAX_NUM_MULTICAST_ADDRESSES) {
rctl |= IXGB_RCTL_MPE;
IXGB_WRITE_REG(hw, RCTL, rctl);
} else {
......@@ -1062,7 +1057,7 @@ ixgb_set_multi(struct net_device *netdev)
IXGB_WRITE_REG(hw, RCTL, rctl);
for(i = 0, mc_ptr = netdev->mc_list; mc_ptr;
for (i = 0, mc_ptr = netdev->mc_list; mc_ptr;
i++, mc_ptr = mc_ptr->next)
memcpy(&mta[i * IXGB_ETH_LENGTH_OF_ADDRESS],
mc_ptr->dmi_addr, IXGB_ETH_LENGTH_OF_ADDRESS);
......@@ -1089,8 +1084,8 @@ ixgb_watchdog(unsigned long data)
netif_stop_queue(netdev);
}
if(adapter->hw.link_up) {
if(!netif_carrier_ok(netdev)) {
if (adapter->hw.link_up) {
if (!netif_carrier_ok(netdev)) {
printk(KERN_INFO "ixgb: %s NIC Link is Up %d Mbps %s\n",
netdev->name, 10000, "Full Duplex");
adapter->link_speed = 10000;
......@@ -1099,8 +1094,9 @@ ixgb_watchdog(unsigned long data)
netif_wake_queue(netdev);
}
} else {
if(netif_carrier_ok(netdev)) {
printk(KERN_INFO "ixgb: %s NIC Link is Down\n", netdev->name);
if (netif_carrier_ok(netdev)) {
printk(KERN_INFO "ixgb: %s NIC Link is Down\n",
netdev->name);
adapter->link_speed = 0;
adapter->link_duplex = 0;
netif_carrier_off(netdev);
......@@ -1118,17 +1114,19 @@ ixgb_watchdog(unsigned long data)
struct ixgb_desc_ring *txdr = &adapter->tx_ring;
int i = txdr->next_to_clean;
if(txdr->buffer_info[i].dma &&
if (txdr->buffer_info[i].dma &&
time_after(jiffies, txdr->buffer_info[i].time_stamp + HZ) &&
!(IXGB_READ_REG(&adapter->hw, STATUS) & IXGB_STATUS_TXOFF)) {
IXGB_DBG("ixgb: %s Hung controller? Watchdog stopping queue\n",
!(IXGB_READ_REG(&adapter->hw, STATUS) & IXGB_STATUS_TXOFF))
{
IXGB_DBG
("ixgb: %s Hung controller? Watchdog stopping queue\n",
netdev->name);
netif_stop_queue(netdev);
}
}
/* generate an interrupt to force clean up of any stragglers */
IXGB_WRITE_REG (&adapter->hw, ICS, IXGB_INT_TXDW);
IXGB_WRITE_REG(&adapter->hw, ICS, IXGB_INT_TXDW);
/* Reset the timer */
mod_timer(&adapter->watchdog_timer, jiffies + 2 * HZ);
......@@ -1153,21 +1151,19 @@ ixgb_tso(struct ixgb_adapter *adapter, struct sk_buff *skb)
uint8_t ipcss, ipcso, tucss, tucso, hdr_len;
uint16_t ipcse, tucse, mss;
if(likely(skb_shinfo(skb)->tso_size)) {
if (likely(skb_shinfo(skb)->tso_size)) {
hdr_len = ((skb->h.raw - skb->data) + (skb->h.th->doff << 2));
mss = skb_shinfo(skb)->tso_size;
skb->nh.iph->tot_len = 0;
skb->nh.iph->check = 0;
skb->h.th->check = ~csum_tcpudp_magic(skb->nh.iph->saddr,
skb->nh.iph->daddr,
0,
IPPROTO_TCP,
0);
0, IPPROTO_TCP, 0);
ipcss = skb->nh.raw - skb->data;
ipcso = (void *)&(skb->nh.iph->check) - (void *)skb->data;
ipcso = (void *) &(skb->nh.iph->check) - (void *) skb->data;
ipcse = skb->h.raw - skb->data - 1;
tucss = skb->h.raw - skb->data;
tucso = (void *)&(skb->h.th->check) - (void *)skb->data;
tucso = (void *) &(skb->h.th->check) - (void *) skb->data;
tucse = 0;
i = adapter->tx_ring.next_to_use;
......@@ -1180,16 +1176,21 @@ ixgb_tso(struct ixgb_adapter *adapter, struct sk_buff *skb)
context_desc->tucso = tucso;
context_desc->tucse = cpu_to_le16(tucse);
context_desc->mss = cpu_to_le16(mss);
context_desc->hdr_len= hdr_len;
context_desc->hdr_len = hdr_len;
context_desc->status = 0;
context_desc->cmd_type_len = cpu_to_le32(
IXGB_CONTEXT_DESC_TYPE
| IXGB_CONTEXT_DESC_CMD_TSE
| IXGB_CONTEXT_DESC_CMD_IP
| IXGB_CONTEXT_DESC_CMD_TCP
| IXGB_CONTEXT_DESC_CMD_RS
| IXGB_CONTEXT_DESC_CMD_IDE
| (skb->len - (hdr_len)));
context_desc->cmd_type_len = cpu_to_le32(IXGB_CONTEXT_DESC_TYPE
|
IXGB_CONTEXT_DESC_CMD_TSE
|
IXGB_CONTEXT_DESC_CMD_IP
|
IXGB_CONTEXT_DESC_CMD_TCP
|
IXGB_CONTEXT_DESC_CMD_RS
|
IXGB_CONTEXT_DESC_CMD_IDE
| (skb->len -
(hdr_len)));
i = (i + 1) % adapter->tx_ring.count;
adapter->tx_ring.next_to_use = i;
......@@ -1200,7 +1201,6 @@ ixgb_tso(struct ixgb_adapter *adapter, struct sk_buff *skb)
return FALSE;
}
/**
* ixgb_tx_csum - prepare context descriptor for checksum offload.
*
......@@ -1215,7 +1215,7 @@ ixgb_tx_csum(struct ixgb_adapter *adapter, struct sk_buff *skb)
int i;
uint8_t css, cso;
if(likely(skb->ip_summed == CHECKSUM_HW)) {
if (likely(skb->ip_summed == CHECKSUM_HW)) {
css = skb->h.raw - skb->data;
cso = (skb->h.raw + skb->csum) - skb->data;
i = adapter->tx_ring.next_to_use;
......@@ -1225,14 +1225,13 @@ ixgb_tx_csum(struct ixgb_adapter *adapter, struct sk_buff *skb)
context_desc->tucso = cso;
context_desc->tucse = 0;
/* zero out any previously existing data in one instruction */
*(uint32_t *)&(context_desc->ipcss) = 0;
*(uint32_t *) & (context_desc->ipcss) = 0;
context_desc->status = 0;
context_desc->hdr_len = 0;
context_desc->mss = 0;
context_desc->cmd_type_len =
cpu_to_le32(IXGB_CONTEXT_DESC_TYPE
| IXGB_TX_DESC_CMD_RS
| IXGB_TX_DESC_CMD_IDE);
| IXGB_TX_DESC_CMD_RS | IXGB_TX_DESC_CMD_IDE);
i = (i + 1) % adapter->tx_ring.count;
adapter->tx_ring.next_to_use = i;
......@@ -1264,7 +1263,7 @@ ixgb_tx_map(struct ixgb_adapter *adapter, struct sk_buff *skb)
offset = 0;
while(len) {
while (len) {
i = (i + 1) % tx_ring->count;
size = min(len, adapter->max_data_per_txd);
tx_ring->buffer_info[i].length = size;
......@@ -1279,14 +1278,14 @@ ixgb_tx_map(struct ixgb_adapter *adapter, struct sk_buff *skb)
count++;
}
for(f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
struct skb_frag_struct *frag;
frag = &skb_shinfo(skb)->frags[f];
len = frag->size;
offset = 0;
while(len) {
while (len) {
i = (i + 1) % tx_ring->count;
size = min(len, adapter->max_data_per_txd);
tx_ring->buffer_info[i].length = size;
......@@ -1316,7 +1315,8 @@ ixgb_tx_map(struct ixgb_adapter *adapter, struct sk_buff *skb)
**/
static inline void
ixgb_tx_queue(struct ixgb_adapter *adapter, int count, int vlan_id,int tx_flags)
ixgb_tx_queue(struct ixgb_adapter *adapter, int count, int vlan_id,
int tx_flags)
{
struct ixgb_desc_ring *tx_ring = &adapter->tx_ring;
struct ixgb_tx_desc *tx_desc = NULL;
......@@ -1325,21 +1325,21 @@ ixgb_tx_queue(struct ixgb_adapter *adapter, int count, int vlan_id,int tx_flags)
uint8_t popts = 0;
int i;
if(tx_flags & IXGB_TX_FLAGS_TSO) {
if (tx_flags & IXGB_TX_FLAGS_TSO) {
cmd_type_len |= IXGB_TX_DESC_CMD_TSE;
popts |= (IXGB_TX_DESC_POPTS_IXSM | IXGB_TX_DESC_POPTS_TXSM);
}
if(tx_flags & IXGB_TX_FLAGS_CSUM)
if (tx_flags & IXGB_TX_FLAGS_CSUM)
popts |= IXGB_TX_DESC_POPTS_TXSM;
if(tx_flags & IXGB_TX_FLAGS_VLAN) {
if (tx_flags & IXGB_TX_FLAGS_VLAN) {
cmd_type_len |= IXGB_TX_DESC_CMD_VLE;
}
i = tx_ring->next_to_use;
while(count--) {
while (count--) {
tx_desc = IXGB_TX_DESC(*tx_ring, i);
tx_desc->buff_addr = cpu_to_le64(tx_ring->buffer_info[i].dma);
tx_desc->cmd_type_len =
......@@ -1384,35 +1384,35 @@ ixgb_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
count =
TXD_USE_COUNT(skb->len - skb->data_len, adapter->max_data_per_txd);
if(count == 0) {
if (count == 0) {
dev_kfree_skb_any(skb);
return 0;
}
for(f = 0; f < skb_shinfo(skb)->nr_frags; f++)
for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size,
adapter->max_data_per_txd);
#ifdef NETIF_F_TSO
if((skb_shinfo(skb)->tso_size) || (skb->ip_summed == CHECKSUM_HW))
if ((skb_shinfo(skb)->tso_size) || (skb->ip_summed == CHECKSUM_HW))
count++;
#else
if(skb->ip_summed == CHECKSUM_HW)
if (skb->ip_summed == CHECKSUM_HW)
count++;
#endif
if(unlikely(IXGB_DESC_UNUSED(&adapter->tx_ring) < count)) {
if (unlikely(IXGB_DESC_UNUSED(&adapter->tx_ring) < count)) {
netif_stop_queue(netdev);
return 1;
}
if(adapter->vlgrp && vlan_tx_tag_present(skb)) {
if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
tx_flags |= IXGB_TX_FLAGS_VLAN;
vlan_id = vlan_tx_tag_get(skb);
}
if(ixgb_tso(adapter, skb))
if (ixgb_tso(adapter, skb))
tx_flags |= IXGB_TX_FLAGS_TSO;
else if(ixgb_tx_csum(adapter, skb))
else if (ixgb_tx_csum(adapter, skb))
tx_flags |= IXGB_TX_FLAGS_CSUM;
count = ixgb_tx_map(adapter, skb);
......@@ -1491,44 +1491,45 @@ ixgb_change_mtu(struct net_device *netdev, int new_mtu)
IXGB_DBG("ixgb_change_mtu\n");
if((max_frame < IXGB_MIN_ENET_FRAME_SIZE_WITHOUT_FCS + ENET_FCS_LENGTH)
if ((max_frame < IXGB_MIN_ENET_FRAME_SIZE_WITHOUT_FCS + ENET_FCS_LENGTH)
|| (max_frame > IXGB_MAX_JUMBO_FRAME_SIZE + ENET_FCS_LENGTH)) {
IXGB_ERR("Invalid MTU setting\n");
return -EINVAL;
}
if((max_frame <= IXGB_MAX_ENET_FRAME_SIZE_WITHOUT_FCS + ENET_FCS_LENGTH)
if ((max_frame <=
IXGB_MAX_ENET_FRAME_SIZE_WITHOUT_FCS + ENET_FCS_LENGTH)
|| (max_frame <= IXGB_RXBUFFER_2048)) {
adapter->rx_buffer_len = IXGB_RXBUFFER_2048;
} else if(max_frame <= IXGB_RXBUFFER_4096) {
} else if (max_frame <= IXGB_RXBUFFER_4096) {
adapter->rx_buffer_len = IXGB_RXBUFFER_4096;
} else if(max_frame <= IXGB_RXBUFFER_8192) {
} else if (max_frame <= IXGB_RXBUFFER_8192) {
adapter->rx_buffer_len = IXGB_RXBUFFER_8192;
} else {
adapter->rx_buffer_len = IXGB_RXBUFFER_16384;
}
if(old_mtu != adapter->rx_buffer_len && netif_running(netdev)) {
if (old_mtu != adapter->rx_buffer_len && netif_running(netdev)) {
ixgb_down(adapter, TRUE);
ixgb_up(adapter);
}
if(adapter->hw.max_frame_size != max_frame) {
if (adapter->hw.max_frame_size != max_frame) {
struct ixgb_hw *hw = &adapter->hw;
adapter->hw.max_frame_size = max_frame;
IXGB_WRITE_REG(hw, MFS, hw->max_frame_size << IXGB_MFS_SHIFT);
if(hw->max_frame_size >
if (hw->max_frame_size >
IXGB_MAX_ENET_FRAME_SIZE_WITHOUT_FCS + ENET_FCS_LENGTH) {
uint32_t ctrl0 = IXGB_READ_REG(hw, CTRL0);
if(!(ctrl0 & IXGB_CTRL0_JFE)) {
if (!(ctrl0 & IXGB_CTRL0_JFE)) {
ctrl0 |= IXGB_CTRL0_JFE;
IXGB_WRITE_REG(hw, CTRL0, ctrl0);
}
......@@ -1648,8 +1649,10 @@ ixgb_update_stats(struct ixgb_adapter *adapter)
/* ignore RLEC as it reports errors for padded (<64bytes) frames
* with a length in the type/len field */
adapter->net_stats.rx_errors =
/* adapter->stats.rnbc + */ adapter->stats.crcerrs + adapter->stats.ruc +
adapter->stats.roc /*+ adapter->stats.rlec*/ + adapter->stats.icbc +
/* adapter->stats.rnbc + */ adapter->stats.crcerrs +
adapter->stats.ruc +
adapter->stats.roc /*+ adapter->stats.rlec */ +
adapter->stats.icbc +
adapter->stats.ecbc + adapter->stats.mpc;
adapter->net_stats.rx_dropped = adapter->stats.mpc;
......@@ -1697,7 +1700,7 @@ ixgb_irq_enable(struct ixgb_adapter *adapter)
{
IXGB_DBG("ixgb_irq_enable\n");
if(atomic_dec_and_test(&adapter->irq_sem)) {
if (atomic_dec_and_test(&adapter->irq_sem)) {
IXGB_WRITE_REG(&adapter->hw, IMS,
IXGB_INT_RXT0 | IXGB_INT_RXDMT0 | IXGB_INT_TXDW |
IXGB_INT_RXO | IXGB_INT_LSC);
......@@ -1728,11 +1731,11 @@ ixgb_intr(int irq, void *data, struct pt_regs *regs)
uint i = IXGB_MAX_INTR;
boolean_t rxdmt0 = FALSE;
while(i && (icr = IXGB_READ_REG(hw, ICR))) {
if(icr & IXGB_INT_RXDMT0)
while (i && (icr = IXGB_READ_REG(hw, ICR))) {
if (icr & IXGB_INT_RXDMT0)
rxdmt0 = TRUE;
if(unlikely(icr & (IXGB_INT_RXSEQ | IXGB_INT_LSC))) {
if (unlikely(icr & (IXGB_INT_RXSEQ | IXGB_INT_LSC))) {
mod_timer(&adapter->watchdog_timer, jiffies);
}
......@@ -1746,7 +1749,7 @@ ixgb_intr(int irq, void *data, struct pt_regs *regs)
/* if RAIDC:EN == 1 and ICR:RXDMT0 == 1, we need to
* set IMS:RXDMT0 to 1 to restart the RBD timer (POLL)
*/
if(rxdmt0 && adapter->raidc) {
if (rxdmt0 && adapter->raidc) {
/* ready the timer by writing the clear reg */
IXGB_WRITE_REG(hw, IMC, IXGB_INT_RXDMT0);
/* now restart it, h/w will decide if its necessary */
......@@ -1764,7 +1767,7 @@ ixgb_process_intr(struct net_device *netdev)
int i = IXGB_MAX_INTR;
int hasReceived = 0;
while(i && (icr = IXGB_READ_REG(&adapter->hw, ICR))) {
while (i && (icr = IXGB_READ_REG(&adapter->hw, ICR))) {
if (icr & IXGB_INT_RXT0)
hasReceived = 1;
......@@ -1796,24 +1799,24 @@ ixgb_clean_tx_irq(struct ixgb_adapter *adapter)
struct pci_dev *pdev = adapter->pdev;
int i = adapter->tx_ring.next_to_clean;
struct ixgb_tx_desc *tx_desc = IXGB_TX_DESC(*tx_ring, i);
while((tx_desc->status & IXGB_TX_DESC_STATUS_DD)) {
while ((tx_desc->status & IXGB_TX_DESC_STATUS_DD)) {
if (tx_desc->popts
& (IXGB_TX_DESC_POPTS_TXSM | IXGB_TX_DESC_POPTS_IXSM))
adapter->hw_csum_tx_good++;
if(tx_ring->buffer_info[i].dma) {
if (tx_ring->buffer_info[i].dma) {
pci_unmap_page(pdev, tx_ring->buffer_info[i].dma,
tx_ring->buffer_info[i].length,
PCI_DMA_TODEVICE);
tx_ring->buffer_info[i].dma = 0;
}
if(tx_ring->buffer_info[i].skb) {
if (tx_ring->buffer_info[i].skb) {
dev_kfree_skb_any(tx_ring->buffer_info[i].skb);
tx_ring->buffer_info[i].skb = NULL;
}
*(uint32_t *)&(tx_desc->status) = 0;
*(uint32_t *) & (tx_desc->status) = 0;
i = (i + 1) % tx_ring->count;
tx_desc = IXGB_TX_DESC(*tx_ring, i);
......@@ -1821,7 +1824,7 @@ ixgb_clean_tx_irq(struct ixgb_adapter *adapter)
tx_ring->next_to_clean = i;
if(netif_queue_stopped(netdev) && netif_carrier_ok(netdev) &&
if (netif_queue_stopped(netdev) && netif_carrier_ok(netdev) &&
(IXGB_DESC_UNUSED(tx_ring) > IXGB_TX_QUEUE_WAKE)) {
netif_wake_queue(netdev);
......@@ -1842,7 +1845,7 @@ ixgb_poll(struct net_device *netdev, int *budget)
int received = 0;
int rx_work_limit = *budget;
if(rx_work_limit > netdev->quota)
if (rx_work_limit > netdev->quota)
rx_work_limit = netdev->quota;
ixgb_process_intr(netdev);
......@@ -1850,8 +1853,8 @@ ixgb_poll(struct net_device *netdev, int *budget)
i = rx_ring->next_to_clean;
rx_desc = IXGB_RX_DESC(*rx_ring, i);
while((rx_desc->status & IXGB_RX_DESC_STATUS_DD)) {
if(--rx_work_limit < 0)
while ((rx_desc->status & IXGB_RX_DESC_STATUS_DD)) {
if (--rx_work_limit < 0)
goto not_done;
pci_unmap_single(pdev,
......@@ -1862,7 +1865,7 @@ ixgb_poll(struct net_device *netdev, int *budget)
skb = rx_ring->buffer_info[i].skb;
length = le16_to_cpu(rx_desc->length);
if(!(rx_desc->status & IXGB_RX_DESC_STATUS_EOP)) {
if (!(rx_desc->status & IXGB_RX_DESC_STATUS_EOP)) {
/* All receives must fit into a single buffer */
......@@ -1878,9 +1881,10 @@ ixgb_poll(struct net_device *netdev, int *budget)
continue;
}
if(rx_desc->
if (rx_desc->
errors & (IXGB_RX_DESC_ERRORS_CE | IXGB_RX_DESC_ERRORS_SE |
IXGB_RX_DESC_ERRORS_P | IXGB_RX_DESC_ERRORS_RXE)) {
IXGB_RX_DESC_ERRORS_P | IXGB_RX_DESC_ERRORS_RXE))
{
IXGB_DBG("Receive Errors Reported by Hardware-%x.\n",
rx_desc->errors);
......@@ -1900,9 +1904,12 @@ ixgb_poll(struct net_device *netdev, int *budget)
ixgb_rx_checksum(adapter, rx_desc, skb);
skb->protocol = eth_type_trans(skb, netdev);
if(adapter->vlgrp && (rx_desc->status & IXGB_RX_DESC_STATUS_VP)) {
if (adapter->vlgrp
&& (rx_desc->status & IXGB_RX_DESC_STATUS_VP)) {
vlan_hwaccel_rx(skb, adapter->vlgrp,
(rx_desc->special & IXGB_RX_DESC_SPECIAL_VLAN_MASK));
(rx_desc->
special &
IXGB_RX_DESC_SPECIAL_VLAN_MASK));
} else {
netif_receive_skb(skb);
}
......@@ -1917,7 +1924,7 @@ ixgb_poll(struct net_device *netdev, int *budget)
received++;
}
if(!received)
if (!received)
received = 1;
ixgb_alloc_rx_buffers(adapter);
......@@ -1932,7 +1939,7 @@ ixgb_poll(struct net_device *netdev, int *budget)
ixgb_irq_enable(adapter);
return 0;
not_done:
not_done:
ixgb_alloc_rx_buffers(adapter);
......@@ -1959,11 +1966,10 @@ ixgb_clean_rx_irq(struct ixgb_adapter *adapter)
uint32_t length;
int i;
i = rx_ring->next_to_clean;
rx_desc = IXGB_RX_DESC(*rx_ring, i);
while((rx_desc->status & IXGB_RX_DESC_STATUS_DD)) {
while ((rx_desc->status & IXGB_RX_DESC_STATUS_DD)) {
pci_unmap_single(pdev, rx_ring->buffer_info[i].dma,
rx_ring->buffer_info[i].length,
PCI_DMA_FROMDEVICE);
......@@ -1971,7 +1977,7 @@ ixgb_clean_rx_irq(struct ixgb_adapter *adapter)
skb = rx_ring->buffer_info[i].skb;
length = le16_to_cpu(rx_desc->length);
if(unlikely(!(rx_desc->status & IXGB_RX_DESC_STATUS_EOP))) {
if (unlikely(!(rx_desc->status & IXGB_RX_DESC_STATUS_EOP))) {
/* All receives must fit into a single buffer */
......@@ -1986,9 +1992,10 @@ ixgb_clean_rx_irq(struct ixgb_adapter *adapter)
continue;
}
if(unlikely(rx_desc->errors
& (IXGB_RX_DESC_ERRORS_CE | IXGB_RX_DESC_ERRORS_SE |
IXGB_RX_DESC_ERRORS_P | IXGB_RX_DESC_ERRORS_RXE))) {
if (unlikely(rx_desc->errors
& (IXGB_RX_DESC_ERRORS_CE | IXGB_RX_DESC_ERRORS_SE
| IXGB_RX_DESC_ERRORS_P |
IXGB_RX_DESC_ERRORS_RXE))) {
IXGB_DBG("Receive Errors Reported by Hardware-%x.\n",
rx_desc->errors);
......@@ -2008,9 +2015,12 @@ ixgb_clean_rx_irq(struct ixgb_adapter *adapter)
ixgb_rx_checksum(adapter, rx_desc, skb);
skb->protocol = eth_type_trans(skb, netdev);
if(adapter->vlgrp && (rx_desc->status & IXGB_RX_DESC_STATUS_VP)) {
if (adapter->vlgrp
&& (rx_desc->status & IXGB_RX_DESC_STATUS_VP)) {
vlan_hwaccel_rx(skb, adapter->vlgrp,
(rx_desc->special & IXGB_RX_DESC_SPECIAL_VLAN_MASK));
(rx_desc->
special &
IXGB_RX_DESC_SPECIAL_VLAN_MASK));
} else {
netif_rx(skb);
}
......@@ -2025,7 +2035,6 @@ ixgb_clean_rx_irq(struct ixgb_adapter *adapter)
rx_desc = IXGB_RX_DESC(*rx_ring, i);
} /* while */
rx_ring->next_to_clean = i;
ixgb_alloc_rx_buffers(adapter);
......@@ -2053,23 +2062,22 @@ ixgb_alloc_rx_buffers(struct ixgb_adapter *adapter)
reserve_len = 2;
i = rx_ring->next_to_use;
cleancount = IXGB_DESC_UNUSED (rx_ring);
cleancount = IXGB_DESC_UNUSED(rx_ring);
/* lessen this to 4 if we're
* in the midst of raidc and rbd is occuring
* because we don't want to delay returning buffers when low
*/
num_group_tail_writes
= adapter->raidc ? 4 : IXGB_RX_BUFFER_WRITE;
num_group_tail_writes = adapter->raidc ? 4 : IXGB_RX_BUFFER_WRITE;
/* leave one descriptor unused */
while(--cleancount > 0) {
while (--cleancount > 0) {
rx_desc = IXGB_RX_DESC(*rx_ring, i);
/* allocate a new one */
skb = dev_alloc_skb(adapter->rx_buffer_len + reserve_len);
if(unlikely(!skb)) {
if (unlikely(!skb)) {
/* better luck next time around */
IXGB_DBG("Could not allocate SKB\n");
break;
......@@ -2090,7 +2098,7 @@ ixgb_alloc_rx_buffers(struct ixgb_adapter *adapter)
rx_desc->buff_addr = cpu_to_le64(rx_ring->buffer_info[i].dma);
if(!(i % num_group_tail_writes)) {
if (!(i % num_group_tail_writes)) {
/* Force memory writes to complete before letting h/w
* know there are new descriptors to fetch. (Only
* applicable for weak-ordered memory model archs,
......@@ -2143,7 +2151,7 @@ ixgb_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
ixgb_irq_disable(adapter);
adapter->vlgrp = grp;
if(grp) {
if (grp) {
/* enable VLAN tag insert/strip */
ctrl = IXGB_READ_REG(&adapter->hw, CTRL0);
ctrl |= IXGB_CTRL0_VME;
......@@ -2203,12 +2211,12 @@ ixgb_vlan_rx_kill_vid(struct net_device *netdev, uint16_t vid)
ixgb_irq_disable(adapter);
if(adapter->vlgrp)
if (adapter->vlgrp)
adapter->vlgrp->vlan_devices[vid] = NULL;
ixgb_irq_enable(adapter);
/* remove VID from filter table*/
/* remove VID from filter table */
index = (vid >> 5) & 0x7F;
vfta = IXGB_READ_REG_ARRAY(&adapter->hw, VFTA, index);
......@@ -2225,10 +2233,10 @@ ixgb_restore_vlan(struct ixgb_adapter *adapter)
{
ixgb_vlan_rx_register(adapter->netdev, adapter->vlgrp);
if(adapter->vlgrp) {
if (adapter->vlgrp) {
uint16_t vid;
for(vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
if(!adapter->vlgrp->vlan_devices[vid])
for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
if (!adapter->vlgrp->vlan_devices[vid])
continue;
ixgb_vlan_rx_add_vid(adapter->netdev, vid);
}
......@@ -2244,13 +2252,12 @@ ixgb_restore_vlan(struct ixgb_adapter *adapter)
static inline void
ixgb_rx_checksum(struct ixgb_adapter *adapter,
struct ixgb_rx_desc *rx_desc,
struct sk_buff *skb)
struct ixgb_rx_desc *rx_desc, struct sk_buff *skb)
{
/* Ignore Checksum bit is set OR
* TCP Checksum has not been calculated
*/
if((rx_desc->status & IXGB_RX_DESC_STATUS_IXSM) ||
if ((rx_desc->status & IXGB_RX_DESC_STATUS_IXSM) ||
(!(rx_desc->status & IXGB_RX_DESC_STATUS_TCPCS))) {
skb->ip_summed = CHECKSUM_NONE;
return;
......@@ -2259,7 +2266,7 @@ ixgb_rx_checksum(struct ixgb_adapter *adapter,
/* At this point we know the hardware did the TCP checksum
* now look at the TCP checksum error bit
*/
if(rx_desc->errors & IXGB_RX_DESC_ERRORS_TCPE) {
if (rx_desc->errors & IXGB_RX_DESC_ERRORS_TCPE) {
/* let the stack verify checksum errors */
skb->ip_summed = CHECKSUM_NONE;
adapter->hw_csum_rx_error++;
......@@ -2278,7 +2285,7 @@ ixgb_rx_checksum(struct ixgb_adapter *adapter,
**/
void
ixgb_write_pci_cfg(struct ixgb_hw *hw, uint32_t reg, uint16_t *value)
ixgb_write_pci_cfg(struct ixgb_hw *hw, uint32_t reg, uint16_t * value)
{
struct ixgb_adapter *adapter = (struct ixgb_adapter *) hw->back;
......@@ -2296,19 +2303,18 @@ ixgb_notify_reboot(struct notifier_block *nb, unsigned long event, void *p)
{
struct pci_dev *pdev = NULL;
switch(event) {
switch (event) {
case SYS_DOWN:
case SYS_HALT:
case SYS_POWER_OFF:
pci_for_each_dev(pdev) {
if(pci_dev_driver(pdev) == &ixgb_driver)
if (pci_dev_driver(pdev) == &ixgb_driver)
ixgb_suspend(pdev, 3);
}
}
return NOTIFY_DONE;
}
/**
* ixgb_suspend - driver suspend function called from notify.
* @param pdev pci driver structure used for passing to
......@@ -2322,7 +2328,7 @@ ixgb_suspend(struct pci_dev *pdev, uint32_t state)
netif_device_detach(netdev);
if(netif_running(netdev))
if (netif_running(netdev))
ixgb_down(adapter, TRUE);
pci_save_state(pdev, adapter->pci_state);
......@@ -2334,5 +2340,4 @@ ixgb_suspend(struct pci_dev *pdev, uint32_t state)
return 0;
}
/* ixgb_main.c */
drivers/net/ixgb/ixgb_osdep.h
View file @ ca247341
......@@ -25,7 +25,6 @@
Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
*******************************************************************************/
/* glue for the OS independant part of ixgb
* includes register access macros
*/
......
drivers/net/ixgb/ixgb_param.c
View file @ ca247341
......@@ -132,7 +132,6 @@ IXGB_PARAM(RxIntDelay, "Receive Interrupt Delay");
IXGB_PARAM(RAIDC, "Disable or enable Receive Interrupt Moderation");
/* Receive Flow control high threshold (when we send a pause frame)
* (FCRTH)
*
......@@ -143,7 +142,6 @@ IXGB_PARAM(RAIDC, "Disable or enable Receive Interrupt Moderation");
IXGB_PARAM(RxFCHighThresh, "Receive Flow Control High Threshold");
/* Receive Flow control low threshold (when we send a resume frame)
* (FCRTL)
*
......@@ -155,7 +153,6 @@ IXGB_PARAM(RxFCHighThresh, "Receive Flow Control High Threshold");
IXGB_PARAM(RxFCLowThresh, "Receive Flow Control Low Threshold");
/* Flow control request timeout (how long to pause the link partner's tx)
* (PAP 15:0)
*
......@@ -166,7 +163,6 @@ IXGB_PARAM(RxFCLowThresh, "Receive Flow Control Low Threshold");
IXGB_PARAM(FCReqTimeout, "Flow Control Request Timeout");
/* Transmit Interrupt Delay in units of 0.8192 microseconds
*
* Valid Range: 0-65535
......@@ -213,7 +209,6 @@ IXGB_PARAM(IntDelayEnable, "Transmit Interrupt Delay Enable");
#define MIN_FCPAUSE 1
#define MAX_FCPAUSE 0xffff
struct ixgb_option {
enum { enable_option, range_option, list_option } type;
char *name;
......@@ -235,10 +230,9 @@ struct ixgb_option {
};
static int __devinit
ixgb_validate_option(int *value,
struct ixgb_option *opt)
ixgb_validate_option(int *value, struct ixgb_option *opt)
{
if(*value == OPTION_UNSET) {
if (*value == OPTION_UNSET) {
*value = opt->def;
return 0;
}
......@@ -255,7 +249,7 @@ ixgb_validate_option(int *value,
}
break;
case range_option:
if(*value >= opt->arg.r.min && *value <= opt->arg.r.max) {
if (*value >= opt->arg.r.min && *value <= opt->arg.r.max) {
printk(KERN_INFO "%s set to %i\n", opt->name, *value);
return 0;
}
......@@ -265,10 +259,10 @@ ixgb_validate_option(int *value,
int i;
struct ixgb_opt_list *ent;
for(i = 0; i < opt->arg.l.nr; i++) {
for (i = 0; i < opt->arg.l.nr; i++) {
ent = &opt->arg.l.p[i];
if(*value == ent->i) {
if(ent->str[0] != '\0')
if (*value == ent->i) {
if (ent->str[0] != '\0')
printk(KERN_INFO "%s",
ent->str);
return 0;
......@@ -305,8 +299,9 @@ ixgb_check_options(struct ixgb_adapter *adapter)
IXGB_DBG("ixgb_check_options\n");
if(board >= IXGB_MAX_NIC) {
printk(KERN_NOTICE "Warning: no configuration for board #%i\n", board);
if (board >= IXGB_MAX_NIC) {
printk(KERN_NOTICE "Warning: no configuration for board #%i\n",
board);
printk(KERN_NOTICE "Using defaults for all values\n");
board = IXGB_MAX_NIC;
}
......@@ -317,7 +312,7 @@ ixgb_check_options(struct ixgb_adapter *adapter)
.name = "Transmit Descriptors",
.err = "using default of " __MODULE_STRING(DEFAULT_TXD),
.def = DEFAULT_TXD,
.arg = {.r = {.min = MIN_TXD, .max = MAX_TXD}}
.arg = {.r = {.min = MIN_TXD,.max = MAX_TXD}}
};
struct ixgb_desc_ring *tx_ring = &adapter->tx_ring;
......@@ -332,7 +327,7 @@ ixgb_check_options(struct ixgb_adapter *adapter)
.name = "Receive Descriptors",
.err = "using default of " __MODULE_STRING(DEFAULT_RXD),
.def = DEFAULT_RXD,
.arg = {.r = {.min = MIN_RXD, .max = MAX_RXD}}
.arg = {.r = {.min = MIN_RXD,.max = MAX_RXD}}
};
struct ixgb_desc_ring *rx_ring = &adapter->rx_ring;
......@@ -381,7 +376,7 @@ ixgb_check_options(struct ixgb_adapter *adapter)
.name = "Flow Control",
.err = "reading default settings from EEPROM",
.def = ixgb_fc_full,
.arg = {.l = {.nr = LIST_LEN(fc_list), .p = fc_list}}
.arg = {.l = {.nr = LIST_LEN(fc_list),.p = fc_list}}
};
int fc = FlowControl[board];
......@@ -393,46 +388,50 @@ ixgb_check_options(struct ixgb_adapter *adapter)
struct ixgb_option fcrth = {
.type = range_option,
.name = "Rx Flow Control High Threshold",
.err = "using default of " __MODULE_STRING(DEFAULT_FCRTH),
.err =
"using default of " __MODULE_STRING(DEFAULT_FCRTH),
.def = DEFAULT_FCRTH,
.arg = {.r = {.min = MIN_FCRTH, .max = MAX_FCRTH}}
.arg = {.r = {.min = MIN_FCRTH,.max = MAX_FCRTH}}
};
adapter->hw.fc.high_water = RxFCHighThresh[board];
ixgb_validate_option(&adapter->hw.fc.high_water, &fcrth);
if ( !(adapter->hw.fc.type & ixgb_fc_rx_pause) )
printk (KERN_INFO
if (!(adapter->hw.fc.type & ixgb_fc_rx_pause))
printk(KERN_INFO
"Ignoring RxFCHighThresh when no RxFC\n");
}
{ /* Receive Flow Control Low Threshold */
struct ixgb_option fcrtl = {
.type = range_option,
.name = "Rx Flow Control Low Threshold",
.err = "using default of " __MODULE_STRING(DEFAULT_FCRTL),
.err =
"using default of " __MODULE_STRING(DEFAULT_FCRTL),
.def = DEFAULT_FCRTL,
.arg = {.r = {.min = MIN_FCRTL, .max = MAX_FCRTL}}
.arg = {.r = {.min = MIN_FCRTL,.max = MAX_FCRTL}}
};
adapter->hw.fc.low_water = RxFCLowThresh[board];
ixgb_validate_option(&adapter->hw.fc.low_water, &fcrtl);
if ( !(adapter->hw.fc.type & ixgb_fc_rx_pause) )
printk (KERN_INFO
if (!(adapter->hw.fc.type & ixgb_fc_rx_pause))
printk(KERN_INFO
"Ignoring RxFCLowThresh when no RxFC\n");
}
{ /* Flow Control Pause Time Request*/
{ /* Flow Control Pause Time Request */
struct ixgb_option fcpap = {
.type = range_option,
.name = "Flow Control Pause Time Request",
.err = "using default of "__MODULE_STRING(DEFAULT_FCPAUSE),
.err =
"using default of "
__MODULE_STRING(DEFAULT_FCPAUSE),
.def = DEFAULT_FCPAUSE,
.arg = {.r = {.min = MIN_FCPAUSE, .max = MAX_FCPAUSE}}
.arg = {.r = {.min = MIN_FCPAUSE,.max = MAX_FCPAUSE}}
};
int pause_time = FCReqTimeout[board];
ixgb_validate_option(&pause_time, &fcpap);
if ( !(adapter->hw.fc.type & ixgb_fc_rx_pause) )
printk (KERN_INFO
if (!(adapter->hw.fc.type & ixgb_fc_rx_pause))
printk(KERN_INFO
"Ignoring FCReqTimeout when no RxFC\n");
adapter->hw.fc.pause_time = pause_time;
}
......@@ -441,7 +440,7 @@ ixgb_check_options(struct ixgb_adapter *adapter)
/* high must be greater than low */
if (adapter->hw.fc.high_water < (adapter->hw.fc.low_water + 8)) {
/* set defaults */
printk (KERN_INFO
printk(KERN_INFO
"RxFCHighThresh must be >= (RxFCLowThresh + 8), "
"Using Defaults\n");
adapter->hw.fc.high_water = DEFAULT_FCRTH;
......@@ -452,9 +451,10 @@ ixgb_check_options(struct ixgb_adapter *adapter)
struct ixgb_option opt = {
.type = range_option,
.name = "Receive Interrupt Delay",
.err = "using default of " __MODULE_STRING(DEFAULT_RDTR),
.err =
"using default of " __MODULE_STRING(DEFAULT_RDTR),
.def = DEFAULT_RDTR,
.arg = {.r = {.min = MIN_RDTR, .max = MAX_RDTR}}
.arg = {.r = {.min = MIN_RDTR,.max = MAX_RDTR}}
};
adapter->rx_int_delay = RxIntDelay[board];
......@@ -477,9 +477,10 @@ ixgb_check_options(struct ixgb_adapter *adapter)
struct ixgb_option opt = {
.type = range_option,
.name = "Transmit Interrupt Delay",
.err = "using default of " __MODULE_STRING(DEFAULT_TIDV),
.err =
"using default of " __MODULE_STRING(DEFAULT_TIDV),
.def = DEFAULT_TIDV,
.arg = {.r = {.min = MIN_TIDV, .max = MAX_TIDV}}
.arg = {.r = {.min = MIN_TIDV,.max = MAX_TIDV}}
};
adapter->tx_int_delay = TxIntDelay[board];
......
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