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Commit cb55ff7a authored by Paolo Abeni's avatar Paolo Abeni
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Merge branch 'add-support-for-lan966x-is2-vcap' 

Horatiu Vultur says:

====================
Add support for lan966x IS2 VCAP

This provides initial support for lan966x for 'tc' traffic control
userspace tool and its flower filter. For this is required to use
the VCAP library.

Currently supported flower filter keys and actions are:
- source and destination MAC address keys
- trap action
====================

Link: https://lore.kernel.org/r/20221125095010.124458-1-horatiu.vultur@microchip.comSigned-off-by: default avatarPaolo Abeni <pabeni@redhat.com>
parents 7a168f56 4f141e36
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Showing with 3321 additions and 727 deletions
drivers/net/ethernet/microchip/lan966x/Kconfig
View file @ cb55ff7a
......@@ -8,5 +8,6 @@ config LAN966X_SWITCH
select PHYLINK
select PACKING
select PAGE_POOL
select VCAP
help
This driver supports the Lan966x network switch device.
drivers/net/ethernet/microchip/lan966x/Makefile
View file @ cb55ff7a
......@@ -12,4 +12,8 @@ lan966x-switch-objs := lan966x_main.o lan966x_phylink.o lan966x_port.o \
lan966x_tc.o lan966x_mqprio.o lan966x_taprio.o \
lan966x_tbf.o lan966x_cbs.o lan966x_ets.o \
lan966x_tc_matchall.o lan966x_police.o lan966x_mirror.o \
lan966x_xdp.o
lan966x_xdp.o lan966x_vcap_impl.o lan966x_vcap_ag_api.o \
lan966x_tc_flower.o lan966x_goto.o
# Provide include files
ccflags-y += -I$(srctree)/drivers/net/ethernet/microchip/vcap
drivers/net/ethernet/microchip/lan966x/lan966x_goto.c 0 → 100644
View file @ cb55ff7a
// SPDX-License-Identifier: GPL-2.0+
#include "lan966x_main.h"
#include "vcap_api_client.h"
int lan966x_goto_port_add(struct lan966x_port *port,
struct flow_action_entry *act,
unsigned long goto_id,
struct netlink_ext_ack *extack)
{
struct lan966x *lan966x = port->lan966x;
int err;
err = vcap_enable_lookups(lan966x->vcap_ctrl, port->dev,
act->chain_index, goto_id,
true);
if (err == -EFAULT) {
NL_SET_ERR_MSG_MOD(extack, "Unsupported goto chain");
return -EOPNOTSUPP;
}
if (err == -EADDRINUSE) {
NL_SET_ERR_MSG_MOD(extack, "VCAP already enabled");
return -EOPNOTSUPP;
}
if (err) {
NL_SET_ERR_MSG_MOD(extack, "Could not enable VCAP lookups");
return err;
}
port->tc.goto_id = goto_id;
return 0;
}
int lan966x_goto_port_del(struct lan966x_port *port,
unsigned long goto_id,
struct netlink_ext_ack *extack)
{
struct lan966x *lan966x = port->lan966x;
int err;
err = vcap_enable_lookups(lan966x->vcap_ctrl, port->dev, 0,
goto_id, false);
if (err) {
NL_SET_ERR_MSG_MOD(extack, "Could not disable VCAP lookups");
return err;
}
port->tc.goto_id = 0;
return 0;
}
drivers/net/ethernet/microchip/lan966x/lan966x_main.c
View file @ cb55ff7a
......@@ -47,6 +47,9 @@ static const struct lan966x_main_io_resource lan966x_main_iomap[] = {
{ TARGET_PTP, 0xc000, 1 }, /* 0xe200c000 */
{ TARGET_CHIP_TOP, 0x10000, 1 }, /* 0xe2010000 */
{ TARGET_REW, 0x14000, 1 }, /* 0xe2014000 */
{ TARGET_VCAP, 0x18000, 1 }, /* 0xe2018000 */
{ TARGET_VCAP + 1, 0x20000, 1 }, /* 0xe2020000 */
{ TARGET_VCAP + 2, 0x24000, 1 }, /* 0xe2024000 */
{ TARGET_SYS, 0x28000, 1 }, /* 0xe2028000 */
{ TARGET_DEV, 0x34000, 1 }, /* 0xe2034000 */
{ TARGET_DEV + 1, 0x38000, 1 }, /* 0xe2038000 */
......@@ -1157,8 +1160,15 @@ static int lan966x_probe(struct platform_device *pdev)
if (err)
goto cleanup_ptp;
err = lan966x_vcap_init(lan966x);
if (err)
goto cleanup_fdma;
return 0;
cleanup_fdma:
lan966x_fdma_deinit(lan966x);
cleanup_ptp:
lan966x_ptp_deinit(lan966x);
......@@ -1182,6 +1192,7 @@ static int lan966x_remove(struct platform_device *pdev)
struct lan966x *lan966x = platform_get_drvdata(pdev);
lan966x_taprio_deinit(lan966x);
lan966x_vcap_deinit(lan966x);
lan966x_fdma_deinit(lan966x);
lan966x_cleanup_ports(lan966x);
......
drivers/net/ethernet/microchip/lan966x/lan966x_main.h
View file @ cb55ff7a
......@@ -300,6 +300,9 @@ struct lan966x {
struct lan966x_port *mirror_monitor;
u32 mirror_mask[2];
u32 mirror_count;
/* vcap */
struct vcap_control *vcap_ctrl;
};
struct lan966x_port_config {
......@@ -317,6 +320,7 @@ struct lan966x_port_tc {
unsigned long police_id;
unsigned long ingress_mirror_id;
unsigned long egress_mirror_id;
unsigned long goto_id;
struct flow_stats police_stat;
struct flow_stats mirror_stat;
};
......@@ -582,6 +586,20 @@ static inline bool lan966x_xdp_port_present(struct lan966x_port *port)
return !!port->xdp_prog;
}
int lan966x_vcap_init(struct lan966x *lan966x);
void lan966x_vcap_deinit(struct lan966x *lan966x);
int lan966x_tc_flower(struct lan966x_port *port,
struct flow_cls_offload *f);
int lan966x_goto_port_add(struct lan966x_port *port,
struct flow_action_entry *act,
unsigned long goto_id,
struct netlink_ext_ack *extack);
int lan966x_goto_port_del(struct lan966x_port *port,
unsigned long goto_id,
struct netlink_ext_ack *extack);
static inline void __iomem *lan_addr(void __iomem *base[],
int id, int tinst, int tcnt,
int gbase, int ginst,
......
drivers/net/ethernet/microchip/lan966x/lan966x_regs.h
View file @ cb55ff7a
......@@ -25,6 +25,7 @@ enum lan966x_target {
TARGET_QSYS = 46,
TARGET_REW = 47,
TARGET_SYS = 52,
TARGET_VCAP = 61,
NUM_TARGETS = 66
};
......@@ -315,6 +316,69 @@ enum lan966x_target {
#define ANA_DROP_CFG_DROP_MC_SMAC_ENA_GET(x)\
FIELD_GET(ANA_DROP_CFG_DROP_MC_SMAC_ENA, x)
/* ANA:PORT:VCAP_S2_CFG */
#define ANA_VCAP_S2_CFG(g) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 28, 0, 1, 4)
#define ANA_VCAP_S2_CFG_ISDX_ENA GENMASK(20, 19)
#define ANA_VCAP_S2_CFG_ISDX_ENA_SET(x)\
FIELD_PREP(ANA_VCAP_S2_CFG_ISDX_ENA, x)
#define ANA_VCAP_S2_CFG_ISDX_ENA_GET(x)\
FIELD_GET(ANA_VCAP_S2_CFG_ISDX_ENA, x)
#define ANA_VCAP_S2_CFG_UDP_PAYLOAD_ENA GENMASK(18, 17)
#define ANA_VCAP_S2_CFG_UDP_PAYLOAD_ENA_SET(x)\
FIELD_PREP(ANA_VCAP_S2_CFG_UDP_PAYLOAD_ENA, x)
#define ANA_VCAP_S2_CFG_UDP_PAYLOAD_ENA_GET(x)\
FIELD_GET(ANA_VCAP_S2_CFG_UDP_PAYLOAD_ENA, x)
#define ANA_VCAP_S2_CFG_ETYPE_PAYLOAD_ENA GENMASK(16, 15)
#define ANA_VCAP_S2_CFG_ETYPE_PAYLOAD_ENA_SET(x)\
FIELD_PREP(ANA_VCAP_S2_CFG_ETYPE_PAYLOAD_ENA, x)
#define ANA_VCAP_S2_CFG_ETYPE_PAYLOAD_ENA_GET(x)\
FIELD_GET(ANA_VCAP_S2_CFG_ETYPE_PAYLOAD_ENA, x)
#define ANA_VCAP_S2_CFG_ENA BIT(14)
#define ANA_VCAP_S2_CFG_ENA_SET(x)\
FIELD_PREP(ANA_VCAP_S2_CFG_ENA, x)
#define ANA_VCAP_S2_CFG_ENA_GET(x)\
FIELD_GET(ANA_VCAP_S2_CFG_ENA, x)
#define ANA_VCAP_S2_CFG_SNAP_DIS GENMASK(13, 12)
#define ANA_VCAP_S2_CFG_SNAP_DIS_SET(x)\
FIELD_PREP(ANA_VCAP_S2_CFG_SNAP_DIS, x)
#define ANA_VCAP_S2_CFG_SNAP_DIS_GET(x)\
FIELD_GET(ANA_VCAP_S2_CFG_SNAP_DIS, x)
#define ANA_VCAP_S2_CFG_ARP_DIS GENMASK(11, 10)
#define ANA_VCAP_S2_CFG_ARP_DIS_SET(x)\
FIELD_PREP(ANA_VCAP_S2_CFG_ARP_DIS, x)
#define ANA_VCAP_S2_CFG_ARP_DIS_GET(x)\
FIELD_GET(ANA_VCAP_S2_CFG_ARP_DIS, x)
#define ANA_VCAP_S2_CFG_IP_TCPUDP_DIS GENMASK(9, 8)
#define ANA_VCAP_S2_CFG_IP_TCPUDP_DIS_SET(x)\
FIELD_PREP(ANA_VCAP_S2_CFG_IP_TCPUDP_DIS, x)
#define ANA_VCAP_S2_CFG_IP_TCPUDP_DIS_GET(x)\
FIELD_GET(ANA_VCAP_S2_CFG_IP_TCPUDP_DIS, x)
#define ANA_VCAP_S2_CFG_IP_OTHER_DIS GENMASK(7, 6)
#define ANA_VCAP_S2_CFG_IP_OTHER_DIS_SET(x)\
FIELD_PREP(ANA_VCAP_S2_CFG_IP_OTHER_DIS, x)
#define ANA_VCAP_S2_CFG_IP_OTHER_DIS_GET(x)\
FIELD_GET(ANA_VCAP_S2_CFG_IP_OTHER_DIS, x)
#define ANA_VCAP_S2_CFG_IP6_CFG GENMASK(5, 2)
#define ANA_VCAP_S2_CFG_IP6_CFG_SET(x)\
FIELD_PREP(ANA_VCAP_S2_CFG_IP6_CFG, x)
#define ANA_VCAP_S2_CFG_IP6_CFG_GET(x)\
FIELD_GET(ANA_VCAP_S2_CFG_IP6_CFG, x)
#define ANA_VCAP_S2_CFG_OAM_DIS GENMASK(1, 0)
#define ANA_VCAP_S2_CFG_OAM_DIS_SET(x)\
FIELD_PREP(ANA_VCAP_S2_CFG_OAM_DIS, x)
#define ANA_VCAP_S2_CFG_OAM_DIS_GET(x)\
FIELD_GET(ANA_VCAP_S2_CFG_OAM_DIS, x)
/* ANA:PORT:CPU_FWD_CFG */
#define ANA_CPU_FWD_CFG(g) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 96, 0, 1, 4)
......@@ -1506,4 +1570,136 @@ enum lan966x_target {
#define SYS_RAM_INIT_RAM_INIT_GET(x)\
FIELD_GET(SYS_RAM_INIT_RAM_INIT, x)
/* VCAP:VCAP_CORE_CFG:VCAP_UPDATE_CTRL */
#define VCAP_UPDATE_CTRL(t) __REG(TARGET_VCAP, t, 3, 0, 0, 1, 8, 0, 0, 1, 4)
#define VCAP_UPDATE_CTRL_UPDATE_CMD GENMASK(24, 22)
#define VCAP_UPDATE_CTRL_UPDATE_CMD_SET(x)\
FIELD_PREP(VCAP_UPDATE_CTRL_UPDATE_CMD, x)
#define VCAP_UPDATE_CTRL_UPDATE_CMD_GET(x)\
FIELD_GET(VCAP_UPDATE_CTRL_UPDATE_CMD, x)
#define VCAP_UPDATE_CTRL_UPDATE_ENTRY_DIS BIT(21)
#define VCAP_UPDATE_CTRL_UPDATE_ENTRY_DIS_SET(x)\
FIELD_PREP(VCAP_UPDATE_CTRL_UPDATE_ENTRY_DIS, x)
#define VCAP_UPDATE_CTRL_UPDATE_ENTRY_DIS_GET(x)\
FIELD_GET(VCAP_UPDATE_CTRL_UPDATE_ENTRY_DIS, x)
#define VCAP_UPDATE_CTRL_UPDATE_ACTION_DIS BIT(20)
#define VCAP_UPDATE_CTRL_UPDATE_ACTION_DIS_SET(x)\
FIELD_PREP(VCAP_UPDATE_CTRL_UPDATE_ACTION_DIS, x)
#define VCAP_UPDATE_CTRL_UPDATE_ACTION_DIS_GET(x)\
FIELD_GET(VCAP_UPDATE_CTRL_UPDATE_ACTION_DIS, x)
#define VCAP_UPDATE_CTRL_UPDATE_CNT_DIS BIT(19)
#define VCAP_UPDATE_CTRL_UPDATE_CNT_DIS_SET(x)\
FIELD_PREP(VCAP_UPDATE_CTRL_UPDATE_CNT_DIS, x)
#define VCAP_UPDATE_CTRL_UPDATE_CNT_DIS_GET(x)\
FIELD_GET(VCAP_UPDATE_CTRL_UPDATE_CNT_DIS, x)
#define VCAP_UPDATE_CTRL_UPDATE_ADDR GENMASK(18, 3)
#define VCAP_UPDATE_CTRL_UPDATE_ADDR_SET(x)\
FIELD_PREP(VCAP_UPDATE_CTRL_UPDATE_ADDR, x)
#define VCAP_UPDATE_CTRL_UPDATE_ADDR_GET(x)\
FIELD_GET(VCAP_UPDATE_CTRL_UPDATE_ADDR, x)
#define VCAP_UPDATE_CTRL_UPDATE_SHOT BIT(2)
#define VCAP_UPDATE_CTRL_UPDATE_SHOT_SET(x)\
FIELD_PREP(VCAP_UPDATE_CTRL_UPDATE_SHOT, x)
#define VCAP_UPDATE_CTRL_UPDATE_SHOT_GET(x)\
FIELD_GET(VCAP_UPDATE_CTRL_UPDATE_SHOT, x)
#define VCAP_UPDATE_CTRL_CLEAR_CACHE BIT(1)
#define VCAP_UPDATE_CTRL_CLEAR_CACHE_SET(x)\
FIELD_PREP(VCAP_UPDATE_CTRL_CLEAR_CACHE, x)
#define VCAP_UPDATE_CTRL_CLEAR_CACHE_GET(x)\
FIELD_GET(VCAP_UPDATE_CTRL_CLEAR_CACHE, x)
#define VCAP_UPDATE_CTRL_MV_TRAFFIC_IGN BIT(0)
#define VCAP_UPDATE_CTRL_MV_TRAFFIC_IGN_SET(x)\
FIELD_PREP(VCAP_UPDATE_CTRL_MV_TRAFFIC_IGN, x)
#define VCAP_UPDATE_CTRL_MV_TRAFFIC_IGN_GET(x)\
FIELD_GET(VCAP_UPDATE_CTRL_MV_TRAFFIC_IGN, x)
/* VCAP:VCAP_CORE_CFG:VCAP_MV_CFG */
#define VCAP_MV_CFG(t) __REG(TARGET_VCAP, t, 3, 0, 0, 1, 8, 4, 0, 1, 4)
#define VCAP_MV_CFG_MV_NUM_POS GENMASK(31, 16)
#define VCAP_MV_CFG_MV_NUM_POS_SET(x)\
FIELD_PREP(VCAP_MV_CFG_MV_NUM_POS, x)
#define VCAP_MV_CFG_MV_NUM_POS_GET(x)\
FIELD_GET(VCAP_MV_CFG_MV_NUM_POS, x)
#define VCAP_MV_CFG_MV_SIZE GENMASK(15, 0)
#define VCAP_MV_CFG_MV_SIZE_SET(x)\
FIELD_PREP(VCAP_MV_CFG_MV_SIZE, x)
#define VCAP_MV_CFG_MV_SIZE_GET(x)\
FIELD_GET(VCAP_MV_CFG_MV_SIZE, x)
/* VCAP:VCAP_CORE_CACHE:VCAP_ENTRY_DAT */
#define VCAP_ENTRY_DAT(t, r) __REG(TARGET_VCAP, t, 3, 8, 0, 1, 904, 0, r, 64, 4)
/* VCAP:VCAP_CORE_CACHE:VCAP_MASK_DAT */
#define VCAP_MASK_DAT(t, r) __REG(TARGET_VCAP, t, 3, 8, 0, 1, 904, 256, r, 64, 4)
/* VCAP:VCAP_CORE_CACHE:VCAP_ACTION_DAT */
#define VCAP_ACTION_DAT(t, r) __REG(TARGET_VCAP, t, 3, 8, 0, 1, 904, 512, r, 64, 4)
/* VCAP:VCAP_CORE_CACHE:VCAP_CNT_DAT */
#define VCAP_CNT_DAT(t, r) __REG(TARGET_VCAP, t, 3, 8, 0, 1, 904, 768, r, 32, 4)
/* VCAP:VCAP_CORE_CACHE:VCAP_CNT_FW_DAT */
#define VCAP_CNT_FW_DAT(t) __REG(TARGET_VCAP, t, 3, 8, 0, 1, 904, 896, 0, 1, 4)
/* VCAP:VCAP_CORE_CACHE:VCAP_TG_DAT */
#define VCAP_TG_DAT(t) __REG(TARGET_VCAP, t, 3, 8, 0, 1, 904, 900, 0, 1, 4)
/* VCAP:VCAP_CORE_MAP:VCAP_CORE_IDX */
#define VCAP_CORE_IDX(t) __REG(TARGET_VCAP, t, 3, 912, 0, 1, 8, 0, 0, 1, 4)
#define VCAP_CORE_IDX_CORE_IDX GENMASK(3, 0)
#define VCAP_CORE_IDX_CORE_IDX_SET(x)\
FIELD_PREP(VCAP_CORE_IDX_CORE_IDX, x)
#define VCAP_CORE_IDX_CORE_IDX_GET(x)\
FIELD_GET(VCAP_CORE_IDX_CORE_IDX, x)
/* VCAP:VCAP_CORE_MAP:VCAP_CORE_MAP */
#define VCAP_CORE_MAP(t) __REG(TARGET_VCAP, t, 3, 912, 0, 1, 8, 4, 0, 1, 4)
#define VCAP_CORE_MAP_CORE_MAP GENMASK(2, 0)
#define VCAP_CORE_MAP_CORE_MAP_SET(x)\
FIELD_PREP(VCAP_CORE_MAP_CORE_MAP, x)
#define VCAP_CORE_MAP_CORE_MAP_GET(x)\
FIELD_GET(VCAP_CORE_MAP_CORE_MAP, x)
/* VCAP:VCAP_CONST:VCAP_VER */
#define VCAP_VER(t) __REG(TARGET_VCAP, t, 3, 924, 0, 1, 40, 0, 0, 1, 4)
/* VCAP:VCAP_CONST:ENTRY_WIDTH */
#define VCAP_ENTRY_WIDTH(t) __REG(TARGET_VCAP, t, 3, 924, 0, 1, 40, 4, 0, 1, 4)
/* VCAP:VCAP_CONST:ENTRY_CNT */
#define VCAP_ENTRY_CNT(t) __REG(TARGET_VCAP, t, 3, 924, 0, 1, 40, 8, 0, 1, 4)
/* VCAP:VCAP_CONST:ENTRY_SWCNT */
#define VCAP_ENTRY_SWCNT(t) __REG(TARGET_VCAP, t, 3, 924, 0, 1, 40, 12, 0, 1, 4)
/* VCAP:VCAP_CONST:ENTRY_TG_WIDTH */
#define VCAP_ENTRY_TG_WIDTH(t) __REG(TARGET_VCAP, t, 3, 924, 0, 1, 40, 16, 0, 1, 4)
/* VCAP:VCAP_CONST:ACTION_DEF_CNT */
#define VCAP_ACTION_DEF_CNT(t) __REG(TARGET_VCAP, t, 3, 924, 0, 1, 40, 20, 0, 1, 4)
/* VCAP:VCAP_CONST:ACTION_WIDTH */
#define VCAP_ACTION_WIDTH(t) __REG(TARGET_VCAP, t, 3, 924, 0, 1, 40, 24, 0, 1, 4)
/* VCAP:VCAP_CONST:CNT_WIDTH */
#define VCAP_CNT_WIDTH(t) __REG(TARGET_VCAP, t, 3, 924, 0, 1, 40, 28, 0, 1, 4)
/* VCAP:VCAP_CONST:CORE_CNT */
#define VCAP_CORE_CNT(t) __REG(TARGET_VCAP, t, 3, 924, 0, 1, 40, 32, 0, 1, 4)
/* VCAP:VCAP_CONST:IF_CNT */
#define VCAP_IF_CNT(t) __REG(TARGET_VCAP, t, 3, 924, 0, 1, 40, 36, 0, 1, 4)
#endif /* _LAN966X_REGS_H_ */
drivers/net/ethernet/microchip/lan966x/lan966x_tc.c
View file @ cb55ff7a
......@@ -69,6 +69,8 @@ static int lan966x_tc_block_cb(enum tc_setup_type type, void *type_data,
switch (type) {
case TC_SETUP_CLSMATCHALL:
return lan966x_tc_matchall(port, type_data, ingress);
case TC_SETUP_CLSFLOWER:
return lan966x_tc_flower(port, type_data);
default:
return -EOPNOTSUPP;
}
......
drivers/net/ethernet/microchip/lan966x/lan966x_tc_flower.c 0 → 100644
View file @ cb55ff7a
// SPDX-License-Identifier: GPL-2.0+
#include "lan966x_main.h"
#include "vcap_api.h"
#include "vcap_api_client.h"
/* Controls how PORT_MASK is applied */
enum LAN966X_PORT_MASK_MODE {
LAN966X_PMM_NO_ACTION,
LAN966X_PMM_REPLACE,
LAN966X_PMM_FORWARDING,
LAN966X_PMM_REDIRECT,
};
struct lan966x_tc_flower_parse_usage {
struct flow_cls_offload *f;
struct flow_rule *frule;
struct vcap_rule *vrule;
unsigned int used_keys;
u16 l3_proto;
};
static int lan966x_tc_flower_handler_ethaddr_usage(struct lan966x_tc_flower_parse_usage *st)
{
enum vcap_key_field smac_key = VCAP_KF_L2_SMAC;
enum vcap_key_field dmac_key = VCAP_KF_L2_DMAC;
struct flow_match_eth_addrs match;
struct vcap_u48_key smac, dmac;
int err = 0;
flow_rule_match_eth_addrs(st->frule, &match);
if (!is_zero_ether_addr(match.mask->src)) {
vcap_netbytes_copy(smac.value, match.key->src, ETH_ALEN);
vcap_netbytes_copy(smac.mask, match.mask->src, ETH_ALEN);
err = vcap_rule_add_key_u48(st->vrule, smac_key, &smac);
if (err)
goto out;
}
if (!is_zero_ether_addr(match.mask->dst)) {
vcap_netbytes_copy(dmac.value, match.key->dst, ETH_ALEN);
vcap_netbytes_copy(dmac.mask, match.mask->dst, ETH_ALEN);
err = vcap_rule_add_key_u48(st->vrule, dmac_key, &dmac);
if (err)
goto out;
}
st->used_keys |= BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS);
return err;
out:
NL_SET_ERR_MSG_MOD(st->f->common.extack, "eth_addr parse error");
return err;
}
static int
(*lan966x_tc_flower_handlers_usage[])(struct lan966x_tc_flower_parse_usage *st) = {
[FLOW_DISSECTOR_KEY_ETH_ADDRS] = lan966x_tc_flower_handler_ethaddr_usage,
};
static int lan966x_tc_flower_use_dissectors(struct flow_cls_offload *f,
struct vcap_admin *admin,
struct vcap_rule *vrule,
u16 *l3_proto)
{
struct lan966x_tc_flower_parse_usage state = {
.f = f,
.vrule = vrule,
.l3_proto = ETH_P_ALL,
};
int err = 0;
state.frule = flow_cls_offload_flow_rule(f);
for (int i = 0; i < ARRAY_SIZE(lan966x_tc_flower_handlers_usage); ++i) {
if (!flow_rule_match_key(state.frule, i) ||
!lan966x_tc_flower_handlers_usage[i])
continue;
err = lan966x_tc_flower_handlers_usage[i](&state);
if (err)
return err;
}
if (l3_proto)
*l3_proto = state.l3_proto;
return err;
}
static int lan966x_tc_flower_action_check(struct vcap_control *vctrl,
struct flow_cls_offload *fco,
struct vcap_admin *admin)
{
struct flow_rule *rule = flow_cls_offload_flow_rule(fco);
struct flow_action_entry *actent, *last_actent = NULL;
struct flow_action *act = &rule->action;
u64 action_mask = 0;
int idx;
if (!flow_action_has_entries(act)) {
NL_SET_ERR_MSG_MOD(fco->common.extack, "No actions");
return -EINVAL;
}
if (!flow_action_basic_hw_stats_check(act, fco->common.extack))
return -EOPNOTSUPP;
flow_action_for_each(idx, actent, act) {
if (action_mask & BIT(actent->id)) {
NL_SET_ERR_MSG_MOD(fco->common.extack,
"More actions of the same type");
return -EINVAL;
}
action_mask |= BIT(actent->id);
last_actent = actent; /* Save last action for later check */
}
/* Check that last action is a goto */
if (last_actent->id != FLOW_ACTION_GOTO) {
NL_SET_ERR_MSG_MOD(fco->common.extack,
"Last action must be 'goto'");
return -EINVAL;
}
/* Check if the goto chain is in the next lookup */
if (!vcap_is_next_lookup(vctrl, fco->common.chain_index,
last_actent->chain_index)) {
NL_SET_ERR_MSG_MOD(fco->common.extack,
"Invalid goto chain");
return -EINVAL;
}
/* Catch unsupported combinations of actions */
if (action_mask & BIT(FLOW_ACTION_TRAP) &&
action_mask & BIT(FLOW_ACTION_ACCEPT)) {
NL_SET_ERR_MSG_MOD(fco->common.extack,
"Cannot combine pass and trap action");
return -EOPNOTSUPP;
}
return 0;
}
static int lan966x_tc_flower_add(struct lan966x_port *port,
struct flow_cls_offload *f,
struct vcap_admin *admin)
{
struct flow_action_entry *act;
u16 l3_proto = ETH_P_ALL;
struct flow_rule *frule;
struct vcap_rule *vrule;
int err, idx;
err = lan966x_tc_flower_action_check(port->lan966x->vcap_ctrl, f,
admin);
if (err)
return err;
vrule = vcap_alloc_rule(port->lan966x->vcap_ctrl, port->dev,
f->common.chain_index, VCAP_USER_TC,
f->common.prio, 0);
if (IS_ERR(vrule))
return PTR_ERR(vrule);
vrule->cookie = f->cookie;
err = lan966x_tc_flower_use_dissectors(f, admin, vrule, &l3_proto);
if (err)
goto out;
frule = flow_cls_offload_flow_rule(f);
flow_action_for_each(idx, act, &frule->action) {
switch (act->id) {
case FLOW_ACTION_TRAP:
err = vcap_rule_add_action_bit(vrule,
VCAP_AF_CPU_COPY_ENA,
VCAP_BIT_1);
err |= vcap_rule_add_action_u32(vrule,
VCAP_AF_CPU_QUEUE_NUM,
0);
err |= vcap_rule_add_action_u32(vrule, VCAP_AF_MASK_MODE,
LAN966X_PMM_REPLACE);
err |= vcap_set_rule_set_actionset(vrule,
VCAP_AFS_BASE_TYPE);
if (err)
goto out;
break;
case FLOW_ACTION_GOTO:
break;
default:
NL_SET_ERR_MSG_MOD(f->common.extack,
"Unsupported TC action");
err = -EOPNOTSUPP;
goto out;
}
}
err = vcap_val_rule(vrule, l3_proto);
if (err) {
vcap_set_tc_exterr(f, vrule);
goto out;
}
err = vcap_add_rule(vrule);
if (err)
NL_SET_ERR_MSG_MOD(f->common.extack,
"Could not add the filter");
out:
vcap_free_rule(vrule);
return err;
}
static int lan966x_tc_flower_del(struct lan966x_port *port,
struct flow_cls_offload *f,
struct vcap_admin *admin)
{
struct vcap_control *vctrl;
int err = -ENOENT, rule_id;
vctrl = port->lan966x->vcap_ctrl;
while (true) {
rule_id = vcap_lookup_rule_by_cookie(vctrl, f->cookie);
if (rule_id <= 0)
break;
err = vcap_del_rule(vctrl, port->dev, rule_id);
if (err) {
NL_SET_ERR_MSG_MOD(f->common.extack,
"Cannot delete rule");
break;
}
}
return err;
}
int lan966x_tc_flower(struct lan966x_port *port,
struct flow_cls_offload *f)
{
struct vcap_admin *admin;
admin = vcap_find_admin(port->lan966x->vcap_ctrl,
f->common.chain_index);
if (!admin) {
NL_SET_ERR_MSG_MOD(f->common.extack, "Invalid chain");
return -EINVAL;
}
switch (f->command) {
case FLOW_CLS_REPLACE:
return lan966x_tc_flower_add(port, f, admin);
case FLOW_CLS_DESTROY:
return lan966x_tc_flower_del(port, f, admin);
default:
return -EOPNOTSUPP;
}
return 0;
}
drivers/net/ethernet/microchip/lan966x/lan966x_tc_matchall.c
View file @ cb55ff7a
......@@ -23,6 +23,9 @@ static int lan966x_tc_matchall_add(struct lan966x_port *port,
case FLOW_ACTION_MIRRED:
return lan966x_mirror_port_add(port, act, f->cookie,
ingress, f->common.extack);
case FLOW_ACTION_GOTO:
return lan966x_goto_port_add(port, act, f->cookie,
f->common.extack);
default:
NL_SET_ERR_MSG_MOD(f->common.extack,
"Unsupported action");
......@@ -43,6 +46,9 @@ static int lan966x_tc_matchall_del(struct lan966x_port *port,
f->cookie == port->tc.egress_mirror_id) {
return lan966x_mirror_port_del(port, ingress,
f->common.extack);
} else if (f->cookie == port->tc.goto_id) {
return lan966x_goto_port_del(port, f->cookie,
f->common.extack);
} else {
NL_SET_ERR_MSG_MOD(f->common.extack,
"Unsupported action");
......
drivers/net/ethernet/microchip/lan966x/lan966x_vcap_ag_api.c 0 → 100644
View file @ cb55ff7a
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
#include <linux/types.h>
#include <linux/kernel.h>
#include "lan966x_vcap_ag_api.h"
/* keyfields */
static const struct vcap_field is2_mac_etype_keyfield[] = {
[VCAP_KF_TYPE] = {
.type = VCAP_FIELD_U32,
.offset = 0,
.width = 4,
},
[VCAP_KF_LOOKUP_FIRST_IS] = {
.type = VCAP_FIELD_BIT,
.offset = 4,
.width = 1,
},
[VCAP_KF_LOOKUP_PAG] = {
.type = VCAP_FIELD_U32,
.offset = 5,
.width = 8,
},
[VCAP_KF_IF_IGR_PORT_MASK] = {
.type = VCAP_FIELD_U32,
.offset = 13,
.width = 9,
},
[VCAP_KF_ISDX_GT0_IS] = {
.type = VCAP_FIELD_BIT,
.offset = 22,
.width = 1,
},
[VCAP_KF_HOST_MATCH] = {
.type = VCAP_FIELD_BIT,
.offset = 23,
.width = 1,
},
[VCAP_KF_L2_MC_IS] = {
.type = VCAP_FIELD_BIT,
.offset = 24,
.width = 1,
},
[VCAP_KF_L2_BC_IS] = {
.type = VCAP_FIELD_BIT,
.offset = 25,
.width = 1,
},
[VCAP_KF_8021Q_VLAN_TAGGED_IS] = {
.type = VCAP_FIELD_BIT,
.offset = 26,
.width = 1,
},
[VCAP_KF_8021Q_VID_CLS] = {
.type = VCAP_FIELD_U32,
.offset = 27,
.width = 12,
},
[VCAP_KF_8021Q_DEI_CLS] = {
.type = VCAP_FIELD_BIT,
.offset = 39,
.width = 1,
},
[VCAP_KF_8021Q_PCP_CLS] = {
.type = VCAP_FIELD_U32,
.offset = 40,
.width = 3,
},
[VCAP_KF_L2_DMAC] = {
.type = VCAP_FIELD_U48,
.offset = 43,
.width = 48,
},
[VCAP_KF_L2_SMAC] = {
.type = VCAP_FIELD_U48,
.offset = 91,
.width = 48,
},
[VCAP_KF_ETYPE] = {
.type = VCAP_FIELD_U32,
.offset = 139,
.width = 16,
},
[VCAP_KF_L2_FRM_TYPE] = {
.type = VCAP_FIELD_U32,
.offset = 155,
.width = 4,
},
[VCAP_KF_L2_PAYLOAD0] = {
.type = VCAP_FIELD_U32,
.offset = 159,
.width = 16,
},
[VCAP_KF_L2_PAYLOAD1] = {
.type = VCAP_FIELD_U32,
.offset = 175,
.width = 8,
},
[VCAP_KF_L2_PAYLOAD2] = {
.type = VCAP_FIELD_U32,
.offset = 183,
.width = 3,
},
};
static const struct vcap_field is2_mac_llc_keyfield[] = {
[VCAP_KF_TYPE] = {
.type = VCAP_FIELD_U32,
.offset = 0,
.width = 4,
},
[VCAP_KF_LOOKUP_FIRST_IS] = {
.type = VCAP_FIELD_BIT,
.offset = 4,
.width = 1,
},
[VCAP_KF_LOOKUP_PAG] = {
.type = VCAP_FIELD_U32,
.offset = 5,
.width = 8,
},
[VCAP_KF_IF_IGR_PORT_MASK] = {
.type = VCAP_FIELD_U32,
.offset = 13,
.width = 9,
},
[VCAP_KF_ISDX_GT0_IS] = {
.type = VCAP_FIELD_BIT,
.offset = 22,
.width = 1,
},
[VCAP_KF_HOST_MATCH] = {
.type = VCAP_FIELD_BIT,
.offset = 23,
.width = 1,
},
[VCAP_KF_L2_MC_IS] = {
.type = VCAP_FIELD_BIT,
.offset = 24,
.width = 1,
},
[VCAP_KF_L2_BC_IS] = {
.type = VCAP_FIELD_BIT,
.offset = 25,
.width = 1,
},
[VCAP_KF_8021Q_VLAN_TAGGED_IS] = {
.type = VCAP_FIELD_BIT,
.offset = 26,
.width = 1,
},
[VCAP_KF_8021Q_VID_CLS] = {
.type = VCAP_FIELD_U32,
.offset = 27,
.width = 12,
},
[VCAP_KF_8021Q_DEI_CLS] = {
.type = VCAP_FIELD_BIT,
.offset = 39,
.width = 1,
},
[VCAP_KF_8021Q_PCP_CLS] = {
.type = VCAP_FIELD_U32,
.offset = 40,
.width = 3,
},
[VCAP_KF_L2_DMAC] = {
.type = VCAP_FIELD_U48,
.offset = 43,
.width = 48,
},
[VCAP_KF_L2_SMAC] = {
.type = VCAP_FIELD_U48,
.offset = 91,
.width = 48,
},
[VCAP_KF_L2_LLC] = {
.type = VCAP_FIELD_U48,
.offset = 139,
.width = 40,
},
};
static const struct vcap_field is2_mac_snap_keyfield[] = {
[VCAP_KF_TYPE] = {
.type = VCAP_FIELD_U32,
.offset = 0,
.width = 4,
},
[VCAP_KF_LOOKUP_FIRST_IS] = {
.type = VCAP_FIELD_BIT,
.offset = 4,
.width = 1,
},
[VCAP_KF_LOOKUP_PAG] = {
.type = VCAP_FIELD_U32,
.offset = 5,
.width = 8,
},
[VCAP_KF_IF_IGR_PORT_MASK] = {
.type = VCAP_FIELD_U32,
.offset = 13,
.width = 9,
},
[VCAP_KF_ISDX_GT0_IS] = {
.type = VCAP_FIELD_BIT,
.offset = 22,
.width = 1,
},
[VCAP_KF_HOST_MATCH] = {
.type = VCAP_FIELD_BIT,
.offset = 23,
.width = 1,
},
[VCAP_KF_L2_MC_IS] = {
.type = VCAP_FIELD_BIT,
.offset = 24,
.width = 1,
},
[VCAP_KF_L2_BC_IS] = {
.type = VCAP_FIELD_BIT,
.offset = 25,
.width = 1,
},
[VCAP_KF_8021Q_VLAN_TAGGED_IS] = {
.type = VCAP_FIELD_BIT,
.offset = 26,
.width = 1,
},
[VCAP_KF_8021Q_VID_CLS] = {
.type = VCAP_FIELD_U32,
.offset = 27,
.width = 12,
},
[VCAP_KF_8021Q_DEI_CLS] = {
.type = VCAP_FIELD_BIT,
.offset = 39,
.width = 1,
},
[VCAP_KF_8021Q_PCP_CLS] = {
.type = VCAP_FIELD_U32,
.offset = 40,
.width = 3,
},
[VCAP_KF_L2_DMAC] = {
.type = VCAP_FIELD_U48,
.offset = 43,
.width = 48,
},
[VCAP_KF_L2_SMAC] = {
.type = VCAP_FIELD_U48,
.offset = 91,
.width = 48,
},
[VCAP_KF_L2_SNAP] = {
.type = VCAP_FIELD_U48,
.offset = 139,
.width = 40,
},
};
static const struct vcap_field is2_arp_keyfield[] = {
[VCAP_KF_TYPE] = {
.type = VCAP_FIELD_U32,
.offset = 0,
.width = 4,
},
[VCAP_KF_LOOKUP_FIRST_IS] = {
.type = VCAP_FIELD_BIT,
.offset = 4,
.width = 1,
},
[VCAP_KF_LOOKUP_PAG] = {
.type = VCAP_FIELD_U32,
.offset = 5,
.width = 8,
},
[VCAP_KF_IF_IGR_PORT_MASK] = {
.type = VCAP_FIELD_U32,
.offset = 13,
.width = 9,
},
[VCAP_KF_ISDX_GT0_IS] = {
.type = VCAP_FIELD_BIT,
.offset = 22,
.width = 1,
},
[VCAP_KF_HOST_MATCH] = {
.type = VCAP_FIELD_BIT,
.offset = 23,
.width = 1,
},
[VCAP_KF_L2_MC_IS] = {
.type = VCAP_FIELD_BIT,
.offset = 24,
.width = 1,
},
[VCAP_KF_L2_BC_IS] = {
.type = VCAP_FIELD_BIT,
.offset = 25,
.width = 1,
},
[VCAP_KF_8021Q_VLAN_TAGGED_IS] = {
.type = VCAP_FIELD_BIT,
.offset = 26,
.width = 1,
},
[VCAP_KF_8021Q_VID_CLS] = {
.type = VCAP_FIELD_U32,
.offset = 27,
.width = 12,
},
[VCAP_KF_8021Q_DEI_CLS] = {
.type = VCAP_FIELD_BIT,
.offset = 39,
.width = 1,
},
[VCAP_KF_8021Q_PCP_CLS] = {
.type = VCAP_FIELD_U32,
.offset = 40,
.width = 3,
},
[VCAP_KF_L2_SMAC] = {
.type = VCAP_FIELD_U48,
.offset = 43,
.width = 48,
},
[VCAP_KF_ARP_ADDR_SPACE_OK_IS] = {
.type = VCAP_FIELD_BIT,
.offset = 91,
.width = 1,
},
[VCAP_KF_ARP_PROTO_SPACE_OK_IS] = {
.type = VCAP_FIELD_BIT,
.offset = 92,
.width = 1,
},
[VCAP_KF_ARP_LEN_OK_IS] = {
.type = VCAP_FIELD_BIT,
.offset = 93,
.width = 1,
},
[VCAP_KF_ARP_TGT_MATCH_IS] = {
.type = VCAP_FIELD_BIT,
.offset = 94,
.width = 1,
},
[VCAP_KF_ARP_SENDER_MATCH_IS] = {
.type = VCAP_FIELD_BIT,
.offset = 95,
.width = 1,
},
[VCAP_KF_ARP_OPCODE_UNKNOWN_IS] = {
.type = VCAP_FIELD_BIT,
.offset = 96,
.width = 1,
},
[VCAP_KF_ARP_OPCODE] = {
.type = VCAP_FIELD_U32,
.offset = 97,
.width = 2,
},
[VCAP_KF_L3_IP4_DIP] = {
.type = VCAP_FIELD_U32,
.offset = 99,
.width = 32,
},
[VCAP_KF_L3_IP4_SIP] = {
.type = VCAP_FIELD_U32,
.offset = 131,
.width = 32,
},
[VCAP_KF_L3_DIP_EQ_SIP_IS] = {
.type = VCAP_FIELD_BIT,
.offset = 163,
.width = 1,
},
};
static const struct vcap_field is2_ip4_tcp_udp_keyfield[] = {
[VCAP_KF_TYPE] = {
.type = VCAP_FIELD_U32,
.offset = 0,
.width = 4,
},
[VCAP_KF_LOOKUP_FIRST_IS] = {
.type = VCAP_FIELD_BIT,
.offset = 4,
.width = 1,
},
[VCAP_KF_LOOKUP_PAG] = {
.type = VCAP_FIELD_U32,
.offset = 5,
.width = 8,
},
[VCAP_KF_IF_IGR_PORT_MASK] = {
.type = VCAP_FIELD_U32,
.offset = 13,
.width = 9,
},
[VCAP_KF_ISDX_GT0_IS] = {
.type = VCAP_FIELD_BIT,
.offset = 22,
.width = 1,
},
[VCAP_KF_HOST_MATCH] = {
.type = VCAP_FIELD_BIT,
.offset = 23,
.width = 1,
},
[VCAP_KF_L2_MC_IS] = {
.type = VCAP_FIELD_BIT,
.offset = 24,
.width = 1,
},
[VCAP_KF_L2_BC_IS] = {
.type = VCAP_FIELD_BIT,
.offset = 25,
.width = 1,
},
[VCAP_KF_8021Q_VLAN_TAGGED_IS] = {
.type = VCAP_FIELD_BIT,
.offset = 26,
.width = 1,
},
[VCAP_KF_8021Q_VID_CLS] = {
.type = VCAP_FIELD_U32,
.offset = 27,
.width = 12,
},
[VCAP_KF_8021Q_DEI_CLS] = {
.type = VCAP_FIELD_BIT,
.offset = 39,
.width = 1,
},
[VCAP_KF_8021Q_PCP_CLS] = {
.type = VCAP_FIELD_U32,
.offset = 40,
.width = 3,
},
[VCAP_KF_IP4_IS] = {
.type = VCAP_FIELD_BIT,
.offset = 43,
.width = 1,
},
[VCAP_KF_L3_FRAGMENT] = {
.type = VCAP_FIELD_BIT,
.offset = 44,
.width = 1,
},
[VCAP_KF_L3_FRAG_OFS_GT0] = {
.type = VCAP_FIELD_BIT,
.offset = 45,
.width = 1,
},
[VCAP_KF_L3_OPTIONS_IS] = {
.type = VCAP_FIELD_BIT,
.offset = 46,
.width = 1,
},
[VCAP_KF_L3_TTL_GT0] = {
.type = VCAP_FIELD_BIT,
.offset = 47,
.width = 1,
},
[VCAP_KF_L3_TOS] = {
.type = VCAP_FIELD_U32,
.offset = 48,
.width = 8,
},
[VCAP_KF_L3_IP4_DIP] = {
.type = VCAP_FIELD_U32,
.offset = 56,
.width = 32,
},
[VCAP_KF_L3_IP4_SIP] = {
.type = VCAP_FIELD_U32,
.offset = 88,
.width = 32,
},
[VCAP_KF_L3_DIP_EQ_SIP_IS] = {
.type = VCAP_FIELD_BIT,
.offset = 120,
.width = 1,
},
[VCAP_KF_TCP_IS] = {
.type = VCAP_FIELD_BIT,
.offset = 121,
.width = 1,
},
[VCAP_KF_L4_DPORT] = {
.type = VCAP_FIELD_U32,
.offset = 122,
.width = 16,
},
[VCAP_KF_L4_SPORT] = {
.type = VCAP_FIELD_U32,
.offset = 138,
.width = 16,
},
[VCAP_KF_L4_RNG] = {
.type = VCAP_FIELD_U32,
.offset = 154,
.width = 8,
},
[VCAP_KF_L4_SPORT_EQ_DPORT_IS] = {
.type = VCAP_FIELD_BIT,
.offset = 162,
.width = 1,
},
[VCAP_KF_L4_SEQUENCE_EQ0_IS] = {
.type = VCAP_FIELD_BIT,
.offset = 163,
.width = 1,
},
[VCAP_KF_L4_FIN] = {
.type = VCAP_FIELD_BIT,
.offset = 164,
.width = 1,
},
[VCAP_KF_L4_SYN] = {
.type = VCAP_FIELD_BIT,
.offset = 165,
.width = 1,
},
[VCAP_KF_L4_RST] = {
.type = VCAP_FIELD_BIT,
.offset = 166,
.width = 1,
},
[VCAP_KF_L4_PSH] = {
.type = VCAP_FIELD_BIT,
.offset = 167,
.width = 1,
},
[VCAP_KF_L4_ACK] = {
.type = VCAP_FIELD_BIT,
.offset = 168,
.width = 1,
},
[VCAP_KF_L4_URG] = {
.type = VCAP_FIELD_BIT,
.offset = 169,
.width = 1,
},
[VCAP_KF_L4_1588_DOM] = {
.type = VCAP_FIELD_U32,
.offset = 170,
.width = 8,
},
[VCAP_KF_L4_1588_VER] = {
.type = VCAP_FIELD_U32,
.offset = 178,
.width = 4,
},
};
static const struct vcap_field is2_ip4_other_keyfield[] = {
[VCAP_KF_TYPE] = {
.type = VCAP_FIELD_U32,
.offset = 0,
.width = 4,
},
[VCAP_KF_LOOKUP_FIRST_IS] = {
.type = VCAP_FIELD_BIT,
.offset = 4,
.width = 1,
},
[VCAP_KF_LOOKUP_PAG] = {
.type = VCAP_FIELD_U32,
.offset = 5,
.width = 8,
},
[VCAP_KF_IF_IGR_PORT_MASK] = {
.type = VCAP_FIELD_U32,
.offset = 13,
.width = 9,
},
[VCAP_KF_ISDX_GT0_IS] = {
.type = VCAP_FIELD_BIT,
.offset = 22,
.width = 1,
},
[VCAP_KF_HOST_MATCH] = {
.type = VCAP_FIELD_BIT,
.offset = 23,
.width = 1,
},
[VCAP_KF_L2_MC_IS] = {
.type = VCAP_FIELD_BIT,
.offset = 24,
.width = 1,
},
[VCAP_KF_L2_BC_IS] = {
.type = VCAP_FIELD_BIT,
.offset = 25,
.width = 1,
},
[VCAP_KF_8021Q_VLAN_TAGGED_IS] = {
.type = VCAP_FIELD_BIT,
.offset = 26,
.width = 1,
},
[VCAP_KF_8021Q_VID_CLS] = {
.type = VCAP_FIELD_U32,
.offset = 27,
.width = 12,
},
[VCAP_KF_8021Q_DEI_CLS] = {
.type = VCAP_FIELD_BIT,
.offset = 39,
.width = 1,
},
[VCAP_KF_8021Q_PCP_CLS] = {
.type = VCAP_FIELD_U32,
.offset = 40,
.width = 3,
},
[VCAP_KF_IP4_IS] = {
.type = VCAP_FIELD_BIT,
.offset = 43,
.width = 1,
},
[VCAP_KF_L3_FRAGMENT] = {
.type = VCAP_FIELD_BIT,
.offset = 44,
.width = 1,
},
[VCAP_KF_L3_FRAG_OFS_GT0] = {
.type = VCAP_FIELD_BIT,
.offset = 45,
.width = 1,
},
[VCAP_KF_L3_OPTIONS_IS] = {
.type = VCAP_FIELD_BIT,
.offset = 46,
.width = 1,
},
[VCAP_KF_L3_TTL_GT0] = {
.type = VCAP_FIELD_BIT,
.offset = 47,
.width = 1,
},
[VCAP_KF_L3_TOS] = {
.type = VCAP_FIELD_U32,
.offset = 48,
.width = 8,
},
[VCAP_KF_L3_IP4_DIP] = {
.type = VCAP_FIELD_U32,
.offset = 56,
.width = 32,
},
[VCAP_KF_L3_IP4_SIP] = {
.type = VCAP_FIELD_U32,
.offset = 88,
.width = 32,
},
[VCAP_KF_L3_DIP_EQ_SIP_IS] = {
.type = VCAP_FIELD_BIT,
.offset = 120,
.width = 1,
},
[VCAP_KF_L3_IP_PROTO] = {
.type = VCAP_FIELD_U32,
.offset = 121,
.width = 8,
},
[VCAP_KF_L3_PAYLOAD] = {
.type = VCAP_FIELD_U56,
.offset = 129,
.width = 56,
},
};
static const struct vcap_field is2_ip6_std_keyfield[] = {
[VCAP_KF_TYPE] = {
.type = VCAP_FIELD_U32,
.offset = 0,
.width = 4,
},
[VCAP_KF_LOOKUP_FIRST_IS] = {
.type = VCAP_FIELD_BIT,
.offset = 4,
.width = 1,
},
[VCAP_KF_LOOKUP_PAG] = {
.type = VCAP_FIELD_U32,
.offset = 5,
.width = 8,
},
[VCAP_KF_IF_IGR_PORT_MASK] = {
.type = VCAP_FIELD_U32,
.offset = 13,
.width = 9,
},
[VCAP_KF_ISDX_GT0_IS] = {
.type = VCAP_FIELD_BIT,
.offset = 22,
.width = 1,
},
[VCAP_KF_HOST_MATCH] = {
.type = VCAP_FIELD_BIT,
.offset = 23,
.width = 1,
},
[VCAP_KF_L2_MC_IS] = {
.type = VCAP_FIELD_BIT,
.offset = 24,
.width = 1,
},
[VCAP_KF_L2_BC_IS] = {
.type = VCAP_FIELD_BIT,
.offset = 25,
.width = 1,
},
[VCAP_KF_8021Q_VLAN_TAGGED_IS] = {
.type = VCAP_FIELD_BIT,
.offset = 26,
.width = 1,
},
[VCAP_KF_8021Q_VID_CLS] = {
.type = VCAP_FIELD_U32,
.offset = 27,
.width = 12,
},
[VCAP_KF_8021Q_DEI_CLS] = {
.type = VCAP_FIELD_BIT,
.offset = 39,
.width = 1,
},
[VCAP_KF_8021Q_PCP_CLS] = {
.type = VCAP_FIELD_U32,
.offset = 40,
.width = 3,
},
[VCAP_KF_L3_TTL_GT0] = {
.type = VCAP_FIELD_BIT,
.offset = 43,
.width = 1,
},
[VCAP_KF_L3_IP6_SIP] = {
.type = VCAP_FIELD_U128,
.offset = 44,
.width = 128,
},
[VCAP_KF_L3_IP_PROTO] = {
.type = VCAP_FIELD_U32,
.offset = 172,
.width = 8,
},
};
static const struct vcap_field is2_oam_keyfield[] = {
[VCAP_KF_TYPE] = {
.type = VCAP_FIELD_U32,
.offset = 0,
.width = 4,
},
[VCAP_KF_LOOKUP_FIRST_IS] = {
.type = VCAP_FIELD_BIT,
.offset = 4,
.width = 1,
},
[VCAP_KF_LOOKUP_PAG] = {
.type = VCAP_FIELD_U32,
.offset = 5,
.width = 8,
},
[VCAP_KF_IF_IGR_PORT_MASK] = {
.type = VCAP_FIELD_U32,
.offset = 13,
.width = 9,
},
[VCAP_KF_ISDX_GT0_IS] = {
.type = VCAP_FIELD_BIT,
.offset = 22,
.width = 1,
},
[VCAP_KF_HOST_MATCH] = {
.type = VCAP_FIELD_BIT,
.offset = 23,
.width = 1,
},
[VCAP_KF_L2_MC_IS] = {
.type = VCAP_FIELD_BIT,
.offset = 24,
.width = 1,
},
[VCAP_KF_L2_BC_IS] = {
.type = VCAP_FIELD_BIT,
.offset = 25,
.width = 1,
},
[VCAP_KF_8021Q_VLAN_TAGGED_IS] = {
.type = VCAP_FIELD_BIT,
.offset = 26,
.width = 1,
},
[VCAP_KF_8021Q_VID_CLS] = {
.type = VCAP_FIELD_U32,
.offset = 27,
.width = 12,
},
[VCAP_KF_8021Q_DEI_CLS] = {
.type = VCAP_FIELD_BIT,
.offset = 39,
.width = 1,
},
[VCAP_KF_8021Q_PCP_CLS] = {
.type = VCAP_FIELD_U32,
.offset = 40,
.width = 3,
},
[VCAP_KF_L2_DMAC] = {
.type = VCAP_FIELD_U48,
.offset = 43,
.width = 48,
},
[VCAP_KF_L2_SMAC] = {
.type = VCAP_FIELD_U48,
.offset = 91,
.width = 48,
},
[VCAP_KF_OAM_MEL_FLAGS] = {
.type = VCAP_FIELD_U32,
.offset = 139,
.width = 7,
},
[VCAP_KF_OAM_VER] = {
.type = VCAP_FIELD_U32,
.offset = 146,
.width = 5,
},
[VCAP_KF_OAM_OPCODE] = {
.type = VCAP_FIELD_U32,
.offset = 151,
.width = 8,
},
[VCAP_KF_OAM_FLAGS] = {
.type = VCAP_FIELD_U32,
.offset = 159,
.width = 8,
},
[VCAP_KF_OAM_MEPID] = {
.type = VCAP_FIELD_U32,
.offset = 167,
.width = 16,
},
[VCAP_KF_OAM_CCM_CNTS_EQ0] = {
.type = VCAP_FIELD_BIT,
.offset = 183,
.width = 1,
},
[VCAP_KF_OAM_Y1731_IS] = {
.type = VCAP_FIELD_BIT,
.offset = 184,
.width = 1,
},
[VCAP_KF_OAM_DETECTED] = {
.type = VCAP_FIELD_BIT,
.offset = 185,
.width = 1,
},
};
static const struct vcap_field is2_ip6_tcp_udp_keyfield[] = {
[VCAP_KF_TYPE] = {
.type = VCAP_FIELD_U32,
.offset = 0,
.width = 2,
},
[VCAP_KF_LOOKUP_FIRST_IS] = {
.type = VCAP_FIELD_BIT,
.offset = 2,
.width = 1,
},
[VCAP_KF_LOOKUP_PAG] = {
.type = VCAP_FIELD_U32,
.offset = 3,
.width = 8,
},
[VCAP_KF_IF_IGR_PORT_MASK] = {
.type = VCAP_FIELD_U32,
.offset = 11,
.width = 9,
},
[VCAP_KF_ISDX_GT0_IS] = {
.type = VCAP_FIELD_BIT,
.offset = 20,
.width = 1,
},
[VCAP_KF_HOST_MATCH] = {
.type = VCAP_FIELD_BIT,
.offset = 21,
.width = 1,
},
[VCAP_KF_L2_MC_IS] = {
.type = VCAP_FIELD_BIT,
.offset = 22,
.width = 1,
},
[VCAP_KF_L2_BC_IS] = {
.type = VCAP_FIELD_BIT,
.offset = 23,
.width = 1,
},
[VCAP_KF_8021Q_VLAN_TAGGED_IS] = {
.type = VCAP_FIELD_BIT,
.offset = 24,
.width = 1,
},
[VCAP_KF_8021Q_VID_CLS] = {
.type = VCAP_FIELD_U32,
.offset = 25,
.width = 12,
},
[VCAP_KF_8021Q_DEI_CLS] = {
.type = VCAP_FIELD_BIT,
.offset = 37,
.width = 1,
},
[VCAP_KF_8021Q_PCP_CLS] = {
.type = VCAP_FIELD_U32,
.offset = 38,
.width = 3,
},
[VCAP_KF_L3_TTL_GT0] = {
.type = VCAP_FIELD_BIT,
.offset = 41,
.width = 1,
},
[VCAP_KF_L3_TOS] = {
.type = VCAP_FIELD_U32,
.offset = 42,
.width = 8,
},
[VCAP_KF_L3_IP6_DIP] = {
.type = VCAP_FIELD_U128,
.offset = 50,
.width = 128,
},
[VCAP_KF_L3_IP6_SIP] = {
.type = VCAP_FIELD_U128,
.offset = 178,
.width = 128,
},
[VCAP_KF_L3_DIP_EQ_SIP_IS] = {
.type = VCAP_FIELD_BIT,
.offset = 306,
.width = 1,
},
[VCAP_KF_TCP_IS] = {
.type = VCAP_FIELD_BIT,
.offset = 307,
.width = 1,
},
[VCAP_KF_L4_DPORT] = {
.type = VCAP_FIELD_U32,
.offset = 308,
.width = 16,
},
[VCAP_KF_L4_SPORT] = {
.type = VCAP_FIELD_U32,
.offset = 324,
.width = 16,
},
[VCAP_KF_L4_RNG] = {
.type = VCAP_FIELD_U32,
.offset = 340,
.width = 8,
},
[VCAP_KF_L4_SPORT_EQ_DPORT_IS] = {
.type = VCAP_FIELD_BIT,
.offset = 348,
.width = 1,
},
[VCAP_KF_L4_SEQUENCE_EQ0_IS] = {
.type = VCAP_FIELD_BIT,
.offset = 349,
.width = 1,
},
[VCAP_KF_L4_FIN] = {
.type = VCAP_FIELD_BIT,
.offset = 350,
.width = 1,
},
[VCAP_KF_L4_SYN] = {
.type = VCAP_FIELD_BIT,
.offset = 351,
.width = 1,
},
[VCAP_KF_L4_RST] = {
.type = VCAP_FIELD_BIT,
.offset = 352,
.width = 1,
},
[VCAP_KF_L4_PSH] = {
.type = VCAP_FIELD_BIT,
.offset = 353,
.width = 1,
},
[VCAP_KF_L4_ACK] = {
.type = VCAP_FIELD_BIT,
.offset = 354,
.width = 1,
},
[VCAP_KF_L4_URG] = {
.type = VCAP_FIELD_BIT,
.offset = 355,
.width = 1,
},
[VCAP_KF_L4_1588_DOM] = {
.type = VCAP_FIELD_U32,
.offset = 356,
.width = 8,
},
[VCAP_KF_L4_1588_VER] = {
.type = VCAP_FIELD_U32,
.offset = 364,
.width = 4,
},
};
static const struct vcap_field is2_ip6_other_keyfield[] = {
[VCAP_KF_TYPE] = {
.type = VCAP_FIELD_U32,
.offset = 0,
.width = 2,
},
[VCAP_KF_LOOKUP_FIRST_IS] = {
.type = VCAP_FIELD_BIT,
.offset = 2,
.width = 1,
},
[VCAP_KF_LOOKUP_PAG] = {
.type = VCAP_FIELD_U32,
.offset = 3,
.width = 8,
},
[VCAP_KF_IF_IGR_PORT_MASK] = {
.type = VCAP_FIELD_U32,
.offset = 11,
.width = 9,
},
[VCAP_KF_ISDX_GT0_IS] = {
.type = VCAP_FIELD_BIT,
.offset = 20,
.width = 1,
},
[VCAP_KF_HOST_MATCH] = {
.type = VCAP_FIELD_BIT,
.offset = 21,
.width = 1,
},
[VCAP_KF_L2_MC_IS] = {
.type = VCAP_FIELD_BIT,
.offset = 22,
.width = 1,
},
[VCAP_KF_L2_BC_IS] = {
.type = VCAP_FIELD_BIT,
.offset = 23,
.width = 1,
},
[VCAP_KF_8021Q_VLAN_TAGGED_IS] = {
.type = VCAP_FIELD_BIT,
.offset = 24,
.width = 1,
},
[VCAP_KF_8021Q_VID_CLS] = {
.type = VCAP_FIELD_U32,
.offset = 25,
.width = 12,
},
[VCAP_KF_8021Q_DEI_CLS] = {
.type = VCAP_FIELD_BIT,
.offset = 37,
.width = 1,
},
[VCAP_KF_8021Q_PCP_CLS] = {
.type = VCAP_FIELD_U32,
.offset = 38,
.width = 3,
},
[VCAP_KF_L3_TTL_GT0] = {
.type = VCAP_FIELD_BIT,
.offset = 41,
.width = 1,
},
[VCAP_KF_L3_TOS] = {
.type = VCAP_FIELD_U32,
.offset = 42,
.width = 8,
},
[VCAP_KF_L3_IP6_DIP] = {
.type = VCAP_FIELD_U128,
.offset = 50,
.width = 128,
},
[VCAP_KF_L3_IP6_SIP] = {
.type = VCAP_FIELD_U128,
.offset = 178,
.width = 128,
},
[VCAP_KF_L3_DIP_EQ_SIP_IS] = {
.type = VCAP_FIELD_BIT,
.offset = 306,
.width = 1,
},
[VCAP_KF_L3_IP_PROTO] = {
.type = VCAP_FIELD_U32,
.offset = 307,
.width = 8,
},
[VCAP_KF_L3_PAYLOAD] = {
.type = VCAP_FIELD_U56,
.offset = 315,
.width = 56,
},
};
static const struct vcap_field is2_smac_sip4_keyfield[] = {
[VCAP_KF_IF_IGR_PORT] = {
.type = VCAP_FIELD_U32,
.offset = 0,
.width = 4,
},
[VCAP_KF_L2_SMAC] = {
.type = VCAP_FIELD_U48,
.offset = 4,
.width = 48,
},
[VCAP_KF_L3_IP4_SIP] = {
.type = VCAP_FIELD_U32,
.offset = 52,
.width = 32,
},
};
static const struct vcap_field is2_smac_sip6_keyfield[] = {
[VCAP_KF_TYPE] = {
.type = VCAP_FIELD_U32,
.offset = 0,
.width = 4,
},
[VCAP_KF_IF_IGR_PORT] = {
.type = VCAP_FIELD_U32,
.offset = 4,
.width = 4,
},
[VCAP_KF_L2_SMAC] = {
.type = VCAP_FIELD_U48,
.offset = 8,
.width = 48,
},
[VCAP_KF_L3_IP6_SIP] = {
.type = VCAP_FIELD_U128,
.offset = 56,
.width = 128,
},
};
/* keyfield_set */
static const struct vcap_set is2_keyfield_set[] = {
[VCAP_KFS_MAC_ETYPE] = {
.type_id = 0,
.sw_per_item = 2,
.sw_cnt = 2,
},
[VCAP_KFS_MAC_LLC] = {
.type_id = 1,
.sw_per_item = 2,
.sw_cnt = 2,
},
[VCAP_KFS_MAC_SNAP] = {
.type_id = 2,
.sw_per_item = 2,
.sw_cnt = 2,
},
[VCAP_KFS_ARP] = {
.type_id = 3,
.sw_per_item = 2,
.sw_cnt = 2,
},
[VCAP_KFS_IP4_TCP_UDP] = {
.type_id = 4,
.sw_per_item = 2,
.sw_cnt = 2,
},
[VCAP_KFS_IP4_OTHER] = {
.type_id = 5,
.sw_per_item = 2,
.sw_cnt = 2,
},
[VCAP_KFS_IP6_STD] = {
.type_id = 6,
.sw_per_item = 2,
.sw_cnt = 2,
},
[VCAP_KFS_OAM] = {
.type_id = 7,
.sw_per_item = 2,
.sw_cnt = 2,
},
[VCAP_KFS_IP6_TCP_UDP] = {
.type_id = 0,
.sw_per_item = 4,
.sw_cnt = 1,
},
[VCAP_KFS_IP6_OTHER] = {
.type_id = 1,
.sw_per_item = 4,
.sw_cnt = 1,
},
[VCAP_KFS_SMAC_SIP4] = {
.type_id = -1,
.sw_per_item = 1,
.sw_cnt = 4,
},
[VCAP_KFS_SMAC_SIP6] = {
.type_id = 8,
.sw_per_item = 2,
.sw_cnt = 2,
},
};
/* keyfield_set map */
static const struct vcap_field *is2_keyfield_set_map[] = {
[VCAP_KFS_MAC_ETYPE] = is2_mac_etype_keyfield,
[VCAP_KFS_MAC_LLC] = is2_mac_llc_keyfield,
[VCAP_KFS_MAC_SNAP] = is2_mac_snap_keyfield,
[VCAP_KFS_ARP] = is2_arp_keyfield,
[VCAP_KFS_IP4_TCP_UDP] = is2_ip4_tcp_udp_keyfield,
[VCAP_KFS_IP4_OTHER] = is2_ip4_other_keyfield,
[VCAP_KFS_IP6_STD] = is2_ip6_std_keyfield,
[VCAP_KFS_OAM] = is2_oam_keyfield,
[VCAP_KFS_IP6_TCP_UDP] = is2_ip6_tcp_udp_keyfield,
[VCAP_KFS_IP6_OTHER] = is2_ip6_other_keyfield,
[VCAP_KFS_SMAC_SIP4] = is2_smac_sip4_keyfield,
[VCAP_KFS_SMAC_SIP6] = is2_smac_sip6_keyfield,
};
/* keyfield_set map sizes */
static int is2_keyfield_set_map_size[] = {
[VCAP_KFS_MAC_ETYPE] = ARRAY_SIZE(is2_mac_etype_keyfield),
[VCAP_KFS_MAC_LLC] = ARRAY_SIZE(is2_mac_llc_keyfield),
[VCAP_KFS_MAC_SNAP] = ARRAY_SIZE(is2_mac_snap_keyfield),
[VCAP_KFS_ARP] = ARRAY_SIZE(is2_arp_keyfield),
[VCAP_KFS_IP4_TCP_UDP] = ARRAY_SIZE(is2_ip4_tcp_udp_keyfield),
[VCAP_KFS_IP4_OTHER] = ARRAY_SIZE(is2_ip4_other_keyfield),
[VCAP_KFS_IP6_STD] = ARRAY_SIZE(is2_ip6_std_keyfield),
[VCAP_KFS_OAM] = ARRAY_SIZE(is2_oam_keyfield),
[VCAP_KFS_IP6_TCP_UDP] = ARRAY_SIZE(is2_ip6_tcp_udp_keyfield),
[VCAP_KFS_IP6_OTHER] = ARRAY_SIZE(is2_ip6_other_keyfield),
[VCAP_KFS_SMAC_SIP4] = ARRAY_SIZE(is2_smac_sip4_keyfield),
[VCAP_KFS_SMAC_SIP6] = ARRAY_SIZE(is2_smac_sip6_keyfield),
};
/* actionfields */
static const struct vcap_field is2_base_type_actionfield[] = {
[VCAP_AF_HIT_ME_ONCE] = {
.type = VCAP_FIELD_BIT,
.offset = 0,
.width = 1,
},
[VCAP_AF_CPU_COPY_ENA] = {
.type = VCAP_FIELD_BIT,
.offset = 1,
.width = 1,
},
[VCAP_AF_CPU_QUEUE_NUM] = {
.type = VCAP_FIELD_U32,
.offset = 2,
.width = 3,
},
[VCAP_AF_MASK_MODE] = {
.type = VCAP_FIELD_U32,
.offset = 5,
.width = 2,
},
[VCAP_AF_MIRROR_ENA] = {
.type = VCAP_FIELD_BIT,
.offset = 7,
.width = 1,
},
[VCAP_AF_LRN_DIS] = {
.type = VCAP_FIELD_BIT,
.offset = 8,
.width = 1,
},
[VCAP_AF_POLICE_ENA] = {
.type = VCAP_FIELD_BIT,
.offset = 9,
.width = 1,
},
[VCAP_AF_POLICE_IDX] = {
.type = VCAP_FIELD_U32,
.offset = 10,
.width = 9,
},
[VCAP_AF_POLICE_VCAP_ONLY] = {
.type = VCAP_FIELD_BIT,
.offset = 19,
.width = 1,
},
[VCAP_AF_PORT_MASK] = {
.type = VCAP_FIELD_U32,
.offset = 20,
.width = 8,
},
[VCAP_AF_REW_OP] = {
.type = VCAP_FIELD_U32,
.offset = 28,
.width = 16,
},
[VCAP_AF_ISDX_ENA] = {
.type = VCAP_FIELD_BIT,
.offset = 44,
.width = 1,
},
[VCAP_AF_ACL_ID] = {
.type = VCAP_FIELD_U32,
.offset = 45,
.width = 6,
},
};
static const struct vcap_field is2_smac_sip_actionfield[] = {
[VCAP_AF_CPU_COPY_ENA] = {
.type = VCAP_FIELD_BIT,
.offset = 0,
.width = 1,
},
[VCAP_AF_CPU_QUEUE_NUM] = {
.type = VCAP_FIELD_U32,
.offset = 1,
.width = 3,
},
[VCAP_AF_FWD_KILL_ENA] = {
.type = VCAP_FIELD_BIT,
.offset = 4,
.width = 1,
},
[VCAP_AF_HOST_MATCH] = {
.type = VCAP_FIELD_BIT,
.offset = 5,
.width = 1,
},
};
/* actionfield_set */
static const struct vcap_set is2_actionfield_set[] = {
[VCAP_AFS_BASE_TYPE] = {
.type_id = -1,
.sw_per_item = 2,
.sw_cnt = 2,
},
[VCAP_AFS_SMAC_SIP] = {
.type_id = -1,
.sw_per_item = 1,
.sw_cnt = 4,
},
};
/* actionfield_set map */
static const struct vcap_field *is2_actionfield_set_map[] = {
[VCAP_AFS_BASE_TYPE] = is2_base_type_actionfield,
[VCAP_AFS_SMAC_SIP] = is2_smac_sip_actionfield,
};
/* actionfield_set map size */
static int is2_actionfield_set_map_size[] = {
[VCAP_AFS_BASE_TYPE] = ARRAY_SIZE(is2_base_type_actionfield),
[VCAP_AFS_SMAC_SIP] = ARRAY_SIZE(is2_smac_sip_actionfield),
};
/* Type Groups */
static const struct vcap_typegroup is2_x4_keyfield_set_typegroups[] = {
{
.offset = 0,
.width = 3,
.value = 4,
},
{
.offset = 96,
.width = 1,
.value = 0,
},
{
.offset = 192,
.width = 2,
.value = 0,
},
{
.offset = 288,
.width = 1,
.value = 0,
},
{}
};
static const struct vcap_typegroup is2_x2_keyfield_set_typegroups[] = {
{
.offset = 0,
.width = 2,
.value = 2,
},
{
.offset = 96,
.width = 1,
.value = 0,
},
{}
};
static const struct vcap_typegroup is2_x1_keyfield_set_typegroups[] = {
{
.offset = 0,
.width = 1,
.value = 1,
},
{}
};
static const struct vcap_typegroup *is2_keyfield_set_typegroups[] = {
[4] = is2_x4_keyfield_set_typegroups,
[2] = is2_x2_keyfield_set_typegroups,
[1] = is2_x1_keyfield_set_typegroups,
[5] = NULL,
};
static const struct vcap_typegroup is2_x2_actionfield_set_typegroups[] = {
{
.offset = 0,
.width = 2,
.value = 2,
},
{
.offset = 31,
.width = 1,
.value = 0,
},
{}
};
static const struct vcap_typegroup is2_x1_actionfield_set_typegroups[] = {
{
.offset = 0,
.width = 1,
.value = 1,
},
{}
};
static const struct vcap_typegroup *is2_actionfield_set_typegroups[] = {
[2] = is2_x2_actionfield_set_typegroups,
[1] = is2_x1_actionfield_set_typegroups,
[5] = NULL,
};
/* Keyfieldset names */
static const char * const vcap_keyfield_set_names[] = {
[VCAP_KFS_NO_VALUE] = "(None)",
[VCAP_KFS_ARP] = "VCAP_KFS_ARP",
[VCAP_KFS_IP4_OTHER] = "VCAP_KFS_IP4_OTHER",
[VCAP_KFS_IP4_TCP_UDP] = "VCAP_KFS_IP4_TCP_UDP",
[VCAP_KFS_IP6_OTHER] = "VCAP_KFS_IP6_OTHER",
[VCAP_KFS_IP6_STD] = "VCAP_KFS_IP6_STD",
[VCAP_KFS_IP6_TCP_UDP] = "VCAP_KFS_IP6_TCP_UDP",
[VCAP_KFS_MAC_ETYPE] = "VCAP_KFS_MAC_ETYPE",
[VCAP_KFS_MAC_LLC] = "VCAP_KFS_MAC_LLC",
[VCAP_KFS_MAC_SNAP] = "VCAP_KFS_MAC_SNAP",
[VCAP_KFS_OAM] = "VCAP_KFS_OAM",
[VCAP_KFS_SMAC_SIP4] = "VCAP_KFS_SMAC_SIP4",
[VCAP_KFS_SMAC_SIP6] = "VCAP_KFS_SMAC_SIP6",
};
/* Actionfieldset names */
static const char * const vcap_actionfield_set_names[] = {
[VCAP_AFS_NO_VALUE] = "(None)",
[VCAP_AFS_BASE_TYPE] = "VCAP_AFS_BASE_TYPE",
[VCAP_AFS_SMAC_SIP] = "VCAP_AFS_SMAC_SIP",
};
/* Keyfield names */
static const char * const vcap_keyfield_names[] = {
[VCAP_KF_NO_VALUE] = "(None)",
[VCAP_KF_8021Q_DEI_CLS] = "8021Q_DEI_CLS",
[VCAP_KF_8021Q_PCP_CLS] = "8021Q_PCP_CLS",
[VCAP_KF_8021Q_VID_CLS] = "8021Q_VID_CLS",
[VCAP_KF_8021Q_VLAN_TAGGED_IS] = "8021Q_VLAN_TAGGED_IS",
[VCAP_KF_ARP_ADDR_SPACE_OK_IS] = "ARP_ADDR_SPACE_OK_IS",
[VCAP_KF_ARP_LEN_OK_IS] = "ARP_LEN_OK_IS",
[VCAP_KF_ARP_OPCODE] = "ARP_OPCODE",
[VCAP_KF_ARP_OPCODE_UNKNOWN_IS] = "ARP_OPCODE_UNKNOWN_IS",
[VCAP_KF_ARP_PROTO_SPACE_OK_IS] = "ARP_PROTO_SPACE_OK_IS",
[VCAP_KF_ARP_SENDER_MATCH_IS] = "ARP_SENDER_MATCH_IS",
[VCAP_KF_ARP_TGT_MATCH_IS] = "ARP_TGT_MATCH_IS",
[VCAP_KF_ETYPE] = "ETYPE",
[VCAP_KF_HOST_MATCH] = "HOST_MATCH",
[VCAP_KF_IF_IGR_PORT] = "IF_IGR_PORT",
[VCAP_KF_IF_IGR_PORT_MASK] = "IF_IGR_PORT_MASK",
[VCAP_KF_IP4_IS] = "IP4_IS",
[VCAP_KF_ISDX_GT0_IS] = "ISDX_GT0_IS",
[VCAP_KF_L2_BC_IS] = "L2_BC_IS",
[VCAP_KF_L2_DMAC] = "L2_DMAC",
[VCAP_KF_L2_FRM_TYPE] = "L2_FRM_TYPE",
[VCAP_KF_L2_LLC] = "L2_LLC",
[VCAP_KF_L2_MC_IS] = "L2_MC_IS",
[VCAP_KF_L2_PAYLOAD0] = "L2_PAYLOAD0",
[VCAP_KF_L2_PAYLOAD1] = "L2_PAYLOAD1",
[VCAP_KF_L2_PAYLOAD2] = "L2_PAYLOAD2",
[VCAP_KF_L2_SMAC] = "L2_SMAC",
[VCAP_KF_L2_SNAP] = "L2_SNAP",
[VCAP_KF_L3_DIP_EQ_SIP_IS] = "L3_DIP_EQ_SIP_IS",
[VCAP_KF_L3_FRAGMENT] = "L3_FRAGMENT",
[VCAP_KF_L3_FRAG_OFS_GT0] = "L3_FRAG_OFS_GT0",
[VCAP_KF_L3_IP4_DIP] = "L3_IP4_DIP",
[VCAP_KF_L3_IP4_SIP] = "L3_IP4_SIP",
[VCAP_KF_L3_IP6_DIP] = "L3_IP6_DIP",
[VCAP_KF_L3_IP6_SIP] = "L3_IP6_SIP",
[VCAP_KF_L3_IP_PROTO] = "L3_IP_PROTO",
[VCAP_KF_L3_OPTIONS_IS] = "L3_OPTIONS_IS",
[VCAP_KF_L3_PAYLOAD] = "L3_PAYLOAD",
[VCAP_KF_L3_TOS] = "L3_TOS",
[VCAP_KF_L3_TTL_GT0] = "L3_TTL_GT0",
[VCAP_KF_L4_1588_DOM] = "L4_1588_DOM",
[VCAP_KF_L4_1588_VER] = "L4_1588_VER",
[VCAP_KF_L4_ACK] = "L4_ACK",
[VCAP_KF_L4_DPORT] = "L4_DPORT",
[VCAP_KF_L4_FIN] = "L4_FIN",
[VCAP_KF_L4_PSH] = "L4_PSH",
[VCAP_KF_L4_RNG] = "L4_RNG",
[VCAP_KF_L4_RST] = "L4_RST",
[VCAP_KF_L4_SEQUENCE_EQ0_IS] = "L4_SEQUENCE_EQ0_IS",
[VCAP_KF_L4_SPORT] = "L4_SPORT",
[VCAP_KF_L4_SPORT_EQ_DPORT_IS] = "L4_SPORT_EQ_DPORT_IS",
[VCAP_KF_L4_SYN] = "L4_SYN",
[VCAP_KF_L4_URG] = "L4_URG",
[VCAP_KF_LOOKUP_FIRST_IS] = "LOOKUP_FIRST_IS",
[VCAP_KF_LOOKUP_PAG] = "LOOKUP_PAG",
[VCAP_KF_OAM_CCM_CNTS_EQ0] = "OAM_CCM_CNTS_EQ0",
[VCAP_KF_OAM_DETECTED] = "OAM_DETECTED",
[VCAP_KF_OAM_FLAGS] = "OAM_FLAGS",
[VCAP_KF_OAM_MEL_FLAGS] = "OAM_MEL_FLAGS",
[VCAP_KF_OAM_MEPID] = "OAM_MEPID",
[VCAP_KF_OAM_OPCODE] = "OAM_OPCODE",
[VCAP_KF_OAM_VER] = "OAM_VER",
[VCAP_KF_OAM_Y1731_IS] = "OAM_Y1731_IS",
[VCAP_KF_TCP_IS] = "TCP_IS",
[VCAP_KF_TYPE] = "TYPE",
};
/* Actionfield names */
static const char * const vcap_actionfield_names[] = {
[VCAP_AF_NO_VALUE] = "(None)",
[VCAP_AF_ACL_ID] = "ACL_ID",
[VCAP_AF_CPU_COPY_ENA] = "CPU_COPY_ENA",
[VCAP_AF_CPU_QUEUE_NUM] = "CPU_QUEUE_NUM",
[VCAP_AF_FWD_KILL_ENA] = "FWD_KILL_ENA",
[VCAP_AF_HIT_ME_ONCE] = "HIT_ME_ONCE",
[VCAP_AF_HOST_MATCH] = "HOST_MATCH",
[VCAP_AF_ISDX_ENA] = "ISDX_ENA",
[VCAP_AF_LRN_DIS] = "LRN_DIS",
[VCAP_AF_MASK_MODE] = "MASK_MODE",
[VCAP_AF_MIRROR_ENA] = "MIRROR_ENA",
[VCAP_AF_POLICE_ENA] = "POLICE_ENA",
[VCAP_AF_POLICE_IDX] = "POLICE_IDX",
[VCAP_AF_POLICE_VCAP_ONLY] = "POLICE_VCAP_ONLY",
[VCAP_AF_PORT_MASK] = "PORT_MASK",
[VCAP_AF_REW_OP] = "REW_OP",
};
/* VCAPs */
const struct vcap_info lan966x_vcaps[] = {
[VCAP_TYPE_IS2] = {
.name = "is2",
.rows = 64,
.sw_count = 4,
.sw_width = 96,
.sticky_width = 32,
.act_width = 31,
.default_cnt = 11,
.require_cnt_dis = 1,
.version = 1,
.keyfield_set = is2_keyfield_set,
.keyfield_set_size = ARRAY_SIZE(is2_keyfield_set),
.actionfield_set = is2_actionfield_set,
.actionfield_set_size = ARRAY_SIZE(is2_actionfield_set),
.keyfield_set_map = is2_keyfield_set_map,
.keyfield_set_map_size = is2_keyfield_set_map_size,
.actionfield_set_map = is2_actionfield_set_map,
.actionfield_set_map_size = is2_actionfield_set_map_size,
.keyfield_set_typegroups = is2_keyfield_set_typegroups,
.actionfield_set_typegroups = is2_actionfield_set_typegroups,
},
};
const struct vcap_statistics lan966x_vcap_stats = {
.name = "lan966x",
.count = 1,
.keyfield_set_names = vcap_keyfield_set_names,
.actionfield_set_names = vcap_actionfield_set_names,
.keyfield_names = vcap_keyfield_names,
.actionfield_names = vcap_actionfield_names,
};
drivers/net/ethernet/microchip/lan966x/lan966x_vcap_ag_api.h 0 → 100644
View file @ cb55ff7a
/* SPDX-License-Identifier: BSD-3-Clause */
#ifndef __LAN966X_VCAP_AG_API_H__
#define __LAN966X_VCAP_AG_API_H__
#include "vcap_api.h"
extern const struct vcap_info lan966x_vcaps[];
extern const struct vcap_statistics lan966x_vcap_stats;
#endif /* __LAN966X_VCAP_AG_API_H__ */
drivers/net/ethernet/microchip/lan966x/lan966x_vcap_impl.c 0 → 100644
View file @ cb55ff7a
// SPDX-License-Identifier: GPL-2.0+
#include "lan966x_main.h"
#include "lan966x_vcap_ag_api.h"
#include "vcap_api.h"
#include "vcap_api_client.h"
#define LAN966X_VCAP_CID_IS2_L0 VCAP_CID_INGRESS_STAGE2_L0 /* IS2 lookup 0 */
#define LAN966X_VCAP_CID_IS2_L1 VCAP_CID_INGRESS_STAGE2_L1 /* IS2 lookup 1 */
#define LAN966X_VCAP_CID_IS2_MAX (VCAP_CID_INGRESS_STAGE2_L2 - 1) /* IS2 Max */
#define STREAMSIZE (64 * 4)
#define LAN966X_IS2_LOOKUPS 2
enum vcap_is2_port_sel_ipv6 {
VCAP_IS2_PS_IPV6_TCPUDP_OTHER,
VCAP_IS2_PS_IPV6_STD,
VCAP_IS2_PS_IPV6_IP4_TCPUDP_IP4_OTHER,
VCAP_IS2_PS_IPV6_MAC_ETYPE,
};
static struct lan966x_vcap_inst {
enum vcap_type vtype; /* type of vcap */
int tgt_inst; /* hardware instance number */
int lookups; /* number of lookups in this vcap type */
int first_cid; /* first chain id in this vcap */
int last_cid; /* last chain id in this vcap */
int count; /* number of available addresses */
} lan966x_vcap_inst_cfg[] = {
{
.vtype = VCAP_TYPE_IS2, /* IS2-0 */
.tgt_inst = 2,
.lookups = LAN966X_IS2_LOOKUPS,
.first_cid = LAN966X_VCAP_CID_IS2_L0,
.last_cid = LAN966X_VCAP_CID_IS2_MAX,
.count = 256,
},
};
struct lan966x_vcap_cmd_cb {
struct lan966x *lan966x;
u32 instance;
};
static u32 lan966x_vcap_read_update_ctrl(const struct lan966x_vcap_cmd_cb *cb)
{
return lan_rd(cb->lan966x, VCAP_UPDATE_CTRL(cb->instance));
}
static void lan966x_vcap_wait_update(struct lan966x *lan966x, int instance)
{
const struct lan966x_vcap_cmd_cb cb = { .lan966x = lan966x,
.instance = instance };
u32 val;
readx_poll_timeout(lan966x_vcap_read_update_ctrl, &cb, val,
(val & VCAP_UPDATE_CTRL_UPDATE_SHOT) == 0, 10,
100000);
}
static void __lan966x_vcap_range_init(struct lan966x *lan966x,
struct vcap_admin *admin,
u32 addr,
u32 count)
{
lan_wr(VCAP_MV_CFG_MV_NUM_POS_SET(0) |
VCAP_MV_CFG_MV_SIZE_SET(count - 1),
lan966x, VCAP_MV_CFG(admin->tgt_inst));
lan_wr(VCAP_UPDATE_CTRL_UPDATE_CMD_SET(VCAP_CMD_INITIALIZE) |
VCAP_UPDATE_CTRL_UPDATE_ENTRY_DIS_SET(0) |
VCAP_UPDATE_CTRL_UPDATE_ACTION_DIS_SET(0) |
VCAP_UPDATE_CTRL_UPDATE_CNT_DIS_SET(0) |
VCAP_UPDATE_CTRL_UPDATE_ADDR_SET(addr) |
VCAP_UPDATE_CTRL_CLEAR_CACHE_SET(true) |
VCAP_UPDATE_CTRL_UPDATE_SHOT_SET(1),
lan966x, VCAP_UPDATE_CTRL(admin->tgt_inst));
lan966x_vcap_wait_update(lan966x, admin->tgt_inst);
}
static int lan966x_vcap_cid_to_lookup(int cid)
{
if (cid >= LAN966X_VCAP_CID_IS2_L1 &&
cid < LAN966X_VCAP_CID_IS2_MAX)
return 1;
return 0;
}
static int
lan966x_vcap_is2_get_port_keysets(struct net_device *dev, int lookup,
struct vcap_keyset_list *keysetlist,
u16 l3_proto)
{
struct lan966x_port *port = netdev_priv(dev);
struct lan966x *lan966x = port->lan966x;
bool found = false;
u32 val;
/* Check if the port keyset selection is enabled */
val = lan_rd(lan966x, ANA_VCAP_S2_CFG(port->chip_port));
if (!ANA_VCAP_S2_CFG_ENA_GET(val))
return -ENOENT;
/* Collect all keysets for the port in a list */
if (l3_proto == ETH_P_ALL)
vcap_keyset_list_add(keysetlist, VCAP_KFS_MAC_ETYPE);
if (l3_proto == ETH_P_ALL || l3_proto == ETH_P_SNAP) {
if (ANA_VCAP_S2_CFG_SNAP_DIS_GET(val) & (BIT(0) << lookup))
vcap_keyset_list_add(keysetlist, VCAP_KFS_MAC_LLC);
else
vcap_keyset_list_add(keysetlist, VCAP_KFS_MAC_SNAP);
found = true;
}
if (l3_proto == ETH_P_ALL || l3_proto == ETH_P_CFM) {
if (ANA_VCAP_S2_CFG_OAM_DIS_GET(val) & (BIT(0) << lookup))
vcap_keyset_list_add(keysetlist, VCAP_KFS_MAC_ETYPE);
else
vcap_keyset_list_add(keysetlist, VCAP_KFS_OAM);
found = true;
}
if (l3_proto == ETH_P_ALL || l3_proto == ETH_P_ARP) {
if (ANA_VCAP_S2_CFG_ARP_DIS_GET(val) & (BIT(0) << lookup))
vcap_keyset_list_add(keysetlist, VCAP_KFS_MAC_ETYPE);
else
vcap_keyset_list_add(keysetlist, VCAP_KFS_ARP);
found = true;
}
if (l3_proto == ETH_P_ALL || l3_proto == ETH_P_IP) {
if (ANA_VCAP_S2_CFG_IP_OTHER_DIS_GET(val) & (BIT(0) << lookup))
vcap_keyset_list_add(keysetlist, VCAP_KFS_MAC_ETYPE);
else
vcap_keyset_list_add(keysetlist, VCAP_KFS_IP4_OTHER);
if (ANA_VCAP_S2_CFG_IP_TCPUDP_DIS_GET(val) & (BIT(0) << lookup))
vcap_keyset_list_add(keysetlist, VCAP_KFS_MAC_ETYPE);
else
vcap_keyset_list_add(keysetlist, VCAP_KFS_IP4_TCP_UDP);
found = true;
}
if (l3_proto == ETH_P_ALL || l3_proto == ETH_P_IPV6) {
switch (ANA_VCAP_S2_CFG_IP6_CFG_GET(val) & (0x3 << lookup)) {
case VCAP_IS2_PS_IPV6_TCPUDP_OTHER:
vcap_keyset_list_add(keysetlist, VCAP_KFS_IP6_OTHER);
vcap_keyset_list_add(keysetlist, VCAP_KFS_IP6_TCP_UDP);
break;
case VCAP_IS2_PS_IPV6_STD:
vcap_keyset_list_add(keysetlist, VCAP_KFS_IP6_STD);
break;
case VCAP_IS2_PS_IPV6_IP4_TCPUDP_IP4_OTHER:
vcap_keyset_list_add(keysetlist, VCAP_KFS_IP4_OTHER);
vcap_keyset_list_add(keysetlist, VCAP_KFS_IP4_TCP_UDP);
break;
case VCAP_IS2_PS_IPV6_MAC_ETYPE:
vcap_keyset_list_add(keysetlist, VCAP_KFS_MAC_ETYPE);
break;
}
found = true;
}
if (!found)
vcap_keyset_list_add(keysetlist, VCAP_KFS_MAC_ETYPE);
return 0;
}
static enum vcap_keyfield_set
lan966x_vcap_validate_keyset(struct net_device *dev,
struct vcap_admin *admin,
struct vcap_rule *rule,
struct vcap_keyset_list *kslist,
u16 l3_proto)
{
struct vcap_keyset_list keysetlist = {};
enum vcap_keyfield_set keysets[10] = {};
int lookup;
int err;
if (!kslist || kslist->cnt == 0)
return VCAP_KFS_NO_VALUE;
lookup = lan966x_vcap_cid_to_lookup(rule->vcap_chain_id);
keysetlist.max = ARRAY_SIZE(keysets);
keysetlist.keysets = keysets;
err = lan966x_vcap_is2_get_port_keysets(dev, lookup, &keysetlist,
l3_proto);
if (err)
return VCAP_KFS_NO_VALUE;
/* Check if there is a match and return the match */
for (int i = 0; i < kslist->cnt; ++i)
for (int j = 0; j < keysetlist.cnt; ++j)
if (kslist->keysets[i] == keysets[j])
return kslist->keysets[i];
return VCAP_KFS_NO_VALUE;
}
static bool lan966x_vcap_is_first_chain(struct vcap_rule *rule)
{
return (rule->vcap_chain_id >= LAN966X_VCAP_CID_IS2_L0 &&
rule->vcap_chain_id < LAN966X_VCAP_CID_IS2_L1);
}
static void lan966x_vcap_add_default_fields(struct net_device *dev,
struct vcap_admin *admin,
struct vcap_rule *rule)
{
struct lan966x_port *port = netdev_priv(dev);
vcap_rule_add_key_u32(rule, VCAP_KF_IF_IGR_PORT_MASK, 0,
~BIT(port->chip_port));
if (lan966x_vcap_is_first_chain(rule))
vcap_rule_add_key_bit(rule, VCAP_KF_LOOKUP_FIRST_IS,
VCAP_BIT_1);
else
vcap_rule_add_key_bit(rule, VCAP_KF_LOOKUP_FIRST_IS,
VCAP_BIT_0);
}
static void lan966x_vcap_cache_erase(struct vcap_admin *admin)
{
memset(admin->cache.keystream, 0, STREAMSIZE);
memset(admin->cache.maskstream, 0, STREAMSIZE);
memset(admin->cache.actionstream, 0, STREAMSIZE);
memset(&admin->cache.counter, 0, sizeof(admin->cache.counter));
}
static void lan966x_vcap_cache_write(struct net_device *dev,
struct vcap_admin *admin,
enum vcap_selection sel,
u32 start,
u32 count)
{
struct lan966x_port *port = netdev_priv(dev);
struct lan966x *lan966x = port->lan966x;
u32 *keystr, *mskstr, *actstr;
keystr = &admin->cache.keystream[start];
mskstr = &admin->cache.maskstream[start];
actstr = &admin->cache.actionstream[start];
switch (sel) {
case VCAP_SEL_ENTRY:
for (int i = 0; i < count; ++i) {
lan_wr(keystr[i] & mskstr[i], lan966x,
VCAP_ENTRY_DAT(admin->tgt_inst, i));
lan_wr(~mskstr[i], lan966x,
VCAP_MASK_DAT(admin->tgt_inst, i));
}
break;
case VCAP_SEL_ACTION:
for (int i = 0; i < count; ++i)
lan_wr(actstr[i], lan966x,
VCAP_ACTION_DAT(admin->tgt_inst, i));
break;
case VCAP_SEL_COUNTER:
admin->cache.sticky = admin->cache.counter > 0;
lan_wr(admin->cache.counter, lan966x,
VCAP_CNT_DAT(admin->tgt_inst, 0));
break;
default:
break;
}
}
static void lan966x_vcap_cache_read(struct net_device *dev,
struct vcap_admin *admin,
enum vcap_selection sel,
u32 start,
u32 count)
{
struct lan966x_port *port = netdev_priv(dev);
struct lan966x *lan966x = port->lan966x;
int instance = admin->tgt_inst;
u32 *keystr, *mskstr, *actstr;
keystr = &admin->cache.keystream[start];
mskstr = &admin->cache.maskstream[start];
actstr = &admin->cache.actionstream[start];
if (sel & VCAP_SEL_ENTRY) {
for (int i = 0; i < count; ++i) {
keystr[i] =
lan_rd(lan966x, VCAP_ENTRY_DAT(instance, i));
mskstr[i] =
~lan_rd(lan966x, VCAP_MASK_DAT(instance, i));
}
}
if (sel & VCAP_SEL_ACTION)
for (int i = 0; i < count; ++i)
actstr[i] =
lan_rd(lan966x, VCAP_ACTION_DAT(instance, i));
if (sel & VCAP_SEL_COUNTER) {
admin->cache.counter =
lan_rd(lan966x, VCAP_CNT_DAT(instance, 0));
admin->cache.sticky = admin->cache.counter > 0;
}
}
static void lan966x_vcap_range_init(struct net_device *dev,
struct vcap_admin *admin,
u32 addr,
u32 count)
{
struct lan966x_port *port = netdev_priv(dev);
struct lan966x *lan966x = port->lan966x;
__lan966x_vcap_range_init(lan966x, admin, addr, count);
}
static void lan966x_vcap_update(struct net_device *dev,
struct vcap_admin *admin,
enum vcap_command cmd,
enum vcap_selection sel,
u32 addr)
{
struct lan966x_port *port = netdev_priv(dev);
struct lan966x *lan966x = port->lan966x;
bool clear;
clear = (cmd == VCAP_CMD_INITIALIZE);
lan_wr(VCAP_MV_CFG_MV_NUM_POS_SET(0) |
VCAP_MV_CFG_MV_SIZE_SET(0),
lan966x, VCAP_MV_CFG(admin->tgt_inst));
lan_wr(VCAP_UPDATE_CTRL_UPDATE_CMD_SET(cmd) |
VCAP_UPDATE_CTRL_UPDATE_ENTRY_DIS_SET((VCAP_SEL_ENTRY & sel) == 0) |
VCAP_UPDATE_CTRL_UPDATE_ACTION_DIS_SET((VCAP_SEL_ACTION & sel) == 0) |
VCAP_UPDATE_CTRL_UPDATE_CNT_DIS_SET((VCAP_SEL_COUNTER & sel) == 0) |
VCAP_UPDATE_CTRL_UPDATE_ADDR_SET(addr) |
VCAP_UPDATE_CTRL_CLEAR_CACHE_SET(clear) |
VCAP_UPDATE_CTRL_UPDATE_SHOT,
lan966x, VCAP_UPDATE_CTRL(admin->tgt_inst));
lan966x_vcap_wait_update(lan966x, admin->tgt_inst);
}
static void lan966x_vcap_move(struct net_device *dev,
struct vcap_admin *admin,
u32 addr, int offset, int count)
{
struct lan966x_port *port = netdev_priv(dev);
struct lan966x *lan966x = port->lan966x;
enum vcap_command cmd;
u16 mv_num_pos;
u16 mv_size;
mv_size = count - 1;
if (offset > 0) {
mv_num_pos = offset - 1;
cmd = VCAP_CMD_MOVE_DOWN;
} else {
mv_num_pos = -offset - 1;
cmd = VCAP_CMD_MOVE_UP;
}
lan_wr(VCAP_MV_CFG_MV_NUM_POS_SET(mv_num_pos) |
VCAP_MV_CFG_MV_SIZE_SET(mv_size),
lan966x, VCAP_MV_CFG(admin->tgt_inst));
lan_wr(VCAP_UPDATE_CTRL_UPDATE_CMD_SET(cmd) |
VCAP_UPDATE_CTRL_UPDATE_ENTRY_DIS_SET(0) |
VCAP_UPDATE_CTRL_UPDATE_ACTION_DIS_SET(0) |
VCAP_UPDATE_CTRL_UPDATE_CNT_DIS_SET(0) |
VCAP_UPDATE_CTRL_UPDATE_ADDR_SET(addr) |
VCAP_UPDATE_CTRL_CLEAR_CACHE_SET(false) |
VCAP_UPDATE_CTRL_UPDATE_SHOT,
lan966x, VCAP_UPDATE_CTRL(admin->tgt_inst));
lan966x_vcap_wait_update(lan966x, admin->tgt_inst);
}
static int lan966x_vcap_port_info(struct net_device *dev,
struct vcap_admin *admin,
struct vcap_output_print *out)
{
return 0;
}
static int lan966x_vcap_enable(struct net_device *dev,
struct vcap_admin *admin,
bool enable)
{
struct lan966x_port *port = netdev_priv(dev);
struct lan966x *lan966x = port->lan966x;
lan_rmw(ANA_VCAP_S2_CFG_ENA_SET(enable),
ANA_VCAP_S2_CFG_ENA,
lan966x, ANA_VCAP_S2_CFG(port->chip_port));
return 0;
}
static struct vcap_operations lan966x_vcap_ops = {
.validate_keyset = lan966x_vcap_validate_keyset,
.add_default_fields = lan966x_vcap_add_default_fields,
.cache_erase = lan966x_vcap_cache_erase,
.cache_write = lan966x_vcap_cache_write,
.cache_read = lan966x_vcap_cache_read,
.init = lan966x_vcap_range_init,
.update = lan966x_vcap_update,
.move = lan966x_vcap_move,
.port_info = lan966x_vcap_port_info,
.enable = lan966x_vcap_enable,
};
static void lan966x_vcap_admin_free(struct vcap_admin *admin)
{
if (!admin)
return;
kfree(admin->cache.keystream);
kfree(admin->cache.maskstream);
kfree(admin->cache.actionstream);
mutex_destroy(&admin->lock);
kfree(admin);
}
static struct vcap_admin *
lan966x_vcap_admin_alloc(struct lan966x *lan966x, struct vcap_control *ctrl,
const struct lan966x_vcap_inst *cfg)
{
struct vcap_admin *admin;
admin = kzalloc(sizeof(*admin), GFP_KERNEL);
if (!admin)
return ERR_PTR(-ENOMEM);
mutex_init(&admin->lock);
INIT_LIST_HEAD(&admin->list);
INIT_LIST_HEAD(&admin->rules);
INIT_LIST_HEAD(&admin->enabled);
admin->vtype = cfg->vtype;
admin->vinst = 0;
admin->w32be = true;
admin->tgt_inst = cfg->tgt_inst;
admin->lookups = cfg->lookups;
admin->lookups_per_instance = cfg->lookups;
admin->first_cid = cfg->first_cid;
admin->last_cid = cfg->last_cid;
admin->cache.keystream = kzalloc(STREAMSIZE, GFP_KERNEL);
admin->cache.maskstream = kzalloc(STREAMSIZE, GFP_KERNEL);
admin->cache.actionstream = kzalloc(STREAMSIZE, GFP_KERNEL);
if (!admin->cache.keystream ||
!admin->cache.maskstream ||
!admin->cache.actionstream) {
lan966x_vcap_admin_free(admin);
return ERR_PTR(-ENOMEM);
}
return admin;
}
static void lan966x_vcap_block_init(struct lan966x *lan966x,
struct vcap_admin *admin,
struct lan966x_vcap_inst *cfg)
{
admin->first_valid_addr = 0;
admin->last_used_addr = cfg->count;
admin->last_valid_addr = cfg->count - 1;
lan_wr(VCAP_CORE_IDX_CORE_IDX_SET(0),
lan966x, VCAP_CORE_IDX(admin->tgt_inst));
lan_wr(VCAP_CORE_MAP_CORE_MAP_SET(1),
lan966x, VCAP_CORE_MAP(admin->tgt_inst));
__lan966x_vcap_range_init(lan966x, admin, admin->first_valid_addr,
admin->last_valid_addr -
admin->first_valid_addr);
}
static void lan966x_vcap_port_key_deselection(struct lan966x *lan966x,
struct vcap_admin *admin)
{
for (int p = 0; p < lan966x->num_phys_ports; ++p)
lan_wr(0, lan966x, ANA_VCAP_S2_CFG(p));
}
int lan966x_vcap_init(struct lan966x *lan966x)
{
struct lan966x_vcap_inst *cfg;
struct vcap_control *ctrl;
struct vcap_admin *admin;
ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
if (!ctrl)
return -ENOMEM;
ctrl->vcaps = lan966x_vcaps;
ctrl->stats = &lan966x_vcap_stats;
ctrl->ops = &lan966x_vcap_ops;
INIT_LIST_HEAD(&ctrl->list);
for (int i = 0; i < ARRAY_SIZE(lan966x_vcap_inst_cfg); ++i) {
cfg = &lan966x_vcap_inst_cfg[i];
admin = lan966x_vcap_admin_alloc(lan966x, ctrl, cfg);
if (IS_ERR(admin))
return PTR_ERR(admin);
lan966x_vcap_block_init(lan966x, admin, cfg);
lan966x_vcap_port_key_deselection(lan966x, admin);
list_add_tail(&admin->list, &ctrl->list);
}
lan966x->vcap_ctrl = ctrl;
return 0;
}
void lan966x_vcap_deinit(struct lan966x *lan966x)
{
struct vcap_admin *admin, *admin_next;
struct vcap_control *ctrl;
ctrl = lan966x->vcap_ctrl;
if (!ctrl)
return;
list_for_each_entry_safe(admin, admin_next, &ctrl->list, list) {
lan966x_vcap_port_key_deselection(lan966x, admin);
vcap_del_rules(ctrl, admin);
list_del(&admin->list);
lan966x_vcap_admin_free(admin);
}
kfree(ctrl);
}
drivers/net/ethernet/microchip/vcap/vcap_ag_api.h
View file @ cb55ff7a
......@@ -11,6 +11,8 @@
#define __VCAP_AG_API__
enum vcap_type {
VCAP_TYPE_ES2,
VCAP_TYPE_IS0,
VCAP_TYPE_IS2,
VCAP_TYPE_MAX
};
......@@ -18,12 +20,29 @@ enum vcap_type {
/* Keyfieldset names with origin information */
enum vcap_keyfield_set {
VCAP_KFS_NO_VALUE, /* initial value */
VCAP_KFS_ARP, /* sparx5 is2 X6 */
VCAP_KFS_IP4_OTHER, /* sparx5 is2 X6 */
VCAP_KFS_IP4_TCP_UDP, /* sparx5 is2 X6 */
VCAP_KFS_ARP, /* sparx5 is2 X6, sparx5 es2 X6 */
VCAP_KFS_ETAG, /* sparx5 is0 X2 */
VCAP_KFS_IP4_OTHER, /* sparx5 is2 X6, sparx5 es2 X6 */
VCAP_KFS_IP4_TCP_UDP, /* sparx5 is2 X6, sparx5 es2 X6 */
VCAP_KFS_IP4_VID, /* sparx5 es2 X3 */
VCAP_KFS_IP6_STD, /* sparx5 is2 X6 */
VCAP_KFS_IP_7TUPLE, /* sparx5 is2 X12 */
VCAP_KFS_MAC_ETYPE, /* sparx5 is2 X6 */
VCAP_KFS_IP6_VID, /* sparx5 is2 X6, sparx5 es2 X6 */
VCAP_KFS_IP_7TUPLE, /* sparx5 is2 X12, sparx5 es2 X12 */
VCAP_KFS_LL_FULL, /* sparx5 is0 X6 */
VCAP_KFS_MAC_ETYPE, /* sparx5 is2 X6, sparx5 es2 X6 */
VCAP_KFS_MLL, /* sparx5 is0 X3 */
VCAP_KFS_NORMAL, /* sparx5 is0 X6 */
VCAP_KFS_NORMAL_5TUPLE_IP4, /* sparx5 is0 X6 */
VCAP_KFS_NORMAL_7TUPLE, /* sparx5 is0 X12 */
VCAP_KFS_PURE_5TUPLE_IP4, /* sparx5 is0 X3 */
VCAP_KFS_TRI_VID, /* sparx5 is0 X2 */
VCAP_KFS_MAC_LLC, /* lan966x is2 X2 */
VCAP_KFS_MAC_SNAP, /* lan966x is2 X2 */
VCAP_KFS_OAM, /* lan966x is2 X2 */
VCAP_KFS_IP6_TCP_UDP, /* lan966x is2 X4 */
VCAP_KFS_IP6_OTHER, /* lan966x is2 X4 */
VCAP_KFS_SMAC_SIP4, /* lan966x is2 X1 */
VCAP_KFS_SMAC_SIP6, /* lan966x is2 X2 */
};
/* List of keyfields with description
......@@ -31,34 +50,93 @@ enum vcap_keyfield_set {
* Keys ending in _IS are booleans derived from frame data
* Keys ending in _CLS are classified frame data
*
* VCAP_KF_8021Q_DEI_CLS: W1, sparx5: is2
* VCAP_KF_8021BR_ECID_BASE: W12, sparx5: is0
* Used by 802.1BR Bridge Port Extension in an E-Tag
* VCAP_KF_8021BR_ECID_EXT: W8, sparx5: is0
* Used by 802.1BR Bridge Port Extension in an E-Tag
* VCAP_KF_8021BR_E_TAGGED: W1, sparx5: is0
* Set for frames containing an E-TAG (802.1BR Ethertype 893f)
* VCAP_KF_8021BR_GRP: W2, sparx5: is0
* E-Tag group bits in 802.1BR Bridge Port Extension
* VCAP_KF_8021BR_IGR_ECID_BASE: W12, sparx5: is0
* Used by 802.1BR Bridge Port Extension in an E-Tag
* VCAP_KF_8021BR_IGR_ECID_EXT: W8, sparx5: is0
* Used by 802.1BR Bridge Port Extension in an E-Tag
* VCAP_KF_8021Q_DEI0: W1, sparx5: is0
* First DEI in multiple vlan tags (outer tag or default port tag)
* VCAP_KF_8021Q_DEI1: W1, sparx5: is0
* Second DEI in multiple vlan tags (inner tag)
* VCAP_KF_8021Q_DEI2: W1, sparx5: is0
* Third DEI in multiple vlan tags (not always available)
* VCAP_KF_8021Q_DEI_CLS: W1, sparx5: is2/es2, lan966x: is2
* Classified DEI
* VCAP_KF_8021Q_PCP_CLS: W3, sparx5: is2
* VCAP_KF_8021Q_PCP0: W3, sparx5: is0
* First PCP in multiple vlan tags (outer tag or default port tag)
* VCAP_KF_8021Q_PCP1: W3, sparx5: is0
* Second PCP in multiple vlan tags (inner tag)
* VCAP_KF_8021Q_PCP2: W3, sparx5: is0
* Third PCP in multiple vlan tags (not always available)
* VCAP_KF_8021Q_PCP_CLS: W3, sparx5: is2/es2, lan966x: is2
* Classified PCP
* VCAP_KF_8021Q_VID_CLS: W13, sparx5: is2
* VCAP_KF_8021Q_TPID0: W3, sparx5: is0
* First TPIC in multiple vlan tags (outer tag or default port tag)
* VCAP_KF_8021Q_TPID1: W3, sparx5: is0
* Second TPID in multiple vlan tags (inner tag)
* VCAP_KF_8021Q_TPID2: W3, sparx5: is0
* Third TPID in multiple vlan tags (not always available)
* VCAP_KF_8021Q_VID0: W12, sparx5: is0
* First VID in multiple vlan tags (outer tag or default port tag)
* VCAP_KF_8021Q_VID1: W12, sparx5: is0
* Second VID in multiple vlan tags (inner tag)
* VCAP_KF_8021Q_VID2: W12, sparx5: is0
* Third VID in multiple vlan tags (not always available)
* VCAP_KF_8021Q_VID_CLS: W13, sparx5: is2/es2, lan966x is2 W12
* Classified VID
* VCAP_KF_8021Q_VLAN_TAGGED_IS: W1, sparx5: is2
* VCAP_KF_8021Q_VLAN_TAGGED_IS: W1, sparx5: is2/es2, lan966x: is2
* Sparx5: Set if frame was received with a VLAN tag, LAN966x: Set if frame has
* one or more Q-tags. Independent of port VLAN awareness
* VCAP_KF_ARP_ADDR_SPACE_OK_IS: W1, sparx5: is2
* VCAP_KF_8021Q_VLAN_TAGS: W3, sparx5: is0
* Number of VLAN tags in frame: 0: Untagged, 1: Single tagged, 3: Double
* tagged, 7: Triple tagged
* VCAP_KF_ACL_GRP_ID: W8, sparx5: es2
* Used in interface map table
* VCAP_KF_ARP_ADDR_SPACE_OK_IS: W1, sparx5: is2/es2, lan966x: is2
* Set if hardware address is Ethernet
* VCAP_KF_ARP_LEN_OK_IS: W1, sparx5: is2
* VCAP_KF_ARP_LEN_OK_IS: W1, sparx5: is2/es2, lan966x: is2
* Set if hardware address length = 6 (Ethernet) and IP address length = 4 (IP).
* VCAP_KF_ARP_OPCODE: W2, sparx5: is2
* VCAP_KF_ARP_OPCODE: W2, sparx5: is2/es2, lan966x: i2
* ARP opcode
* VCAP_KF_ARP_OPCODE_UNKNOWN_IS: W1, sparx5: is2
* VCAP_KF_ARP_OPCODE_UNKNOWN_IS: W1, sparx5: is2/es2, lan966x: is2
* Set if not one of the codes defined in VCAP_KF_ARP_OPCODE
* VCAP_KF_ARP_PROTO_SPACE_OK_IS: W1, sparx5: is2
* VCAP_KF_ARP_PROTO_SPACE_OK_IS: W1, sparx5: is2/es2, lan966x: is2
* Set if protocol address space is 0x0800
* VCAP_KF_ARP_SENDER_MATCH_IS: W1, sparx5: is2
* VCAP_KF_ARP_SENDER_MATCH_IS: W1, sparx5: is2/es2, lan966x: is2
* Sender Hardware Address = SMAC (ARP)
* VCAP_KF_ARP_TGT_MATCH_IS: W1, sparx5: is2
* VCAP_KF_ARP_TGT_MATCH_IS: W1, sparx5: is2/es2, lan966x: is2
* Target Hardware Address = SMAC (RARP)
* VCAP_KF_ETYPE: W16, sparx5: is2
* VCAP_KF_COSID_CLS: W3, sparx5: es2
* Class of service
* VCAP_KF_DST_ENTRY: W1, sparx5: is0
* Selects whether the frame’s destination or source information is used for
* fields L2_SMAC and L3_IP4_SIP
* VCAP_KF_ES0_ISDX_KEY_ENA: W1, sparx5: es2
* The value taken from the IFH .FWD.ES0_ISDX_KEY_ENA
* VCAP_KF_ETYPE: W16, sparx5: is0/is2/es2, lan966x: is2
* Ethernet type
* VCAP_KF_ETYPE_LEN_IS: W1, sparx5: is2
* VCAP_KF_ETYPE_LEN_IS: W1, sparx5: is0/is2/es2
* Set if frame has EtherType >= 0x600
* VCAP_KF_IF_IGR_PORT_MASK: sparx5 is2 W32, sparx5 is2 W65
* VCAP_KF_ETYPE_MPLS: W2, sparx5: is0
* Type of MPLS Ethertype (or not)
* VCAP_KF_IF_EGR_PORT_MASK: W32, sparx5: es2
* Egress port mask, one bit per port
* VCAP_KF_IF_EGR_PORT_MASK_RNG: W3, sparx5: es2
* Select which 32 port group is available in IF_EGR_PORT (or virtual ports or
* CPU queue)
* VCAP_KF_IF_IGR_PORT: sparx5 is0 W7, sparx5 es2 W9
* Sparx5: Logical ingress port number retrieved from
* ANA_CL::PORT_ID_CFG.LPORT_NUM or ERLEG, LAN966x: ingress port nunmber
* VCAP_KF_IF_IGR_PORT_MASK: sparx5 is0 W65, sparx5 is2 W32, sparx5 is2 W65,
* lan966x is2 W9
* Ingress port mask, one bit per port/erleg
* VCAP_KF_IF_IGR_PORT_MASK_L3: W1, sparx5: is2
* If set, IF_IGR_PORT_MASK, IF_IGR_PORT_MASK_RNG, and IF_IGR_PORT_MASK_SEL are
......@@ -66,123 +144,206 @@ enum vcap_keyfield_set {
* VCAP_KF_IF_IGR_PORT_MASK_RNG: W4, sparx5: is2
* Range selector for IF_IGR_PORT_MASK. Specifies which group of 32 ports are
* available in IF_IGR_PORT_MASK
* VCAP_KF_IF_IGR_PORT_MASK_SEL: W2, sparx5: is2
* VCAP_KF_IF_IGR_PORT_MASK_SEL: W2, sparx5: is0/is2
* Mode selector for IF_IGR_PORT_MASK, applicable when IF_IGR_PORT_MASK_L3 == 0.
* Mapping: 0: DEFAULT 1: LOOPBACK 2: MASQUERADE 3: CPU_VD
* VCAP_KF_IP4_IS: W1, sparx5: is2
* VCAP_KF_IF_IGR_PORT_SEL: W1, sparx5: es2
* Selector for IF_IGR_PORT: physical port number or ERLEG
* VCAP_KF_IP4_IS: W1, sparx5: is0/is2/es2, lan966x: is2
* Set if frame has EtherType = 0x800 and IP version = 4
* VCAP_KF_ISDX_CLS: W12, sparx5: is2
* VCAP_KF_IP_MC_IS: W1, sparx5: is0
* Set if frame is IPv4 frame and frame’s destination MAC address is an IPv4
* multicast address (0x01005E0 /25). Set if frame is IPv6 frame and frame’s
* destination MAC address is an IPv6 multicast address (0x3333/16).
* VCAP_KF_IP_PAYLOAD_5TUPLE: W32, sparx5: is0
* Payload bytes after IP header
* VCAP_KF_IP_SNAP_IS: W1, sparx5: is0
* Set if frame is IPv4, IPv6, or SNAP frame
* VCAP_KF_ISDX_CLS: W12, sparx5: is2/es2
* Classified ISDX
* VCAP_KF_ISDX_GT0_IS: W1, sparx5: is2
* VCAP_KF_ISDX_GT0_IS: W1, sparx5: is2/es2, lan966x: is2
* Set if classified ISDX > 0
* VCAP_KF_L2_BC_IS: W1, sparx5: is2
* VCAP_KF_L2_BC_IS: W1, sparx5: is0/is2/es2, lan966x: is2
* Set if frame’s destination MAC address is the broadcast address
* (FF-FF-FF-FF-FF-FF).
* VCAP_KF_L2_DMAC: W48, sparx5: is2
* VCAP_KF_L2_DMAC: W48, sparx5: is0/is2/es2, lan966x: is2
* Destination MAC address
* VCAP_KF_L2_FWD_IS: W1, sparx5: is2
* Set if the frame is allowed to be forwarded to front ports
* VCAP_KF_L2_MC_IS: W1, sparx5: is2
* VCAP_KF_L2_MC_IS: W1, sparx5: is0/is2/es2, lan9966x is2
* Set if frame’s destination MAC address is a multicast address (bit 40 = 1).
* VCAP_KF_L2_PAYLOAD_ETYPE: W64, sparx5: is2
* VCAP_KF_L2_PAYLOAD_ETYPE: W64, sparx5: is2/es2
* Byte 0-7 of L2 payload after Type/Len field and overloading for OAM
* VCAP_KF_L2_SMAC: W48, sparx5: is2
* VCAP_KF_L2_SMAC: W48, sparx5: is0/is2/es2, lan966x is2
* Source MAC address
* VCAP_KF_L3_DIP_EQ_SIP_IS: W1, sparx5: is2
* VCAP_KF_L3_DIP_EQ_SIP_IS: W1, sparx5: is2/es2, lan966x: is2
* Set if Src IP matches Dst IP address
* VCAP_KF_L3_DMAC_DIP_MATCH: W1, sparx5: is2
* Match found in DIP security lookup in ANA_L3
* VCAP_KF_L3_DPL_CLS: W1, sparx5: es2
* The frames drop precedence level
* VCAP_KF_L3_DSCP: W6, sparx5: is0
* Frame’s DSCP value
* VCAP_KF_L3_DST_IS: W1, sparx5: is2
* Set if lookup is done for egress router leg
* VCAP_KF_L3_FRAGMENT_TYPE: W2, sparx5: is2
* VCAP_KF_L3_FRAGMENT_TYPE: W2, sparx5: is0/is2/es2
* L3 Fragmentation type (none, initial, suspicious, valid follow up)
* VCAP_KF_L3_FRAG_INVLD_L4_LEN: W1, sparx5: is2
* VCAP_KF_L3_FRAG_INVLD_L4_LEN: W1, sparx5: is0/is2
* Set if frame's L4 length is less than ANA_CL:COMMON:CLM_FRAGMENT_CFG.L4_MIN_L
* EN
* VCAP_KF_L3_IP4_DIP: W32, sparx5: is2
* VCAP_KF_L3_IP4_DIP: W32, sparx5: is0/is2/es2, lan966x: is2
* Destination IPv4 Address
* VCAP_KF_L3_IP4_SIP: W32, sparx5: is2
* VCAP_KF_L3_IP4_SIP: W32, sparx5: is0/is2/es2, lan966x: is2
* Source IPv4 Address
* VCAP_KF_L3_IP6_DIP: W128, sparx5: is2
* VCAP_KF_L3_IP6_DIP: W128, sparx5: is0/is2/es2, lan966x: is2
* Sparx5: Full IPv6 DIP, LAN966x: Either Full IPv6 DIP or a subset depending on
* frame type
* VCAP_KF_L3_IP6_SIP: W128, sparx5: is2
* VCAP_KF_L3_IP6_SIP: W128, sparx5: is0/is2/es2, lan966x: is2
* Sparx5: Full IPv6 SIP, LAN966x: Either Full IPv6 SIP or a subset depending on
* frame type
* VCAP_KF_L3_IP_PROTO: W8, sparx5: is2
* VCAP_KF_L3_IP_PROTO: W8, sparx5: is0/is2/es2, lan966x: is2
* IPv4 frames: IP protocol. IPv6 frames: Next header, same as for IPV4
* VCAP_KF_L3_OPTIONS_IS: W1, sparx5: is2
* VCAP_KF_L3_OPTIONS_IS: W1, sparx5: is0/is2/es2, lan966x: is2
* Set if IPv4 frame contains options (IP len > 5)
* VCAP_KF_L3_PAYLOAD: sparx5 is2 W96, sparx5 is2 W40
* VCAP_KF_L3_PAYLOAD: sparx5 is2 W96, sparx5 is2 W40, sparx5 es2 W96,
* lan966x is2 W56
* Sparx5: Payload bytes after IP header. IPv4: IPv4 options are not parsed so
* payload is always taken 20 bytes after the start of the IPv4 header, LAN966x:
* Bytes 0-6 after IP header
* VCAP_KF_L3_RT_IS: W1, sparx5: is2
* VCAP_KF_L3_RT_IS: W1, sparx5: is2/es2
* Set if frame has hit a router leg
* VCAP_KF_L3_TOS: W8, sparx5: is2
* VCAP_KF_L3_SMAC_SIP_MATCH: W1, sparx5: is2
* Match found in SIP security lookup in ANA_L3
* VCAP_KF_L3_TOS: W8, sparx5: is2/es2, lan966x: is2
* Sparx5: Frame's IPv4/IPv6 DSCP and ECN fields, LAN966x: IP TOS field
* VCAP_KF_L3_TTL_GT0: W1, sparx5: is2
* VCAP_KF_L3_TTL_GT0: W1, sparx5: is2/es2, lan966x: is2
* Set if IPv4 TTL / IPv6 hop limit is greater than 0
* VCAP_KF_L4_ACK: W1, sparx5: is2
* VCAP_KF_L4_ACK: W1, sparx5: is2/es2, lan966x: is2
* Sparx5 and LAN966x: TCP flag ACK, LAN966x only: PTP over UDP: flagField bit 2
* (unicastFlag)
* VCAP_KF_L4_DPORT: W16, sparx5: is2
* VCAP_KF_L4_DPORT: W16, sparx5: is2/es2, lan966x: is2
* Sparx5: TCP/UDP destination port. Overloading for IP_7TUPLE: Non-TCP/UDP IP
* frames: L4_DPORT = L3_IP_PROTO, LAN966x: TCP/UDP destination port
* VCAP_KF_L4_FIN: W1, sparx5: is2
* VCAP_KF_L4_FIN: W1, sparx5: is2/es2
* TCP flag FIN, LAN966x: TCP flag FIN, and for PTP over UDP: messageType bit 1
* VCAP_KF_L4_PAYLOAD: W64, sparx5: is2
* VCAP_KF_L4_PAYLOAD: W64, sparx5: is2/es2
* Payload bytes after TCP/UDP header Overloading for IP_7TUPLE: Non TCP/UDP
* frames: Payload bytes 0–7 after IP header. IPv4 options are not parsed so
* payload is always taken 20 bytes after the start of the IPv4 header for non
* TCP/UDP IPv4 frames
* VCAP_KF_L4_PSH: W1, sparx5: is2
* VCAP_KF_L4_PSH: W1, sparx5: is2/es2, lan966x: is2
* Sparx5: TCP flag PSH, LAN966x: TCP: TCP flag PSH. PTP over UDP: flagField bit
* 1 (twoStepFlag)
* VCAP_KF_L4_RNG: W16, sparx5: is2
* VCAP_KF_L4_RNG: sparx5 is0 W8, sparx5 is2 W16, sparx5 es2 W16, lan966x: is2
* Range checker bitmask (one for each range checker). Input into range checkers
* is taken from classified results (VID, DSCP) and frame (SPORT, DPORT, ETYPE,
* outer VID, inner VID)
* VCAP_KF_L4_RST: W1, sparx5: is2
* VCAP_KF_L4_RST: W1, sparx5: is2/es2, lan966x: is2
* Sparx5: TCP flag RST , LAN966x: TCP: TCP flag RST. PTP over UDP: messageType
* bit 3
* VCAP_KF_L4_SEQUENCE_EQ0_IS: W1, sparx5: is2
* VCAP_KF_L4_SEQUENCE_EQ0_IS: W1, sparx5: is2/es2, lan966x: is2
* Set if TCP sequence number is 0, LAN966x: Overlayed with PTP over UDP:
* messageType bit 0
* VCAP_KF_L4_SPORT: W16, sparx5: is2
* VCAP_KF_L4_SPORT: W16, sparx5: is0/is2/es2, lan966x: is2
* TCP/UDP source port
* VCAP_KF_L4_SPORT_EQ_DPORT_IS: W1, sparx5: is2
* VCAP_KF_L4_SPORT_EQ_DPORT_IS: W1, sparx5: is2/es2, lan966x: is2
* Set if UDP or TCP source port equals UDP or TCP destination port
* VCAP_KF_L4_SYN: W1, sparx5: is2
* VCAP_KF_L4_SYN: W1, sparx5: is2/es2, lan966x: is2
* Sparx5: TCP flag SYN, LAN966x: TCP: TCP flag SYN. PTP over UDP: messageType
* bit 2
* VCAP_KF_L4_URG: W1, sparx5: is2
* VCAP_KF_L4_URG: W1, sparx5: is2/es2, lan966x: is2
* Sparx5: TCP flag URG, LAN966x: TCP: TCP flag URG. PTP over UDP: flagField bit
* 7 (reserved)
* VCAP_KF_LOOKUP_FIRST_IS: W1, sparx5: is2
* VCAP_KF_LOOKUP_FIRST_IS: W1, sparx5: is0/is2/es2, lan966x: is2
* Selects between entries relevant for first and second lookup. Set for first
* lookup, cleared for second lookup.
* VCAP_KF_LOOKUP_PAG: W8, sparx5: is2
* VCAP_KF_LOOKUP_GEN_IDX: W12, sparx5: is0
* Generic index - for chaining CLM instances
* VCAP_KF_LOOKUP_GEN_IDX_SEL: W2, sparx5: is0
* Select the mode of the Generic Index
* VCAP_KF_LOOKUP_PAG: W8, sparx5: is2, lan966x: is2
* Classified Policy Association Group: chains rules from IS1/CLM to IS2
* VCAP_KF_OAM_CCM_CNTS_EQ0: W1, sparx5: is2
* VCAP_KF_OAM_CCM_CNTS_EQ0: W1, sparx5: is2/es2, lan966x: is2
* Dual-ended loss measurement counters in CCM frames are all zero
* VCAP_KF_OAM_Y1731_IS: W1, sparx5: is2
* VCAP_KF_OAM_MEL_FLAGS: W7, sparx5: is0, lan966x: is2
* Encoding of MD level/MEG level (MEL)
* VCAP_KF_OAM_Y1731_IS: W1, sparx5: is0/is2/es2, lan966x: is2
* Set if frame’s EtherType = 0x8902
* VCAP_KF_TCP_IS: W1, sparx5: is2
* VCAP_KF_PROT_ACTIVE: W1, sparx5: es2
* Protection is active
* VCAP_KF_TCP_IS: W1, sparx5: is0/is2/es2, lan966x: is2
* Set if frame is IPv4 TCP frame (IP protocol = 6) or IPv6 TCP frames (Next
* header = 6)
* VCAP_KF_TCP_UDP_IS: W1, sparx5: is2
* VCAP_KF_TCP_UDP_IS: W1, sparx5: is0/is2/es2, lan966x: is2
* Set if frame is IPv4/IPv6 TCP or UDP frame (IP protocol/next header equals 6
* or 17)
* VCAP_KF_TYPE: sparx5 is2 W4, sparx5 is2 W2
* VCAP_KF_TYPE: sparx5 is0 W2, sparx5 is0 W1, sparx5 is2 W4, sparx5 is2 W2,
* sparx5 es2 W3, lan966x: is2
* Keyset type id - set by the API
* VCAP_KF_HOST_MATCH: W1, lan966x: is2
* The action from the SMAC_SIP4 or SMAC_SIP6 lookups. Used for IP source
* guarding.
* VCAP_KF_L2_FRM_TYPE: W4, lan966x: is2
* Frame subtype for specific EtherTypes (MRP, DLR)
* VCAP_KF_L2_PAYLOAD0: W16, lan966x: is2
* Payload bytes 0-1 after the frame’s EtherType
* VCAP_KF_L2_PAYLOAD1: W8, lan966x: is2
* Payload byte 4 after the frame’s EtherType. This is specifically for PTP
* frames.
* VCAP_KF_L2_PAYLOAD2: W3, lan966x: is2
* Bits 7, 2, and 1 from payload byte 6 after the frame’s EtherType. This is
* specifically for PTP frames.
* VCAP_KF_L2_LLC: W40, lan966x: is2
* LLC header and data after up to two VLAN tags and the type/length field
* VCAP_KF_L3_FRAGMENT: W1, lan966x: is2
* Set if IPv4 frame is fragmented
* VCAP_KF_L3_FRAG_OFS_GT0: W1, lan966x: is2
* Set if IPv4 frame is fragmented and it is not the first fragment
* VCAP_KF_L2_SNAP: W40, lan966x: is2
* SNAP header after LLC header (AA-AA-03)
* VCAP_KF_L4_1588_DOM: W8, lan966x: is2
* PTP over UDP: domainNumber
* VCAP_KF_L4_1588_VER: W4, lan966x: is2
* PTP over UDP: version
* VCAP_KF_OAM_MEPID: W16, lan966x: is2
* CCM frame’s OAM MEP ID
* VCAP_KF_OAM_OPCODE: W8, lan966x: is2
* Frame’s OAM opcode
* VCAP_KF_OAM_VER: W5, lan966x: is2
* Frame’s OAM version
* VCAP_KF_OAM_FLAGS: W8, lan966x: is2
* Frame’s OAM flags
* VCAP_KF_OAM_DETECTED: W1, lan966x: is2
* This is missing in the datasheet, but present in the OAM keyset in XML
*/
/* Keyfield names */
enum vcap_key_field {
VCAP_KF_NO_VALUE, /* initial value */
VCAP_KF_8021BR_ECID_BASE,
VCAP_KF_8021BR_ECID_EXT,
VCAP_KF_8021BR_E_TAGGED,
VCAP_KF_8021BR_GRP,
VCAP_KF_8021BR_IGR_ECID_BASE,
VCAP_KF_8021BR_IGR_ECID_EXT,
VCAP_KF_8021Q_DEI0,
VCAP_KF_8021Q_DEI1,
VCAP_KF_8021Q_DEI2,
VCAP_KF_8021Q_DEI_CLS,
VCAP_KF_8021Q_PCP0,
VCAP_KF_8021Q_PCP1,
VCAP_KF_8021Q_PCP2,
VCAP_KF_8021Q_PCP_CLS,
VCAP_KF_8021Q_TPID0,
VCAP_KF_8021Q_TPID1,
VCAP_KF_8021Q_TPID2,
VCAP_KF_8021Q_VID0,
VCAP_KF_8021Q_VID1,
VCAP_KF_8021Q_VID2,
VCAP_KF_8021Q_VID_CLS,
VCAP_KF_8021Q_VLAN_TAGGED_IS,
VCAP_KF_8021Q_VLAN_TAGS,
VCAP_KF_ACL_GRP_ID,
VCAP_KF_ARP_ADDR_SPACE_OK_IS,
VCAP_KF_ARP_LEN_OK_IS,
VCAP_KF_ARP_OPCODE,
......@@ -190,13 +351,24 @@ enum vcap_key_field {
VCAP_KF_ARP_PROTO_SPACE_OK_IS,
VCAP_KF_ARP_SENDER_MATCH_IS,
VCAP_KF_ARP_TGT_MATCH_IS,
VCAP_KF_COSID_CLS,
VCAP_KF_DST_ENTRY,
VCAP_KF_ES0_ISDX_KEY_ENA,
VCAP_KF_ETYPE,
VCAP_KF_ETYPE_LEN_IS,
VCAP_KF_ETYPE_MPLS,
VCAP_KF_IF_EGR_PORT_MASK,
VCAP_KF_IF_EGR_PORT_MASK_RNG,
VCAP_KF_IF_IGR_PORT,
VCAP_KF_IF_IGR_PORT_MASK,
VCAP_KF_IF_IGR_PORT_MASK_L3,
VCAP_KF_IF_IGR_PORT_MASK_RNG,
VCAP_KF_IF_IGR_PORT_MASK_SEL,
VCAP_KF_IF_IGR_PORT_SEL,
VCAP_KF_IP4_IS,
VCAP_KF_IP_MC_IS,
VCAP_KF_IP_PAYLOAD_5TUPLE,
VCAP_KF_IP_SNAP_IS,
VCAP_KF_ISDX_CLS,
VCAP_KF_ISDX_GT0_IS,
VCAP_KF_L2_BC_IS,
......@@ -206,6 +378,9 @@ enum vcap_key_field {
VCAP_KF_L2_PAYLOAD_ETYPE,
VCAP_KF_L2_SMAC,
VCAP_KF_L3_DIP_EQ_SIP_IS,
VCAP_KF_L3_DMAC_DIP_MATCH,
VCAP_KF_L3_DPL_CLS,
VCAP_KF_L3_DSCP,
VCAP_KF_L3_DST_IS,
VCAP_KF_L3_FRAGMENT_TYPE,
VCAP_KF_L3_FRAG_INVLD_L4_LEN,
......@@ -217,6 +392,7 @@ enum vcap_key_field {
VCAP_KF_L3_OPTIONS_IS,
VCAP_KF_L3_PAYLOAD,
VCAP_KF_L3_RT_IS,
VCAP_KF_L3_SMAC_SIP_MATCH,
VCAP_KF_L3_TOS,
VCAP_KF_L3_TTL_GT0,
VCAP_KF_L4_ACK,
......@@ -232,95 +408,328 @@ enum vcap_key_field {
VCAP_KF_L4_SYN,
VCAP_KF_L4_URG,
VCAP_KF_LOOKUP_FIRST_IS,
VCAP_KF_LOOKUP_GEN_IDX,
VCAP_KF_LOOKUP_GEN_IDX_SEL,
VCAP_KF_LOOKUP_PAG,
VCAP_KF_MIRROR_ENA,
VCAP_KF_OAM_CCM_CNTS_EQ0,
VCAP_KF_OAM_MEL_FLAGS,
VCAP_KF_OAM_Y1731_IS,
VCAP_KF_PROT_ACTIVE,
VCAP_KF_TCP_IS,
VCAP_KF_TCP_UDP_IS,
VCAP_KF_TYPE,
VCAP_KF_HOST_MATCH,
VCAP_KF_L2_FRM_TYPE,
VCAP_KF_L2_PAYLOAD0,
VCAP_KF_L2_PAYLOAD1,
VCAP_KF_L2_PAYLOAD2,
VCAP_KF_L2_LLC,
VCAP_KF_L3_FRAGMENT,
VCAP_KF_L3_FRAG_OFS_GT0,
VCAP_KF_L2_SNAP,
VCAP_KF_L4_1588_DOM,
VCAP_KF_L4_1588_VER,
VCAP_KF_OAM_MEPID,
VCAP_KF_OAM_OPCODE,
VCAP_KF_OAM_VER,
VCAP_KF_OAM_FLAGS,
VCAP_KF_OAM_DETECTED,
};
/* Actionset names with origin information */
enum vcap_actionfield_set {
VCAP_AFS_NO_VALUE, /* initial value */
VCAP_AFS_BASE_TYPE, /* sparx5 is2 X3 */
VCAP_AFS_BASE_TYPE, /* sparx5 is2 X3, sparx5 es2 X3, lan966x is2 X2 */
VCAP_AFS_CLASSIFICATION, /* sparx5 is0 X2 */
VCAP_AFS_CLASS_REDUCED, /* sparx5 is0 X1 */
VCAP_AFS_FULL, /* sparx5 is0 X3 */
VCAP_AFS_MLBS, /* sparx5 is0 X2 */
VCAP_AFS_MLBS_REDUCED, /* sparx5 is0 X1 */
VCAP_AFS_SMAC_SIP, /* lan966x is2 x1 */
};
/* List of actionfields with description
*
* VCAP_AF_CNT_ID: W12, sparx5: is2
* VCAP_AF_CLS_VID_SEL: W3, sparx5: is0
* Controls the classified VID: 0: VID_NONE: No action. 1: VID_ADD: New VID =
* old VID + VID_VAL. 2: VID_REPLACE: New VID = VID_VAL. 3: VID_FIRST_TAG: New
* VID = VID from frame's first tag (outer tag) if available, otherwise VID_VAL.
* 4: VID_SECOND_TAG: New VID = VID from frame's second tag (middle tag) if
* available, otherwise VID_VAL. 5: VID_THIRD_TAG: New VID = VID from frame's
* third tag (inner tag) if available, otherwise VID_VAL.
* VCAP_AF_CNT_ID: sparx5 is2 W12, sparx5 es2 W11
* Counter ID, used per lookup to index the 4K frame counters (ANA_ACL:CNT_TBL).
* Multiple VCAP IS2 entries can use the same counter.
* VCAP_AF_CPU_COPY_ENA: W1, sparx5: is2
* VCAP_AF_COPY_PORT_NUM: W7, sparx5: es2
* QSYS port number when FWD_MODE is redirect or copy
* VCAP_AF_COPY_QUEUE_NUM: W16, sparx5: es2
* QSYS queue number when FWD_MODE is redirect or copy
* VCAP_AF_CPU_COPY_ENA: W1, sparx5: is2/es2, lan966x: is2
* Setting this bit to 1 causes all frames that hit this action to be copied to
* the CPU extraction queue specified in CPU_QUEUE_NUM.
* VCAP_AF_CPU_QUEUE_NUM: W3, sparx5: is2
* VCAP_AF_CPU_QUEUE_NUM: W3, sparx5: is2/es2, lan966x: is2
* CPU queue number. Used when CPU_COPY_ENA is set.
* VCAP_AF_HIT_ME_ONCE: W1, sparx5: is2
* VCAP_AF_DEI_ENA: W1, sparx5: is0
* If set, use DEI_VAL as classified DEI value. Otherwise, DEI from basic
* classification is used
* VCAP_AF_DEI_VAL: W1, sparx5: is0
* See DEI_ENA
* VCAP_AF_DP_ENA: W1, sparx5: is0
* If set, use DP_VAL as classified drop precedence level. Otherwise, drop
* precedence level from basic classification is used.
* VCAP_AF_DP_VAL: W2, sparx5: is0
* See DP_ENA.
* VCAP_AF_DSCP_ENA: W1, sparx5: is0
* If set, use DSCP_VAL as classified DSCP value. Otherwise, DSCP value from
* basic classification is used.
* VCAP_AF_DSCP_VAL: W6, sparx5: is0
* See DSCP_ENA.
* VCAP_AF_ES2_REW_CMD: W3, sparx5: es2
* Command forwarded to REW: 0: No action. 1: SWAP MAC addresses. 2: Do L2CP
* DMAC translation when entering or leaving a tunnel.
* VCAP_AF_FWD_MODE: W2, sparx5: es2
* Forward selector: 0: Forward. 1: Discard. 2: Redirect. 3: Copy.
* VCAP_AF_HIT_ME_ONCE: W1, sparx5: is2/es2, lan966x: is2
* Setting this bit to 1 causes the first frame that hits this action where the
* HIT_CNT counter is zero to be copied to the CPU extraction queue specified in
* CPU_QUEUE_NUM. The HIT_CNT counter is then incremented and any frames that
* hit this action later are not copied to the CPU. To re-enable the HIT_ME_ONCE
* functionality, the HIT_CNT counter must be cleared.
* VCAP_AF_IGNORE_PIPELINE_CTRL: W1, sparx5: is2
* VCAP_AF_IGNORE_PIPELINE_CTRL: W1, sparx5: is2/es2
* Ignore ingress pipeline control. This enforces the use of the VCAP IS2 action
* even when the pipeline control has terminated the frame before VCAP IS2.
* VCAP_AF_INTR_ENA: W1, sparx5: is2
* VCAP_AF_INTR_ENA: W1, sparx5: is2/es2
* If set, an interrupt is triggered when this rule is hit
* VCAP_AF_LRN_DIS: W1, sparx5: is2
* VCAP_AF_ISDX_ADD_REPLACE_SEL: W1, sparx5: is0
* Controls the classified ISDX. 0: New ISDX = old ISDX + ISDX_VAL. 1: New ISDX
* = ISDX_VAL.
* VCAP_AF_ISDX_VAL: W12, sparx5: is0
* See isdx_add_replace_sel
* VCAP_AF_LRN_DIS: W1, sparx5: is2, lan966x: is2
* Setting this bit to 1 disables learning of frames hitting this action.
* VCAP_AF_MASK_MODE: W3, sparx5: is2
* VCAP_AF_MAP_IDX: W9, sparx5: is0
* Index for QoS mapping table lookup
* VCAP_AF_MAP_KEY: W3, sparx5: is0
* Key type for QoS mapping table lookup. 0: DEI0, PCP0 (outer tag). 1: DEI1,
* PCP1 (middle tag). 2: DEI2, PCP2 (inner tag). 3: MPLS TC. 4: PCP0 (outer
* tag). 5: E-DEI, E-PCP (E-TAG). 6: DSCP if available, otherwise none. 7: DSCP
* if available, otherwise DEI0, PCP0 (outer tag) if available using MAP_IDX+8,
* otherwise none
* VCAP_AF_MAP_LOOKUP_SEL: W2, sparx5: is0
* Selects which of the two QoS Mapping Table lookups that MAP_KEY and MAP_IDX
* are applied to. 0: No changes to the QoS Mapping Table lookup. 1: Update key
* type and index for QoS Mapping Table lookup #0. 2: Update key type and index
* for QoS Mapping Table lookup #1. 3: Reserved.
* VCAP_AF_MASK_MODE: W3, sparx5: is0/is2, lan966x is2 W2
* Controls the PORT_MASK use. Sparx5: 0: OR_DSTMASK, 1: AND_VLANMASK, 2:
* REPLACE_PGID, 3: REPLACE_ALL, 4: REDIR_PGID, 5: OR_PGID_MASK, 6: VSTAX, 7:
* Not applicable. LAN966X: 0: No action, 1: Permit/deny (AND), 2: Policy
* forwarding (DMAC lookup), 3: Redirect. The CPU port is untouched by
* MASK_MODE.
* VCAP_AF_MATCH_ID: W16, sparx5: is2
* VCAP_AF_MATCH_ID: W16, sparx5: is0/is2
* Logical ID for the entry. The MATCH_ID is extracted together with the frame
* if the frame is forwarded to the CPU (CPU_COPY_ENA). The result is placed in
* IFH.CL_RSLT.
* VCAP_AF_MATCH_ID_MASK: W16, sparx5: is2
* VCAP_AF_MATCH_ID_MASK: W16, sparx5: is0/is2
* Mask used by MATCH_ID.
* VCAP_AF_MIRROR_PROBE: W2, sparx5: is2
* Mirroring performed according to configuration of a mirror probe. 0: No
* mirroring. 1: Mirror probe 0. 2: Mirror probe 1. 3: Mirror probe 2
* VCAP_AF_PIPELINE_FORCE_ENA: W1, sparx5: is2
* VCAP_AF_MIRROR_PROBE_ID: W2, sparx5: es2
* Signals a mirror probe to be placed in the IFH. Only possible when FWD_MODE
* is copy. 0: No mirroring. 1–3: Use mirror probe 0-2.
* VCAP_AF_NXT_IDX: W12, sparx5: is0
* Index used as part of key (field G_IDX) in the next lookup.
* VCAP_AF_NXT_IDX_CTRL: W3, sparx5: is0
* Controls the generation of the G_IDX used in the VCAP CLM next lookup
* VCAP_AF_PAG_OVERRIDE_MASK: W8, sparx5: is0
* Bits set in this mask will override PAG_VAL from port profile.  New PAG =
* (PAG (input) AND ~PAG_OVERRIDE_MASK) OR (PAG_VAL AND PAG_OVERRIDE_MASK)
* VCAP_AF_PAG_VAL: W8, sparx5: is0
* See PAG_OVERRIDE_MASK.
* VCAP_AF_PCP_ENA: W1, sparx5: is0
* If set, use PCP_VAL as classified PCP value. Otherwise, PCP from basic
* classification is used.
* VCAP_AF_PCP_VAL: W3, sparx5: is0
* See PCP_ENA.
* VCAP_AF_PIPELINE_FORCE_ENA: sparx5 is0 W2, sparx5 is2 W1
* If set, use PIPELINE_PT unconditionally and set PIPELINE_ACT = NONE if
* PIPELINE_PT == NONE. Overrules previous settings of pipeline point.
* VCAP_AF_PIPELINE_PT: W5, sparx5: is2
* VCAP_AF_PIPELINE_PT: W5, sparx5: is0/is2
* Pipeline point used if PIPELINE_FORCE_ENA is set
* VCAP_AF_POLICE_ENA: W1, sparx5: is2
* VCAP_AF_POLICE_ENA: W1, sparx5: is2/es2, lan966x: is2
* Setting this bit to 1 causes frames that hit this action to be policed by the
* ACL policer specified in POLICE_IDX. Only applies to the first lookup.
* VCAP_AF_POLICE_IDX: W6, sparx5: is2
* VCAP_AF_POLICE_IDX: W6, sparx5: is2/es2, lan966x: is2 W9
* Selects VCAP policer used when policing frames (POLICE_ENA)
* VCAP_AF_PORT_MASK: W68, sparx5: is2
* VCAP_AF_POLICE_REMARK: W1, sparx5: es2
* If set, frames exceeding policer rates are marked as yellow but not
* discarded.
* VCAP_AF_PORT_MASK: sparx5 is0 W65, sparx5 is2 W68, lan966x is2 W8
* Port mask applied to the forwarding decision based on MASK_MODE.
* VCAP_AF_QOS_ENA: W1, sparx5: is0
* If set, use QOS_VAL as classified QoS class. Otherwise, QoS class from basic
* classification is used.
* VCAP_AF_QOS_VAL: W3, sparx5: is0
* See QOS_ENA.
* VCAP_AF_RT_DIS: W1, sparx5: is2
* If set, routing is disallowed. Only applies when IS_INNER_ACL is 0. See also
* IGR_ACL_ENA, EGR_ACL_ENA, and RLEG_STAT_IDX.
* VCAP_AF_TYPE: W1, sparx5: is0
* Actionset type id - Set by the API
* VCAP_AF_VID_VAL: W13, sparx5: is0
* New VID Value
* VCAP_AF_MIRROR_ENA: W1, lan966x: is2
* Setting this bit to 1 causes frames to be mirrored to the mirror target
* port (ANA::MIRRPORPORTS).
* VCAP_AF_POLICE_VCAP_ONLY: W1, lan966x: is2
* Disable policing from QoS, and port policers. Only the VCAP policer
* selected by POLICE_IDX is active. Only applies to the second lookup.
* VCAP_AF_REW_OP: W16, lan966x: is2
* Rewriter operation command.
* VCAP_AF_ISDX_ENA: W1, lan966x: is2
* Setting this bit to 1 causes the classified ISDX to be set to the value of
* POLICE_IDX[8:0].
* VCAP_AF_ACL_ID: W6, lan966x: is2
* Logical ID for the entry. This ID is extracted together with the frame in
* the CPU extraction header. Only applicable to actions with CPU_COPY_ENA or
* HIT_ME_ONCE set.
* VCAP_AF_FWD_KILL_ENA: W1, lan966x: is2
* Setting this bit to 1 denies forwarding of the frame forwarding to any
* front port. The frame can still be copied to the CPU by other actions.
* VCAP_AF_HOST_MATCH: W1, lan966x: is2
* Used for IP source guarding. If set, it signals that the host is a valid
* (for instance a valid combination of source MAC address and source IP
* address). HOST_MATCH is input to the IS2 keys.
*/
/* Actionfield names */
enum vcap_action_field {
VCAP_AF_NO_VALUE, /* initial value */
VCAP_AF_ACL_MAC,
VCAP_AF_ACL_RT_MODE,
VCAP_AF_CLS_VID_SEL,
VCAP_AF_CNT_ID,
VCAP_AF_COPY_PORT_NUM,
VCAP_AF_COPY_QUEUE_NUM,
VCAP_AF_COSID_ENA,
VCAP_AF_COSID_VAL,
VCAP_AF_CPU_COPY_ENA,
VCAP_AF_CPU_DIS,
VCAP_AF_CPU_ENA,
VCAP_AF_CPU_Q,
VCAP_AF_CPU_QUEUE_NUM,
VCAP_AF_CUSTOM_ACE_ENA,
VCAP_AF_CUSTOM_ACE_OFFSET,
VCAP_AF_DEI_ENA,
VCAP_AF_DEI_VAL,
VCAP_AF_DLB_OFFSET,
VCAP_AF_DMAC_OFFSET_ENA,
VCAP_AF_DP_ENA,
VCAP_AF_DP_VAL,
VCAP_AF_DSCP_ENA,
VCAP_AF_DSCP_VAL,
VCAP_AF_EGR_ACL_ENA,
VCAP_AF_ES2_REW_CMD,
VCAP_AF_FWD_DIS,
VCAP_AF_FWD_MODE,
VCAP_AF_FWD_TYPE,
VCAP_AF_GVID_ADD_REPLACE_SEL,
VCAP_AF_HIT_ME_ONCE,
VCAP_AF_IGNORE_PIPELINE_CTRL,
VCAP_AF_IGR_ACL_ENA,
VCAP_AF_INJ_MASQ_ENA,
VCAP_AF_INJ_MASQ_LPORT,
VCAP_AF_INJ_MASQ_PORT,
VCAP_AF_INTR_ENA,
VCAP_AF_ISDX_ADD_REPLACE_SEL,
VCAP_AF_ISDX_VAL,
VCAP_AF_IS_INNER_ACL,
VCAP_AF_L3_MAC_UPDATE_DIS,
VCAP_AF_LOG_MSG_INTERVAL,
VCAP_AF_LPM_AFFIX_ENA,
VCAP_AF_LPM_AFFIX_VAL,
VCAP_AF_LPORT_ENA,
VCAP_AF_LRN_DIS,
VCAP_AF_MAP_IDX,
VCAP_AF_MAP_KEY,
VCAP_AF_MAP_LOOKUP_SEL,
VCAP_AF_MASK_MODE,
VCAP_AF_MATCH_ID,
VCAP_AF_MATCH_ID_MASK,
VCAP_AF_MIP_SEL,
VCAP_AF_MIRROR_PROBE,
VCAP_AF_MIRROR_PROBE_ID,
VCAP_AF_MPLS_IP_CTRL_ENA,
VCAP_AF_MPLS_MEP_ENA,
VCAP_AF_MPLS_MIP_ENA,
VCAP_AF_MPLS_OAM_FLAVOR,
VCAP_AF_MPLS_OAM_TYPE,
VCAP_AF_NUM_VLD_LABELS,
VCAP_AF_NXT_IDX,
VCAP_AF_NXT_IDX_CTRL,
VCAP_AF_NXT_KEY_TYPE,
VCAP_AF_NXT_NORMALIZE,
VCAP_AF_NXT_NORM_W16_OFFSET,
VCAP_AF_NXT_NORM_W32_OFFSET,
VCAP_AF_NXT_OFFSET_FROM_TYPE,
VCAP_AF_NXT_TYPE_AFTER_OFFSET,
VCAP_AF_OAM_IP_BFD_ENA,
VCAP_AF_OAM_TWAMP_ENA,
VCAP_AF_OAM_Y1731_SEL,
VCAP_AF_PAG_OVERRIDE_MASK,
VCAP_AF_PAG_VAL,
VCAP_AF_PCP_ENA,
VCAP_AF_PCP_VAL,
VCAP_AF_PIPELINE_ACT_SEL,
VCAP_AF_PIPELINE_FORCE_ENA,
VCAP_AF_PIPELINE_PT,
VCAP_AF_PIPELINE_PT_REDUCED,
VCAP_AF_POLICE_ENA,
VCAP_AF_POLICE_IDX,
VCAP_AF_POLICE_REMARK,
VCAP_AF_PORT_MASK,
VCAP_AF_PTP_MASTER_SEL,
VCAP_AF_QOS_ENA,
VCAP_AF_QOS_VAL,
VCAP_AF_REW_CMD,
VCAP_AF_RLEG_DMAC_CHK_DIS,
VCAP_AF_RLEG_STAT_IDX,
VCAP_AF_RSDX_ENA,
VCAP_AF_RSDX_VAL,
VCAP_AF_RSVD_LBL_VAL,
VCAP_AF_RT_DIS,
VCAP_AF_RT_SEL,
VCAP_AF_S2_KEY_SEL_ENA,
VCAP_AF_S2_KEY_SEL_IDX,
VCAP_AF_SAM_SEQ_ENA,
VCAP_AF_SIP_IDX,
VCAP_AF_SWAP_MAC_ENA,
VCAP_AF_TCP_UDP_DPORT,
VCAP_AF_TCP_UDP_ENA,
VCAP_AF_TCP_UDP_SPORT,
VCAP_AF_TC_ENA,
VCAP_AF_TC_LABEL,
VCAP_AF_TPID_SEL,
VCAP_AF_TTL_DECR_DIS,
VCAP_AF_TTL_ENA,
VCAP_AF_TTL_LABEL,
VCAP_AF_TTL_UPDATE_ENA,
VCAP_AF_TYPE,
VCAP_AF_VID_VAL,
VCAP_AF_VLAN_POP_CNT,
VCAP_AF_VLAN_POP_CNT_ENA,
VCAP_AF_VLAN_PUSH_CNT,
VCAP_AF_VLAN_PUSH_CNT_ENA,
VCAP_AF_VLAN_WAS_TAGGED,
VCAP_AF_MIRROR_ENA,
VCAP_AF_POLICE_VCAP_ONLY,
VCAP_AF_REW_OP,
VCAP_AF_ISDX_ENA,
VCAP_AF_ACL_ID,
VCAP_AF_FWD_KILL_ENA,
VCAP_AF_HOST_MATCH,
};
#endif /* __VCAP_AG_API__ */
drivers/net/ethernet/microchip/vcap/vcap_ag_api_kunit.h deleted 100644 → 0
View file @ 7a168f56
/* SPDX-License-Identifier: BSD-3-Clause */
/* Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries.
* Microchip VCAP API interface for kunit testing
* This is a different interface, to be able to include different VCAPs
*/
/* Use same include guard as the official API to be able to override it */
#ifndef __VCAP_AG_API__
#define __VCAP_AG_API__
enum vcap_type {
VCAP_TYPE_ES2,
VCAP_TYPE_IS0,
VCAP_TYPE_IS2,
VCAP_TYPE_MAX
};
/* Keyfieldset names with origin information */
enum vcap_keyfield_set {
VCAP_KFS_NO_VALUE, /* initial value */
VCAP_KFS_ARP, /* sparx5 is2 X6, sparx5 es2 X6 */
VCAP_KFS_ETAG, /* sparx5 is0 X2 */
VCAP_KFS_IP4_OTHER, /* sparx5 is2 X6, sparx5 es2 X6 */
VCAP_KFS_IP4_TCP_UDP, /* sparx5 is2 X6, sparx5 es2 X6 */
VCAP_KFS_IP4_VID, /* sparx5 es2 X3 */
VCAP_KFS_IP6_STD, /* sparx5 is2 X6 */
VCAP_KFS_IP6_VID, /* sparx5 is2 X6, sparx5 es2 X6 */
VCAP_KFS_IP_7TUPLE, /* sparx5 is2 X12, sparx5 es2 X12 */
VCAP_KFS_LL_FULL, /* sparx5 is0 X6 */
VCAP_KFS_MAC_ETYPE, /* sparx5 is2 X6, sparx5 es2 X6 */
VCAP_KFS_MLL, /* sparx5 is0 X3 */
VCAP_KFS_NORMAL, /* sparx5 is0 X6 */
VCAP_KFS_NORMAL_5TUPLE_IP4, /* sparx5 is0 X6 */
VCAP_KFS_NORMAL_7TUPLE, /* sparx5 is0 X12 */
VCAP_KFS_PURE_5TUPLE_IP4, /* sparx5 is0 X3 */
VCAP_KFS_TRI_VID, /* sparx5 is0 X2 */
};
/* List of keyfields with description
*
* Keys ending in _IS are booleans derived from frame data
* Keys ending in _CLS are classified frame data
*
* VCAP_KF_8021BR_ECID_BASE: W12, sparx5: is0
* Used by 802.1BR Bridge Port Extension in an E-Tag
* VCAP_KF_8021BR_ECID_EXT: W8, sparx5: is0
* Used by 802.1BR Bridge Port Extension in an E-Tag
* VCAP_KF_8021BR_E_TAGGED: W1, sparx5: is0
* Set for frames containing an E-TAG (802.1BR Ethertype 893f)
* VCAP_KF_8021BR_GRP: W2, sparx5: is0
* E-Tag group bits in 802.1BR Bridge Port Extension
* VCAP_KF_8021BR_IGR_ECID_BASE: W12, sparx5: is0
* Used by 802.1BR Bridge Port Extension in an E-Tag
* VCAP_KF_8021BR_IGR_ECID_EXT: W8, sparx5: is0
* Used by 802.1BR Bridge Port Extension in an E-Tag
* VCAP_KF_8021Q_DEI0: W1, sparx5: is0
* First DEI in multiple vlan tags (outer tag or default port tag)
* VCAP_KF_8021Q_DEI1: W1, sparx5: is0
* Second DEI in multiple vlan tags (inner tag)
* VCAP_KF_8021Q_DEI2: W1, sparx5: is0
* Third DEI in multiple vlan tags (not always available)
* VCAP_KF_8021Q_DEI_CLS: W1, sparx5: is2/es2
* Classified DEI
* VCAP_KF_8021Q_PCP0: W3, sparx5: is0
* First PCP in multiple vlan tags (outer tag or default port tag)
* VCAP_KF_8021Q_PCP1: W3, sparx5: is0
* Second PCP in multiple vlan tags (inner tag)
* VCAP_KF_8021Q_PCP2: W3, sparx5: is0
* Third PCP in multiple vlan tags (not always available)
* VCAP_KF_8021Q_PCP_CLS: W3, sparx5: is2/es2
* Classified PCP
* VCAP_KF_8021Q_TPID0: W3, sparx5: is0
* First TPIC in multiple vlan tags (outer tag or default port tag)
* VCAP_KF_8021Q_TPID1: W3, sparx5: is0
* Second TPID in multiple vlan tags (inner tag)
* VCAP_KF_8021Q_TPID2: W3, sparx5: is0
* Third TPID in multiple vlan tags (not always available)
* VCAP_KF_8021Q_VID0: W12, sparx5: is0
* First VID in multiple vlan tags (outer tag or default port tag)
* VCAP_KF_8021Q_VID1: W12, sparx5: is0
* Second VID in multiple vlan tags (inner tag)
* VCAP_KF_8021Q_VID2: W12, sparx5: is0
* Third VID in multiple vlan tags (not always available)
* VCAP_KF_8021Q_VID_CLS: W13, sparx5: is2/es2
* Classified VID
* VCAP_KF_8021Q_VLAN_TAGGED_IS: W1, sparx5: is2/es2
* Sparx5: Set if frame was received with a VLAN tag, LAN966x: Set if frame has
* one or more Q-tags. Independent of port VLAN awareness
* VCAP_KF_8021Q_VLAN_TAGS: W3, sparx5: is0
* Number of VLAN tags in frame: 0: Untagged, 1: Single tagged, 3: Double
* tagged, 7: Triple tagged
* VCAP_KF_ACL_GRP_ID: W8, sparx5: es2
* Used in interface map table
* VCAP_KF_ARP_ADDR_SPACE_OK_IS: W1, sparx5: is2/es2
* Set if hardware address is Ethernet
* VCAP_KF_ARP_LEN_OK_IS: W1, sparx5: is2/es2
* Set if hardware address length = 6 (Ethernet) and IP address length = 4 (IP).
* VCAP_KF_ARP_OPCODE: W2, sparx5: is2/es2
* ARP opcode
* VCAP_KF_ARP_OPCODE_UNKNOWN_IS: W1, sparx5: is2/es2
* Set if not one of the codes defined in VCAP_KF_ARP_OPCODE
* VCAP_KF_ARP_PROTO_SPACE_OK_IS: W1, sparx5: is2/es2
* Set if protocol address space is 0x0800
* VCAP_KF_ARP_SENDER_MATCH_IS: W1, sparx5: is2/es2
* Sender Hardware Address = SMAC (ARP)
* VCAP_KF_ARP_TGT_MATCH_IS: W1, sparx5: is2/es2
* Target Hardware Address = SMAC (RARP)
* VCAP_KF_COSID_CLS: W3, sparx5: es2
* Class of service
* VCAP_KF_DST_ENTRY: W1, sparx5: is0
* Selects whether the frame’s destination or source information is used for
* fields L2_SMAC and L3_IP4_SIP
* VCAP_KF_ES0_ISDX_KEY_ENA: W1, sparx5: es2
* The value taken from the IFH .FWD.ES0_ISDX_KEY_ENA
* VCAP_KF_ETYPE: W16, sparx5: is0/is2/es2
* Ethernet type
* VCAP_KF_ETYPE_LEN_IS: W1, sparx5: is0/is2/es2
* Set if frame has EtherType >= 0x600
* VCAP_KF_ETYPE_MPLS: W2, sparx5: is0
* Type of MPLS Ethertype (or not)
* VCAP_KF_IF_EGR_PORT_MASK: W32, sparx5: es2
* Egress port mask, one bit per port
* VCAP_KF_IF_EGR_PORT_MASK_RNG: W3, sparx5: es2
* Select which 32 port group is available in IF_EGR_PORT (or virtual ports or
* CPU queue)
* VCAP_KF_IF_IGR_PORT: sparx5 is0 W7, sparx5 es2 W9
* Sparx5: Logical ingress port number retrieved from
* ANA_CL::PORT_ID_CFG.LPORT_NUM or ERLEG, LAN966x: ingress port nunmber
* VCAP_KF_IF_IGR_PORT_MASK: sparx5 is0 W65, sparx5 is2 W32, sparx5 is2 W65
* Ingress port mask, one bit per port/erleg
* VCAP_KF_IF_IGR_PORT_MASK_L3: W1, sparx5: is2
* If set, IF_IGR_PORT_MASK, IF_IGR_PORT_MASK_RNG, and IF_IGR_PORT_MASK_SEL are
* used to specify L3 interfaces
* VCAP_KF_IF_IGR_PORT_MASK_RNG: W4, sparx5: is2
* Range selector for IF_IGR_PORT_MASK. Specifies which group of 32 ports are
* available in IF_IGR_PORT_MASK
* VCAP_KF_IF_IGR_PORT_MASK_SEL: W2, sparx5: is0/is2
* Mode selector for IF_IGR_PORT_MASK, applicable when IF_IGR_PORT_MASK_L3 == 0.
* Mapping: 0: DEFAULT 1: LOOPBACK 2: MASQUERADE 3: CPU_VD
* VCAP_KF_IF_IGR_PORT_SEL: W1, sparx5: es2
* Selector for IF_IGR_PORT: physical port number or ERLEG
* VCAP_KF_IP4_IS: W1, sparx5: is0/is2/es2
* Set if frame has EtherType = 0x800 and IP version = 4
* VCAP_KF_IP_MC_IS: W1, sparx5: is0
* Set if frame is IPv4 frame and frame’s destination MAC address is an IPv4
* multicast address (0x01005E0 /25). Set if frame is IPv6 frame and frame’s
* destination MAC address is an IPv6 multicast address (0x3333/16).
* VCAP_KF_IP_PAYLOAD_5TUPLE: W32, sparx5: is0
* Payload bytes after IP header
* VCAP_KF_IP_SNAP_IS: W1, sparx5: is0
* Set if frame is IPv4, IPv6, or SNAP frame
* VCAP_KF_ISDX_CLS: W12, sparx5: is2/es2
* Classified ISDX
* VCAP_KF_ISDX_GT0_IS: W1, sparx5: is2/es2
* Set if classified ISDX > 0
* VCAP_KF_L2_BC_IS: W1, sparx5: is0/is2/es2
* Set if frame’s destination MAC address is the broadcast address
* (FF-FF-FF-FF-FF-FF).
* VCAP_KF_L2_DMAC: W48, sparx5: is0/is2/es2
* Destination MAC address
* VCAP_KF_L2_FWD_IS: W1, sparx5: is2
* Set if the frame is allowed to be forwarded to front ports
* VCAP_KF_L2_MC_IS: W1, sparx5: is0/is2/es2
* Set if frame’s destination MAC address is a multicast address (bit 40 = 1).
* VCAP_KF_L2_PAYLOAD_ETYPE: W64, sparx5: is2/es2
* Byte 0-7 of L2 payload after Type/Len field and overloading for OAM
* VCAP_KF_L2_SMAC: W48, sparx5: is0/is2/es2
* Source MAC address
* VCAP_KF_L3_DIP_EQ_SIP_IS: W1, sparx5: is2/es2
* Set if Src IP matches Dst IP address
* VCAP_KF_L3_DMAC_DIP_MATCH: W1, sparx5: is2
* Match found in DIP security lookup in ANA_L3
* VCAP_KF_L3_DPL_CLS: W1, sparx5: es2
* The frames drop precedence level
* VCAP_KF_L3_DSCP: W6, sparx5: is0
* Frame’s DSCP value
* VCAP_KF_L3_DST_IS: W1, sparx5: is2
* Set if lookup is done for egress router leg
* VCAP_KF_L3_FRAGMENT_TYPE: W2, sparx5: is0/is2/es2
* L3 Fragmentation type (none, initial, suspicious, valid follow up)
* VCAP_KF_L3_FRAG_INVLD_L4_LEN: W1, sparx5: is0/is2
* Set if frame's L4 length is less than ANA_CL:COMMON:CLM_FRAGMENT_CFG.L4_MIN_L
* EN
* VCAP_KF_L3_IP4_DIP: W32, sparx5: is0/is2/es2
* Destination IPv4 Address
* VCAP_KF_L3_IP4_SIP: W32, sparx5: is0/is2/es2
* Source IPv4 Address
* VCAP_KF_L3_IP6_DIP: W128, sparx5: is0/is2/es2
* Sparx5: Full IPv6 DIP, LAN966x: Either Full IPv6 DIP or a subset depending on
* frame type
* VCAP_KF_L3_IP6_SIP: W128, sparx5: is0/is2/es2
* Sparx5: Full IPv6 SIP, LAN966x: Either Full IPv6 SIP or a subset depending on
* frame type
* VCAP_KF_L3_IP_PROTO: W8, sparx5: is0/is2/es2
* IPv4 frames: IP protocol. IPv6 frames: Next header, same as for IPV4
* VCAP_KF_L3_OPTIONS_IS: W1, sparx5: is0/is2/es2
* Set if IPv4 frame contains options (IP len > 5)
* VCAP_KF_L3_PAYLOAD: sparx5 is2 W96, sparx5 is2 W40, sparx5 es2 W96
* Sparx5: Payload bytes after IP header. IPv4: IPv4 options are not parsed so
* payload is always taken 20 bytes after the start of the IPv4 header, LAN966x:
* Bytes 0-6 after IP header
* VCAP_KF_L3_RT_IS: W1, sparx5: is2/es2
* Set if frame has hit a router leg
* VCAP_KF_L3_SMAC_SIP_MATCH: W1, sparx5: is2
* Match found in SIP security lookup in ANA_L3
* VCAP_KF_L3_TOS: W8, sparx5: is2/es2
* Sparx5: Frame's IPv4/IPv6 DSCP and ECN fields, LAN966x: IP TOS field
* VCAP_KF_L3_TTL_GT0: W1, sparx5: is2/es2
* Set if IPv4 TTL / IPv6 hop limit is greater than 0
* VCAP_KF_L4_ACK: W1, sparx5: is2/es2
* Sparx5 and LAN966x: TCP flag ACK, LAN966x only: PTP over UDP: flagField bit 2
* (unicastFlag)
* VCAP_KF_L4_DPORT: W16, sparx5: is2/es2
* Sparx5: TCP/UDP destination port. Overloading for IP_7TUPLE: Non-TCP/UDP IP
* frames: L4_DPORT = L3_IP_PROTO, LAN966x: TCP/UDP destination port
* VCAP_KF_L4_FIN: W1, sparx5: is2/es2
* TCP flag FIN, LAN966x: TCP flag FIN, and for PTP over UDP: messageType bit 1
* VCAP_KF_L4_PAYLOAD: W64, sparx5: is2/es2
* Payload bytes after TCP/UDP header Overloading for IP_7TUPLE: Non TCP/UDP
* frames: Payload bytes 0–7 after IP header. IPv4 options are not parsed so
* payload is always taken 20 bytes after the start of the IPv4 header for non
* TCP/UDP IPv4 frames
* VCAP_KF_L4_PSH: W1, sparx5: is2/es2
* Sparx5: TCP flag PSH, LAN966x: TCP: TCP flag PSH. PTP over UDP: flagField bit
* 1 (twoStepFlag)
* VCAP_KF_L4_RNG: sparx5 is0 W8, sparx5 is2 W16, sparx5 es2 W16
* Range checker bitmask (one for each range checker). Input into range checkers
* is taken from classified results (VID, DSCP) and frame (SPORT, DPORT, ETYPE,
* outer VID, inner VID)
* VCAP_KF_L4_RST: W1, sparx5: is2/es2
* Sparx5: TCP flag RST , LAN966x: TCP: TCP flag RST. PTP over UDP: messageType
* bit 3
* VCAP_KF_L4_SEQUENCE_EQ0_IS: W1, sparx5: is2/es2
* Set if TCP sequence number is 0, LAN966x: Overlayed with PTP over UDP:
* messageType bit 0
* VCAP_KF_L4_SPORT: W16, sparx5: is0/is2/es2
* TCP/UDP source port
* VCAP_KF_L4_SPORT_EQ_DPORT_IS: W1, sparx5: is2/es2
* Set if UDP or TCP source port equals UDP or TCP destination port
* VCAP_KF_L4_SYN: W1, sparx5: is2/es2
* Sparx5: TCP flag SYN, LAN966x: TCP: TCP flag SYN. PTP over UDP: messageType
* bit 2
* VCAP_KF_L4_URG: W1, sparx5: is2/es2
* Sparx5: TCP flag URG, LAN966x: TCP: TCP flag URG. PTP over UDP: flagField bit
* 7 (reserved)
* VCAP_KF_LOOKUP_FIRST_IS: W1, sparx5: is0/is2/es2
* Selects between entries relevant for first and second lookup. Set for first
* lookup, cleared for second lookup.
* VCAP_KF_LOOKUP_GEN_IDX: W12, sparx5: is0
* Generic index - for chaining CLM instances
* VCAP_KF_LOOKUP_GEN_IDX_SEL: W2, sparx5: is0
* Select the mode of the Generic Index
* VCAP_KF_LOOKUP_PAG: W8, sparx5: is2
* Classified Policy Association Group: chains rules from IS1/CLM to IS2
* VCAP_KF_OAM_CCM_CNTS_EQ0: W1, sparx5: is2/es2
* Dual-ended loss measurement counters in CCM frames are all zero
* VCAP_KF_OAM_MEL_FLAGS: W7, sparx5: is0
* Encoding of MD level/MEG level (MEL)
* VCAP_KF_OAM_Y1731_IS: W1, sparx5: is0/is2/es2
* Set if frame’s EtherType = 0x8902
* VCAP_KF_PROT_ACTIVE: W1, sparx5: es2
* Protection is active
* VCAP_KF_TCP_IS: W1, sparx5: is0/is2/es2
* Set if frame is IPv4 TCP frame (IP protocol = 6) or IPv6 TCP frames (Next
* header = 6)
* VCAP_KF_TCP_UDP_IS: W1, sparx5: is0/is2/es2
* Set if frame is IPv4/IPv6 TCP or UDP frame (IP protocol/next header equals 6
* or 17)
* VCAP_KF_TYPE: sparx5 is0 W2, sparx5 is0 W1, sparx5 is2 W4, sparx5 is2 W2,
* sparx5 es2 W3
* Keyset type id - set by the API
*/
/* Keyfield names */
enum vcap_key_field {
VCAP_KF_NO_VALUE, /* initial value */
VCAP_KF_8021BR_ECID_BASE,
VCAP_KF_8021BR_ECID_EXT,
VCAP_KF_8021BR_E_TAGGED,
VCAP_KF_8021BR_GRP,
VCAP_KF_8021BR_IGR_ECID_BASE,
VCAP_KF_8021BR_IGR_ECID_EXT,
VCAP_KF_8021Q_DEI0,
VCAP_KF_8021Q_DEI1,
VCAP_KF_8021Q_DEI2,
VCAP_KF_8021Q_DEI_CLS,
VCAP_KF_8021Q_PCP0,
VCAP_KF_8021Q_PCP1,
VCAP_KF_8021Q_PCP2,
VCAP_KF_8021Q_PCP_CLS,
VCAP_KF_8021Q_TPID0,
VCAP_KF_8021Q_TPID1,
VCAP_KF_8021Q_TPID2,
VCAP_KF_8021Q_VID0,
VCAP_KF_8021Q_VID1,
VCAP_KF_8021Q_VID2,
VCAP_KF_8021Q_VID_CLS,
VCAP_KF_8021Q_VLAN_TAGGED_IS,
VCAP_KF_8021Q_VLAN_TAGS,
VCAP_KF_ACL_GRP_ID,
VCAP_KF_ARP_ADDR_SPACE_OK_IS,
VCAP_KF_ARP_LEN_OK_IS,
VCAP_KF_ARP_OPCODE,
VCAP_KF_ARP_OPCODE_UNKNOWN_IS,
VCAP_KF_ARP_PROTO_SPACE_OK_IS,
VCAP_KF_ARP_SENDER_MATCH_IS,
VCAP_KF_ARP_TGT_MATCH_IS,
VCAP_KF_COSID_CLS,
VCAP_KF_DST_ENTRY,
VCAP_KF_ES0_ISDX_KEY_ENA,
VCAP_KF_ETYPE,
VCAP_KF_ETYPE_LEN_IS,
VCAP_KF_ETYPE_MPLS,
VCAP_KF_IF_EGR_PORT_MASK,
VCAP_KF_IF_EGR_PORT_MASK_RNG,
VCAP_KF_IF_IGR_PORT,
VCAP_KF_IF_IGR_PORT_MASK,
VCAP_KF_IF_IGR_PORT_MASK_L3,
VCAP_KF_IF_IGR_PORT_MASK_RNG,
VCAP_KF_IF_IGR_PORT_MASK_SEL,
VCAP_KF_IF_IGR_PORT_SEL,
VCAP_KF_IP4_IS,
VCAP_KF_IP_MC_IS,
VCAP_KF_IP_PAYLOAD_5TUPLE,
VCAP_KF_IP_SNAP_IS,
VCAP_KF_ISDX_CLS,
VCAP_KF_ISDX_GT0_IS,
VCAP_KF_L2_BC_IS,
VCAP_KF_L2_DMAC,
VCAP_KF_L2_FWD_IS,
VCAP_KF_L2_MC_IS,
VCAP_KF_L2_PAYLOAD_ETYPE,
VCAP_KF_L2_SMAC,
VCAP_KF_L3_DIP_EQ_SIP_IS,
VCAP_KF_L3_DMAC_DIP_MATCH,
VCAP_KF_L3_DPL_CLS,
VCAP_KF_L3_DSCP,
VCAP_KF_L3_DST_IS,
VCAP_KF_L3_FRAGMENT_TYPE,
VCAP_KF_L3_FRAG_INVLD_L4_LEN,
VCAP_KF_L3_IP4_DIP,
VCAP_KF_L3_IP4_SIP,
VCAP_KF_L3_IP6_DIP,
VCAP_KF_L3_IP6_SIP,
VCAP_KF_L3_IP_PROTO,
VCAP_KF_L3_OPTIONS_IS,
VCAP_KF_L3_PAYLOAD,
VCAP_KF_L3_RT_IS,
VCAP_KF_L3_SMAC_SIP_MATCH,
VCAP_KF_L3_TOS,
VCAP_KF_L3_TTL_GT0,
VCAP_KF_L4_ACK,
VCAP_KF_L4_DPORT,
VCAP_KF_L4_FIN,
VCAP_KF_L4_PAYLOAD,
VCAP_KF_L4_PSH,
VCAP_KF_L4_RNG,
VCAP_KF_L4_RST,
VCAP_KF_L4_SEQUENCE_EQ0_IS,
VCAP_KF_L4_SPORT,
VCAP_KF_L4_SPORT_EQ_DPORT_IS,
VCAP_KF_L4_SYN,
VCAP_KF_L4_URG,
VCAP_KF_LOOKUP_FIRST_IS,
VCAP_KF_LOOKUP_GEN_IDX,
VCAP_KF_LOOKUP_GEN_IDX_SEL,
VCAP_KF_LOOKUP_PAG,
VCAP_KF_MIRROR_ENA,
VCAP_KF_OAM_CCM_CNTS_EQ0,
VCAP_KF_OAM_MEL_FLAGS,
VCAP_KF_OAM_Y1731_IS,
VCAP_KF_PROT_ACTIVE,
VCAP_KF_TCP_IS,
VCAP_KF_TCP_UDP_IS,
VCAP_KF_TYPE,
};
/* Actionset names with origin information */
enum vcap_actionfield_set {
VCAP_AFS_NO_VALUE, /* initial value */
VCAP_AFS_BASE_TYPE, /* sparx5 is2 X3, sparx5 es2 X3 */
VCAP_AFS_CLASSIFICATION, /* sparx5 is0 X2 */
VCAP_AFS_CLASS_REDUCED, /* sparx5 is0 X1 */
VCAP_AFS_FULL, /* sparx5 is0 X3 */
VCAP_AFS_MLBS, /* sparx5 is0 X2 */
VCAP_AFS_MLBS_REDUCED, /* sparx5 is0 X1 */
};
/* List of actionfields with description
*
* VCAP_AF_CLS_VID_SEL: W3, sparx5: is0
* Controls the classified VID: 0: VID_NONE: No action. 1: VID_ADD: New VID =
* old VID + VID_VAL. 2: VID_REPLACE: New VID = VID_VAL. 3: VID_FIRST_TAG: New
* VID = VID from frame's first tag (outer tag) if available, otherwise VID_VAL.
* 4: VID_SECOND_TAG: New VID = VID from frame's second tag (middle tag) if
* available, otherwise VID_VAL. 5: VID_THIRD_TAG: New VID = VID from frame's
* third tag (inner tag) if available, otherwise VID_VAL.
* VCAP_AF_CNT_ID: sparx5 is2 W12, sparx5 es2 W11
* Counter ID, used per lookup to index the 4K frame counters (ANA_ACL:CNT_TBL).
* Multiple VCAP IS2 entries can use the same counter.
* VCAP_AF_COPY_PORT_NUM: W7, sparx5: es2
* QSYS port number when FWD_MODE is redirect or copy
* VCAP_AF_COPY_QUEUE_NUM: W16, sparx5: es2
* QSYS queue number when FWD_MODE is redirect or copy
* VCAP_AF_CPU_COPY_ENA: W1, sparx5: is2/es2
* Setting this bit to 1 causes all frames that hit this action to be copied to
* the CPU extraction queue specified in CPU_QUEUE_NUM.
* VCAP_AF_CPU_QUEUE_NUM: W3, sparx5: is2/es2
* CPU queue number. Used when CPU_COPY_ENA is set.
* VCAP_AF_DEI_ENA: W1, sparx5: is0
* If set, use DEI_VAL as classified DEI value. Otherwise, DEI from basic
* classification is used
* VCAP_AF_DEI_VAL: W1, sparx5: is0
* See DEI_ENA
* VCAP_AF_DP_ENA: W1, sparx5: is0
* If set, use DP_VAL as classified drop precedence level. Otherwise, drop
* precedence level from basic classification is used.
* VCAP_AF_DP_VAL: W2, sparx5: is0
* See DP_ENA.
* VCAP_AF_DSCP_ENA: W1, sparx5: is0
* If set, use DSCP_VAL as classified DSCP value. Otherwise, DSCP value from
* basic classification is used.
* VCAP_AF_DSCP_VAL: W6, sparx5: is0
* See DSCP_ENA.
* VCAP_AF_ES2_REW_CMD: W3, sparx5: es2
* Command forwarded to REW: 0: No action. 1: SWAP MAC addresses. 2: Do L2CP
* DMAC translation when entering or leaving a tunnel.
* VCAP_AF_FWD_MODE: W2, sparx5: es2
* Forward selector: 0: Forward. 1: Discard. 2: Redirect. 3: Copy.
* VCAP_AF_HIT_ME_ONCE: W1, sparx5: is2/es2
* Setting this bit to 1 causes the first frame that hits this action where the
* HIT_CNT counter is zero to be copied to the CPU extraction queue specified in
* CPU_QUEUE_NUM. The HIT_CNT counter is then incremented and any frames that
* hit this action later are not copied to the CPU. To re-enable the HIT_ME_ONCE
* functionality, the HIT_CNT counter must be cleared.
* VCAP_AF_IGNORE_PIPELINE_CTRL: W1, sparx5: is2/es2
* Ignore ingress pipeline control. This enforces the use of the VCAP IS2 action
* even when the pipeline control has terminated the frame before VCAP IS2.
* VCAP_AF_INTR_ENA: W1, sparx5: is2/es2
* If set, an interrupt is triggered when this rule is hit
* VCAP_AF_ISDX_ADD_REPLACE_SEL: W1, sparx5: is0
* Controls the classified ISDX. 0: New ISDX = old ISDX + ISDX_VAL. 1: New ISDX
* = ISDX_VAL.
* VCAP_AF_ISDX_VAL: W12, sparx5: is0
* See isdx_add_replace_sel
* VCAP_AF_LRN_DIS: W1, sparx5: is2
* Setting this bit to 1 disables learning of frames hitting this action.
* VCAP_AF_MAP_IDX: W9, sparx5: is0
* Index for QoS mapping table lookup
* VCAP_AF_MAP_KEY: W3, sparx5: is0
* Key type for QoS mapping table lookup. 0: DEI0, PCP0 (outer tag). 1: DEI1,
* PCP1 (middle tag). 2: DEI2, PCP2 (inner tag). 3: MPLS TC. 4: PCP0 (outer
* tag). 5: E-DEI, E-PCP (E-TAG). 6: DSCP if available, otherwise none. 7: DSCP
* if available, otherwise DEI0, PCP0 (outer tag) if available using MAP_IDX+8,
* otherwise none
* VCAP_AF_MAP_LOOKUP_SEL: W2, sparx5: is0
* Selects which of the two QoS Mapping Table lookups that MAP_KEY and MAP_IDX
* are applied to. 0: No changes to the QoS Mapping Table lookup. 1: Update key
* type and index for QoS Mapping Table lookup #0. 2: Update key type and index
* for QoS Mapping Table lookup #1. 3: Reserved.
* VCAP_AF_MASK_MODE: W3, sparx5: is0/is2
* Controls the PORT_MASK use. Sparx5: 0: OR_DSTMASK, 1: AND_VLANMASK, 2:
* REPLACE_PGID, 3: REPLACE_ALL, 4: REDIR_PGID, 5: OR_PGID_MASK, 6: VSTAX, 7:
* Not applicable. LAN966X: 0: No action, 1: Permit/deny (AND), 2: Policy
* forwarding (DMAC lookup), 3: Redirect. The CPU port is untouched by
* MASK_MODE.
* VCAP_AF_MATCH_ID: W16, sparx5: is0/is2
* Logical ID for the entry. The MATCH_ID is extracted together with the frame
* if the frame is forwarded to the CPU (CPU_COPY_ENA). The result is placed in
* IFH.CL_RSLT.
* VCAP_AF_MATCH_ID_MASK: W16, sparx5: is0/is2
* Mask used by MATCH_ID.
* VCAP_AF_MIRROR_PROBE: W2, sparx5: is2
* Mirroring performed according to configuration of a mirror probe. 0: No
* mirroring. 1: Mirror probe 0. 2: Mirror probe 1. 3: Mirror probe 2
* VCAP_AF_MIRROR_PROBE_ID: W2, sparx5: es2
* Signals a mirror probe to be placed in the IFH. Only possible when FWD_MODE
* is copy. 0: No mirroring. 1–3: Use mirror probe 0-2.
* VCAP_AF_NXT_IDX: W12, sparx5: is0
* Index used as part of key (field G_IDX) in the next lookup.
* VCAP_AF_NXT_IDX_CTRL: W3, sparx5: is0
* Controls the generation of the G_IDX used in the VCAP CLM next lookup
* VCAP_AF_PAG_OVERRIDE_MASK: W8, sparx5: is0
* Bits set in this mask will override PAG_VAL from port profile.  New PAG =
* (PAG (input) AND ~PAG_OVERRIDE_MASK) OR (PAG_VAL AND PAG_OVERRIDE_MASK)
* VCAP_AF_PAG_VAL: W8, sparx5: is0
* See PAG_OVERRIDE_MASK.
* VCAP_AF_PCP_ENA: W1, sparx5: is0
* If set, use PCP_VAL as classified PCP value. Otherwise, PCP from basic
* classification is used.
* VCAP_AF_PCP_VAL: W3, sparx5: is0
* See PCP_ENA.
* VCAP_AF_PIPELINE_FORCE_ENA: sparx5 is0 W2, sparx5 is2 W1
* If set, use PIPELINE_PT unconditionally and set PIPELINE_ACT = NONE if
* PIPELINE_PT == NONE. Overrules previous settings of pipeline point.
* VCAP_AF_PIPELINE_PT: W5, sparx5: is0/is2
* Pipeline point used if PIPELINE_FORCE_ENA is set
* VCAP_AF_POLICE_ENA: W1, sparx5: is2/es2
* Setting this bit to 1 causes frames that hit this action to be policed by the
* ACL policer specified in POLICE_IDX. Only applies to the first lookup.
* VCAP_AF_POLICE_IDX: W6, sparx5: is2/es2
* Selects VCAP policer used when policing frames (POLICE_ENA)
* VCAP_AF_POLICE_REMARK: W1, sparx5: es2
* If set, frames exceeding policer rates are marked as yellow but not
* discarded.
* VCAP_AF_PORT_MASK: sparx5 is0 W65, sparx5 is2 W68
* Port mask applied to the forwarding decision based on MASK_MODE.
* VCAP_AF_QOS_ENA: W1, sparx5: is0
* If set, use QOS_VAL as classified QoS class. Otherwise, QoS class from basic
* classification is used.
* VCAP_AF_QOS_VAL: W3, sparx5: is0
* See QOS_ENA.
* VCAP_AF_RT_DIS: W1, sparx5: is2
* If set, routing is disallowed. Only applies when IS_INNER_ACL is 0. See also
* IGR_ACL_ENA, EGR_ACL_ENA, and RLEG_STAT_IDX.
* VCAP_AF_TYPE: W1, sparx5: is0
* Actionset type id - Set by the API
* VCAP_AF_VID_VAL: W13, sparx5: is0
* New VID Value
*/
/* Actionfield names */
enum vcap_action_field {
VCAP_AF_NO_VALUE, /* initial value */
VCAP_AF_ACL_MAC,
VCAP_AF_ACL_RT_MODE,
VCAP_AF_CLS_VID_SEL,
VCAP_AF_CNT_ID,
VCAP_AF_COPY_PORT_NUM,
VCAP_AF_COPY_QUEUE_NUM,
VCAP_AF_COSID_ENA,
VCAP_AF_COSID_VAL,
VCAP_AF_CPU_COPY_ENA,
VCAP_AF_CPU_DIS,
VCAP_AF_CPU_ENA,
VCAP_AF_CPU_Q,
VCAP_AF_CPU_QUEUE_NUM,
VCAP_AF_CUSTOM_ACE_ENA,
VCAP_AF_CUSTOM_ACE_OFFSET,
VCAP_AF_DEI_ENA,
VCAP_AF_DEI_VAL,
VCAP_AF_DLB_OFFSET,
VCAP_AF_DMAC_OFFSET_ENA,
VCAP_AF_DP_ENA,
VCAP_AF_DP_VAL,
VCAP_AF_DSCP_ENA,
VCAP_AF_DSCP_VAL,
VCAP_AF_EGR_ACL_ENA,
VCAP_AF_ES2_REW_CMD,
VCAP_AF_FWD_DIS,
VCAP_AF_FWD_MODE,
VCAP_AF_FWD_TYPE,
VCAP_AF_GVID_ADD_REPLACE_SEL,
VCAP_AF_HIT_ME_ONCE,
VCAP_AF_IGNORE_PIPELINE_CTRL,
VCAP_AF_IGR_ACL_ENA,
VCAP_AF_INJ_MASQ_ENA,
VCAP_AF_INJ_MASQ_LPORT,
VCAP_AF_INJ_MASQ_PORT,
VCAP_AF_INTR_ENA,
VCAP_AF_ISDX_ADD_REPLACE_SEL,
VCAP_AF_ISDX_VAL,
VCAP_AF_IS_INNER_ACL,
VCAP_AF_L3_MAC_UPDATE_DIS,
VCAP_AF_LOG_MSG_INTERVAL,
VCAP_AF_LPM_AFFIX_ENA,
VCAP_AF_LPM_AFFIX_VAL,
VCAP_AF_LPORT_ENA,
VCAP_AF_LRN_DIS,
VCAP_AF_MAP_IDX,
VCAP_AF_MAP_KEY,
VCAP_AF_MAP_LOOKUP_SEL,
VCAP_AF_MASK_MODE,
VCAP_AF_MATCH_ID,
VCAP_AF_MATCH_ID_MASK,
VCAP_AF_MIP_SEL,
VCAP_AF_MIRROR_PROBE,
VCAP_AF_MIRROR_PROBE_ID,
VCAP_AF_MPLS_IP_CTRL_ENA,
VCAP_AF_MPLS_MEP_ENA,
VCAP_AF_MPLS_MIP_ENA,
VCAP_AF_MPLS_OAM_FLAVOR,
VCAP_AF_MPLS_OAM_TYPE,
VCAP_AF_NUM_VLD_LABELS,
VCAP_AF_NXT_IDX,
VCAP_AF_NXT_IDX_CTRL,
VCAP_AF_NXT_KEY_TYPE,
VCAP_AF_NXT_NORMALIZE,
VCAP_AF_NXT_NORM_W16_OFFSET,
VCAP_AF_NXT_NORM_W32_OFFSET,
VCAP_AF_NXT_OFFSET_FROM_TYPE,
VCAP_AF_NXT_TYPE_AFTER_OFFSET,
VCAP_AF_OAM_IP_BFD_ENA,
VCAP_AF_OAM_TWAMP_ENA,
VCAP_AF_OAM_Y1731_SEL,
VCAP_AF_PAG_OVERRIDE_MASK,
VCAP_AF_PAG_VAL,
VCAP_AF_PCP_ENA,
VCAP_AF_PCP_VAL,
VCAP_AF_PIPELINE_ACT_SEL,
VCAP_AF_PIPELINE_FORCE_ENA,
VCAP_AF_PIPELINE_PT,
VCAP_AF_PIPELINE_PT_REDUCED,
VCAP_AF_POLICE_ENA,
VCAP_AF_POLICE_IDX,
VCAP_AF_POLICE_REMARK,
VCAP_AF_PORT_MASK,
VCAP_AF_PTP_MASTER_SEL,
VCAP_AF_QOS_ENA,
VCAP_AF_QOS_VAL,
VCAP_AF_REW_CMD,
VCAP_AF_RLEG_DMAC_CHK_DIS,
VCAP_AF_RLEG_STAT_IDX,
VCAP_AF_RSDX_ENA,
VCAP_AF_RSDX_VAL,
VCAP_AF_RSVD_LBL_VAL,
VCAP_AF_RT_DIS,
VCAP_AF_RT_SEL,
VCAP_AF_S2_KEY_SEL_ENA,
VCAP_AF_S2_KEY_SEL_IDX,
VCAP_AF_SAM_SEQ_ENA,
VCAP_AF_SIP_IDX,
VCAP_AF_SWAP_MAC_ENA,
VCAP_AF_TCP_UDP_DPORT,
VCAP_AF_TCP_UDP_ENA,
VCAP_AF_TCP_UDP_SPORT,
VCAP_AF_TC_ENA,
VCAP_AF_TC_LABEL,
VCAP_AF_TPID_SEL,
VCAP_AF_TTL_DECR_DIS,
VCAP_AF_TTL_ENA,
VCAP_AF_TTL_LABEL,
VCAP_AF_TTL_UPDATE_ENA,
VCAP_AF_TYPE,
VCAP_AF_VID_VAL,
VCAP_AF_VLAN_POP_CNT,
VCAP_AF_VLAN_POP_CNT_ENA,
VCAP_AF_VLAN_PUSH_CNT,
VCAP_AF_VLAN_PUSH_CNT_ENA,
VCAP_AF_VLAN_WAS_TAGGED,
};
#endif /* __VCAP_AG_API__ */
drivers/net/ethernet/microchip/vcap/vcap_api.c
View file @ cb55ff7a
......@@ -8,6 +8,28 @@
#include "vcap_api_private.h"
static int keyfield_size_table[] = {
[VCAP_FIELD_BIT] = sizeof(struct vcap_u1_key),
[VCAP_FIELD_U32] = sizeof(struct vcap_u32_key),
[VCAP_FIELD_U48] = sizeof(struct vcap_u48_key),
[VCAP_FIELD_U56] = sizeof(struct vcap_u56_key),
[VCAP_FIELD_U64] = sizeof(struct vcap_u64_key),
[VCAP_FIELD_U72] = sizeof(struct vcap_u72_key),
[VCAP_FIELD_U112] = sizeof(struct vcap_u112_key),
[VCAP_FIELD_U128] = sizeof(struct vcap_u128_key),
};
static int actionfield_size_table[] = {
[VCAP_FIELD_BIT] = sizeof(struct vcap_u1_action),
[VCAP_FIELD_U32] = sizeof(struct vcap_u32_action),
[VCAP_FIELD_U48] = sizeof(struct vcap_u48_action),
[VCAP_FIELD_U56] = sizeof(struct vcap_u56_action),
[VCAP_FIELD_U64] = sizeof(struct vcap_u64_action),
[VCAP_FIELD_U72] = sizeof(struct vcap_u72_action),
[VCAP_FIELD_U112] = sizeof(struct vcap_u112_action),
[VCAP_FIELD_U128] = sizeof(struct vcap_u128_action),
};
/* Moving a rule in the VCAP address space */
struct vcap_rule_move {
int addr; /* address to move */
......@@ -1312,12 +1334,67 @@ const struct vcap_field *vcap_lookup_keyfield(struct vcap_rule *rule,
}
EXPORT_SYMBOL_GPL(vcap_lookup_keyfield);
/* Copy data from src to dst but reverse the data in chunks of 32bits.
* For example if src is 00:11:22:33:44:55 where 55 is LSB the dst will
* have the value 22:33:44:55:00:11.
*/
static void vcap_copy_to_w32be(u8 *dst, u8 *src, int size)
{
for (int idx = 0; idx < size; ++idx) {
int first_byte_index = 0;
int nidx;
first_byte_index = size - (((idx >> 2) + 1) << 2);
if (first_byte_index < 0)
first_byte_index = 0;
nidx = idx + first_byte_index - (idx & ~0x3);
dst[nidx] = src[idx];
}
}
static void vcap_copy_from_client_keyfield(struct vcap_rule *rule,
struct vcap_client_keyfield *field,
struct vcap_client_keyfield_data *data)
{
/* This will be expanded later to handle different vcap memory layouts */
memcpy(&field->data, data, sizeof(field->data));
struct vcap_rule_internal *ri = to_intrule(rule);
int size;
if (!ri->admin->w32be) {
memcpy(&field->data, data, sizeof(field->data));
return;
}
size = keyfield_size_table[field->ctrl.type] / 2;
switch (field->ctrl.type) {
case VCAP_FIELD_BIT:
case VCAP_FIELD_U32:
memcpy(&field->data, data, sizeof(field->data));
break;
case VCAP_FIELD_U48:
vcap_copy_to_w32be(field->data.u48.value, data->u48.value, size);
vcap_copy_to_w32be(field->data.u48.mask, data->u48.mask, size);
break;
case VCAP_FIELD_U56:
vcap_copy_to_w32be(field->data.u56.value, data->u56.value, size);
vcap_copy_to_w32be(field->data.u56.mask, data->u56.mask, size);
break;
case VCAP_FIELD_U64:
vcap_copy_to_w32be(field->data.u64.value, data->u64.value, size);
vcap_copy_to_w32be(field->data.u64.mask, data->u64.mask, size);
break;
case VCAP_FIELD_U72:
vcap_copy_to_w32be(field->data.u72.value, data->u72.value, size);
vcap_copy_to_w32be(field->data.u72.mask, data->u72.mask, size);
break;
case VCAP_FIELD_U112:
vcap_copy_to_w32be(field->data.u112.value, data->u112.value, size);
vcap_copy_to_w32be(field->data.u112.mask, data->u112.mask, size);
break;
case VCAP_FIELD_U128:
vcap_copy_to_w32be(field->data.u128.value, data->u128.value, size);
vcap_copy_to_w32be(field->data.u128.mask, data->u128.mask, size);
break;
};
}
/* Check if the keyfield is already in the rule */
......@@ -1475,8 +1552,39 @@ static void vcap_copy_from_client_actionfield(struct vcap_rule *rule,
struct vcap_client_actionfield *field,
struct vcap_client_actionfield_data *data)
{
/* This will be expanded later to handle different vcap memory layouts */
memcpy(&field->data, data, sizeof(field->data));
struct vcap_rule_internal *ri = to_intrule(rule);
int size;
if (!ri->admin->w32be) {
memcpy(&field->data, data, sizeof(field->data));
return;
}
size = actionfield_size_table[field->ctrl.type];
switch (field->ctrl.type) {
case VCAP_FIELD_BIT:
case VCAP_FIELD_U32:
memcpy(&field->data, data, sizeof(field->data));
break;
case VCAP_FIELD_U48:
vcap_copy_to_w32be(field->data.u48.value, data->u48.value, size);
break;
case VCAP_FIELD_U56:
vcap_copy_to_w32be(field->data.u56.value, data->u56.value, size);
break;
case VCAP_FIELD_U64:
vcap_copy_to_w32be(field->data.u64.value, data->u64.value, size);
break;
case VCAP_FIELD_U72:
vcap_copy_to_w32be(field->data.u72.value, data->u72.value, size);
break;
case VCAP_FIELD_U112:
vcap_copy_to_w32be(field->data.u112.value, data->u112.value, size);
break;
case VCAP_FIELD_U128:
vcap_copy_to_w32be(field->data.u128.value, data->u128.value, size);
break;
};
}
/* Check if the actionfield is already in the rule */
......
drivers/net/ethernet/microchip/vcap/vcap_api.h
View file @ cb55ff7a
......@@ -11,9 +11,6 @@
#include <linux/netdevice.h>
/* Use the generated API model */
#ifdef CONFIG_VCAP_KUNIT_TEST
#include "vcap_ag_api_kunit.h"
#endif
#include "vcap_ag_api.h"
#define VCAP_CID_LOOKUP_SIZE 100000 /* Chains in a lookup */
......
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