Commit cc1338f2 authored by Matt Roper's avatar Matt Roper

drm/i915/xehp: Update topology dumps for Xe_HP

When running on Xe_HP or beyond, let's use an updated format for
describing topology in our error state dumps and debugfs to give a
more accurate view of the hardware:

 - Just report DSS directly without the legacy "slice0" output that's no
   longer meaningful.
 - Indicate whether each DSS is accessible for geometry and/or compute.
 - Rename "rcs_topology" to "sseu_topology" since the information
   reported is common to both RCS and CCS engines now.

v2:
 - Name static functions in a more consistent manner.  (Lucas)
Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Reviewed-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220311225459.385515-2-matthew.d.roper@intel.com
parent 144ce0ac
...@@ -8,6 +8,8 @@ ...@@ -8,6 +8,8 @@
#include "intel_gt_regs.h" #include "intel_gt_regs.h"
#include "intel_sseu.h" #include "intel_sseu.h"
#include "linux/string_helpers.h"
void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices, void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices,
u8 max_subslices, u8 max_eus_per_subslice) u8 max_subslices, u8 max_eus_per_subslice)
{ {
...@@ -33,7 +35,7 @@ intel_sseu_subslice_total(const struct sseu_dev_info *sseu) ...@@ -33,7 +35,7 @@ intel_sseu_subslice_total(const struct sseu_dev_info *sseu)
} }
static u32 static u32
_intel_sseu_get_subslices(const struct sseu_dev_info *sseu, sseu_get_subslices(const struct sseu_dev_info *sseu,
const u8 *subslice_mask, u8 slice) const u8 *subslice_mask, u8 slice)
{ {
int i, offset = slice * sseu->ss_stride; int i, offset = slice * sseu->ss_stride;
...@@ -49,12 +51,17 @@ _intel_sseu_get_subslices(const struct sseu_dev_info *sseu, ...@@ -49,12 +51,17 @@ _intel_sseu_get_subslices(const struct sseu_dev_info *sseu,
u32 intel_sseu_get_subslices(const struct sseu_dev_info *sseu, u8 slice) u32 intel_sseu_get_subslices(const struct sseu_dev_info *sseu, u8 slice)
{ {
return _intel_sseu_get_subslices(sseu, sseu->subslice_mask, slice); return sseu_get_subslices(sseu, sseu->subslice_mask, slice);
}
static u32 sseu_get_geometry_subslices(const struct sseu_dev_info *sseu)
{
return sseu_get_subslices(sseu, sseu->geometry_subslice_mask, 0);
} }
u32 intel_sseu_get_compute_subslices(const struct sseu_dev_info *sseu) u32 intel_sseu_get_compute_subslices(const struct sseu_dev_info *sseu)
{ {
return _intel_sseu_get_subslices(sseu, sseu->compute_subslice_mask, 0); return sseu_get_subslices(sseu, sseu->compute_subslice_mask, 0);
} }
void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice, void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,
...@@ -717,16 +724,11 @@ void intel_sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p) ...@@ -717,16 +724,11 @@ void intel_sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p)
drm_printf(p, "has EU power gating: %s\n", yesno(sseu->has_eu_pg)); drm_printf(p, "has EU power gating: %s\n", yesno(sseu->has_eu_pg));
} }
void intel_sseu_print_topology(const struct sseu_dev_info *sseu, static void sseu_print_hsw_topology(const struct sseu_dev_info *sseu,
struct drm_printer *p) struct drm_printer *p)
{ {
int s, ss; int s, ss;
if (sseu->max_slices == 0) {
drm_printf(p, "Unavailable\n");
return;
}
for (s = 0; s < sseu->max_slices; s++) { for (s = 0; s < sseu->max_slices; s++) {
drm_printf(p, "slice%d: %u subslice(s) (0x%08x):\n", drm_printf(p, "slice%d: %u subslice(s) (0x%08x):\n",
s, intel_sseu_subslices_per_slice(sseu, s), s, intel_sseu_subslices_per_slice(sseu, s),
...@@ -741,6 +743,36 @@ void intel_sseu_print_topology(const struct sseu_dev_info *sseu, ...@@ -741,6 +743,36 @@ void intel_sseu_print_topology(const struct sseu_dev_info *sseu,
} }
} }
static void sseu_print_xehp_topology(const struct sseu_dev_info *sseu,
struct drm_printer *p)
{
u32 g_dss_mask = sseu_get_geometry_subslices(sseu);
u32 c_dss_mask = intel_sseu_get_compute_subslices(sseu);
int dss;
for (dss = 0; dss < sseu->max_subslices; dss++) {
u16 enabled_eus = sseu_get_eus(sseu, 0, dss);
drm_printf(p, "DSS_%02d: G:%3s C:%3s, %2u EUs (0x%04hx)\n", dss,
str_yes_no(g_dss_mask & BIT(dss)),
str_yes_no(c_dss_mask & BIT(dss)),
hweight16(enabled_eus), enabled_eus);
}
}
void intel_sseu_print_topology(struct drm_i915_private *i915,
const struct sseu_dev_info *sseu,
struct drm_printer *p)
{
if (sseu->max_slices == 0) {
drm_printf(p, "Unavailable\n");
} else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
sseu_print_xehp_topology(sseu, p);
} else {
sseu_print_hsw_topology(sseu, p);
}
}
u16 intel_slicemask_from_dssmask(u64 dss_mask, int dss_per_slice) u16 intel_slicemask_from_dssmask(u64 dss_mask, int dss_per_slice)
{ {
u16 slice_mask = 0; u16 slice_mask = 0;
......
...@@ -139,7 +139,8 @@ u32 intel_sseu_make_rpcs(struct intel_gt *gt, ...@@ -139,7 +139,8 @@ u32 intel_sseu_make_rpcs(struct intel_gt *gt,
const struct intel_sseu *req_sseu); const struct intel_sseu *req_sseu);
void intel_sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p); void intel_sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p);
void intel_sseu_print_topology(const struct sseu_dev_info *sseu, void intel_sseu_print_topology(struct drm_i915_private *i915,
const struct sseu_dev_info *sseu,
struct drm_printer *p); struct drm_printer *p);
u16 intel_slicemask_from_dssmask(u64 dss_mask, int dss_per_slice); u16 intel_slicemask_from_dssmask(u64 dss_mask, int dss_per_slice);
......
...@@ -285,22 +285,22 @@ static int sseu_status_show(struct seq_file *m, void *unused) ...@@ -285,22 +285,22 @@ static int sseu_status_show(struct seq_file *m, void *unused)
} }
DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(sseu_status); DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(sseu_status);
static int rcs_topology_show(struct seq_file *m, void *unused) static int sseu_topology_show(struct seq_file *m, void *unused)
{ {
struct intel_gt *gt = m->private; struct intel_gt *gt = m->private;
struct drm_printer p = drm_seq_file_printer(m); struct drm_printer p = drm_seq_file_printer(m);
intel_sseu_print_topology(&gt->info.sseu, &p); intel_sseu_print_topology(gt->i915, &gt->info.sseu, &p);
return 0; return 0;
} }
DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(rcs_topology); DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(sseu_topology);
void intel_sseu_debugfs_register(struct intel_gt *gt, struct dentry *root) void intel_sseu_debugfs_register(struct intel_gt *gt, struct dentry *root)
{ {
static const struct intel_gt_debugfs_file files[] = { static const struct intel_gt_debugfs_file files[] = {
{ "sseu_status", &sseu_status_fops, NULL }, { "sseu_status", &sseu_status_fops, NULL },
{ "rcs_topology", &rcs_topology_fops, NULL }, { "sseu_topology", &sseu_topology_fops, NULL },
}; };
intel_gt_debugfs_register_files(root, files, ARRAY_SIZE(files), gt); intel_gt_debugfs_register_files(root, files, ARRAY_SIZE(files), gt);
......
...@@ -710,7 +710,7 @@ static void err_print_gt_info(struct drm_i915_error_state_buf *m, ...@@ -710,7 +710,7 @@ static void err_print_gt_info(struct drm_i915_error_state_buf *m,
struct drm_printer p = i915_error_printer(m); struct drm_printer p = i915_error_printer(m);
intel_gt_info_print(&gt->info, &p); intel_gt_info_print(&gt->info, &p);
intel_sseu_print_topology(&gt->info.sseu, &p); intel_sseu_print_topology(gt->_gt->i915, &gt->info.sseu, &p);
} }
static void err_print_gt(struct drm_i915_error_state_buf *m, static void err_print_gt(struct drm_i915_error_state_buf *m,
......
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