Commit cc4db579 authored by Igor Leshenko's avatar Igor Leshenko Committed by Saeed Mahameed

net/mlx5: FPGA, support network cards with standalone FPGA

Not all mlx5 cards with FPGA device use it for network processing.

mlx5_core driver configures network connection to FPGA device
for all mlx5 cards with installed FPGA. If FPGA is not a part of
network path, driver crashes in this case

Check FPGA name in function mlx5_fpga_device_start() and continue
integrate FPGA into packets flow only for dedicated cards.
Currently there are Newton and Edison cards.
Signed-off-by: default avatarIgor Leshenko <igorle@mellanox.com>
Reviewed-by: default avatarMeir Lichtinger <meirl@mellanox.com>
Reviewed-by: default avatarBoris Pismenny <borisp@mellanox.com>
Signed-off-by: default avatarSaeed Mahameed <saeedm@mellanox.com>
parent 40416d8e
...@@ -35,11 +35,11 @@ ...@@ -35,11 +35,11 @@
#include <linux/mlx5/driver.h> #include <linux/mlx5/driver.h>
enum mlx5_fpga_device_id { enum mlx5_fpga_id {
MLX5_FPGA_DEVICE_UNKNOWN = 0, MLX5_FPGA_NEWTON = 0,
MLX5_FPGA_DEVICE_KU040 = 1, MLX5_FPGA_EDISON = 1,
MLX5_FPGA_DEVICE_KU060 = 2, MLX5_FPGA_MORSE = 2,
MLX5_FPGA_DEVICE_KU060_2 = 3, MLX5_FPGA_MORSEQ = 3,
}; };
enum mlx5_fpga_image { enum mlx5_fpga_image {
......
...@@ -81,19 +81,28 @@ static const char *mlx5_fpga_image_name(enum mlx5_fpga_image image) ...@@ -81,19 +81,28 @@ static const char *mlx5_fpga_image_name(enum mlx5_fpga_image image)
} }
} }
static const char *mlx5_fpga_device_name(u32 device) static const char *mlx5_fpga_name(u32 fpga_id)
{ {
switch (device) { static char ret[32];
case MLX5_FPGA_DEVICE_KU040:
return "ku040"; switch (fpga_id) {
case MLX5_FPGA_DEVICE_KU060: case MLX5_FPGA_NEWTON:
return "ku060"; return "Newton";
case MLX5_FPGA_DEVICE_KU060_2: case MLX5_FPGA_EDISON:
return "ku060_2"; return "Edison";
case MLX5_FPGA_DEVICE_UNKNOWN: case MLX5_FPGA_MORSE:
default: return "Morse";
return "unknown"; case MLX5_FPGA_MORSEQ:
return "MorseQ";
} }
snprintf(ret, sizeof(ret), "Unknown %d", fpga_id);
return ret;
}
static int mlx5_is_fpga_lookaside(u32 fpga_id)
{
return fpga_id != MLX5_FPGA_NEWTON && fpga_id != MLX5_FPGA_EDISON;
} }
static int mlx5_fpga_device_load_check(struct mlx5_fpga_device *fdev) static int mlx5_fpga_device_load_check(struct mlx5_fpga_device *fdev)
...@@ -110,9 +119,13 @@ static int mlx5_fpga_device_load_check(struct mlx5_fpga_device *fdev) ...@@ -110,9 +119,13 @@ static int mlx5_fpga_device_load_check(struct mlx5_fpga_device *fdev)
fdev->last_admin_image = query.admin_image; fdev->last_admin_image = query.admin_image;
fdev->last_oper_image = query.oper_image; fdev->last_oper_image = query.oper_image;
mlx5_fpga_dbg(fdev, "Status %u; Admin image %u; Oper image %u\n", mlx5_fpga_info(fdev, "Status %u; Admin image %u; Oper image %u\n",
query.status, query.admin_image, query.oper_image); query.status, query.admin_image, query.oper_image);
/* for FPGA lookaside projects FPGA load status is not important */
if (mlx5_is_fpga_lookaside(MLX5_CAP_FPGA(fdev->mdev, fpga_id)))
return 0;
if (query.status != MLX5_FPGA_STATUS_SUCCESS) { if (query.status != MLX5_FPGA_STATUS_SUCCESS) {
mlx5_fpga_err(fdev, "%s image failed to load; status %u\n", mlx5_fpga_err(fdev, "%s image failed to load; status %u\n",
mlx5_fpga_image_name(fdev->last_oper_image), mlx5_fpga_image_name(fdev->last_oper_image),
...@@ -167,25 +180,30 @@ int mlx5_fpga_device_start(struct mlx5_core_dev *mdev) ...@@ -167,25 +180,30 @@ int mlx5_fpga_device_start(struct mlx5_core_dev *mdev)
struct mlx5_fpga_device *fdev = mdev->fpga; struct mlx5_fpga_device *fdev = mdev->fpga;
unsigned int max_num_qps; unsigned int max_num_qps;
unsigned long flags; unsigned long flags;
u32 fpga_device_id; u32 fpga_id;
int err; int err;
if (!fdev) if (!fdev)
return 0; return 0;
err = mlx5_fpga_device_load_check(fdev); err = mlx5_fpga_caps(fdev->mdev);
if (err) if (err)
goto out; goto out;
err = mlx5_fpga_caps(fdev->mdev); err = mlx5_fpga_device_load_check(fdev);
if (err) if (err)
goto out; goto out;
fpga_device_id = MLX5_CAP_FPGA(fdev->mdev, fpga_device); fpga_id = MLX5_CAP_FPGA(fdev->mdev, fpga_id);
mlx5_fpga_info(fdev, "%s:%u; %s image, version %u; SBU %06x:%04x version %d\n", mlx5_fpga_info(fdev, "FPGA card %s:%u\n", mlx5_fpga_name(fpga_id), fpga_id);
mlx5_fpga_device_name(fpga_device_id),
fpga_device_id, /* No QPs if FPGA does not participate in net processing */
if (mlx5_is_fpga_lookaside(fpga_id))
goto out;
mlx5_fpga_info(fdev, "%s(%d): image, version %u; SBU %06x:%04x version %d\n",
mlx5_fpga_image_name(fdev->last_oper_image), mlx5_fpga_image_name(fdev->last_oper_image),
fdev->last_oper_image,
MLX5_CAP_FPGA(fdev->mdev, image_version), MLX5_CAP_FPGA(fdev->mdev, image_version),
MLX5_CAP_FPGA(fdev->mdev, ieee_vendor_id), MLX5_CAP_FPGA(fdev->mdev, ieee_vendor_id),
MLX5_CAP_FPGA(fdev->mdev, sandbox_product_id), MLX5_CAP_FPGA(fdev->mdev, sandbox_product_id),
...@@ -264,6 +282,9 @@ void mlx5_fpga_device_stop(struct mlx5_core_dev *mdev) ...@@ -264,6 +282,9 @@ void mlx5_fpga_device_stop(struct mlx5_core_dev *mdev)
if (!fdev) if (!fdev)
return; return;
if (mlx5_is_fpga_lookaside(MLX5_CAP_FPGA(fdev->mdev, fpga_id)))
return;
spin_lock_irqsave(&fdev->state_lock, flags); spin_lock_irqsave(&fdev->state_lock, flags);
if (fdev->state != MLX5_FPGA_STATUS_SUCCESS) { if (fdev->state != MLX5_FPGA_STATUS_SUCCESS) {
spin_unlock_irqrestore(&fdev->state_lock, flags); spin_unlock_irqrestore(&fdev->state_lock, flags);
......
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