Commit cc54a828 authored by Tvrtko Ursulin's avatar Tvrtko Ursulin

drm/i915: Consolidate seqno_barrier vfunc

Signed-off-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
parent 7445a2a4
...@@ -2889,10 +2889,12 @@ static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv, ...@@ -2889,10 +2889,12 @@ static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv,
{ {
engine->write_tail = ring_write_tail; engine->write_tail = ring_write_tail;
if (INTEL_GEN(dev_priv) >= 6) if (INTEL_GEN(dev_priv) >= 6) {
engine->add_request = gen6_add_request; engine->add_request = gen6_add_request;
else engine->irq_seqno_barrier = gen6_seqno_barrier;
} else {
engine->add_request = i9xx_add_request; engine->add_request = i9xx_add_request;
}
} }
int intel_init_render_ring_buffer(struct drm_device *dev) int intel_init_render_ring_buffer(struct drm_device *dev)
...@@ -2950,7 +2952,6 @@ int intel_init_render_ring_buffer(struct drm_device *dev) ...@@ -2950,7 +2952,6 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
engine->irq_get = gen6_ring_get_irq; engine->irq_get = gen6_ring_get_irq;
engine->irq_put = gen6_ring_put_irq; engine->irq_put = gen6_ring_put_irq;
engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT; engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
engine->irq_seqno_barrier = gen6_seqno_barrier;
engine->get_seqno = ring_get_seqno; engine->get_seqno = ring_get_seqno;
engine->set_seqno = ring_set_seqno; engine->set_seqno = ring_set_seqno;
if (i915_semaphore_is_enabled(dev_priv)) { if (i915_semaphore_is_enabled(dev_priv)) {
...@@ -3065,7 +3066,6 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev) ...@@ -3065,7 +3066,6 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
if (IS_GEN6(dev_priv)) if (IS_GEN6(dev_priv))
engine->write_tail = gen6_bsd_ring_write_tail; engine->write_tail = gen6_bsd_ring_write_tail;
engine->flush = gen6_bsd_ring_flush; engine->flush = gen6_bsd_ring_flush;
engine->irq_seqno_barrier = gen6_seqno_barrier;
engine->get_seqno = ring_get_seqno; engine->get_seqno = ring_get_seqno;
engine->set_seqno = ring_set_seqno; engine->set_seqno = ring_set_seqno;
if (INTEL_GEN(dev_priv) >= 8) { if (INTEL_GEN(dev_priv) >= 8) {
...@@ -3139,7 +3139,6 @@ int intel_init_bsd2_ring_buffer(struct drm_device *dev) ...@@ -3139,7 +3139,6 @@ int intel_init_bsd2_ring_buffer(struct drm_device *dev)
intel_ring_default_vfuncs(dev_priv, engine); intel_ring_default_vfuncs(dev_priv, engine);
engine->flush = gen6_bsd_ring_flush; engine->flush = gen6_bsd_ring_flush;
engine->irq_seqno_barrier = gen6_seqno_barrier;
engine->get_seqno = ring_get_seqno; engine->get_seqno = ring_get_seqno;
engine->set_seqno = ring_set_seqno; engine->set_seqno = ring_set_seqno;
engine->irq_enable_mask = engine->irq_enable_mask =
...@@ -3172,7 +3171,6 @@ int intel_init_blt_ring_buffer(struct drm_device *dev) ...@@ -3172,7 +3171,6 @@ int intel_init_blt_ring_buffer(struct drm_device *dev)
intel_ring_default_vfuncs(dev_priv, engine); intel_ring_default_vfuncs(dev_priv, engine);
engine->flush = gen6_ring_flush; engine->flush = gen6_ring_flush;
engine->irq_seqno_barrier = gen6_seqno_barrier;
engine->get_seqno = ring_get_seqno; engine->get_seqno = ring_get_seqno;
engine->set_seqno = ring_set_seqno; engine->set_seqno = ring_set_seqno;
if (INTEL_GEN(dev_priv) >= 8) { if (INTEL_GEN(dev_priv) >= 8) {
...@@ -3232,7 +3230,6 @@ int intel_init_vebox_ring_buffer(struct drm_device *dev) ...@@ -3232,7 +3230,6 @@ int intel_init_vebox_ring_buffer(struct drm_device *dev)
intel_ring_default_vfuncs(dev_priv, engine); intel_ring_default_vfuncs(dev_priv, engine);
engine->flush = gen6_ring_flush; engine->flush = gen6_ring_flush;
engine->irq_seqno_barrier = gen6_seqno_barrier;
engine->get_seqno = ring_get_seqno; engine->get_seqno = ring_get_seqno;
engine->set_seqno = ring_set_seqno; engine->set_seqno = ring_set_seqno;
......
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